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e126ba97 | 1 | /* |
302bdf68 | 2 | * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved. |
e126ba97 EC |
3 | * |
4 | * This software is available to you under a choice of one of two | |
5 | * licenses. You may choose to be licensed under the terms of the GNU | |
6 | * General Public License (GPL) Version 2, available from the file | |
7 | * COPYING in the main directory of this source tree, or the | |
8 | * OpenIB.org BSD license below: | |
9 | * | |
10 | * Redistribution and use in source and binary forms, with or | |
11 | * without modification, are permitted provided that the following | |
12 | * conditions are met: | |
13 | * | |
14 | * - Redistributions of source code must retain the above | |
15 | * copyright notice, this list of conditions and the following | |
16 | * disclaimer. | |
17 | * | |
18 | * - Redistributions in binary form must reproduce the above | |
19 | * copyright notice, this list of conditions and the following | |
20 | * disclaimer in the documentation and/or other materials | |
21 | * provided with the distribution. | |
22 | * | |
23 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, | |
24 | * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | |
25 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND | |
26 | * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS | |
27 | * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN | |
28 | * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN | |
29 | * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE | |
30 | * SOFTWARE. | |
31 | */ | |
32 | ||
33 | #ifndef MLX5_QP_H | |
34 | #define MLX5_QP_H | |
35 | ||
36 | #include <linux/mlx5/device.h> | |
37 | #include <linux/mlx5/driver.h> | |
38 | ||
39 | #define MLX5_INVALID_LKEY 0x100 | |
e1e66cc2 | 40 | #define MLX5_SIG_WQE_SIZE (MLX5_SEND_WQE_BB * 5) |
e6631814 SG |
41 | #define MLX5_DIF_SIZE 8 |
42 | #define MLX5_STRIDE_BLOCK_OP 0x400 | |
fd22f78c SG |
43 | #define MLX5_CPY_GRD_MASK 0xc0 |
44 | #define MLX5_CPY_APP_MASK 0x30 | |
45 | #define MLX5_CPY_REF_MASK 0x0f | |
142537f4 SG |
46 | #define MLX5_BSF_INC_REFTAG (1 << 6) |
47 | #define MLX5_BSF_INL_VALID (1 << 15) | |
48 | #define MLX5_BSF_REFRESH_DIF (1 << 14) | |
49 | #define MLX5_BSF_REPEAT_BLOCK (1 << 7) | |
50 | #define MLX5_BSF_APPTAG_ESCAPE 0x1 | |
51 | #define MLX5_BSF_APPREF_ESCAPE 0x2 | |
e126ba97 | 52 | |
e420f0c0 HE |
53 | #define MLX5_QPN_BITS 24 |
54 | #define MLX5_QPN_MASK ((1 << MLX5_QPN_BITS) - 1) | |
55 | ||
e126ba97 EC |
56 | enum mlx5_qp_optpar { |
57 | MLX5_QP_OPTPAR_ALT_ADDR_PATH = 1 << 0, | |
58 | MLX5_QP_OPTPAR_RRE = 1 << 1, | |
59 | MLX5_QP_OPTPAR_RAE = 1 << 2, | |
60 | MLX5_QP_OPTPAR_RWE = 1 << 3, | |
61 | MLX5_QP_OPTPAR_PKEY_INDEX = 1 << 4, | |
62 | MLX5_QP_OPTPAR_Q_KEY = 1 << 5, | |
63 | MLX5_QP_OPTPAR_RNR_TIMEOUT = 1 << 6, | |
64 | MLX5_QP_OPTPAR_PRIMARY_ADDR_PATH = 1 << 7, | |
65 | MLX5_QP_OPTPAR_SRA_MAX = 1 << 8, | |
66 | MLX5_QP_OPTPAR_RRA_MAX = 1 << 9, | |
67 | MLX5_QP_OPTPAR_PM_STATE = 1 << 10, | |
68 | MLX5_QP_OPTPAR_RETRY_COUNT = 1 << 12, | |
69 | MLX5_QP_OPTPAR_RNR_RETRY = 1 << 13, | |
70 | MLX5_QP_OPTPAR_ACK_TIMEOUT = 1 << 14, | |
71 | MLX5_QP_OPTPAR_PRI_PORT = 1 << 16, | |
72 | MLX5_QP_OPTPAR_SRQN = 1 << 18, | |
73 | MLX5_QP_OPTPAR_CQN_RCV = 1 << 19, | |
74 | MLX5_QP_OPTPAR_DC_HS = 1 << 20, | |
75 | MLX5_QP_OPTPAR_DC_KEY = 1 << 21, | |
76 | }; | |
77 | ||
78 | enum mlx5_qp_state { | |
79 | MLX5_QP_STATE_RST = 0, | |
80 | MLX5_QP_STATE_INIT = 1, | |
81 | MLX5_QP_STATE_RTR = 2, | |
82 | MLX5_QP_STATE_RTS = 3, | |
83 | MLX5_QP_STATE_SQER = 4, | |
84 | MLX5_QP_STATE_SQD = 5, | |
85 | MLX5_QP_STATE_ERR = 6, | |
86 | MLX5_QP_STATE_SQ_DRAINING = 7, | |
87 | MLX5_QP_STATE_SUSPENDED = 9, | |
88 | MLX5_QP_NUM_STATE | |
89 | }; | |
90 | ||
91 | enum { | |
92 | MLX5_QP_ST_RC = 0x0, | |
93 | MLX5_QP_ST_UC = 0x1, | |
94 | MLX5_QP_ST_UD = 0x2, | |
95 | MLX5_QP_ST_XRC = 0x3, | |
96 | MLX5_QP_ST_MLX = 0x4, | |
97 | MLX5_QP_ST_DCI = 0x5, | |
98 | MLX5_QP_ST_DCT = 0x6, | |
99 | MLX5_QP_ST_QP0 = 0x7, | |
100 | MLX5_QP_ST_QP1 = 0x8, | |
101 | MLX5_QP_ST_RAW_ETHERTYPE = 0x9, | |
102 | MLX5_QP_ST_RAW_IPV6 = 0xa, | |
103 | MLX5_QP_ST_SNIFFER = 0xb, | |
104 | MLX5_QP_ST_SYNC_UMR = 0xe, | |
105 | MLX5_QP_ST_PTP_1588 = 0xd, | |
106 | MLX5_QP_ST_REG_UMR = 0xc, | |
107 | MLX5_QP_ST_MAX | |
108 | }; | |
109 | ||
110 | enum { | |
111 | MLX5_QP_PM_MIGRATED = 0x3, | |
112 | MLX5_QP_PM_ARMED = 0x0, | |
113 | MLX5_QP_PM_REARM = 0x1 | |
114 | }; | |
115 | ||
116 | enum { | |
117 | MLX5_NON_ZERO_RQ = 0 << 24, | |
118 | MLX5_SRQ_RQ = 1 << 24, | |
119 | MLX5_CRQ_RQ = 2 << 24, | |
120 | MLX5_ZERO_LEN_RQ = 3 << 24 | |
121 | }; | |
122 | ||
123 | enum { | |
124 | /* params1 */ | |
125 | MLX5_QP_BIT_SRE = 1 << 15, | |
126 | MLX5_QP_BIT_SWE = 1 << 14, | |
127 | MLX5_QP_BIT_SAE = 1 << 13, | |
128 | /* params2 */ | |
129 | MLX5_QP_BIT_RRE = 1 << 15, | |
130 | MLX5_QP_BIT_RWE = 1 << 14, | |
131 | MLX5_QP_BIT_RAE = 1 << 13, | |
132 | MLX5_QP_BIT_RIC = 1 << 4, | |
051f2630 LR |
133 | MLX5_QP_BIT_CC_SLAVE_RECV = 1 << 2, |
134 | MLX5_QP_BIT_CC_SLAVE_SEND = 1 << 1, | |
135 | MLX5_QP_BIT_CC_MASTER = 1 << 0 | |
e126ba97 EC |
136 | }; |
137 | ||
138 | enum { | |
139 | MLX5_WQE_CTRL_CQ_UPDATE = 2 << 2, | |
e281682b | 140 | MLX5_WQE_CTRL_CQ_UPDATE_AND_EQE = 3 << 2, |
e126ba97 EC |
141 | MLX5_WQE_CTRL_SOLICITED = 1 << 1, |
142 | }; | |
143 | ||
144 | enum { | |
e281682b | 145 | MLX5_SEND_WQE_DS = 16, |
e126ba97 EC |
146 | MLX5_SEND_WQE_BB = 64, |
147 | }; | |
148 | ||
e281682b SM |
149 | #define MLX5_SEND_WQEBB_NUM_DS (MLX5_SEND_WQE_BB / MLX5_SEND_WQE_DS) |
150 | ||
151 | enum { | |
152 | MLX5_SEND_WQE_MAX_WQEBBS = 16, | |
153 | }; | |
154 | ||
e126ba97 EC |
155 | enum { |
156 | MLX5_WQE_FMR_PERM_LOCAL_READ = 1 << 27, | |
157 | MLX5_WQE_FMR_PERM_LOCAL_WRITE = 1 << 28, | |
158 | MLX5_WQE_FMR_PERM_REMOTE_READ = 1 << 29, | |
159 | MLX5_WQE_FMR_PERM_REMOTE_WRITE = 1 << 30, | |
160 | MLX5_WQE_FMR_PERM_ATOMIC = 1 << 31 | |
161 | }; | |
162 | ||
163 | enum { | |
164 | MLX5_FENCE_MODE_NONE = 0 << 5, | |
165 | MLX5_FENCE_MODE_INITIATOR_SMALL = 1 << 5, | |
166 | MLX5_FENCE_MODE_STRONG_ORDERING = 3 << 5, | |
167 | MLX5_FENCE_MODE_SMALL_AND_FENCE = 4 << 5, | |
168 | }; | |
169 | ||
170 | enum { | |
171 | MLX5_QP_LAT_SENSITIVE = 1 << 28, | |
f360d88a | 172 | MLX5_QP_BLOCK_MCAST = 1 << 30, |
e126ba97 EC |
173 | MLX5_QP_ENABLE_SIG = 1 << 31, |
174 | }; | |
175 | ||
176 | enum { | |
177 | MLX5_RCV_DBR = 0, | |
178 | MLX5_SND_DBR = 1, | |
179 | }; | |
180 | ||
e6631814 SG |
181 | enum { |
182 | MLX5_FLAGS_INLINE = 1<<7, | |
183 | MLX5_FLAGS_CHECK_FREE = 1<<5, | |
184 | }; | |
185 | ||
e126ba97 EC |
186 | struct mlx5_wqe_fmr_seg { |
187 | __be32 flags; | |
188 | __be32 mem_key; | |
189 | __be64 buf_list; | |
190 | __be64 start_addr; | |
191 | __be64 reg_len; | |
192 | __be32 offset; | |
193 | __be32 page_size; | |
194 | u32 reserved[2]; | |
195 | }; | |
196 | ||
197 | struct mlx5_wqe_ctrl_seg { | |
198 | __be32 opmod_idx_opcode; | |
199 | __be32 qpn_ds; | |
200 | u8 signature; | |
201 | u8 rsvd[2]; | |
202 | u8 fm_ce_se; | |
203 | __be32 imm; | |
204 | }; | |
205 | ||
c1395a2a | 206 | #define MLX5_WQE_CTRL_DS_MASK 0x3f |
7bdf65d4 HE |
207 | #define MLX5_WQE_CTRL_QPN_MASK 0xffffff00 |
208 | #define MLX5_WQE_CTRL_QPN_SHIFT 8 | |
c1395a2a | 209 | #define MLX5_WQE_DS_UNITS 16 |
7bdf65d4 HE |
210 | #define MLX5_WQE_CTRL_OPCODE_MASK 0xff |
211 | #define MLX5_WQE_CTRL_WQE_INDEX_MASK 0x00ffff00 | |
212 | #define MLX5_WQE_CTRL_WQE_INDEX_SHIFT 8 | |
c1395a2a | 213 | |
e281682b SM |
214 | enum { |
215 | MLX5_ETH_WQE_L3_INNER_CSUM = 1 << 4, | |
216 | MLX5_ETH_WQE_L4_INNER_CSUM = 1 << 5, | |
217 | MLX5_ETH_WQE_L3_CSUM = 1 << 6, | |
218 | MLX5_ETH_WQE_L4_CSUM = 1 << 7, | |
219 | }; | |
220 | ||
221 | struct mlx5_wqe_eth_seg { | |
222 | u8 rsvd0[4]; | |
223 | u8 cs_flags; | |
224 | u8 rsvd1; | |
225 | __be16 mss; | |
226 | __be32 rsvd2; | |
227 | __be16 inline_hdr_sz; | |
228 | u8 inline_hdr_start[2]; | |
229 | }; | |
230 | ||
e126ba97 EC |
231 | struct mlx5_wqe_xrc_seg { |
232 | __be32 xrc_srqn; | |
233 | u8 rsvd[12]; | |
234 | }; | |
235 | ||
236 | struct mlx5_wqe_masked_atomic_seg { | |
237 | __be64 swap_add; | |
238 | __be64 compare; | |
239 | __be64 swap_add_mask; | |
240 | __be64 compare_mask; | |
241 | }; | |
242 | ||
243 | struct mlx5_av { | |
244 | union { | |
245 | struct { | |
246 | __be32 qkey; | |
247 | __be32 reserved; | |
248 | } qkey; | |
249 | __be64 dc_key; | |
250 | } key; | |
251 | __be32 dqp_dct; | |
252 | u8 stat_rate_sl; | |
253 | u8 fl_mlid; | |
2811ba51 AS |
254 | union { |
255 | __be16 rlid; | |
256 | __be16 udp_sport; | |
257 | }; | |
258 | u8 reserved0[4]; | |
259 | u8 rmac[6]; | |
e126ba97 EC |
260 | u8 tclass; |
261 | u8 hop_limit; | |
262 | __be32 grh_gid_fl; | |
263 | u8 rgid[16]; | |
264 | }; | |
265 | ||
266 | struct mlx5_wqe_datagram_seg { | |
267 | struct mlx5_av av; | |
268 | }; | |
269 | ||
270 | struct mlx5_wqe_raddr_seg { | |
271 | __be64 raddr; | |
272 | __be32 rkey; | |
273 | u32 reserved; | |
274 | }; | |
275 | ||
276 | struct mlx5_wqe_atomic_seg { | |
277 | __be64 swap_add; | |
278 | __be64 compare; | |
279 | }; | |
280 | ||
281 | struct mlx5_wqe_data_seg { | |
282 | __be32 byte_count; | |
283 | __be32 lkey; | |
284 | __be64 addr; | |
285 | }; | |
286 | ||
287 | struct mlx5_wqe_umr_ctrl_seg { | |
288 | u8 flags; | |
289 | u8 rsvd0[3]; | |
290 | __be16 klm_octowords; | |
291 | __be16 bsf_octowords; | |
292 | __be64 mkey_mask; | |
293 | u8 rsvd1[32]; | |
294 | }; | |
295 | ||
296 | struct mlx5_seg_set_psv { | |
297 | __be32 psv_num; | |
298 | __be16 syndrome; | |
299 | __be16 status; | |
300 | __be32 transient_sig; | |
301 | __be32 ref_tag; | |
302 | }; | |
303 | ||
304 | struct mlx5_seg_get_psv { | |
305 | u8 rsvd[19]; | |
306 | u8 num_psv; | |
307 | __be32 l_key; | |
308 | __be64 va; | |
309 | __be32 psv_index[4]; | |
310 | }; | |
311 | ||
312 | struct mlx5_seg_check_psv { | |
313 | u8 rsvd0[2]; | |
314 | __be16 err_coalescing_op; | |
315 | u8 rsvd1[2]; | |
316 | __be16 xport_err_op; | |
317 | u8 rsvd2[2]; | |
318 | __be16 xport_err_mask; | |
319 | u8 rsvd3[7]; | |
320 | u8 num_psv; | |
321 | __be32 l_key; | |
322 | __be64 va; | |
323 | __be32 psv_index[4]; | |
324 | }; | |
325 | ||
326 | struct mlx5_rwqe_sig { | |
327 | u8 rsvd0[4]; | |
328 | u8 signature; | |
329 | u8 rsvd1[11]; | |
330 | }; | |
331 | ||
332 | struct mlx5_wqe_signature_seg { | |
333 | u8 rsvd0[4]; | |
334 | u8 signature; | |
335 | u8 rsvd1[11]; | |
336 | }; | |
337 | ||
7bdf65d4 HE |
338 | #define MLX5_WQE_INLINE_SEG_BYTE_COUNT_MASK 0x3ff |
339 | ||
e126ba97 EC |
340 | struct mlx5_wqe_inline_seg { |
341 | __be32 byte_count; | |
342 | }; | |
343 | ||
142537f4 SG |
344 | enum mlx5_sig_type { |
345 | MLX5_DIF_CRC = 0x1, | |
346 | MLX5_DIF_IPCS = 0x2, | |
347 | }; | |
348 | ||
349 | struct mlx5_bsf_inl { | |
350 | __be16 vld_refresh; | |
351 | __be16 dif_apptag; | |
352 | __be32 dif_reftag; | |
353 | u8 sig_type; | |
354 | u8 rp_inv_seed; | |
355 | u8 rsvd[3]; | |
356 | u8 dif_inc_ref_guard_check; | |
357 | __be16 dif_app_bitmask_check; | |
358 | }; | |
359 | ||
e6631814 SG |
360 | struct mlx5_bsf { |
361 | struct mlx5_bsf_basic { | |
362 | u8 bsf_size_sbs; | |
363 | u8 check_byte_mask; | |
364 | union { | |
365 | u8 copy_byte_mask; | |
366 | u8 bs_selector; | |
367 | u8 rsvd_wflags; | |
368 | } wire; | |
369 | union { | |
370 | u8 bs_selector; | |
371 | u8 rsvd_mflags; | |
372 | } mem; | |
373 | __be32 raw_data_size; | |
374 | __be32 w_bfs_psv; | |
375 | __be32 m_bfs_psv; | |
376 | } basic; | |
377 | struct mlx5_bsf_ext { | |
378 | __be32 t_init_gen_pro_size; | |
379 | __be32 rsvd_epi_size; | |
380 | __be32 w_tfs_psv; | |
381 | __be32 m_tfs_psv; | |
382 | } ext; | |
142537f4 SG |
383 | struct mlx5_bsf_inl w_inl; |
384 | struct mlx5_bsf_inl m_inl; | |
e6631814 SG |
385 | }; |
386 | ||
387 | struct mlx5_klm { | |
388 | __be32 bcount; | |
389 | __be32 key; | |
390 | __be64 va; | |
391 | }; | |
392 | ||
393 | struct mlx5_stride_block_entry { | |
394 | __be16 stride; | |
395 | __be16 bcount; | |
396 | __be32 key; | |
397 | __be64 va; | |
398 | }; | |
399 | ||
400 | struct mlx5_stride_block_ctrl_seg { | |
401 | __be32 bcount_per_cycle; | |
402 | __be32 op; | |
403 | __be32 repeat_count; | |
404 | u16 rsvd; | |
405 | __be16 num_entries; | |
406 | }; | |
407 | ||
e420f0c0 HE |
408 | enum mlx5_pagefault_flags { |
409 | MLX5_PFAULT_REQUESTOR = 1 << 0, | |
410 | MLX5_PFAULT_WRITE = 1 << 1, | |
411 | MLX5_PFAULT_RDMA = 1 << 2, | |
412 | }; | |
413 | ||
414 | /* Contains the details of a pagefault. */ | |
415 | struct mlx5_pagefault { | |
416 | u32 bytes_committed; | |
417 | u8 event_subtype; | |
418 | enum mlx5_pagefault_flags flags; | |
419 | union { | |
420 | /* Initiator or send message responder pagefault details. */ | |
421 | struct { | |
422 | /* Received packet size, only valid for responders. */ | |
423 | u32 packet_size; | |
424 | /* | |
425 | * WQE index. Refers to either the send queue or | |
426 | * receive queue, according to event_subtype. | |
427 | */ | |
428 | u16 wqe_index; | |
429 | } wqe; | |
430 | /* RDMA responder pagefault details */ | |
431 | struct { | |
432 | u32 r_key; | |
433 | /* | |
434 | * Received packet size, minimal size page fault | |
435 | * resolution required for forward progress. | |
436 | */ | |
437 | u32 packet_size; | |
438 | u32 rdma_op_len; | |
439 | u64 rdma_va; | |
440 | } rdma; | |
441 | }; | |
442 | }; | |
443 | ||
e126ba97 | 444 | struct mlx5_core_qp { |
5903325a | 445 | struct mlx5_core_rsc_common common; /* must be first */ |
e126ba97 | 446 | void (*event) (struct mlx5_core_qp *, int); |
e420f0c0 | 447 | void (*pfault_handler)(struct mlx5_core_qp *, struct mlx5_pagefault *); |
e126ba97 | 448 | int qpn; |
e126ba97 EC |
449 | struct mlx5_rsc_debug *dbg; |
450 | int pid; | |
451 | }; | |
452 | ||
453 | struct mlx5_qp_path { | |
454 | u8 fl; | |
455 | u8 rsvd3; | |
456 | u8 free_ar; | |
457 | u8 pkey_index; | |
458 | u8 rsvd0; | |
459 | u8 grh_mlid; | |
460 | __be16 rlid; | |
461 | u8 ackto_lt; | |
462 | u8 mgid_index; | |
463 | u8 static_rate; | |
464 | u8 hop_limit; | |
465 | __be32 tclass_flowlabel; | |
2811ba51 AS |
466 | union { |
467 | u8 rgid[16]; | |
468 | u8 rip[16]; | |
469 | }; | |
470 | u8 f_dscp_ecn_prio; | |
471 | u8 ecn_dscp; | |
472 | __be16 udp_sport; | |
473 | u8 dci_cfi_prio_sl; | |
e126ba97 | 474 | u8 port; |
2811ba51 | 475 | u8 rmac[6]; |
e126ba97 EC |
476 | }; |
477 | ||
478 | struct mlx5_qp_context { | |
479 | __be32 flags; | |
480 | __be32 flags_pd; | |
481 | u8 mtu_msgmax; | |
482 | u8 rq_size_stride; | |
483 | __be16 sq_crq_size; | |
484 | __be32 qp_counter_set_usr_page; | |
485 | __be32 wire_qpn; | |
486 | __be32 log_pg_sz_remote_qpn; | |
487 | struct mlx5_qp_path pri_path; | |
488 | struct mlx5_qp_path alt_path; | |
489 | __be32 params1; | |
490 | u8 reserved2[4]; | |
491 | __be32 next_send_psn; | |
492 | __be32 cqn_send; | |
493 | u8 reserved3[8]; | |
494 | __be32 last_acked_psn; | |
495 | __be32 ssn; | |
496 | __be32 params2; | |
497 | __be32 rnr_nextrecvpsn; | |
498 | __be32 xrcd; | |
499 | __be32 cqn_recv; | |
500 | __be64 db_rec_addr; | |
501 | __be32 qkey; | |
502 | __be32 rq_type_srqn; | |
503 | __be32 rmsn; | |
504 | __be16 hw_sq_wqe_counter; | |
505 | __be16 sw_sq_wqe_counter; | |
506 | __be16 hw_rcyclic_byte_counter; | |
507 | __be16 hw_rq_counter; | |
508 | __be16 sw_rcyclic_byte_counter; | |
509 | __be16 sw_rq_counter; | |
510 | u8 rsvd0[5]; | |
511 | u8 cgs; | |
512 | u8 cs_req; | |
513 | u8 cs_res; | |
514 | __be64 dc_access_key; | |
515 | u8 rsvd1[24]; | |
516 | }; | |
517 | ||
518 | struct mlx5_create_qp_mbox_in { | |
519 | struct mlx5_inbox_hdr hdr; | |
520 | __be32 input_qpn; | |
521 | u8 rsvd0[4]; | |
522 | __be32 opt_param_mask; | |
523 | u8 rsvd1[4]; | |
524 | struct mlx5_qp_context ctx; | |
525 | u8 rsvd3[16]; | |
526 | __be64 pas[0]; | |
527 | }; | |
528 | ||
529 | struct mlx5_create_qp_mbox_out { | |
530 | struct mlx5_outbox_hdr hdr; | |
531 | __be32 qpn; | |
532 | u8 rsvd0[4]; | |
533 | }; | |
534 | ||
535 | struct mlx5_destroy_qp_mbox_in { | |
536 | struct mlx5_inbox_hdr hdr; | |
537 | __be32 qpn; | |
538 | u8 rsvd0[4]; | |
539 | }; | |
540 | ||
541 | struct mlx5_destroy_qp_mbox_out { | |
542 | struct mlx5_outbox_hdr hdr; | |
543 | u8 rsvd0[8]; | |
544 | }; | |
545 | ||
546 | struct mlx5_modify_qp_mbox_in { | |
547 | struct mlx5_inbox_hdr hdr; | |
548 | __be32 qpn; | |
549 | u8 rsvd1[4]; | |
550 | __be32 optparam; | |
551 | u8 rsvd0[4]; | |
552 | struct mlx5_qp_context ctx; | |
553 | }; | |
554 | ||
555 | struct mlx5_modify_qp_mbox_out { | |
556 | struct mlx5_outbox_hdr hdr; | |
557 | u8 rsvd0[8]; | |
558 | }; | |
559 | ||
560 | struct mlx5_query_qp_mbox_in { | |
561 | struct mlx5_inbox_hdr hdr; | |
562 | __be32 qpn; | |
563 | u8 rsvd[4]; | |
564 | }; | |
565 | ||
566 | struct mlx5_query_qp_mbox_out { | |
567 | struct mlx5_outbox_hdr hdr; | |
568 | u8 rsvd1[8]; | |
569 | __be32 optparam; | |
570 | u8 rsvd0[4]; | |
571 | struct mlx5_qp_context ctx; | |
572 | u8 rsvd2[16]; | |
573 | __be64 pas[0]; | |
574 | }; | |
575 | ||
576 | struct mlx5_conf_sqp_mbox_in { | |
577 | struct mlx5_inbox_hdr hdr; | |
578 | __be32 qpn; | |
579 | u8 rsvd[3]; | |
580 | u8 type; | |
581 | }; | |
582 | ||
583 | struct mlx5_conf_sqp_mbox_out { | |
584 | struct mlx5_outbox_hdr hdr; | |
585 | u8 rsvd[8]; | |
586 | }; | |
587 | ||
588 | struct mlx5_alloc_xrcd_mbox_in { | |
589 | struct mlx5_inbox_hdr hdr; | |
590 | u8 rsvd[8]; | |
591 | }; | |
592 | ||
593 | struct mlx5_alloc_xrcd_mbox_out { | |
594 | struct mlx5_outbox_hdr hdr; | |
595 | __be32 xrcdn; | |
596 | u8 rsvd[4]; | |
597 | }; | |
598 | ||
599 | struct mlx5_dealloc_xrcd_mbox_in { | |
600 | struct mlx5_inbox_hdr hdr; | |
601 | __be32 xrcdn; | |
602 | u8 rsvd[4]; | |
603 | }; | |
604 | ||
605 | struct mlx5_dealloc_xrcd_mbox_out { | |
606 | struct mlx5_outbox_hdr hdr; | |
607 | u8 rsvd[8]; | |
608 | }; | |
609 | ||
610 | static inline struct mlx5_core_qp *__mlx5_qp_lookup(struct mlx5_core_dev *dev, u32 qpn) | |
611 | { | |
612 | return radix_tree_lookup(&dev->priv.qp_table.tree, qpn); | |
613 | } | |
614 | ||
d5436ba0 SG |
615 | static inline struct mlx5_core_mr *__mlx5_mr_lookup(struct mlx5_core_dev *dev, u32 key) |
616 | { | |
617 | return radix_tree_lookup(&dev->priv.mr_table.tree, key); | |
618 | } | |
619 | ||
e420f0c0 HE |
620 | struct mlx5_page_fault_resume_mbox_in { |
621 | struct mlx5_inbox_hdr hdr; | |
622 | __be32 flags_qpn; | |
623 | u8 reserved[4]; | |
624 | }; | |
625 | ||
626 | struct mlx5_page_fault_resume_mbox_out { | |
627 | struct mlx5_outbox_hdr hdr; | |
628 | u8 rsvd[8]; | |
629 | }; | |
630 | ||
e126ba97 EC |
631 | int mlx5_core_create_qp(struct mlx5_core_dev *dev, |
632 | struct mlx5_core_qp *qp, | |
633 | struct mlx5_create_qp_mbox_in *in, | |
634 | int inlen); | |
635 | int mlx5_core_qp_modify(struct mlx5_core_dev *dev, enum mlx5_qp_state cur_state, | |
636 | enum mlx5_qp_state new_state, | |
637 | struct mlx5_modify_qp_mbox_in *in, int sqd_event, | |
638 | struct mlx5_core_qp *qp); | |
639 | int mlx5_core_destroy_qp(struct mlx5_core_dev *dev, | |
640 | struct mlx5_core_qp *qp); | |
641 | int mlx5_core_qp_query(struct mlx5_core_dev *dev, struct mlx5_core_qp *qp, | |
642 | struct mlx5_query_qp_mbox_out *out, int outlen); | |
643 | ||
644 | int mlx5_core_xrcd_alloc(struct mlx5_core_dev *dev, u32 *xrcdn); | |
645 | int mlx5_core_xrcd_dealloc(struct mlx5_core_dev *dev, u32 xrcdn); | |
646 | void mlx5_init_qp_table(struct mlx5_core_dev *dev); | |
647 | void mlx5_cleanup_qp_table(struct mlx5_core_dev *dev); | |
648 | int mlx5_debug_qp_add(struct mlx5_core_dev *dev, struct mlx5_core_qp *qp); | |
649 | void mlx5_debug_qp_remove(struct mlx5_core_dev *dev, struct mlx5_core_qp *qp); | |
e420f0c0 HE |
650 | #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING |
651 | int mlx5_core_page_fault_resume(struct mlx5_core_dev *dev, u32 qpn, | |
652 | u8 context, int error); | |
653 | #endif | |
e126ba97 | 654 | |
db81a5c3 EC |
655 | static inline const char *mlx5_qp_type_str(int type) |
656 | { | |
657 | switch (type) { | |
658 | case MLX5_QP_ST_RC: return "RC"; | |
659 | case MLX5_QP_ST_UC: return "C"; | |
660 | case MLX5_QP_ST_UD: return "UD"; | |
661 | case MLX5_QP_ST_XRC: return "XRC"; | |
662 | case MLX5_QP_ST_MLX: return "MLX"; | |
663 | case MLX5_QP_ST_QP0: return "QP0"; | |
664 | case MLX5_QP_ST_QP1: return "QP1"; | |
665 | case MLX5_QP_ST_RAW_ETHERTYPE: return "RAW_ETHERTYPE"; | |
666 | case MLX5_QP_ST_RAW_IPV6: return "RAW_IPV6"; | |
667 | case MLX5_QP_ST_SNIFFER: return "SNIFFER"; | |
668 | case MLX5_QP_ST_SYNC_UMR: return "SYNC_UMR"; | |
669 | case MLX5_QP_ST_PTP_1588: return "PTP_1588"; | |
670 | case MLX5_QP_ST_REG_UMR: return "REG_UMR"; | |
671 | default: return "Invalid transport type"; | |
672 | } | |
673 | } | |
674 | ||
675 | static inline const char *mlx5_qp_state_str(int state) | |
676 | { | |
677 | switch (state) { | |
678 | case MLX5_QP_STATE_RST: | |
679 | return "RST"; | |
680 | case MLX5_QP_STATE_INIT: | |
681 | return "INIT"; | |
682 | case MLX5_QP_STATE_RTR: | |
683 | return "RTR"; | |
684 | case MLX5_QP_STATE_RTS: | |
685 | return "RTS"; | |
686 | case MLX5_QP_STATE_SQER: | |
687 | return "SQER"; | |
688 | case MLX5_QP_STATE_SQD: | |
689 | return "SQD"; | |
690 | case MLX5_QP_STATE_ERR: | |
691 | return "ERR"; | |
692 | case MLX5_QP_STATE_SQ_DRAINING: | |
693 | return "SQ_DRAINING"; | |
694 | case MLX5_QP_STATE_SUSPENDED: | |
695 | return "SUSPENDED"; | |
696 | default: return "Invalid QP state"; | |
697 | } | |
698 | } | |
699 | ||
e126ba97 | 700 | #endif /* MLX5_QP_H */ |