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Commit | Line | Data |
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d2912cb1 | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
1da177e4 LT |
2 | /* |
3 | * linux/include/linux/mmc/host.h | |
4 | * | |
1da177e4 LT |
5 | * Host driver specific definitions. |
6 | */ | |
7 | #ifndef LINUX_MMC_HOST_H | |
8 | #define LINUX_MMC_HOST_H | |
9 | ||
d43c36dc | 10 | #include <linux/sched.h> |
313162d0 | 11 | #include <linux/device.h> |
1b676f70 | 12 | #include <linux/fault-inject.h> |
af8350c7 | 13 | |
aaac1b47 | 14 | #include <linux/mmc/core.h> |
cdc99179 | 15 | #include <linux/mmc/card.h> |
da68c4eb | 16 | #include <linux/mmc/pm.h> |
6335d683 | 17 | #include <linux/dma-direction.h> |
1da177e4 LT |
18 | |
19 | struct mmc_ios { | |
20 | unsigned int clock; /* clock rate */ | |
21 | unsigned short vdd; | |
6d796c68 | 22 | unsigned int power_delay_ms; /* waiting for stable power */ |
1da177e4 | 23 | |
4be34c99 | 24 | /* vdd stores the bit number of the selected voltage range from below. */ |
1da177e4 LT |
25 | |
26 | unsigned char bus_mode; /* command output mode */ | |
27 | ||
28 | #define MMC_BUSMODE_OPENDRAIN 1 | |
29 | #define MMC_BUSMODE_PUSHPULL 2 | |
30 | ||
865e9f13 PO |
31 | unsigned char chip_select; /* SPI chip select */ |
32 | ||
33 | #define MMC_CS_DONTCARE 0 | |
34 | #define MMC_CS_HIGH 1 | |
35 | #define MMC_CS_LOW 2 | |
36 | ||
1da177e4 LT |
37 | unsigned char power_mode; /* power supply mode */ |
38 | ||
39 | #define MMC_POWER_OFF 0 | |
40 | #define MMC_POWER_UP 1 | |
41 | #define MMC_POWER_ON 2 | |
8af465db | 42 | #define MMC_POWER_UNDEFINED 3 |
f218278a PO |
43 | |
44 | unsigned char bus_width; /* data bus width */ | |
45 | ||
46 | #define MMC_BUS_WIDTH_1 0 | |
47 | #define MMC_BUS_WIDTH_4 2 | |
b30f8af3 | 48 | #define MMC_BUS_WIDTH_8 3 |
cd9277c0 PO |
49 | |
50 | unsigned char timing; /* timing specification used */ | |
51 | ||
52 | #define MMC_TIMING_LEGACY 0 | |
53 | #define MMC_TIMING_MMC_HS 1 | |
54 | #define MMC_TIMING_SD_HS 2 | |
ed9dbb6e KL |
55 | #define MMC_TIMING_UHS_SDR12 3 |
56 | #define MMC_TIMING_UHS_SDR25 4 | |
57 | #define MMC_TIMING_UHS_SDR50 5 | |
58 | #define MMC_TIMING_UHS_SDR104 6 | |
59 | #define MMC_TIMING_UHS_DDR50 7 | |
79f7ae7c SJ |
60 | #define MMC_TIMING_MMC_DDR52 8 |
61 | #define MMC_TIMING_MMC_HS200 9 | |
0a5b6438 | 62 | #define MMC_TIMING_MMC_HS400 10 |
ead49373 UH |
63 | #define MMC_TIMING_SD_EXP 11 |
64 | #define MMC_TIMING_SD_EXP_1_2V 12 | |
0f8d8ea6 | 65 | |
f2119df6 AN |
66 | unsigned char signal_voltage; /* signalling voltage (1.8V or 3.3V) */ |
67 | ||
68 | #define MMC_SIGNAL_VOLTAGE_330 0 | |
69 | #define MMC_SIGNAL_VOLTAGE_180 1 | |
4c4cb171 | 70 | #define MMC_SIGNAL_VOLTAGE_120 2 |
d6d50a15 AN |
71 | |
72 | unsigned char drv_type; /* driver type (A, B, C, D) */ | |
73 | ||
74 | #define MMC_SET_DRIVER_TYPE_B 0 | |
75 | #define MMC_SET_DRIVER_TYPE_A 1 | |
76 | #define MMC_SET_DRIVER_TYPE_C 2 | |
77 | #define MMC_SET_DRIVER_TYPE_D 3 | |
81ac2af6 SL |
78 | |
79 | bool enhanced_strobe; /* hs400es selection */ | |
1da177e4 LT |
80 | }; |
81 | ||
8da00734 UH |
82 | struct mmc_host; |
83 | ||
1da177e4 | 84 | struct mmc_host_ops { |
aa8b683a PF |
85 | /* |
86 | * It is optional for the host to implement pre_req and post_req in | |
87 | * order to support double buffering of requests (prepare one | |
88 | * request while another request is active). | |
7c8a2829 PF |
89 | * pre_req() must always be followed by a post_req(). |
90 | * To undo a call made to pre_req(), call post_req() with | |
91 | * a nonzero err condition. | |
aa8b683a PF |
92 | */ |
93 | void (*post_req)(struct mmc_host *host, struct mmc_request *req, | |
94 | int err); | |
d3c6aac3 | 95 | void (*pre_req)(struct mmc_host *host, struct mmc_request *req); |
1da177e4 | 96 | void (*request)(struct mmc_host *host, struct mmc_request *req); |
6db96e58 BW |
97 | /* Submit one request to host in atomic context. */ |
98 | int (*request_atomic)(struct mmc_host *host, | |
99 | struct mmc_request *req); | |
93b6911a WS |
100 | |
101 | /* | |
102 | * Avoid calling the next three functions too often or in a "fast | |
103 | * path", since underlaying controller might implement them in an | |
104 | * expensive and/or slow way. Also note that these functions might | |
105 | * sleep, so don't call them in the atomic contexts! | |
106 | */ | |
107 | ||
108 | /* | |
109 | * Notes to the set_ios callback: | |
110 | * ios->clock might be 0. For some controllers, setting 0Hz | |
111 | * as any other frequency works. However, some controllers | |
112 | * explicitly need to disable the clock. Otherwise e.g. voltage | |
113 | * switching might fail because the SDCLK is not really quiet. | |
114 | */ | |
115 | void (*set_ios)(struct mmc_host *host, struct mmc_ios *ios); | |
116 | ||
28f52482 | 117 | /* |
08f80bb5 AV |
118 | * Return values for the get_ro callback should be: |
119 | * 0 for a read/write card | |
120 | * 1 for a read-only card | |
121 | * -ENOSYS when not supported (equal to NULL callback) | |
122 | * or a negative errno value when something bad happened | |
93b6911a WS |
123 | */ |
124 | int (*get_ro)(struct mmc_host *host); | |
125 | ||
126 | /* | |
ee63a7d2 | 127 | * Return values for the get_cd callback should be: |
08f80bb5 AV |
128 | * 0 for a absent card |
129 | * 1 for a present card | |
130 | * -ENOSYS when not supported (equal to NULL callback) | |
131 | * or a negative errno value when something bad happened | |
28f52482 | 132 | */ |
28f52482 AV |
133 | int (*get_cd)(struct mmc_host *host); |
134 | ||
17b759af | 135 | void (*enable_sdio_irq)(struct mmc_host *host, int enable); |
2c32dbbb | 136 | /* Mandatory callback when using MMC_CAP2_SDIO_IRQ_NOTHREAD. */ |
68269660 | 137 | void (*ack_sdio_irq)(struct mmc_host *host); |
3fcb027d DM |
138 | |
139 | /* optional callback for HC quirks */ | |
140 | void (*init_card)(struct mmc_host *host, struct mmc_card *card); | |
f2119df6 AN |
141 | |
142 | int (*start_signal_voltage_switch)(struct mmc_host *host, struct mmc_ios *ios); | |
a4924c71 | 143 | |
d887874e JR |
144 | /* Check if the card is pulling dat[0:3] low */ |
145 | int (*card_busy)(struct mmc_host *host); | |
146 | ||
a4924c71 G |
147 | /* The tuning command opcode value is different for SD and eMMC cards */ |
148 | int (*execute_tuning)(struct mmc_host *host, u32 opcode); | |
0a5b6438 SJ |
149 | |
150 | /* Prepare HS400 target operating frequency depending host driver */ | |
151 | int (*prepare_hs400_tuning)(struct mmc_host *host, struct mmc_ios *ios); | |
ba6c7ac3 | 152 | |
cc14eec0 YZ |
153 | /* Prepare switch to DDR during the HS400 init sequence */ |
154 | int (*hs400_prepare_ddr)(struct mmc_host *host); | |
155 | ||
ba6c7ac3 SH |
156 | /* Prepare for switching from HS400 to HS200 */ |
157 | void (*hs400_downgrade)(struct mmc_host *host); | |
158 | ||
159 | /* Complete selection of HS400 */ | |
160 | void (*hs400_complete)(struct mmc_host *host); | |
161 | ||
81ac2af6 SL |
162 | /* Prepare enhanced strobe depending host driver */ |
163 | void (*hs400_enhanced_strobe)(struct mmc_host *host, | |
164 | struct mmc_ios *ios); | |
f168359e AH |
165 | int (*select_drive_strength)(struct mmc_card *card, |
166 | unsigned int max_dtr, int host_drv, | |
b4f30a17 | 167 | int card_drv, int *drv_type); |
69327941 | 168 | /* Reset the eMMC card via RST_n */ |
b2499518 | 169 | void (*hw_reset)(struct mmc_host *host); |
9f1fb60a | 170 | void (*card_event)(struct mmc_host *host); |
2e47e842 KM |
171 | |
172 | /* | |
173 | * Optional callback to support controllers with HW issues for multiple | |
174 | * I/O. Returns the number of supported blocks for the request. | |
175 | */ | |
176 | int (*multi_io_quirk)(struct mmc_card *card, | |
177 | unsigned int direction, int blk_size); | |
ead49373 UH |
178 | |
179 | /* Initialize an SD express card, mandatory for MMC_CAP2_SD_EXP. */ | |
180 | int (*init_sd_express)(struct mmc_host *host, struct mmc_ios *ios); | |
1da177e4 LT |
181 | }; |
182 | ||
d3bf68ae AH |
183 | struct mmc_cqe_ops { |
184 | /* Allocate resources, and make the CQE operational */ | |
185 | int (*cqe_enable)(struct mmc_host *host, struct mmc_card *card); | |
186 | /* Free resources, and make the CQE non-operational */ | |
187 | void (*cqe_disable)(struct mmc_host *host); | |
188 | /* | |
189 | * Issue a read, write or DCMD request to the CQE. Also deal with the | |
190 | * effect of ->cqe_off(). | |
191 | */ | |
192 | int (*cqe_request)(struct mmc_host *host, struct mmc_request *mrq); | |
193 | /* Free resources (e.g. DMA mapping) associated with the request */ | |
194 | void (*cqe_post_req)(struct mmc_host *host, struct mmc_request *mrq); | |
195 | /* | |
196 | * Prepare the CQE and host controller to accept non-CQ commands. There | |
197 | * is no corresponding ->cqe_on(), instead ->cqe_request() is required | |
198 | * to deal with that. | |
199 | */ | |
200 | void (*cqe_off)(struct mmc_host *host); | |
201 | /* | |
202 | * Wait for all CQE tasks to complete. Return an error if recovery | |
203 | * becomes necessary. | |
204 | */ | |
205 | int (*cqe_wait_for_idle)(struct mmc_host *host); | |
206 | /* | |
207 | * Notify CQE that a request has timed out. Return false if the request | |
208 | * completed or true if a timeout happened in which case indicate if | |
209 | * recovery is needed. | |
210 | */ | |
211 | bool (*cqe_timeout)(struct mmc_host *host, struct mmc_request *mrq, | |
212 | bool *recovery_needed); | |
213 | /* | |
214 | * Stop all CQE activity and prepare the CQE and host controller to | |
215 | * accept recovery commands. | |
216 | */ | |
217 | void (*cqe_recovery_start)(struct mmc_host *host); | |
218 | /* | |
219 | * Clear the queue and call mmc_cqe_request_done() on all requests. | |
220 | * Requests that errored will have the error set on the mmc_request | |
221 | * (data->error or cmd->error for DCMD). Requests that did not error | |
222 | * will have zero data bytes transferred. | |
223 | */ | |
224 | void (*cqe_recovery_finish)(struct mmc_host *host); | |
225 | }; | |
226 | ||
aa8b683a PF |
227 | struct mmc_async_req { |
228 | /* active mmc request */ | |
229 | struct mmc_request *mrq; | |
230 | /* | |
231 | * Check error status of completed mmc request. | |
232 | * Returns 0 if success otherwise non zero. | |
233 | */ | |
8e8b3f51 | 234 | enum mmc_blk_status (*err_check)(struct mmc_card *, struct mmc_async_req *); |
aa8b683a PF |
235 | }; |
236 | ||
27410ee7 GL |
237 | /** |
238 | * struct mmc_slot - MMC slot functions | |
239 | * | |
240 | * @cd_irq: MMC/SD-card slot hotplug detection IRQ or -EINVAL | |
241 | * @handler_priv: MMC/SD-card slot context | |
242 | * | |
243 | * Some MMC/SD host controllers implement slot-functions like card and | |
244 | * write-protect detection natively. However, a large number of controllers | |
245 | * leave these functions to the CPU. This struct provides a hook to attach | |
246 | * such slot-function drivers. | |
247 | */ | |
248 | struct mmc_slot { | |
249 | int cd_irq; | |
03dbaa04 | 250 | bool cd_wake_enabled; |
b67e1980 GL |
251 | void *handler_priv; |
252 | }; | |
253 | ||
2220eedf KD |
254 | /** |
255 | * mmc_context_info - synchronization details for mmc context | |
256 | * @is_done_rcv wake up reason was done request | |
257 | * @is_new_req wake up reason was new request | |
258 | * @is_waiting_last_req mmc context waiting for single running request | |
259 | * @wait wait queue | |
2220eedf KD |
260 | */ |
261 | struct mmc_context_info { | |
262 | bool is_done_rcv; | |
263 | bool is_new_req; | |
264 | bool is_waiting_last_req; | |
265 | wait_queue_head_t wait; | |
2220eedf KD |
266 | }; |
267 | ||
e137788d | 268 | struct regulator; |
3aa8793f | 269 | struct mmc_pwrseq; |
e137788d GL |
270 | |
271 | struct mmc_supply { | |
272 | struct regulator *vmmc; /* Card power supply */ | |
273 | struct regulator *vqmmc; /* Optional Vccq supply */ | |
274 | }; | |
275 | ||
6c0cedd1 AH |
276 | struct mmc_ctx { |
277 | struct task_struct *task; | |
278 | }; | |
279 | ||
1da177e4 | 280 | struct mmc_host { |
fcaf71fd GKH |
281 | struct device *parent; |
282 | struct device class_dev; | |
dce77377 | 283 | int index; |
f57b225e | 284 | const struct mmc_host_ops *ops; |
3aa8793f | 285 | struct mmc_pwrseq *pwrseq; |
1da177e4 LT |
286 | unsigned int f_min; |
287 | unsigned int f_max; | |
88ae8b86 | 288 | unsigned int f_init; |
1da177e4 | 289 | u32 ocr_avail; |
8f230f45 TI |
290 | u32 ocr_avail_sdio; /* SDIO-specific OCR */ |
291 | u32 ocr_avail_sd; /* SD-specific OCR */ | |
292 | u32 ocr_avail_mmc; /* MMC-specific OCR */ | |
b52fb259 | 293 | struct wakeup_source *ws; /* Enable consume of uevents */ |
55c4665e AL |
294 | u32 max_current_330; |
295 | u32 max_current_300; | |
296 | u32 max_current_180; | |
1da177e4 | 297 | |
55556da0 | 298 | #define MMC_VDD_165_195 0x00000080 /* VDD voltage 1.65 - 1.95 */ |
f74d132c PO |
299 | #define MMC_VDD_20_21 0x00000100 /* VDD voltage 2.0 ~ 2.1 */ |
300 | #define MMC_VDD_21_22 0x00000200 /* VDD voltage 2.1 ~ 2.2 */ | |
301 | #define MMC_VDD_22_23 0x00000400 /* VDD voltage 2.2 ~ 2.3 */ | |
302 | #define MMC_VDD_23_24 0x00000800 /* VDD voltage 2.3 ~ 2.4 */ | |
303 | #define MMC_VDD_24_25 0x00001000 /* VDD voltage 2.4 ~ 2.5 */ | |
304 | #define MMC_VDD_25_26 0x00002000 /* VDD voltage 2.5 ~ 2.6 */ | |
305 | #define MMC_VDD_26_27 0x00004000 /* VDD voltage 2.6 ~ 2.7 */ | |
306 | #define MMC_VDD_27_28 0x00008000 /* VDD voltage 2.7 ~ 2.8 */ | |
307 | #define MMC_VDD_28_29 0x00010000 /* VDD voltage 2.8 ~ 2.9 */ | |
308 | #define MMC_VDD_29_30 0x00020000 /* VDD voltage 2.9 ~ 3.0 */ | |
309 | #define MMC_VDD_30_31 0x00040000 /* VDD voltage 3.0 ~ 3.1 */ | |
310 | #define MMC_VDD_31_32 0x00080000 /* VDD voltage 3.1 ~ 3.2 */ | |
311 | #define MMC_VDD_32_33 0x00100000 /* VDD voltage 3.2 ~ 3.3 */ | |
312 | #define MMC_VDD_33_34 0x00200000 /* VDD voltage 3.3 ~ 3.4 */ | |
313 | #define MMC_VDD_34_35 0x00400000 /* VDD voltage 3.4 ~ 3.5 */ | |
314 | #define MMC_VDD_35_36 0x00800000 /* VDD voltage 3.5 ~ 3.6 */ | |
315 | ||
5f1a4dd0 | 316 | u32 caps; /* Host capabilities */ |
f218278a PO |
317 | |
318 | #define MMC_CAP_4_BIT_DATA (1 << 0) /* Can the host do 4 bit transfers */ | |
23af6039 PO |
319 | #define MMC_CAP_MMC_HIGHSPEED (1 << 1) /* Can do MMC high-speed timing */ |
320 | #define MMC_CAP_SD_HIGHSPEED (1 << 2) /* Can do SD high-speed timing */ | |
321 | #define MMC_CAP_SDIO_IRQ (1 << 3) /* Can signal pending SDIO IRQs */ | |
322 | #define MMC_CAP_SPI (1 << 4) /* Talks only SPI protocols */ | |
323 | #define MMC_CAP_NEEDS_POLL (1 << 5) /* Needs polling for card-detection */ | |
b30f8af3 | 324 | #define MMC_CAP_8_BIT_DATA (1 << 6) /* Can the host do 8 bit transfers */ |
c4d770d7 | 325 | #define MMC_CAP_AGGRESSIVE_PM (1 << 7) /* Suspend (e)MMC/SD at idle */ |
9feae246 | 326 | #define MMC_CAP_NONREMOVABLE (1 << 8) /* Nonremovable e.g. eMMC */ |
b1ebe384 | 327 | #define MMC_CAP_WAIT_WHILE_BUSY (1 << 9) /* Waits while card is busy */ |
20f921bb UH |
328 | #define MMC_CAP_3_3V_DDR (1 << 11) /* Host supports eMMC DDR 3.3V */ |
329 | #define MMC_CAP_1_8V_DDR (1 << 12) /* Host supports eMMC DDR 1.8V */ | |
330 | #define MMC_CAP_1_2V_DDR (1 << 13) /* Host supports eMMC DDR 1.2V */ | |
8ee5fc0e FA |
331 | #define MMC_CAP_DDR (MMC_CAP_3_3V_DDR | MMC_CAP_1_8V_DDR | \ |
332 | MMC_CAP_1_2V_DDR) | |
20f921bb UH |
333 | #define MMC_CAP_POWER_OFF_CARD (1 << 14) /* Can power off after boot */ |
334 | #define MMC_CAP_BUS_WIDTH_TEST (1 << 15) /* CMD14/CMD19 bus width ok */ | |
335 | #define MMC_CAP_UHS_SDR12 (1 << 16) /* Host supports UHS SDR12 mode */ | |
336 | #define MMC_CAP_UHS_SDR25 (1 << 17) /* Host supports UHS SDR25 mode */ | |
337 | #define MMC_CAP_UHS_SDR50 (1 << 18) /* Host supports UHS SDR50 mode */ | |
338 | #define MMC_CAP_UHS_SDR104 (1 << 19) /* Host supports UHS SDR104 mode */ | |
339 | #define MMC_CAP_UHS_DDR50 (1 << 20) /* Host supports UHS DDR50 mode */ | |
c16bc9a7 KVA |
340 | #define MMC_CAP_UHS (MMC_CAP_UHS_SDR12 | MMC_CAP_UHS_SDR25 | \ |
341 | MMC_CAP_UHS_SDR50 | MMC_CAP_UHS_SDR104 | \ | |
342 | MMC_CAP_UHS_DDR50) | |
7d5ef512 | 343 | #define MMC_CAP_SYNC_RUNTIME_PM (1 << 21) /* Synced runtime PM suspends. */ |
1292e3ef | 344 | #define MMC_CAP_NEED_RSP_BUSY (1 << 22) /* Commands with R1B can't use R1. */ |
d6d50a15 AN |
345 | #define MMC_CAP_DRIVER_TYPE_A (1 << 23) /* Host supports Driver Type A */ |
346 | #define MMC_CAP_DRIVER_TYPE_C (1 << 24) /* Host supports Driver Type C */ | |
347 | #define MMC_CAP_DRIVER_TYPE_D (1 << 25) /* Host supports Driver Type D */ | |
10f21df4 | 348 | #define MMC_CAP_DONE_COMPLETE (1 << 27) /* RW reqs can be completed within mmc_request_done() */ |
03dbaa04 | 349 | #define MMC_CAP_CD_WAKE (1 << 28) /* Enable card detect wake */ |
5163af5a | 350 | #define MMC_CAP_CMD_DURING_TFR (1 << 29) /* Commands during data transfer */ |
d0c97cfb | 351 | #define MMC_CAP_CMD23 (1 << 30) /* CMD23 supported. */ |
69327941 | 352 | #define MMC_CAP_HW_RESET (1 << 31) /* Reset the eMMC card via RST_n */ |
f218278a | 353 | |
5f1a4dd0 | 354 | u32 caps2; /* More host capabilities */ |
f7c56ef2 AH |
355 | |
356 | #define MMC_CAP2_BOOTPART_NOACC (1 << 0) /* Boot partition no access */ | |
53275c21 | 357 | #define MMC_CAP2_FULL_PWR_CYCLE (1 << 2) /* Can do full power cycle */ |
ec02760b | 358 | #define MMC_CAP2_FULL_PWR_CYCLE_IN_SUSPEND (1 << 3) /* Can do full power cycle in suspend */ |
a4924c71 G |
359 | #define MMC_CAP2_HS200_1_8V_SDR (1 << 5) /* can support */ |
360 | #define MMC_CAP2_HS200_1_2V_SDR (1 << 6) /* can support */ | |
361 | #define MMC_CAP2_HS200 (MMC_CAP2_HS200_1_8V_SDR | \ | |
362 | MMC_CAP2_HS200_1_2V_SDR) | |
ead49373 UH |
363 | #define MMC_CAP2_SD_EXP (1 << 7) /* SD express via PCIe */ |
364 | #define MMC_CAP2_SD_EXP_1_2V (1 << 8) /* SD express 1.2V */ | |
5c08d7fa GL |
365 | #define MMC_CAP2_CD_ACTIVE_HIGH (1 << 10) /* Card-detect signal active high */ |
366 | #define MMC_CAP2_RO_ACTIVE_HIGH (1 << 11) /* Write-protect signal active high */ | |
0d3e3350 | 367 | #define MMC_CAP2_NO_PRESCAN_POWERUP (1 << 14) /* Don't power up before scan */ |
0a5b6438 SJ |
368 | #define MMC_CAP2_HS400_1_8V (1 << 15) /* Can support HS400 1.8V */ |
369 | #define MMC_CAP2_HS400_1_2V (1 << 16) /* Can support HS400 1.2V */ | |
370 | #define MMC_CAP2_HS400 (MMC_CAP2_HS400_1_8V | \ | |
371 | MMC_CAP2_HS400_1_2V) | |
c16bc9a7 | 372 | #define MMC_CAP2_HSX00_1_8V (MMC_CAP2_HS200_1_8V_SDR | MMC_CAP2_HS400_1_8V) |
549c0b18 | 373 | #define MMC_CAP2_HSX00_1_2V (MMC_CAP2_HS200_1_2V_SDR | MMC_CAP2_HS400_1_2V) |
bf3b5ec6 | 374 | #define MMC_CAP2_SDIO_IRQ_NOTHREAD (1 << 17) |
9f6e0bff | 375 | #define MMC_CAP2_NO_WRITE_PROTECT (1 << 18) /* No physical write protect pin, assume that card is always read-write */ |
100a606d | 376 | #define MMC_CAP2_NO_SDIO (1 << 19) /* Do not send SDIO commands during initialization */ |
ef29c0e2 | 377 | #define MMC_CAP2_HS400_ES (1 << 20) /* Host supports enhanced strobe */ |
1b8d79c5 | 378 | #define MMC_CAP2_NO_SD (1 << 21) /* Do not send SD commands during initialization */ |
a0c3b68c | 379 | #define MMC_CAP2_NO_MMC (1 << 22) /* Do not send (e)MMC commands during initialization */ |
d3bf68ae AH |
380 | #define MMC_CAP2_CQE (1 << 23) /* Has eMMC command queue engine */ |
381 | #define MMC_CAP2_CQE_DCMD (1 << 24) /* CQE can issue a direct command */ | |
247cfe53 | 382 | #define MMC_CAP2_AVOID_3_3V (1 << 25) /* Host must negotiate down from 3.3V */ |
427b0034 | 383 | #define MMC_CAP2_MERGE_CAPABLE (1 << 26) /* Host can merge a segment over the segment size */ |
f7c56ef2 | 384 | |
6186d06c WS |
385 | int fixed_drv_type; /* fixed driver type for non-removable media */ |
386 | ||
da68c4eb NP |
387 | mmc_pm_flag_t pm_caps; /* supported pm features */ |
388 | ||
1da177e4 LT |
389 | /* host specific block data */ |
390 | unsigned int max_seg_size; /* see blk_queue_max_segment_size */ | |
a36274e0 | 391 | unsigned short max_segs; /* see blk_queue_max_segments */ |
1da177e4 | 392 | unsigned short unused; |
55db890a | 393 | unsigned int max_req_size; /* maximum number of bytes in one req */ |
fe4a3c7a | 394 | unsigned int max_blk_size; /* maximum size of one mmc block */ |
55db890a | 395 | unsigned int max_blk_count; /* maximum number of blocks in one req */ |
68eb80e0 | 396 | unsigned int max_busy_timeout; /* max busy timeout in ms */ |
1da177e4 LT |
397 | |
398 | /* private data */ | |
7ea239d9 PO |
399 | spinlock_t lock; /* lock for claim and bus ops */ |
400 | ||
1da177e4 | 401 | struct mmc_ios ios; /* current io bus settings */ |
1da177e4 | 402 | |
97018580 DB |
403 | /* group bitfields together to minimize padding */ |
404 | unsigned int use_spi_crc:1; | |
405 | unsigned int claimed:1; /* host exclusively claimed */ | |
406 | unsigned int bus_dead:1; /* bus has been released */ | |
97a7d87e | 407 | unsigned int doing_init_tune:1; /* initial tuning in progress */ |
dfa13ebb AH |
408 | unsigned int can_retune:1; /* re-tuning can be used */ |
409 | unsigned int doing_retune:1; /* re-tuning in progress */ | |
410 | unsigned int retune_now:1; /* do re-tuning at next req */ | |
7ff27609 | 411 | unsigned int retune_paused:1; /* re-tuning is temporarily disabled */ |
c3d53d0d | 412 | unsigned int use_blk_mq:1; /* use blk-mq */ |
0a55f4ab | 413 | unsigned int retune_crc_disable:1; /* don't trigger retune upon crc */ |
38c38cb7 | 414 | unsigned int can_dma_map_merge:1; /* merging can be used */ |
97018580 | 415 | |
4c2ef25f | 416 | int rescan_disable; /* disable card detection */ |
3339d1e3 | 417 | int rescan_entered; /* used with nonremovable devices */ |
8ea926b2 | 418 | |
dfa13ebb AH |
419 | int need_retune; /* re-tuning is needed */ |
420 | int hold_retune; /* hold off re-tuning */ | |
421 | unsigned int retune_period; /* re-tuning period in secs */ | |
422 | struct timer_list retune_timer; /* for periodic re-tuning */ | |
423 | ||
fa372a51 MM |
424 | bool trigger_card_event; /* card_event necessary */ |
425 | ||
b855885e | 426 | struct mmc_card *card; /* device attached to this host */ |
1da177e4 LT |
427 | |
428 | wait_queue_head_t wq; | |
6c0cedd1 | 429 | struct mmc_ctx *claimer; /* context that has host claimed */ |
319a3f14 | 430 | int claim_cnt; /* "claim" nesting count */ |
6c0cedd1 | 431 | struct mmc_ctx default_ctx; /* default context */ |
f22ee4ed | 432 | |
c4028958 | 433 | struct delayed_work detect; |
d3049504 | 434 | int detect_change; /* card detect flag */ |
27410ee7 | 435 | struct mmc_slot slot; |
01357dca | 436 | |
7ea239d9 PO |
437 | const struct mmc_bus_ops *bus_ops; /* current bus driver */ |
438 | unsigned int bus_refs; /* reference counter */ | |
7ea239d9 | 439 | |
d1496c39 NP |
440 | unsigned int sdio_irqs; |
441 | struct task_struct *sdio_irq_thread; | |
68269660 | 442 | struct delayed_work sdio_irq_work; |
bbbc4c4d | 443 | bool sdio_irq_pending; |
d1496c39 NP |
444 | atomic_t sdio_irq_thread_abort; |
445 | ||
da68c4eb NP |
446 | mmc_pm_flag_t pm_flags; /* requested pm features */ |
447 | ||
af8350c7 | 448 | struct led_trigger *led; /* activity led */ |
af8350c7 | 449 | |
99fc5131 LW |
450 | #ifdef CONFIG_REGULATOR |
451 | bool regulator_enabled; /* regulator state */ | |
452 | #endif | |
e137788d | 453 | struct mmc_supply supply; |
99fc5131 | 454 | |
6edd8ee6 HS |
455 | struct dentry *debugfs_root; |
456 | ||
5163af5a AH |
457 | /* Ongoing data transfer that allows commands during transfer */ |
458 | struct mmc_request *ongoing_mrq; | |
459 | ||
1b676f70 PF |
460 | #ifdef CONFIG_FAIL_MMC_REQUEST |
461 | struct fault_attr fail_mmc_request; | |
462 | #endif | |
463 | ||
df16219f GC |
464 | unsigned int actual_clock; /* Actual HC clock rate */ |
465 | ||
eed222ac AL |
466 | unsigned int slotno; /* used for sdio acpi binding */ |
467 | ||
3d705d14 SH |
468 | int dsr_req; /* DSR value is valid */ |
469 | u32 dsr; /* optional driver stage (DSR) value */ | |
470 | ||
d3bf68ae AH |
471 | /* Command Queue Engine (CQE) support */ |
472 | const struct mmc_cqe_ops *cqe_ops; | |
473 | void *cqe_private; | |
474 | int cqe_qdepth; | |
475 | bool cqe_enabled; | |
476 | bool cqe_on; | |
477 | ||
511ce378 BW |
478 | /* Host Software Queue support */ |
479 | bool hsq_enabled; | |
480 | ||
1a91a36a | 481 | unsigned long private[] ____cacheline_aligned; |
1da177e4 LT |
482 | }; |
483 | ||
9e1bbc72 UH |
484 | struct device_node; |
485 | ||
8c9beb11 GL |
486 | struct mmc_host *mmc_alloc_host(int extra, struct device *); |
487 | int mmc_add_host(struct mmc_host *); | |
488 | void mmc_remove_host(struct mmc_host *); | |
489 | void mmc_free_host(struct mmc_host *); | |
ec0a7517 | 490 | int mmc_of_parse(struct mmc_host *host); |
9e1bbc72 | 491 | int mmc_of_parse_voltage(struct device_node *np, u32 *mask); |
1da177e4 | 492 | |
01357dca RK |
493 | static inline void *mmc_priv(struct mmc_host *host) |
494 | { | |
495 | return (void *)host->private; | |
496 | } | |
497 | ||
c58ccf2b LW |
498 | static inline struct mmc_host *mmc_from_priv(void *priv) |
499 | { | |
500 | return container_of(priv, struct mmc_host, private); | |
501 | } | |
502 | ||
97018580 DB |
503 | #define mmc_host_is_spi(host) ((host)->caps & MMC_CAP_SPI) |
504 | ||
fcaf71fd | 505 | #define mmc_dev(x) ((x)->parent) |
11354d03 | 506 | #define mmc_classdev(x) (&(x)->class_dev) |
d1b26863 | 507 | #define mmc_hostname(x) (dev_name(&(x)->class_dev)) |
1da177e4 | 508 | |
8c9beb11 GL |
509 | void mmc_detect_change(struct mmc_host *, unsigned long delay); |
510 | void mmc_request_done(struct mmc_host *, struct mmc_request *); | |
5163af5a | 511 | void mmc_command_done(struct mmc_host *host, struct mmc_request *mrq); |
1da177e4 | 512 | |
72a5af55 AH |
513 | void mmc_cqe_request_done(struct mmc_host *host, struct mmc_request *mrq); |
514 | ||
bd880b00 UH |
515 | /* |
516 | * May be called from host driver's system/runtime suspend/resume callbacks, | |
517 | * to know if SDIO IRQs has been claimed. | |
518 | */ | |
519 | static inline bool sdio_irq_claimed(struct mmc_host *host) | |
520 | { | |
521 | return host->sdio_irqs > 0; | |
522 | } | |
523 | ||
17b759af NP |
524 | static inline void mmc_signal_sdio_irq(struct mmc_host *host) |
525 | { | |
526 | host->ops->enable_sdio_irq(host, 0); | |
bbbc4c4d | 527 | host->sdio_irq_pending = true; |
f13e5b9f YL |
528 | if (host->sdio_irq_thread) |
529 | wake_up_process(host->sdio_irq_thread); | |
17b759af NP |
530 | } |
531 | ||
68269660 | 532 | void sdio_signal_irq(struct mmc_host *host); |
bf3b5ec6 | 533 | |
99fc5131 | 534 | #ifdef CONFIG_REGULATOR |
99fc5131 LW |
535 | int mmc_regulator_set_ocr(struct mmc_host *mmc, |
536 | struct regulator *supply, | |
537 | unsigned short vdd_bit); | |
2086f801 | 538 | int mmc_regulator_set_vqmmc(struct mmc_host *mmc, struct mmc_ios *ios); |
99fc5131 | 539 | #else |
99fc5131 LW |
540 | static inline int mmc_regulator_set_ocr(struct mmc_host *mmc, |
541 | struct regulator *supply, | |
542 | unsigned short vdd_bit) | |
543 | { | |
544 | return 0; | |
545 | } | |
2086f801 DA |
546 | |
547 | static inline int mmc_regulator_set_vqmmc(struct mmc_host *mmc, | |
548 | struct mmc_ios *ios) | |
549 | { | |
550 | return -EINVAL; | |
551 | } | |
99fc5131 | 552 | #endif |
5c13941a | 553 | |
4d1f52f9 TK |
554 | int mmc_regulator_get_supply(struct mmc_host *mmc); |
555 | ||
71d7d3d1 MF |
556 | static inline int mmc_card_is_removable(struct mmc_host *host) |
557 | { | |
2501c917 | 558 | return !(host->caps & MMC_CAP_NONREMOVABLE); |
71d7d3d1 MF |
559 | } |
560 | ||
a5e9425d | 561 | static inline int mmc_card_keep_power(struct mmc_host *host) |
080bc977 OBC |
562 | { |
563 | return host->pm_flags & MMC_PM_KEEP_POWER; | |
564 | } | |
565 | ||
6b93d01f OBC |
566 | static inline int mmc_card_wake_sdio_irq(struct mmc_host *host) |
567 | { | |
568 | return host->pm_flags & MMC_PM_WAKE_SDIO_IRQ; | |
569 | } | |
d0c97cfb | 570 | |
5857b29b | 571 | /* TODO: Move to private header */ |
cdc99179 SJ |
572 | static inline int mmc_card_hs(struct mmc_card *card) |
573 | { | |
574 | return card->host->ios.timing == MMC_TIMING_SD_HS || | |
575 | card->host->ios.timing == MMC_TIMING_MMC_HS; | |
576 | } | |
577 | ||
5857b29b | 578 | /* TODO: Move to private header */ |
cdc99179 SJ |
579 | static inline int mmc_card_uhs(struct mmc_card *card) |
580 | { | |
581 | return card->host->ios.timing >= MMC_TIMING_UHS_SDR12 && | |
582 | card->host->ios.timing <= MMC_TIMING_UHS_DDR50; | |
583 | } | |
584 | ||
dfa13ebb AH |
585 | void mmc_retune_timer_stop(struct mmc_host *host); |
586 | ||
587 | static inline void mmc_retune_needed(struct mmc_host *host) | |
588 | { | |
589 | if (host->can_retune) | |
590 | host->need_retune = 1; | |
591 | } | |
592 | ||
c820af5f SH |
593 | static inline bool mmc_can_retune(struct mmc_host *host) |
594 | { | |
595 | return host->can_retune == 1; | |
596 | } | |
597 | ||
cbf6d82c NS |
598 | static inline bool mmc_doing_retune(struct mmc_host *host) |
599 | { | |
600 | return host->doing_retune == 1; | |
601 | } | |
602 | ||
97a7d87e WS |
603 | static inline bool mmc_doing_tune(struct mmc_host *host) |
604 | { | |
605 | return host->doing_retune == 1 || host->doing_init_tune == 1; | |
606 | } | |
607 | ||
6335d683 HK |
608 | static inline enum dma_data_direction mmc_get_dma_dir(struct mmc_data *data) |
609 | { | |
610 | return data->flags & MMC_DATA_WRITE ? DMA_TO_DEVICE : DMA_FROM_DEVICE; | |
611 | } | |
612 | ||
9e1bbc72 UH |
613 | int mmc_send_tuning(struct mmc_host *host, u32 opcode, int *cmd_error); |
614 | int mmc_abort_tuning(struct mmc_host *host, u32 opcode); | |
7ff27609 | 615 | |
100e9186 | 616 | #endif /* LINUX_MMC_HOST_H */ |