]>
Commit | Line | Data |
---|---|---|
1da177e4 LT |
1 | /* |
2 | * Header for MultiMediaCard (MMC) | |
3 | * | |
4 | * Copyright 2002 Hewlett-Packard Company | |
5 | * | |
6 | * Use consistent with the GNU GPL is permitted, | |
7 | * provided that this copyright notice is | |
8 | * preserved in its entirety in all copies and derived works. | |
9 | * | |
10 | * HEWLETT-PACKARD COMPANY MAKES NO WARRANTIES, EXPRESSED OR IMPLIED, | |
11 | * AS TO THE USEFULNESS OR CORRECTNESS OF THIS CODE OR ITS | |
12 | * FITNESS FOR ANY PARTICULAR PURPOSE. | |
13 | * | |
14 | * Many thanks to Alessandro Rubini and Jonathan Corbet! | |
15 | * | |
16 | * Based strongly on code by: | |
17 | * | |
18 | * Author: Yong-iL Joh <tolkien@mizi.com> | |
1da177e4 LT |
19 | * |
20 | * Author: Andrew Christian | |
21 | * 15 May 2002 | |
22 | */ | |
23 | ||
da7fbe58 PO |
24 | #ifndef MMC_MMC_H |
25 | #define MMC_MMC_H | |
1da177e4 | 26 | |
bce40a36 | 27 | /* Standard MMC commands (4.1) type argument response */ |
1da177e4 | 28 | /* class 1 */ |
97018580 | 29 | #define MMC_GO_IDLE_STATE 0 /* bc */ |
1da177e4 LT |
30 | #define MMC_SEND_OP_COND 1 /* bcr [31:0] OCR R3 */ |
31 | #define MMC_ALL_SEND_CID 2 /* bcr R2 */ | |
32 | #define MMC_SET_RELATIVE_ADDR 3 /* ac [31:16] RCA R1 */ | |
33 | #define MMC_SET_DSR 4 /* bc [31:16] RCA */ | |
b1ebe384 | 34 | #define MMC_SLEEP_AWAKE 5 /* ac [31:16] RCA 15:flg R1b */ |
bce40a36 | 35 | #define MMC_SWITCH 6 /* ac [31:0] See below R1b */ |
1da177e4 | 36 | #define MMC_SELECT_CARD 7 /* ac [31:16] RCA R1 */ |
bce40a36 | 37 | #define MMC_SEND_EXT_CSD 8 /* adtc R1 */ |
1da177e4 LT |
38 | #define MMC_SEND_CSD 9 /* ac [31:16] RCA R2 */ |
39 | #define MMC_SEND_CID 10 /* ac [31:16] RCA R2 */ | |
40 | #define MMC_READ_DAT_UNTIL_STOP 11 /* adtc [31:0] dadr R1 */ | |
41 | #define MMC_STOP_TRANSMISSION 12 /* ac R1b */ | |
97018580 | 42 | #define MMC_SEND_STATUS 13 /* ac [31:16] RCA R1 */ |
22113efd | 43 | #define MMC_BUS_TEST_R 14 /* adtc R1 */ |
1da177e4 | 44 | #define MMC_GO_INACTIVE_STATE 15 /* ac [31:16] RCA */ |
22113efd | 45 | #define MMC_BUS_TEST_W 19 /* adtc R1 */ |
97018580 DB |
46 | #define MMC_SPI_READ_OCR 58 /* spi spi_R3 */ |
47 | #define MMC_SPI_CRC_ON_OFF 59 /* spi [0:0] flag spi_R1 */ | |
1da177e4 LT |
48 | |
49 | /* class 2 */ | |
50 | #define MMC_SET_BLOCKLEN 16 /* ac [31:0] block len R1 */ | |
51 | #define MMC_READ_SINGLE_BLOCK 17 /* adtc [31:0] data addr R1 */ | |
52 | #define MMC_READ_MULTIPLE_BLOCK 18 /* adtc [31:0] data addr R1 */ | |
53 | ||
54 | /* class 3 */ | |
55 | #define MMC_WRITE_DAT_UNTIL_STOP 20 /* adtc [31:0] data addr R1 */ | |
56 | ||
57 | /* class 4 */ | |
58 | #define MMC_SET_BLOCK_COUNT 23 /* adtc [31:0] data addr R1 */ | |
59 | #define MMC_WRITE_BLOCK 24 /* adtc [31:0] data addr R1 */ | |
60 | #define MMC_WRITE_MULTIPLE_BLOCK 25 /* adtc R1 */ | |
61 | #define MMC_PROGRAM_CID 26 /* adtc R1 */ | |
62 | #define MMC_PROGRAM_CSD 27 /* adtc R1 */ | |
63 | ||
64 | /* class 6 */ | |
65 | #define MMC_SET_WRITE_PROT 28 /* ac [31:0] data addr R1b */ | |
66 | #define MMC_CLR_WRITE_PROT 29 /* ac [31:0] data addr R1b */ | |
67 | #define MMC_SEND_WRITE_PROT 30 /* adtc [31:0] wpdata addr R1 */ | |
68 | ||
69 | /* class 5 */ | |
70 | #define MMC_ERASE_GROUP_START 35 /* ac [31:0] data addr R1 */ | |
71 | #define MMC_ERASE_GROUP_END 36 /* ac [31:0] data addr R1 */ | |
24117def | 72 | #define MMC_ERASE 38 /* ac R1b */ |
1da177e4 LT |
73 | |
74 | /* class 9 */ | |
75 | #define MMC_FAST_IO 39 /* ac <Complex> R4 */ | |
76 | #define MMC_GO_IRQ_STATE 40 /* bcr R5 */ | |
77 | ||
78 | /* class 7 */ | |
79 | #define MMC_LOCK_UNLOCK 42 /* adtc R1b */ | |
80 | ||
81 | /* class 8 */ | |
82 | #define MMC_APP_CMD 55 /* ac [31:16] RCA R1 */ | |
24117def | 83 | #define MMC_GEN_CMD 56 /* adtc [0] RD/WR R1 */ |
1da177e4 | 84 | |
bce40a36 PL |
85 | /* |
86 | * MMC_SWITCH argument format: | |
87 | * | |
88 | * [31:26] Always 0 | |
89 | * [25:24] Access Mode | |
90 | * [23:16] Location of target Byte in EXT_CSD | |
91 | * [15:08] Value Byte | |
92 | * [07:03] Always 0 | |
93 | * [02:00] Command Set | |
94 | */ | |
95 | ||
1da177e4 | 96 | /* |
97018580 | 97 | MMC status in R1, for native mode (SPI bits are different) |
1da177e4 | 98 | Type |
97018580 | 99 | e : error bit |
1da177e4 LT |
100 | s : status bit |
101 | r : detected and set for the actual command response | |
102 | x : detected and set during command execution. the host must poll | |
103 | the card by sending status command in order to read these bits. | |
104 | Clear condition | |
97018580 | 105 | a : according to the card state |
1da177e4 LT |
106 | b : always related to the previous command. Reception of |
107 | a valid command will clear it (with a delay of one command) | |
108 | c : clear by read | |
109 | */ | |
110 | ||
111 | #define R1_OUT_OF_RANGE (1 << 31) /* er, c */ | |
112 | #define R1_ADDRESS_ERROR (1 << 30) /* erx, c */ | |
113 | #define R1_BLOCK_LEN_ERROR (1 << 29) /* er, c */ | |
114 | #define R1_ERASE_SEQ_ERROR (1 << 28) /* er, c */ | |
115 | #define R1_ERASE_PARAM (1 << 27) /* ex, c */ | |
116 | #define R1_WP_VIOLATION (1 << 26) /* erx, c */ | |
117 | #define R1_CARD_IS_LOCKED (1 << 25) /* sx, a */ | |
118 | #define R1_LOCK_UNLOCK_FAILED (1 << 24) /* erx, c */ | |
119 | #define R1_COM_CRC_ERROR (1 << 23) /* er, b */ | |
120 | #define R1_ILLEGAL_COMMAND (1 << 22) /* er, b */ | |
121 | #define R1_CARD_ECC_FAILED (1 << 21) /* ex, c */ | |
122 | #define R1_CC_ERROR (1 << 20) /* erx, c */ | |
123 | #define R1_ERROR (1 << 19) /* erx, c */ | |
124 | #define R1_UNDERRUN (1 << 18) /* ex, c */ | |
125 | #define R1_OVERRUN (1 << 17) /* ex, c */ | |
126 | #define R1_CID_CSD_OVERWRITE (1 << 16) /* erx, c, CID/CSD overwrite */ | |
127 | #define R1_WP_ERASE_SKIP (1 << 15) /* sx, c */ | |
128 | #define R1_CARD_ECC_DISABLED (1 << 14) /* sx, a */ | |
129 | #define R1_ERASE_RESET (1 << 13) /* sr, c */ | |
130 | #define R1_STATUS(x) (x & 0xFFFFE000) | |
97018580 | 131 | #define R1_CURRENT_STATE(x) ((x & 0x00001E00) >> 9) /* sx, b (4 bits) */ |
1da177e4 | 132 | #define R1_READY_FOR_DATA (1 << 8) /* sx, a */ |
ef0b27d4 | 133 | #define R1_SWITCH_ERROR (1 << 7) /* sx, c */ |
1da177e4 LT |
134 | #define R1_APP_CMD (1 << 5) /* sr, c */ |
135 | ||
97018580 DB |
136 | /* |
137 | * MMC/SD in SPI mode reports R1 status always, and R2 for SEND_STATUS | |
138 | * R1 is the low order byte; R2 is the next highest byte, when present. | |
139 | */ | |
140 | #define R1_SPI_IDLE (1 << 0) | |
141 | #define R1_SPI_ERASE_RESET (1 << 1) | |
142 | #define R1_SPI_ILLEGAL_COMMAND (1 << 2) | |
143 | #define R1_SPI_COM_CRC (1 << 3) | |
144 | #define R1_SPI_ERASE_SEQ (1 << 4) | |
145 | #define R1_SPI_ADDRESS (1 << 5) | |
146 | #define R1_SPI_PARAMETER (1 << 6) | |
147 | /* R1 bit 7 is always zero */ | |
148 | #define R2_SPI_CARD_LOCKED (1 << 8) | |
149 | #define R2_SPI_WP_ERASE_SKIP (1 << 9) /* or lock/unlock fail */ | |
150 | #define R2_SPI_LOCK_UNLOCK_FAIL R2_SPI_WP_ERASE_SKIP | |
151 | #define R2_SPI_ERROR (1 << 10) | |
152 | #define R2_SPI_CC_ERROR (1 << 11) | |
153 | #define R2_SPI_CARD_ECC_ERROR (1 << 12) | |
154 | #define R2_SPI_WP_VIOLATION (1 << 13) | |
155 | #define R2_SPI_ERASE_PARAM (1 << 14) | |
156 | #define R2_SPI_OUT_OF_RANGE (1 << 15) /* or CSD overwrite */ | |
157 | #define R2_SPI_CSD_OVERWRITE R2_SPI_OUT_OF_RANGE | |
158 | ||
1da177e4 LT |
159 | /* These are unpacked versions of the actual responses */ |
160 | ||
161 | struct _mmc_csd { | |
162 | u8 csd_structure; | |
163 | u8 spec_vers; | |
164 | u8 taac; | |
165 | u8 nsac; | |
166 | u8 tran_speed; | |
167 | u16 ccc; | |
168 | u8 read_bl_len; | |
169 | u8 read_bl_partial; | |
170 | u8 write_blk_misalign; | |
171 | u8 read_blk_misalign; | |
172 | u8 dsr_imp; | |
173 | u16 c_size; | |
174 | u8 vdd_r_curr_min; | |
175 | u8 vdd_r_curr_max; | |
176 | u8 vdd_w_curr_min; | |
177 | u8 vdd_w_curr_max; | |
178 | u8 c_size_mult; | |
179 | union { | |
180 | struct { /* MMC system specification version 3.1 */ | |
181 | u8 erase_grp_size; | |
182 | u8 erase_grp_mult; | |
183 | } v31; | |
184 | struct { /* MMC system specification version 2.2 */ | |
185 | u8 sector_size; | |
186 | u8 erase_grp_size; | |
187 | } v22; | |
188 | } erase; | |
189 | u8 wp_grp_size; | |
190 | u8 wp_grp_enable; | |
191 | u8 default_ecc; | |
192 | u8 r2w_factor; | |
193 | u8 write_bl_len; | |
194 | u8 write_bl_partial; | |
195 | u8 file_format_grp; | |
196 | u8 copy; | |
197 | u8 perm_write_protect; | |
198 | u8 tmp_write_protect; | |
199 | u8 file_format; | |
200 | u8 ecc; | |
201 | }; | |
202 | ||
f74d132c PO |
203 | /* |
204 | * OCR bits are mostly in host.h | |
205 | */ | |
1da177e4 LT |
206 | #define MMC_CARD_BUSY 0x80000000 /* Card Power up status bit */ |
207 | ||
912490db PO |
208 | /* |
209 | * Card Command Classes (CCC) | |
210 | */ | |
211 | #define CCC_BASIC (1<<0) /* (0) Basic protocol functions */ | |
212 | /* (CMD0,1,2,3,4,7,9,10,12,13,15) */ | |
97018580 | 213 | /* (and for SPI, CMD58,59) */ |
912490db PO |
214 | #define CCC_STREAM_READ (1<<1) /* (1) Stream read commands */ |
215 | /* (CMD11) */ | |
216 | #define CCC_BLOCK_READ (1<<2) /* (2) Block read commands */ | |
217 | /* (CMD16,17,18) */ | |
218 | #define CCC_STREAM_WRITE (1<<3) /* (3) Stream write commands */ | |
219 | /* (CMD20) */ | |
220 | #define CCC_BLOCK_WRITE (1<<4) /* (4) Block write commands */ | |
221 | /* (CMD16,24,25,26,27) */ | |
222 | #define CCC_ERASE (1<<5) /* (5) Ability to erase blocks */ | |
223 | /* (CMD32,33,34,35,36,37,38,39) */ | |
224 | #define CCC_WRITE_PROT (1<<6) /* (6) Able to write protect blocks */ | |
225 | /* (CMD28,29,30) */ | |
226 | #define CCC_LOCK_CARD (1<<7) /* (7) Able to lock down card */ | |
227 | /* (CMD16,CMD42) */ | |
228 | #define CCC_APP_SPEC (1<<8) /* (8) Application specific */ | |
229 | /* (CMD55,56,57,ACMD*) */ | |
230 | #define CCC_IO_MODE (1<<9) /* (9) I/O mode */ | |
231 | /* (CMD5,39,40,52,53) */ | |
232 | #define CCC_SWITCH (1<<10) /* (10) High speed switch */ | |
233 | /* (CMD6,34,35,36,37,50) */ | |
234 | /* (11) Reserved */ | |
235 | /* (CMD?) */ | |
1da177e4 LT |
236 | |
237 | /* | |
238 | * CSD field definitions | |
239 | */ | |
240 | ||
241 | #define CSD_STRUCT_VER_1_0 0 /* Valid for system specification 1.0 - 1.2 */ | |
242 | #define CSD_STRUCT_VER_1_1 1 /* Valid for system specification 1.4 - 2.2 */ | |
bce40a36 PL |
243 | #define CSD_STRUCT_VER_1_2 2 /* Valid for system specification 3.1 - 3.2 - 3.31 - 4.0 - 4.1 */ |
244 | #define CSD_STRUCT_EXT_CSD 3 /* Version is coded in CSD_STRUCTURE in EXT_CSD */ | |
1da177e4 LT |
245 | |
246 | #define CSD_SPEC_VER_0 0 /* Implements system specification 1.0 - 1.2 */ | |
247 | #define CSD_SPEC_VER_1 1 /* Implements system specification 1.4 */ | |
248 | #define CSD_SPEC_VER_2 2 /* Implements system specification 2.0 - 2.2 */ | |
bce40a36 PL |
249 | #define CSD_SPEC_VER_3 3 /* Implements system specification 3.1 - 3.2 - 3.31 */ |
250 | #define CSD_SPEC_VER_4 4 /* Implements system specification 4.0 - 4.1 */ | |
251 | ||
252 | /* | |
253 | * EXT_CSD fields | |
254 | */ | |
255 | ||
dfe86cba AH |
256 | #define EXT_CSD_ERASE_GROUP_DEF 175 /* R/W */ |
257 | #define EXT_CSD_ERASED_MEM_CONT 181 /* RO */ | |
258 | #define EXT_CSD_BUS_WIDTH 183 /* R/W */ | |
259 | #define EXT_CSD_HS_TIMING 185 /* R/W */ | |
260 | #define EXT_CSD_REV 192 /* RO */ | |
261 | #define EXT_CSD_STRUCTURE 194 /* RO */ | |
262 | #define EXT_CSD_CARD_TYPE 196 /* RO */ | |
263 | #define EXT_CSD_SEC_CNT 212 /* RO, 4 bytes */ | |
264 | #define EXT_CSD_S_A_TIMEOUT 217 /* RO */ | |
265 | #define EXT_CSD_ERASE_TIMEOUT_MULT 223 /* RO */ | |
266 | #define EXT_CSD_HC_ERASE_GRP_SIZE 224 /* RO */ | |
267 | #define EXT_CSD_SEC_TRIM_MULT 229 /* RO */ | |
268 | #define EXT_CSD_SEC_ERASE_MULT 230 /* RO */ | |
269 | #define EXT_CSD_SEC_FEATURE_SUPPORT 231 /* RO */ | |
270 | #define EXT_CSD_TRIM_MULT 232 /* RO */ | |
bce40a36 PL |
271 | |
272 | /* | |
273 | * EXT_CSD field definitions | |
274 | */ | |
275 | ||
276 | #define EXT_CSD_CMD_SET_NORMAL (1<<0) | |
277 | #define EXT_CSD_CMD_SET_SECURE (1<<1) | |
278 | #define EXT_CSD_CMD_SET_CPSECURE (1<<2) | |
279 | ||
280 | #define EXT_CSD_CARD_TYPE_26 (1<<0) /* Card can run at 26MHz */ | |
281 | #define EXT_CSD_CARD_TYPE_52 (1<<1) /* Card can run at 52MHz */ | |
dfc13e84 HP |
282 | #define EXT_CSD_CARD_TYPE_MASK 0xF /* Mask out reserved bits */ |
283 | #define EXT_CSD_CARD_TYPE_DDR_1_8V (1<<2) /* Card can run at 52MHz */ | |
284 | /* DDR mode @1.8V or 3V I/O */ | |
285 | #define EXT_CSD_CARD_TYPE_DDR_1_2V (1<<3) /* Card can run at 52MHz */ | |
286 | /* DDR mode @1.2V I/O */ | |
287 | #define EXT_CSD_CARD_TYPE_DDR_52 (EXT_CSD_CARD_TYPE_DDR_1_8V \ | |
288 | | EXT_CSD_CARD_TYPE_DDR_1_2V) | |
bce40a36 | 289 | |
e45a1bd2 PL |
290 | #define EXT_CSD_BUS_WIDTH_1 0 /* Card is in 1 bit mode */ |
291 | #define EXT_CSD_BUS_WIDTH_4 1 /* Card is in 4 bit mode */ | |
292 | #define EXT_CSD_BUS_WIDTH_8 2 /* Card is in 8 bit mode */ | |
dfc13e84 HP |
293 | #define EXT_CSD_DDR_BUS_WIDTH_4 5 /* Card is in 4 bit DDR mode */ |
294 | #define EXT_CSD_DDR_BUS_WIDTH_8 6 /* Card is in 8 bit DDR mode */ | |
e45a1bd2 | 295 | |
dfe86cba AH |
296 | #define EXT_CSD_SEC_ER_EN BIT(0) |
297 | #define EXT_CSD_SEC_BD_BLK_EN BIT(2) | |
298 | #define EXT_CSD_SEC_GB_CL_EN BIT(4) | |
299 | ||
bce40a36 PL |
300 | /* |
301 | * MMC_SWITCH access modes | |
302 | */ | |
1da177e4 | 303 | |
bce40a36 PL |
304 | #define MMC_SWITCH_MODE_CMD_SET 0x00 /* Change the command set */ |
305 | #define MMC_SWITCH_MODE_SET_BITS 0x01 /* Set bits which are 1 in value */ | |
306 | #define MMC_SWITCH_MODE_CLEAR_BITS 0x02 /* Clear bits which are 1 in value */ | |
307 | #define MMC_SWITCH_MODE_WRITE_BYTE 0x03 /* Set target to value */ | |
f218278a | 308 | |
1da177e4 LT |
309 | #endif /* MMC_MMC_PROTOCOL_H */ |
310 |