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fdc50a94 YG |
1 | /* |
2 | * include/linux/mmc/sh_mmcif.h | |
3 | * | |
4 | * platform data for eMMC driver | |
5 | * | |
6 | * Copyright (C) 2010 Renesas Solutions Corp. | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or modify | |
9 | * it under the terms of the GNU General Public License as published by | |
10 | * the Free Software Foundation; either version 2 of the License. | |
11 | * | |
12 | */ | |
13 | ||
14 | #ifndef __SH_MMCIF_H__ | |
15 | #define __SH_MMCIF_H__ | |
16 | ||
487d9fc5 MD |
17 | #include <linux/platform_device.h> |
18 | #include <linux/io.h> | |
19 | ||
fdc50a94 YG |
20 | /* |
21 | * MMCIF : CE_CLK_CTRL [19:16] | |
22 | * 1000 : Peripheral clock / 512 | |
23 | * 0111 : Peripheral clock / 256 | |
24 | * 0110 : Peripheral clock / 128 | |
25 | * 0101 : Peripheral clock / 64 | |
26 | * 0100 : Peripheral clock / 32 | |
27 | * 0011 : Peripheral clock / 16 | |
28 | * 0010 : Peripheral clock / 8 | |
29 | * 0001 : Peripheral clock / 4 | |
30 | * 0000 : Peripheral clock / 2 | |
31 | * 1111 : Peripheral clock (sup_pclk set '1') | |
32 | */ | |
33 | ||
34 | struct sh_mmcif_plat_data { | |
35 | void (*set_pwr)(struct platform_device *pdev, int state); | |
36 | void (*down_pwr)(struct platform_device *pdev); | |
777271d0 | 37 | int (*get_cd)(struct platform_device *pdef); |
fdc50a94 YG |
38 | u8 sup_pclk; /* 1 :SH7757, 0: SH7724/SH7372 */ |
39 | unsigned long caps; | |
40 | u32 ocr; | |
41 | }; | |
42 | ||
487d9fc5 MD |
43 | #define MMCIF_CE_CMD_SET 0x00000000 |
44 | #define MMCIF_CE_ARG 0x00000008 | |
45 | #define MMCIF_CE_ARG_CMD12 0x0000000C | |
46 | #define MMCIF_CE_CMD_CTRL 0x00000010 | |
47 | #define MMCIF_CE_BLOCK_SET 0x00000014 | |
48 | #define MMCIF_CE_CLK_CTRL 0x00000018 | |
49 | #define MMCIF_CE_BUF_ACC 0x0000001C | |
50 | #define MMCIF_CE_RESP3 0x00000020 | |
51 | #define MMCIF_CE_RESP2 0x00000024 | |
52 | #define MMCIF_CE_RESP1 0x00000028 | |
53 | #define MMCIF_CE_RESP0 0x0000002C | |
54 | #define MMCIF_CE_RESP_CMD12 0x00000030 | |
55 | #define MMCIF_CE_DATA 0x00000034 | |
56 | #define MMCIF_CE_INT 0x00000040 | |
57 | #define MMCIF_CE_INT_MASK 0x00000044 | |
58 | #define MMCIF_CE_HOST_STS1 0x00000048 | |
59 | #define MMCIF_CE_HOST_STS2 0x0000004C | |
60 | #define MMCIF_CE_VERSION 0x0000007C | |
61 | ||
da1d39e3 SH |
62 | /* CE_BUF_ACC */ |
63 | #define BUF_ACC_DMAWEN (1 << 25) | |
64 | #define BUF_ACC_DMAREN (1 << 24) | |
65 | #define BUF_ACC_BUSW_32 (0 << 17) | |
66 | #define BUF_ACC_BUSW_16 (1 << 17) | |
67 | #define BUF_ACC_ATYP (1 << 16) | |
68 | ||
69 | /* CE_CLK_CTRL */ | |
70 | #define CLK_ENABLE (1 << 24) /* 1: output mmc clock */ | |
71 | #define CLK_CLEAR ((1 << 19) | (1 << 18) | (1 << 17) | (1 << 16)) | |
72 | #define CLK_SUP_PCLK ((1 << 19) | (1 << 18) | (1 << 17) | (1 << 16)) | |
22efa0fe SH |
73 | #define CLKDIV_4 (1<<16) /* mmc clock frequency. |
74 | * n: bus clock/(2^(n+1)) */ | |
75 | #define CLKDIV_256 (7<<16) /* mmc clock frequency. (see above) */ | |
da1d39e3 SH |
76 | #define SRSPTO_256 ((1 << 13) | (0 << 12)) /* resp timeout */ |
77 | #define SRBSYTO_29 ((1 << 11) | (1 << 10) | \ | |
78 | (1 << 9) | (1 << 8)) /* resp busy timeout */ | |
79 | #define SRWDTO_29 ((1 << 7) | (1 << 6) | \ | |
80 | (1 << 5) | (1 << 4)) /* read/write timeout */ | |
81 | #define SCCSTO_29 ((1 << 3) | (1 << 2) | \ | |
82 | (1 << 1) | (1 << 0)) /* ccs timeout */ | |
83 | ||
84 | /* CE_VERSION */ | |
85 | #define SOFT_RST_ON (1 << 31) | |
1ae0affe | 86 | #define SOFT_RST_OFF 0 |
da1d39e3 | 87 | |
2f6ba579 | 88 | static inline u32 sh_mmcif_readl(void __iomem *addr, int reg) |
487d9fc5 MD |
89 | { |
90 | return readl(addr + reg); | |
91 | } | |
92 | ||
2f6ba579 | 93 | static inline void sh_mmcif_writel(void __iomem *addr, int reg, u32 val) |
487d9fc5 MD |
94 | { |
95 | writel(val, addr + reg); | |
96 | } | |
97 | ||
8a768952 MD |
98 | #define SH_MMCIF_BBS 512 /* boot block size */ |
99 | ||
9f843706 SH |
100 | enum { MMCIF_PROGRESS_ENTER, MMCIF_PROGRESS_INIT, |
101 | MMCIF_PROGRESS_LOAD, MMCIF_PROGRESS_DONE }; | |
102 | ||
2f6ba579 | 103 | static inline void sh_mmcif_boot_cmd_send(void __iomem *base, |
8a768952 MD |
104 | unsigned long cmd, unsigned long arg) |
105 | { | |
106 | sh_mmcif_writel(base, MMCIF_CE_INT, 0); | |
107 | sh_mmcif_writel(base, MMCIF_CE_ARG, arg); | |
108 | sh_mmcif_writel(base, MMCIF_CE_CMD_SET, cmd); | |
109 | } | |
110 | ||
2f6ba579 | 111 | static inline int sh_mmcif_boot_cmd_poll(void __iomem *base, unsigned long mask) |
8a768952 MD |
112 | { |
113 | unsigned long tmp; | |
114 | int cnt; | |
115 | ||
116 | for (cnt = 0; cnt < 1000000; cnt++) { | |
117 | tmp = sh_mmcif_readl(base, MMCIF_CE_INT); | |
118 | if (tmp & mask) { | |
119 | sh_mmcif_writel(base, MMCIF_CE_INT, tmp & ~mask); | |
120 | return 0; | |
121 | } | |
122 | } | |
123 | ||
124 | return -1; | |
125 | } | |
126 | ||
2f6ba579 | 127 | static inline int sh_mmcif_boot_cmd(void __iomem *base, |
8a768952 MD |
128 | unsigned long cmd, unsigned long arg) |
129 | { | |
130 | sh_mmcif_boot_cmd_send(base, cmd, arg); | |
131 | return sh_mmcif_boot_cmd_poll(base, 0x00010000); | |
132 | } | |
133 | ||
2f6ba579 | 134 | static inline int sh_mmcif_boot_do_read_single(void __iomem *base, |
8a768952 MD |
135 | unsigned int block_nr, |
136 | unsigned long *buf) | |
137 | { | |
138 | int k; | |
139 | ||
140 | /* CMD13 - Status */ | |
141 | sh_mmcif_boot_cmd(base, 0x0d400000, 0x00010000); | |
142 | ||
143 | if (sh_mmcif_readl(base, MMCIF_CE_RESP0) != 0x0900) | |
144 | return -1; | |
145 | ||
146 | /* CMD17 - Read */ | |
147 | sh_mmcif_boot_cmd(base, 0x11480000, block_nr * SH_MMCIF_BBS); | |
148 | if (sh_mmcif_boot_cmd_poll(base, 0x00100000) < 0) | |
149 | return -1; | |
150 | ||
151 | for (k = 0; k < (SH_MMCIF_BBS / 4); k++) | |
152 | buf[k] = sh_mmcif_readl(base, MMCIF_CE_DATA); | |
153 | ||
154 | return 0; | |
155 | } | |
156 | ||
2f6ba579 | 157 | static inline int sh_mmcif_boot_do_read(void __iomem *base, |
8a768952 MD |
158 | unsigned long first_block, |
159 | unsigned long nr_blocks, | |
160 | void *buf) | |
161 | { | |
162 | unsigned long k; | |
163 | int ret = 0; | |
164 | ||
54b38463 SH |
165 | /* In data transfer mode: Set clock to Bus clock/4 (about 20Mhz) */ |
166 | sh_mmcif_writel(base, MMCIF_CE_CLK_CTRL, | |
167 | CLK_ENABLE | CLKDIV_4 | SRSPTO_256 | | |
168 | SRBSYTO_29 | SRWDTO_29 | SCCSTO_29); | |
169 | ||
170 | /* CMD9 - Get CSD */ | |
171 | sh_mmcif_boot_cmd(base, 0x09806000, 0x00010000); | |
172 | ||
173 | /* CMD7 - Select the card */ | |
174 | sh_mmcif_boot_cmd(base, 0x07400000, 0x00010000); | |
175 | ||
8a768952 MD |
176 | /* CMD16 - Set the block size */ |
177 | sh_mmcif_boot_cmd(base, 0x10400000, SH_MMCIF_BBS); | |
178 | ||
179 | for (k = 0; !ret && k < nr_blocks; k++) | |
180 | ret = sh_mmcif_boot_do_read_single(base, first_block + k, | |
181 | buf + (k * SH_MMCIF_BBS)); | |
182 | ||
183 | return ret; | |
184 | } | |
185 | ||
2f6ba579 | 186 | static inline void sh_mmcif_boot_init(void __iomem *base) |
8a768952 | 187 | { |
8a768952 | 188 | /* reset */ |
1ae0affe SH |
189 | sh_mmcif_writel(base, MMCIF_CE_VERSION, SOFT_RST_ON); |
190 | sh_mmcif_writel(base, MMCIF_CE_VERSION, SOFT_RST_OFF); | |
8a768952 MD |
191 | |
192 | /* byte swap */ | |
da1d39e3 | 193 | sh_mmcif_writel(base, MMCIF_CE_BUF_ACC, BUF_ACC_ATYP); |
8a768952 MD |
194 | |
195 | /* Set block size in MMCIF hardware */ | |
196 | sh_mmcif_writel(base, MMCIF_CE_BLOCK_SET, SH_MMCIF_BBS); | |
197 | ||
22efa0fe | 198 | /* Enable the clock, set it to Bus clock/256 (about 325Khz). */ |
da1d39e3 | 199 | sh_mmcif_writel(base, MMCIF_CE_CLK_CTRL, |
22efa0fe SH |
200 | CLK_ENABLE | CLKDIV_256 | SRSPTO_256 | |
201 | SRBSYTO_29 | SRWDTO_29 | SCCSTO_29); | |
8a768952 MD |
202 | |
203 | /* CMD0 */ | |
204 | sh_mmcif_boot_cmd(base, 0x00000040, 0); | |
205 | ||
206 | /* CMD1 - Get OCR */ | |
207 | do { | |
208 | sh_mmcif_boot_cmd(base, 0x01405040, 0x40300000); /* CMD1 */ | |
209 | } while ((sh_mmcif_readl(base, MMCIF_CE_RESP0) & 0x80000000) | |
210 | != 0x80000000); | |
211 | ||
212 | /* CMD2 - Get CID */ | |
213 | sh_mmcif_boot_cmd(base, 0x02806040, 0); | |
214 | ||
215 | /* CMD3 - Set card relative address */ | |
216 | sh_mmcif_boot_cmd(base, 0x03400040, 0x00010000); | |
217 | } | |
218 | ||
fdc50a94 | 219 | #endif /* __SH_MMCIF_H__ */ |