]>
Commit | Line | Data |
---|---|---|
b2441318 | 1 | /* SPDX-License-Identifier: GPL-2.0 */ |
3b7d1921 EB |
2 | #ifndef LINUX_MSI_H |
3 | #define LINUX_MSI_H | |
4 | ||
b50cac55 | 5 | #include <linux/kobject.h> |
4aa9bc95 ME |
6 | #include <linux/list.h> |
7 | ||
3b7d1921 EB |
8 | struct msi_msg { |
9 | u32 address_lo; /* low 32 bits of msi message address */ | |
10 | u32 address_hi; /* high 32 bits of msi message address */ | |
11 | u32 data; /* 16 bits of msi message data */ | |
12 | }; | |
13 | ||
38737d82 | 14 | extern int pci_msi_ignore_mask; |
c54c1879 | 15 | /* Helper functions */ |
1c9db525 | 16 | struct irq_data; |
39431acb | 17 | struct msi_desc; |
25a98bd4 | 18 | struct pci_dev; |
c09fcc4b | 19 | struct platform_msi_priv_data; |
2366d06e | 20 | void __get_cached_msi_msg(struct msi_desc *entry, struct msi_msg *msg); |
2f44e29c | 21 | #ifdef CONFIG_GENERIC_MSI_IRQ |
2366d06e | 22 | void get_cached_msi_msg(unsigned int irq, struct msi_msg *msg); |
2f44e29c AB |
23 | #else |
24 | static inline void get_cached_msi_msg(unsigned int irq, struct msi_msg *msg) | |
25 | { | |
26 | } | |
27 | #endif | |
891d4a48 | 28 | |
c09fcc4b MZ |
29 | typedef void (*irq_write_msi_msg_t)(struct msi_desc *desc, |
30 | struct msi_msg *msg); | |
31 | ||
32 | /** | |
33 | * platform_msi_desc - Platform device specific msi descriptor data | |
34 | * @msi_priv_data: Pointer to platform private data | |
35 | * @msi_index: The index of the MSI descriptor for multi MSI | |
36 | */ | |
37 | struct platform_msi_desc { | |
38 | struct platform_msi_priv_data *msi_priv_data; | |
39 | u16 msi_index; | |
40 | }; | |
41 | ||
550308e4 GR |
42 | /** |
43 | * fsl_mc_msi_desc - FSL-MC device specific msi descriptor data | |
44 | * @msi_index: The index of the MSI descriptor | |
45 | */ | |
46 | struct fsl_mc_msi_desc { | |
47 | u16 msi_index; | |
48 | }; | |
49 | ||
fc88419c JL |
50 | /** |
51 | * struct msi_desc - Descriptor structure for MSI based interrupts | |
52 | * @list: List head for management | |
53 | * @irq: The base interrupt number | |
54 | * @nvec_used: The number of vectors used | |
55 | * @dev: Pointer to the device which uses this descriptor | |
56 | * @msg: The last set MSI message cached for reuse | |
0972fa57 | 57 | * @affinity: Optional pointer to a cpu affinity mask for this descriptor |
fc88419c JL |
58 | * |
59 | * @masked: [PCI MSI/X] Mask bits | |
60 | * @is_msix: [PCI MSI/X] True if MSI-X | |
61 | * @multiple: [PCI MSI/X] log2 num of messages allocated | |
62 | * @multi_cap: [PCI MSI/X] log2 num of messages supported | |
63 | * @maskbit: [PCI MSI/X] Mask-Pending bit supported? | |
64 | * @is_64: [PCI MSI/X] Address size: 0=32bit 1=64bit | |
65 | * @entry_nr: [PCI MSI/X] Entry which is described by this descriptor | |
66 | * @default_irq:[PCI MSI/X] The default pre-assigned non-MSI irq | |
67 | * @mask_pos: [PCI MSI] Mask register position | |
68 | * @mask_base: [PCI MSI-X] Mask register base address | |
c09fcc4b | 69 | * @platform: [platform] Platform device specific msi descriptor data |
87840fb5 | 70 | * @fsl_mc: [fsl-mc] FSL MC device specific msi descriptor data |
fc88419c | 71 | */ |
3b7d1921 | 72 | struct msi_desc { |
fc88419c JL |
73 | /* Shared device/bus type independent data */ |
74 | struct list_head list; | |
75 | unsigned int irq; | |
76 | unsigned int nvec_used; | |
77 | struct device *dev; | |
78 | struct msi_msg msg; | |
28f4b041 | 79 | struct cpumask *affinity; |
3b7d1921 | 80 | |
264d9caa | 81 | union { |
fc88419c JL |
82 | /* PCI MSI/X specific data */ |
83 | struct { | |
84 | u32 masked; | |
85 | struct { | |
86 | __u8 is_msix : 1; | |
87 | __u8 multiple : 3; | |
88 | __u8 multi_cap : 3; | |
89 | __u8 maskbit : 1; | |
90 | __u8 is_64 : 1; | |
91 | __u16 entry_nr; | |
92 | unsigned default_irq; | |
93 | } msi_attrib; | |
94 | union { | |
95 | u8 mask_pos; | |
96 | void __iomem *mask_base; | |
97 | }; | |
98 | }; | |
3b7d1921 | 99 | |
fc88419c JL |
100 | /* |
101 | * Non PCI variants add their data structure here. New | |
102 | * entries need to use a named structure. We want | |
103 | * proper name spaces for this. The PCI part is | |
104 | * anonymous for now as it would require an immediate | |
105 | * tree wide cleanup. | |
106 | */ | |
c09fcc4b | 107 | struct platform_msi_desc platform; |
550308e4 | 108 | struct fsl_mc_msi_desc fsl_mc; |
fc88419c | 109 | }; |
3b7d1921 EB |
110 | }; |
111 | ||
d31eb342 | 112 | /* Helpers to hide struct msi_desc implementation details */ |
25a98bd4 | 113 | #define msi_desc_to_dev(desc) ((desc)->dev) |
4a7cc831 | 114 | #define dev_to_msi_list(dev) (&(dev)->msi_list) |
d31eb342 JL |
115 | #define first_msi_entry(dev) \ |
116 | list_first_entry(dev_to_msi_list((dev)), struct msi_desc, list) | |
117 | #define for_each_msi_entry(desc, dev) \ | |
118 | list_for_each_entry((desc), dev_to_msi_list((dev)), list) | |
119 | ||
120 | #ifdef CONFIG_PCI_MSI | |
121 | #define first_pci_msi_entry(pdev) first_msi_entry(&(pdev)->dev) | |
122 | #define for_each_pci_msi_entry(desc, pdev) \ | |
123 | for_each_msi_entry((desc), &(pdev)->dev) | |
124 | ||
25a98bd4 | 125 | struct pci_dev *msi_desc_to_pci_dev(struct msi_desc *desc); |
c179c9b9 | 126 | void *msi_desc_to_pci_sysdata(struct msi_desc *desc); |
2f44e29c | 127 | void pci_write_msi_msg(unsigned int irq, struct msi_msg *msg); |
c179c9b9 JL |
128 | #else /* CONFIG_PCI_MSI */ |
129 | static inline void *msi_desc_to_pci_sysdata(struct msi_desc *desc) | |
130 | { | |
131 | return NULL; | |
132 | } | |
2f44e29c AB |
133 | static inline void pci_write_msi_msg(unsigned int irq, struct msi_msg *msg) |
134 | { | |
135 | } | |
d31eb342 JL |
136 | #endif /* CONFIG_PCI_MSI */ |
137 | ||
28f4b041 TG |
138 | struct msi_desc *alloc_msi_entry(struct device *dev, int nvec, |
139 | const struct cpumask *affinity); | |
aa48b6f7 | 140 | void free_msi_entry(struct msi_desc *entry); |
891d4a48 | 141 | void __pci_read_msi_msg(struct msi_desc *entry, struct msi_msg *msg); |
83a18912 | 142 | void __pci_write_msi_msg(struct msi_desc *entry, struct msi_msg *msg); |
83a18912 | 143 | |
23ed8d57 TG |
144 | u32 __pci_msix_desc_mask_irq(struct msi_desc *desc, u32 flag); |
145 | u32 __pci_msi_desc_mask_irq(struct msi_desc *desc, u32 mask, u32 flag); | |
146 | void pci_msi_mask_irq(struct irq_data *data); | |
147 | void pci_msi_unmask_irq(struct irq_data *data); | |
148 | ||
83a18912 JL |
149 | /* Conversion helpers. Should be removed after merging */ |
150 | static inline void __write_msi_msg(struct msi_desc *entry, struct msi_msg *msg) | |
151 | { | |
152 | __pci_write_msi_msg(entry, msg); | |
153 | } | |
154 | static inline void write_msi_msg(int irq, struct msi_msg *msg) | |
155 | { | |
156 | pci_write_msi_msg(irq, msg); | |
157 | } | |
23ed8d57 TG |
158 | static inline void mask_msi_irq(struct irq_data *data) |
159 | { | |
160 | pci_msi_mask_irq(data); | |
161 | } | |
162 | static inline void unmask_msi_irq(struct irq_data *data) | |
163 | { | |
164 | pci_msi_unmask_irq(data); | |
165 | } | |
891d4a48 | 166 | |
3b7d1921 | 167 | /* |
4287d824 TP |
168 | * The arch hooks to setup up msi irqs. Those functions are |
169 | * implemented as weak symbols so that they /can/ be overriden by | |
170 | * architecture specific code if needed. | |
3b7d1921 | 171 | */ |
f7feaca7 | 172 | int arch_setup_msi_irq(struct pci_dev *dev, struct msi_desc *desc); |
3b7d1921 | 173 | void arch_teardown_msi_irq(unsigned int irq); |
2366d06e BH |
174 | int arch_setup_msi_irqs(struct pci_dev *dev, int nvec, int type); |
175 | void arch_teardown_msi_irqs(struct pci_dev *dev); | |
ac8344c4 | 176 | void arch_restore_msi_irqs(struct pci_dev *dev); |
4287d824 TP |
177 | |
178 | void default_teardown_msi_irqs(struct pci_dev *dev); | |
ac8344c4 | 179 | void default_restore_msi_irqs(struct pci_dev *dev); |
3b7d1921 | 180 | |
c2791b80 | 181 | struct msi_controller { |
0cbdcfcf TR |
182 | struct module *owner; |
183 | struct device *dev; | |
0d5a6db3 TP |
184 | struct device_node *of_node; |
185 | struct list_head list; | |
0cbdcfcf | 186 | |
c2791b80 | 187 | int (*setup_irq)(struct msi_controller *chip, struct pci_dev *dev, |
0cbdcfcf | 188 | struct msi_desc *desc); |
339e5b44 LS |
189 | int (*setup_irqs)(struct msi_controller *chip, struct pci_dev *dev, |
190 | int nvec, int type); | |
c2791b80 | 191 | void (*teardown_irq)(struct msi_controller *chip, unsigned int irq); |
0cbdcfcf TR |
192 | }; |
193 | ||
f3cf8bb0 | 194 | #ifdef CONFIG_GENERIC_MSI_IRQ_DOMAIN |
d9109698 | 195 | |
aeeb5965 | 196 | #include <linux/irqhandler.h> |
d9109698 JL |
197 | #include <asm/msi.h> |
198 | ||
f3cf8bb0 | 199 | struct irq_domain; |
552c494a | 200 | struct irq_domain_ops; |
f3cf8bb0 JL |
201 | struct irq_chip; |
202 | struct device_node; | |
be5436c8 | 203 | struct fwnode_handle; |
f3cf8bb0 JL |
204 | struct msi_domain_info; |
205 | ||
206 | /** | |
207 | * struct msi_domain_ops - MSI interrupt domain callbacks | |
208 | * @get_hwirq: Retrieve the resulting hw irq number | |
209 | * @msi_init: Domain specific init function for MSI interrupts | |
210 | * @msi_free: Domain specific function to free a MSI interrupts | |
d9109698 JL |
211 | * @msi_check: Callback for verification of the domain/info/dev data |
212 | * @msi_prepare: Prepare the allocation of the interrupts in the domain | |
1d1e8cdc | 213 | * @msi_finish: Optional callback to finalize the allocation |
d9109698 JL |
214 | * @set_desc: Set the msi descriptor for an interrupt |
215 | * @handle_error: Optional error handler if the allocation fails | |
216 | * | |
217 | * @get_hwirq, @msi_init and @msi_free are callbacks used by | |
218 | * msi_create_irq_domain() and related interfaces | |
219 | * | |
220 | * @msi_check, @msi_prepare, @msi_finish, @set_desc and @handle_error | |
1d1e8cdc | 221 | * are callbacks used by msi_domain_alloc_irqs() and related |
d9109698 | 222 | * interfaces which are based on msi_desc. |
f3cf8bb0 JL |
223 | */ |
224 | struct msi_domain_ops { | |
aeeb5965 JL |
225 | irq_hw_number_t (*get_hwirq)(struct msi_domain_info *info, |
226 | msi_alloc_info_t *arg); | |
f3cf8bb0 JL |
227 | int (*msi_init)(struct irq_domain *domain, |
228 | struct msi_domain_info *info, | |
229 | unsigned int virq, irq_hw_number_t hwirq, | |
aeeb5965 | 230 | msi_alloc_info_t *arg); |
f3cf8bb0 JL |
231 | void (*msi_free)(struct irq_domain *domain, |
232 | struct msi_domain_info *info, | |
233 | unsigned int virq); | |
d9109698 JL |
234 | int (*msi_check)(struct irq_domain *domain, |
235 | struct msi_domain_info *info, | |
236 | struct device *dev); | |
237 | int (*msi_prepare)(struct irq_domain *domain, | |
238 | struct device *dev, int nvec, | |
239 | msi_alloc_info_t *arg); | |
240 | void (*msi_finish)(msi_alloc_info_t *arg, int retval); | |
241 | void (*set_desc)(msi_alloc_info_t *arg, | |
242 | struct msi_desc *desc); | |
243 | int (*handle_error)(struct irq_domain *domain, | |
244 | struct msi_desc *desc, int error); | |
f3cf8bb0 JL |
245 | }; |
246 | ||
247 | /** | |
248 | * struct msi_domain_info - MSI interrupt domain data | |
aeeb5965 JL |
249 | * @flags: Flags to decribe features and capabilities |
250 | * @ops: The callback data structure | |
251 | * @chip: Optional: associated interrupt chip | |
252 | * @chip_data: Optional: associated interrupt chip data | |
253 | * @handler: Optional: associated interrupt flow handler | |
254 | * @handler_data: Optional: associated interrupt flow handler data | |
255 | * @handler_name: Optional: associated interrupt flow handler name | |
256 | * @data: Optional: domain specific data | |
f3cf8bb0 JL |
257 | */ |
258 | struct msi_domain_info { | |
aeeb5965 | 259 | u32 flags; |
f3cf8bb0 JL |
260 | struct msi_domain_ops *ops; |
261 | struct irq_chip *chip; | |
aeeb5965 JL |
262 | void *chip_data; |
263 | irq_flow_handler_t handler; | |
264 | void *handler_data; | |
265 | const char *handler_name; | |
f3cf8bb0 JL |
266 | void *data; |
267 | }; | |
268 | ||
aeeb5965 JL |
269 | /* Flags for msi_domain_info */ |
270 | enum { | |
271 | /* | |
272 | * Init non implemented ops callbacks with default MSI domain | |
273 | * callbacks. | |
274 | */ | |
275 | MSI_FLAG_USE_DEF_DOM_OPS = (1 << 0), | |
276 | /* | |
277 | * Init non implemented chip callbacks with default MSI chip | |
278 | * callbacks. | |
279 | */ | |
280 | MSI_FLAG_USE_DEF_CHIP_OPS = (1 << 1), | |
aeeb5965 | 281 | /* Support multiple PCI MSI interrupts */ |
b6140914 | 282 | MSI_FLAG_MULTI_PCI_MSI = (1 << 2), |
aeeb5965 | 283 | /* Support PCI MSIX interrupts */ |
b6140914 | 284 | MSI_FLAG_PCI_MSIX = (1 << 3), |
f3b0946d MZ |
285 | /* Needs early activate, required for PCI */ |
286 | MSI_FLAG_ACTIVATE_EARLY = (1 << 4), | |
22d0b12f TG |
287 | /* |
288 | * Must reactivate when irq is started even when | |
289 | * MSI_FLAG_ACTIVATE_EARLY has been set. | |
290 | */ | |
291 | MSI_FLAG_MUST_REACTIVATE = (1 << 5), | |
0be8153c MZ |
292 | /* Is level-triggered capable, using two messages */ |
293 | MSI_FLAG_LEVEL_CAPABLE = (1 << 6), | |
aeeb5965 JL |
294 | }; |
295 | ||
f3cf8bb0 JL |
296 | int msi_domain_set_affinity(struct irq_data *data, const struct cpumask *mask, |
297 | bool force); | |
298 | ||
be5436c8 | 299 | struct irq_domain *msi_create_irq_domain(struct fwnode_handle *fwnode, |
f3cf8bb0 JL |
300 | struct msi_domain_info *info, |
301 | struct irq_domain *parent); | |
d9109698 JL |
302 | int msi_domain_alloc_irqs(struct irq_domain *domain, struct device *dev, |
303 | int nvec); | |
304 | void msi_domain_free_irqs(struct irq_domain *domain, struct device *dev); | |
f3cf8bb0 JL |
305 | struct msi_domain_info *msi_get_domain_info(struct irq_domain *domain); |
306 | ||
be5436c8 | 307 | struct irq_domain *platform_msi_create_irq_domain(struct fwnode_handle *fwnode, |
c09fcc4b MZ |
308 | struct msi_domain_info *info, |
309 | struct irq_domain *parent); | |
310 | int platform_msi_domain_alloc_irqs(struct device *dev, unsigned int nvec, | |
311 | irq_write_msi_msg_t write_msi_msg); | |
312 | void platform_msi_domain_free_irqs(struct device *dev); | |
b2eba39b MZ |
313 | |
314 | /* When an MSI domain is used as an intermediate domain */ | |
315 | int msi_domain_prepare_irqs(struct irq_domain *domain, struct device *dev, | |
316 | int nvec, msi_alloc_info_t *args); | |
2145ac93 MZ |
317 | int msi_domain_populate_irqs(struct irq_domain *domain, struct device *dev, |
318 | int virq, int nvec, msi_alloc_info_t *args); | |
552c494a | 319 | struct irq_domain * |
1f83515b MZ |
320 | __platform_msi_create_device_domain(struct device *dev, |
321 | unsigned int nvec, | |
322 | bool is_tree, | |
323 | irq_write_msi_msg_t write_msi_msg, | |
324 | const struct irq_domain_ops *ops, | |
325 | void *host_data); | |
326 | ||
327 | #define platform_msi_create_device_domain(dev, nvec, write, ops, data) \ | |
328 | __platform_msi_create_device_domain(dev, nvec, false, write, ops, data) | |
329 | #define platform_msi_create_device_tree_domain(dev, nvec, write, ops, data) \ | |
330 | __platform_msi_create_device_domain(dev, nvec, true, write, ops, data) | |
331 | ||
552c494a MZ |
332 | int platform_msi_domain_alloc(struct irq_domain *domain, unsigned int virq, |
333 | unsigned int nr_irqs); | |
334 | void platform_msi_domain_free(struct irq_domain *domain, unsigned int virq, | |
335 | unsigned int nvec); | |
336 | void *platform_msi_get_host_data(struct irq_domain *domain); | |
f3cf8bb0 JL |
337 | #endif /* CONFIG_GENERIC_MSI_IRQ_DOMAIN */ |
338 | ||
3878eaef JL |
339 | #ifdef CONFIG_PCI_MSI_IRQ_DOMAIN |
340 | void pci_msi_domain_write_msg(struct irq_data *irq_data, struct msi_msg *msg); | |
be5436c8 | 341 | struct irq_domain *pci_msi_create_irq_domain(struct fwnode_handle *fwnode, |
3878eaef JL |
342 | struct msi_domain_info *info, |
343 | struct irq_domain *parent); | |
3878eaef JL |
344 | irq_hw_number_t pci_msi_domain_calc_hwirq(struct pci_dev *dev, |
345 | struct msi_desc *desc); | |
346 | int pci_msi_domain_check_cap(struct irq_domain *domain, | |
347 | struct msi_domain_info *info, struct device *dev); | |
b6eec9b7 | 348 | u32 pci_msi_domain_get_msi_rid(struct irq_domain *domain, struct pci_dev *pdev); |
54fa97ee MZ |
349 | struct irq_domain *pci_msi_get_device_domain(struct pci_dev *pdev); |
350 | #else | |
351 | static inline struct irq_domain *pci_msi_get_device_domain(struct pci_dev *pdev) | |
352 | { | |
353 | return NULL; | |
354 | } | |
3878eaef JL |
355 | #endif /* CONFIG_PCI_MSI_IRQ_DOMAIN */ |
356 | ||
3b7d1921 | 357 | #endif /* LINUX_MSI_H */ |