[mirror_ubuntu-bionic-kernel.git] / include / linux / mtd / cfi.h


/* Common Flash Interface structures
 * See http://support.intel.com/design/flash/technote/index.htm
 */

#ifndef __MTD_CFI_H__
#define __MTD_CFI_H__

#include <linux/delay.h>
#include <linux/types.h>
#include <linux/interrupt.h>
#include <linux/mtd/flashchip.h>
#include <linux/mtd/map.h>
#include <linux/mtd/cfi_endian.h>
#include <linux/mtd/xip.h>

#ifdef CONFIG_MTD_CFI_I1
#define cfi_interleave(cfi) 1
#define cfi_interleave_is_1(cfi) (cfi_interleave(cfi) == 1)
#else
#define cfi_interleave_is_1(cfi) (0)
#endif

#ifdef CONFIG_MTD_CFI_I2
# ifdef cfi_interleave
#  undef cfi_interleave
#  define cfi_interleave(cfi) ((cfi)->interleave)
# else
#  define cfi_interleave(cfi) 2
# endif
#define cfi_interleave_is_2(cfi) (cfi_interleave(cfi) == 2)
#else
#define cfi_interleave_is_2(cfi) (0)
#endif

#ifdef CONFIG_MTD_CFI_I4
# ifdef cfi_interleave
#  undef cfi_interleave
#  define cfi_interleave(cfi) ((cfi)->interleave)
# else
#  define cfi_interleave(cfi) 4
# endif
#define cfi_interleave_is_4(cfi) (cfi_interleave(cfi) == 4)
#else
#define cfi_interleave_is_4(cfi) (0)
#endif

#ifdef CONFIG_MTD_CFI_I8
# ifdef cfi_interleave
#  undef cfi_interleave
#  define cfi_interleave(cfi) ((cfi)->interleave)
# else
#  define cfi_interleave(cfi) 8
# endif
#define cfi_interleave_is_8(cfi) (cfi_interleave(cfi) == 8)
#else
#define cfi_interleave_is_8(cfi) (0)
#endif

#ifndef cfi_interleave
#warning No CONFIG_MTD_CFI_Ix selected. No NOR chip support can work.
static inline int cfi_interleave(void *cfi)
{
	BUG();
	return 0;
}
#endif

static inline int cfi_interleave_supported(int i)
{
	switch (i) {
#ifdef CONFIG_MTD_CFI_I1
	case 1:
#endif
#ifdef CONFIG_MTD_CFI_I2
	case 2:
#endif
#ifdef CONFIG_MTD_CFI_I4
	case 4:
#endif
#ifdef CONFIG_MTD_CFI_I8
	case 8:
#endif
		return 1;

	default:
		return 0;
	}
}


/* NB: these values must represents the number of bytes needed to meet the
 *     device type (x8, x16, x32).  Eg. a 32 bit device is 4 x 8 bytes.
 *     These numbers are used in calculations.
 */
#define CFI_DEVICETYPE_X8  (8 / 8)
#define CFI_DEVICETYPE_X16 (16 / 8)
#define CFI_DEVICETYPE_X32 (32 / 8)
#define CFI_DEVICETYPE_X64 (64 / 8)


/* Device Interface Code Assignments from the "Common Flash Memory Interface
 * Publication 100" dated December 1, 2001.
 */
#define CFI_INTERFACE_X8_ASYNC		0x0000
#define CFI_INTERFACE_X16_ASYNC		0x0001
#define CFI_INTERFACE_X8_BY_X16_ASYNC	0x0002
#define CFI_INTERFACE_X32_ASYNC		0x0003
#define CFI_INTERFACE_X16_BY_X32_ASYNC	0x0005
#define CFI_INTERFACE_NOT_ALLOWED	0xffff


/* NB: We keep these structures in memory in HOST byteorder, except
 * where individually noted.
 */

/* Basic Query Structure */
struct cfi_ident {
	uint8_t  qry[3];
	uint16_t P_ID;
	uint16_t P_ADR;
	uint16_t A_ID;
	uint16_t A_ADR;
	uint8_t  VccMin;
	uint8_t  VccMax;
	uint8_t  VppMin;
	uint8_t  VppMax;
	uint8_t  WordWriteTimeoutTyp;
	uint8_t  BufWriteTimeoutTyp;
	uint8_t  BlockEraseTimeoutTyp;
	uint8_t  ChipEraseTimeoutTyp;
	uint8_t  WordWriteTimeoutMax;
	uint8_t  BufWriteTimeoutMax;
	uint8_t  BlockEraseTimeoutMax;
	uint8_t  ChipEraseTimeoutMax;
	uint8_t  DevSize;
	uint16_t InterfaceDesc;
	uint16_t MaxBufWriteSize;
	uint8_t  NumEraseRegions;
	uint32_t EraseRegionInfo[0]; /* Not host ordered */
} __attribute__((packed));

/* Extended Query Structure for both PRI and ALT */

struct cfi_extquery {
	uint8_t  pri[3];
	uint8_t  MajorVersion;
	uint8_t  MinorVersion;
} __attribute__((packed));

/* Vendor-Specific PRI for Intel/Sharp Extended Command Set (0x0001) */

struct cfi_pri_intelext {
	uint8_t  pri[3];
	uint8_t  MajorVersion;
	uint8_t  MinorVersion;
	uint32_t FeatureSupport; /* if bit 31 is set then an additional uint32_t feature
				    block follows - FIXME - not currently supported */
	uint8_t  SuspendCmdSupport;
	uint16_t BlkStatusRegMask;
	uint8_t  VccOptimal;
	uint8_t  VppOptimal;
	uint8_t  NumProtectionFields;
	uint16_t ProtRegAddr;
	uint8_t  FactProtRegSize;
	uint8_t  UserProtRegSize;
	uint8_t  extra[0];
} __attribute__((packed));

struct cfi_intelext_otpinfo {
	uint32_t ProtRegAddr;
	uint16_t FactGroups;
	uint8_t  FactProtRegSize;
	uint16_t UserGroups;
	uint8_t  UserProtRegSize;
} __attribute__((packed));

struct cfi_intelext_blockinfo {
	uint16_t NumIdentBlocks;
	uint16_t BlockSize;
	uint16_t MinBlockEraseCycles;
	uint8_t  BitsPerCell;
	uint8_t  BlockCap;
} __attribute__((packed));

struct cfi_intelext_regioninfo {
	uint16_t NumIdentPartitions;
	uint8_t  NumOpAllowed;
	uint8_t  NumOpAllowedSimProgMode;
	uint8_t  NumOpAllowedSimEraMode;
	uint8_t  NumBlockTypes;
	struct cfi_intelext_blockinfo BlockTypes[1];
} __attribute__((packed));

struct cfi_intelext_programming_regioninfo {
	uint8_t  ProgRegShift;
	uint8_t  Reserved1;
	uint8_t  ControlValid;
	uint8_t  Reserved2;
	uint8_t  ControlInvalid;
	uint8_t  Reserved3;
} __attribute__((packed));

/* Vendor-Specific PRI for AMD/Fujitsu Extended Command Set (0x0002) */

struct cfi_pri_amdstd {
	uint8_t  pri[3];
	uint8_t  MajorVersion;
	uint8_t  MinorVersion;
	uint8_t  SiliconRevision; /* bits 1-0: Address Sensitive Unlock */
	uint8_t  EraseSuspend;
	uint8_t  BlkProt;
	uint8_t  TmpBlkUnprotect;
	uint8_t  BlkProtUnprot;
	uint8_t  SimultaneousOps;
	uint8_t  BurstMode;
	uint8_t  PageMode;
	uint8_t  VppMin;
	uint8_t  VppMax;
	uint8_t  TopBottom;
} __attribute__((packed));

/* Vendor-Specific PRI for Atmel chips (command set 0x0002) */

struct cfi_pri_atmel {
	uint8_t pri[3];
	uint8_t MajorVersion;
	uint8_t MinorVersion;
	uint8_t Features;
	uint8_t BottomBoot;
	uint8_t BurstMode;
	uint8_t PageMode;
} __attribute__((packed));

struct cfi_pri_query {
	uint8_t  NumFields;
	uint32_t ProtField[1]; /* Not host ordered */
} __attribute__((packed));

struct cfi_bri_query {
	uint8_t  PageModeReadCap;
	uint8_t  NumFields;
	uint32_t ConfField[1]; /* Not host ordered */
} __attribute__((packed));

#define P_ID_NONE               0x0000
#define P_ID_INTEL_EXT          0x0001
#define P_ID_AMD_STD            0x0002
#define P_ID_INTEL_STD          0x0003
#define P_ID_AMD_EXT            0x0004
#define P_ID_WINBOND            0x0006
#define P_ID_ST_ADV             0x0020
#define P_ID_MITSUBISHI_STD     0x0100
#define P_ID_MITSUBISHI_EXT     0x0101
#define P_ID_SST_PAGE           0x0102
#define P_ID_INTEL_PERFORMANCE  0x0200
#define P_ID_INTEL_DATA         0x0210
#define P_ID_RESERVED           0xffff


#define CFI_MODE_CFI	1
#define CFI_MODE_JEDEC	0

struct cfi_private {
	uint16_t cmdset;
	void *cmdset_priv;
	int interleave;
	int device_type;
	int cfi_mode;		/* Are we a JEDEC device pretending to be CFI? */
	int addr_unlock1;
	int addr_unlock2;
	struct mtd_info *(*cmdset_setup)(struct map_info *);
	struct cfi_ident *cfiq; /* For now only one. We insist that all devs
				  must be of the same type. */
	int mfr, id;
	int numchips;
	unsigned long chipshift; /* Because they're of the same type */
	const char *im_name;	 /* inter_module name for cmdset_setup */
	struct flchip chips[0];  /* per-chip data structure for each chip */
};

/*
 * Returns the command address according to the given geometry.
 */
static inline uint32_t cfi_build_cmd_addr(uint32_t cmd_ofs, int interleave, int type)
{
	return (cmd_ofs * type) * interleave;
}

/*
 * Transforms the CFI command for the given geometry (bus width & interleave).
 * It looks too long to be inline, but in the common case it should almost all
 * get optimised away.
 */
static inline map_word cfi_build_cmd(u_long cmd, struct map_info *map, struct cfi_private *cfi)
{
	map_word val = { {0} };
	int wordwidth, words_per_bus, chip_mode, chips_per_word;
	unsigned long onecmd;
	int i;

	/* We do it this way to give the compiler a fighting chance
	   of optimising away all the crap for 'bankwidth' larger than
	   an unsigned long, in the common case where that support is
	   disabled */
	if (map_bankwidth_is_large(map)) {
		wordwidth = sizeof(unsigned long);
		words_per_bus = (map_bankwidth(map)) / wordwidth; // i.e. normally 1
	} else {
		wordwidth = map_bankwidth(map);
		words_per_bus = 1;
	}

	chip_mode = map_bankwidth(map) / cfi_interleave(cfi);
	chips_per_word = wordwidth * cfi_interleave(cfi) / map_bankwidth(map);

	/* First, determine what the bit-pattern should be for a single
	   device, according to chip mode and endianness... */
	switch (chip_mode) {
	default: BUG();
	case 1:
		onecmd = cmd;
		break;
	case 2:
		onecmd = cpu_to_cfi16(cmd);
		break;
	case 4:
		onecmd = cpu_to_cfi32(cmd);
		break;
	}

	/* Now replicate it across the size of an unsigned long, or
	   just to the bus width as appropriate */
	switch (chips_per_word) {
	default: BUG();
#if BITS_PER_LONG >= 64
	case 8:
		onecmd |= (onecmd << (chip_mode * 32));
#endif
	case 4:
		onecmd |= (onecmd << (chip_mode * 16));
	case 2:
		onecmd |= (onecmd << (chip_mode * 8));
	case 1:
		;
	}

	/* And finally, for the multi-word case, replicate it
	   in all words in the structure */
	for (i=0; i < words_per_bus; i++) {
		val.x[i] = onecmd;
	}

	return val;
}
#define CMD(x)  cfi_build_cmd((x), map, cfi)


static inline unsigned long cfi_merge_status(map_word val, struct map_info *map,
					   struct cfi_private *cfi)
{
	int wordwidth, words_per_bus, chip_mode, chips_per_word;
	unsigned long onestat, res = 0;
	int i;

	/* We do it this way to give the compiler a fighting chance
	   of optimising away all the crap for 'bankwidth' larger than
	   an unsigned long, in the common case where that support is
	   disabled */
	if (map_bankwidth_is_large(map)) {
		wordwidth = sizeof(unsigned long);
		words_per_bus = (map_bankwidth(map)) / wordwidth; // i.e. normally 1
	} else {
		wordwidth = map_bankwidth(map);
		words_per_bus = 1;
	}

	chip_mode = map_bankwidth(map) / cfi_interleave(cfi);
	chips_per_word = wordwidth * cfi_interleave(cfi) / map_bankwidth(map);

	onestat = val.x[0];
	/* Or all status words together */
	for (i=1; i < words_per_bus; i++) {
		onestat |= val.x[i];
	}

	res = onestat;
	switch(chips_per_word) {
	default: BUG();
#if BITS_PER_LONG >= 64
	case 8:
		res |= (onestat >> (chip_mode * 32));
#endif
	case 4:
		res |= (onestat >> (chip_mode * 16));
	case 2:
		res |= (onestat >> (chip_mode * 8));
	case 1:
		;
	}

	/* Last, determine what the bit-pattern should be for a single
	   device, according to chip mode and endianness... */
	switch (chip_mode) {
	case 1:
		break;
	case 2:
		res = cfi16_to_cpu(res);
		break;
	case 4:
		res = cfi32_to_cpu(res);
		break;
	default: BUG();
	}
	return res;
}

#define MERGESTATUS(x) cfi_merge_status((x), map, cfi)


/*
 * Sends a CFI command to a bank of flash for the given geometry.
 *
 * Returns the offset in flash where the command was written.
 * If prev_val is non-null, it will be set to the value at the command address,
 * before the command was written.
 */
static inline uint32_t cfi_send_gen_cmd(u_char cmd, uint32_t cmd_addr, uint32_t base,
				struct map_info *map, struct cfi_private *cfi,
				int type, map_word *prev_val)
{
	map_word val;
	uint32_t addr = base + cfi_build_cmd_addr(cmd_addr, cfi_interleave(cfi), type);
	val = cfi_build_cmd(cmd, map, cfi);

	if (prev_val)
		*prev_val = map_read(map, addr);

	map_write(map, val, addr);

	return addr - base;
}

static inline uint8_t cfi_read_query(struct map_info *map, uint32_t addr)
{
	map_word val = map_read(map, addr);

	if (map_bankwidth_is_1(map)) {
		return val.x[0];
	} else if (map_bankwidth_is_2(map)) {
		return cfi16_to_cpu(val.x[0]);
	} else {
		/* No point in a 64-bit byteswap since that would just be
		   swapping the responses from different chips, and we are
		   only interested in one chip (a representative sample) */
		return cfi32_to_cpu(val.x[0]);
	}
}

static inline uint16_t cfi_read_query16(struct map_info *map, uint32_t addr)
{
	map_word val = map_read(map, addr);

	if (map_bankwidth_is_1(map)) {
		return val.x[0] & 0xff;
	} else if (map_bankwidth_is_2(map)) {
		return cfi16_to_cpu(val.x[0]);
	} else {
		/* No point in a 64-bit byteswap since that would just be
		   swapping the responses from different chips, and we are
		   only interested in one chip (a representative sample) */
		return cfi32_to_cpu(val.x[0]);
	}
}

static inline void cfi_udelay(int us)
{
	if (us >= 1000) {
		msleep((us+999)/1000);
	} else {
		udelay(us);
		cond_resched();
	}
}

int __xipram qry_present(struct map_info *map, __u32 base,
				struct cfi_private *cfi);
int __xipram qry_mode_on(uint32_t base, struct map_info *map,
				struct cfi_private *cfi);
void __xipram qry_mode_off(uint32_t base, struct map_info *map,
				struct cfi_private *cfi);

struct cfi_extquery *cfi_read_pri(struct map_info *map, uint16_t adr, uint16_t size,
			     const char* name);
struct cfi_fixup {
	uint16_t mfr;
	uint16_t id;
	void (*fixup)(struct mtd_info *mtd, void* param);
	void* param;
};

#define CFI_MFR_ANY 0xffff
#define CFI_ID_ANY  0xffff

#define CFI_MFR_AMD 0x0001
#define CFI_MFR_ATMEL 0x001F
#define CFI_MFR_ST  0x0020 	/* STMicroelectronics */

void cfi_fixup(struct mtd_info *mtd, struct cfi_fixup* fixups);

typedef int (*varsize_frob_t)(struct map_info *map, struct flchip *chip,
			      unsigned long adr, int len, void *thunk);

int cfi_varsize_frob(struct mtd_info *mtd, varsize_frob_t frob,
	loff_t ofs, size_t len, void *thunk);


#endif /* __MTD_CFI_H__ */
Commit	Line	Data
1da177e4	1
61ecfa87	2	/* Common Flash Interface structures
1da177e4	3	* See http://support.intel.com/design/flash/technote/index.htm
1da177e4 LT	4	*/
	5
	6	#ifndef __MTD_CFI_H__
	7	#define __MTD_CFI_H__
	8
1da177e4 LT	9	#include <linux/delay.h>
	10	#include <linux/types.h>
	11	#include <linux/interrupt.h>
	12	#include <linux/mtd/flashchip.h>
	13	#include <linux/mtd/map.h>
	14	#include <linux/mtd/cfi_endian.h>
2e489e07	15	#include <linux/mtd/xip.h>
1da177e4 LT	16
	17	#ifdef CONFIG_MTD_CFI_I1
	18	#define cfi_interleave(cfi) 1
	19	#define cfi_interleave_is_1(cfi) (cfi_interleave(cfi) == 1)
	20	#else
	21	#define cfi_interleave_is_1(cfi) (0)
	22	#endif
	23
	24	#ifdef CONFIG_MTD_CFI_I2
	25	# ifdef cfi_interleave
	26	# undef cfi_interleave
	27	# define cfi_interleave(cfi) ((cfi)->interleave)
	28	# else
	29	# define cfi_interleave(cfi) 2
	30	# endif
	31	#define cfi_interleave_is_2(cfi) (cfi_interleave(cfi) == 2)
	32	#else
	33	#define cfi_interleave_is_2(cfi) (0)
	34	#endif
	35
	36	#ifdef CONFIG_MTD_CFI_I4
	37	# ifdef cfi_interleave
	38	# undef cfi_interleave
	39	# define cfi_interleave(cfi) ((cfi)->interleave)
	40	# else
	41	# define cfi_interleave(cfi) 4
	42	# endif
	43	#define cfi_interleave_is_4(cfi) (cfi_interleave(cfi) == 4)
	44	#else
	45	#define cfi_interleave_is_4(cfi) (0)
	46	#endif
	47
	48	#ifdef CONFIG_MTD_CFI_I8
	49	# ifdef cfi_interleave
	50	# undef cfi_interleave
	51	# define cfi_interleave(cfi) ((cfi)->interleave)
	52	# else
	53	# define cfi_interleave(cfi) 8
	54	# endif
	55	#define cfi_interleave_is_8(cfi) (cfi_interleave(cfi) == 8)
	56	#else
	57	#define cfi_interleave_is_8(cfi) (0)
	58	#endif
	59
241651d0 DW	60	#ifndef cfi_interleave
	61	#warning No CONFIG_MTD_CFI_Ix selected. No NOR chip support can work.
	62	static inline int cfi_interleave(void *cfi)
	63	{
	64	BUG();
	65	return 0;
	66	}
	67	#endif
	68
1da177e4 LT	69	static inline int cfi_interleave_supported(int i)
	70	{
	71	switch (i) {
	72	#ifdef CONFIG_MTD_CFI_I1
	73	case 1:
	74	#endif
	75	#ifdef CONFIG_MTD_CFI_I2
	76	case 2:
	77	#endif
	78	#ifdef CONFIG_MTD_CFI_I4
	79	case 4:
	80	#endif
	81	#ifdef CONFIG_MTD_CFI_I8
	82	case 8:
	83	#endif
	84	return 1;
	85
	86	default:
	87	return 0;
	88	}
	89	}
	90
	91
61ecfa87 TG	92	/* NB: these values must represents the number of bytes needed to meet the
61ecfa87 TG	93	* device type (x8, x16, x32). Eg. a 32 bit device is 4 x 8 bytes.
1da177e4 LT	94	* These numbers are used in calculations.
	95	*/
	96	#define CFI_DEVICETYPE_X8 (8 / 8)
	97	#define CFI_DEVICETYPE_X16 (16 / 8)
	98	#define CFI_DEVICETYPE_X32 (32 / 8)
	99	#define CFI_DEVICETYPE_X64 (64 / 8)
	100
de7921f0 BS	101
	102	/* Device Interface Code Assignments from the "Common Flash Memory Interface
	103	* Publication 100" dated December 1, 2001.
	104	*/
	105	#define CFI_INTERFACE_X8_ASYNC 0x0000
	106	#define CFI_INTERFACE_X16_ASYNC 0x0001
	107	#define CFI_INTERFACE_X8_BY_X16_ASYNC 0x0002
	108	#define CFI_INTERFACE_X32_ASYNC 0x0003
	109	#define CFI_INTERFACE_X16_BY_X32_ASYNC 0x0005
	110	#define CFI_INTERFACE_NOT_ALLOWED 0xffff
	111
	112
1da177e4 LT	113	/* NB: We keep these structures in memory in HOST byteorder, except
	114	* where individually noted.
	115	*/
	116
	117	/* Basic Query Structure */
	118	struct cfi_ident {
	119	uint8_t qry[3];
	120	uint16_t P_ID;
	121	uint16_t P_ADR;
	122	uint16_t A_ID;
	123	uint16_t A_ADR;
	124	uint8_t VccMin;
	125	uint8_t VccMax;
	126	uint8_t VppMin;
	127	uint8_t VppMax;
	128	uint8_t WordWriteTimeoutTyp;
	129	uint8_t BufWriteTimeoutTyp;
	130	uint8_t BlockEraseTimeoutTyp;
	131	uint8_t ChipEraseTimeoutTyp;
	132	uint8_t WordWriteTimeoutMax;
	133	uint8_t BufWriteTimeoutMax;
	134	uint8_t BlockEraseTimeoutMax;
	135	uint8_t ChipEraseTimeoutMax;
	136	uint8_t DevSize;
	137	uint16_t InterfaceDesc;
	138	uint16_t MaxBufWriteSize;
	139	uint8_t NumEraseRegions;
	140	uint32_t EraseRegionInfo[0]; /* Not host ordered */
	141	} __attribute__((packed));
	142
	143	/* Extended Query Structure for both PRI and ALT */
	144
	145	struct cfi_extquery {
	146	uint8_t pri[3];
	147	uint8_t MajorVersion;
	148	uint8_t MinorVersion;
	149	} __attribute__((packed));
	150
	151	/* Vendor-Specific PRI for Intel/Sharp Extended Command Set (0x0001) */
	152
	153	struct cfi_pri_intelext {
	154	uint8_t pri[3];
	155	uint8_t MajorVersion;
	156	uint8_t MinorVersion;
	157	uint32_t FeatureSupport; /* if bit 31 is set then an additional uint32_t feature
	158	block follows - FIXME - not currently supported */
	159	uint8_t SuspendCmdSupport;
	160	uint16_t BlkStatusRegMask;
	161	uint8_t VccOptimal;
	162	uint8_t VppOptimal;
	163	uint8_t NumProtectionFields;
	164	uint16_t ProtRegAddr;
	165	uint8_t FactProtRegSize;
	166	uint8_t UserProtRegSize;
	167	uint8_t extra[0];
	168	} __attribute__((packed));
	169
72b56a2d NP	170	struct cfi_intelext_otpinfo {
	171	uint32_t ProtRegAddr;
	172	uint16_t FactGroups;
	173	uint8_t FactProtRegSize;
	174	uint16_t UserGroups;
	175	uint8_t UserProtRegSize;
	176	} __attribute__((packed));
	177
1da177e4 LT	178	struct cfi_intelext_blockinfo {
	179	uint16_t NumIdentBlocks;
	180	uint16_t BlockSize;
	181	uint16_t MinBlockEraseCycles;
	182	uint8_t BitsPerCell;
	183	uint8_t BlockCap;
	184	} __attribute__((packed));
	185
	186	struct cfi_intelext_regioninfo {
	187	uint16_t NumIdentPartitions;
	188	uint8_t NumOpAllowed;
	189	uint8_t NumOpAllowedSimProgMode;
	190	uint8_t NumOpAllowedSimEraMode;
	191	uint8_t NumBlockTypes;
	192	struct cfi_intelext_blockinfo BlockTypes[1];
	193	} __attribute__((packed));
	194
638d9838 NP	195	struct cfi_intelext_programming_regioninfo {
	196	uint8_t ProgRegShift;
	197	uint8_t Reserved1;
	198	uint8_t ControlValid;
	199	uint8_t Reserved2;
	200	uint8_t ControlInvalid;
	201	uint8_t Reserved3;
	202	} __attribute__((packed));
	203
1da177e4 LT	204	/* Vendor-Specific PRI for AMD/Fujitsu Extended Command Set (0x0002) */
	205
	206	struct cfi_pri_amdstd {
	207	uint8_t pri[3];
	208	uint8_t MajorVersion;
	209	uint8_t MinorVersion;
	210	uint8_t SiliconRevision; /* bits 1-0: Address Sensitive Unlock */
	211	uint8_t EraseSuspend;
	212	uint8_t BlkProt;
	213	uint8_t TmpBlkUnprotect;
	214	uint8_t BlkProtUnprot;
	215	uint8_t SimultaneousOps;
	216	uint8_t BurstMode;
	217	uint8_t PageMode;
	218	uint8_t VppMin;
	219	uint8_t VppMax;
	220	uint8_t TopBottom;
	221	} __attribute__((packed));
	222
5b0c5c2c HS	223	/* Vendor-Specific PRI for Atmel chips (command set 0x0002) */
	224
	225	struct cfi_pri_atmel {
	226	uint8_t pri[3];
	227	uint8_t MajorVersion;
	228	uint8_t MinorVersion;
	229	uint8_t Features;
	230	uint8_t BottomBoot;
	231	uint8_t BurstMode;
	232	uint8_t PageMode;
	233	} __attribute__((packed));
	234
1da177e4 LT	235	struct cfi_pri_query {
	236	uint8_t NumFields;
	237	uint32_t ProtField[1]; /* Not host ordered */
	238	} __attribute__((packed));
	239
	240	struct cfi_bri_query {
	241	uint8_t PageModeReadCap;
	242	uint8_t NumFields;
	243	uint32_t ConfField[1]; /* Not host ordered */
	244	} __attribute__((packed));
	245
	246	#define P_ID_NONE 0x0000
	247	#define P_ID_INTEL_EXT 0x0001
	248	#define P_ID_AMD_STD 0x0002
	249	#define P_ID_INTEL_STD 0x0003
	250	#define P_ID_AMD_EXT 0x0004
	251	#define P_ID_WINBOND 0x0006
	252	#define P_ID_ST_ADV 0x0020
	253	#define P_ID_MITSUBISHI_STD 0x0100
	254	#define P_ID_MITSUBISHI_EXT 0x0101
	255	#define P_ID_SST_PAGE 0x0102
	256	#define P_ID_INTEL_PERFORMANCE 0x0200
	257	#define P_ID_INTEL_DATA 0x0210
	258	#define P_ID_RESERVED 0xffff
	259
	260
	261	#define CFI_MODE_CFI 1
	262	#define CFI_MODE_JEDEC 0
	263
	264	struct cfi_private {
	265	uint16_t cmdset;
	266	void *cmdset_priv;
	267	int interleave;
	268	int device_type;
	269	int cfi_mode; /* Are we a JEDEC device pretending to be CFI? */
	270	int addr_unlock1;
	271	int addr_unlock2;
	272	struct mtd_info (cmdset_setup)(struct map_info *);
	273	struct cfi_ident cfiq; / For now only one. We insist that all devs
	274	must be of the same type. */
	275	int mfr, id;
	276	int numchips;
	277	unsigned long chipshift; /* Because they're of the same type */
	278	const char im_name; / inter_module name for cmdset_setup */
	279	struct flchip chips[0]; /* per-chip data structure for each chip */
	280	};
	281
	282	/*
	283	* Returns the command address according to the given geometry.
	284	*/
	285	static inline uint32_t cfi_build_cmd_addr(uint32_t cmd_ofs, int interleave, int type)
	286	{
	287	return (cmd_ofs * type) * interleave;
	288	}
	289
	290	/*
	291	* Transforms the CFI command for the given geometry (bus width & interleave).
	292	* It looks too long to be inline, but in the common case it should almost all
61ecfa87	293	* get optimised away.
1da177e4	294	*/
f77814dd	295	static inline map_word cfi_build_cmd(u_long cmd, struct map_info map, struct cfi_private cfi)
1da177e4 LT	296	{
	297	map_word val = { {0} };
	298	int wordwidth, words_per_bus, chip_mode, chips_per_word;
	299	unsigned long onecmd;
	300	int i;
	301
61ecfa87	302	/* We do it this way to give the compiler a fighting chance
1da177e4 LT	303	of optimising away all the crap for 'bankwidth' larger than
	304	an unsigned long, in the common case where that support is
	305	disabled */
	306	if (map_bankwidth_is_large(map)) {
	307	wordwidth = sizeof(unsigned long);
	308	words_per_bus = (map_bankwidth(map)) / wordwidth; // i.e. normally 1
	309	} else {
	310	wordwidth = map_bankwidth(map);
	311	words_per_bus = 1;
	312	}
61ecfa87	313
1da177e4 LT	314	chip_mode = map_bankwidth(map) / cfi_interleave(cfi);
	315	chips_per_word = wordwidth * cfi_interleave(cfi) / map_bankwidth(map);
	316
	317	/* First, determine what the bit-pattern should be for a single
	318	device, according to chip mode and endianness... */
	319	switch (chip_mode) {
	320	default: BUG();
	321	case 1:
	322	onecmd = cmd;
	323	break;
	324	case 2:
	325	onecmd = cpu_to_cfi16(cmd);
	326	break;
	327	case 4:
	328	onecmd = cpu_to_cfi32(cmd);
	329	break;
	330	}
	331
61ecfa87	332	/* Now replicate it across the size of an unsigned long, or
1da177e4 LT	333	just to the bus width as appropriate */
	334	switch (chips_per_word) {
	335	default: BUG();
	336	#if BITS_PER_LONG >= 64
	337	case 8:
	338	onecmd \|= (onecmd << (chip_mode * 32));
	339	#endif
	340	case 4:
	341	onecmd \|= (onecmd << (chip_mode * 16));
	342	case 2:
	343	onecmd \|= (onecmd << (chip_mode * 8));
	344	case 1:
	345	;
	346	}
	347
61ecfa87	348	/* And finally, for the multi-word case, replicate it
1da177e4 LT	349	in all words in the structure */
	350	for (i=0; i < words_per_bus; i++) {
	351	val.x[i] = onecmd;
	352	}
	353
	354	return val;
	355	}
	356	#define CMD(x) cfi_build_cmd((x), map, cfi)
	357
c927cd3a	358
61ecfa87	359	static inline unsigned long cfi_merge_status(map_word val, struct map_info *map,
c927cd3a TG	360	struct cfi_private *cfi)
	361	{
	362	int wordwidth, words_per_bus, chip_mode, chips_per_word;
	363	unsigned long onestat, res = 0;
	364	int i;
	365
61ecfa87	366	/* We do it this way to give the compiler a fighting chance
c927cd3a TG	367	of optimising away all the crap for 'bankwidth' larger than
	368	an unsigned long, in the common case where that support is
	369	disabled */
	370	if (map_bankwidth_is_large(map)) {
	371	wordwidth = sizeof(unsigned long);
	372	words_per_bus = (map_bankwidth(map)) / wordwidth; // i.e. normally 1
	373	} else {
	374	wordwidth = map_bankwidth(map);
	375	words_per_bus = 1;
	376	}
61ecfa87	377
c927cd3a TG	378	chip_mode = map_bankwidth(map) / cfi_interleave(cfi);
	379	chips_per_word = wordwidth * cfi_interleave(cfi) / map_bankwidth(map);
	380
	381	onestat = val.x[0];
	382	/* Or all status words together */
	383	for (i=1; i < words_per_bus; i++) {
	384	onestat \|= val.x[i];
	385	}
	386
	387	res = onestat;
	388	switch(chips_per_word) {
	389	default: BUG();
	390	#if BITS_PER_LONG >= 64
	391	case 8:
	392	res \|= (onestat >> (chip_mode * 32));
	393	#endif
	394	case 4:
	395	res \|= (onestat >> (chip_mode * 16));
	396	case 2:
	397	res \|= (onestat >> (chip_mode * 8));
	398	case 1:
	399	;
	400	}
	401
	402	/* Last, determine what the bit-pattern should be for a single
	403	device, according to chip mode and endianness... */
	404	switch (chip_mode) {
	405	case 1:
	406	break;
	407	case 2:
	408	res = cfi16_to_cpu(res);
	409	break;
	410	case 4:
	411	res = cfi32_to_cpu(res);
	412	break;
	413	default: BUG();
	414	}
	415	return res;
	416	}
	417
	418	#define MERGESTATUS(x) cfi_merge_status((x), map, cfi)
	419
	420
1da177e4 LT	421	/*
	422	* Sends a CFI command to a bank of flash for the given geometry.
	423	*
	424	* Returns the offset in flash where the command was written.
	425	* If prev_val is non-null, it will be set to the value at the command address,
	426	* before the command was written.
	427	*/
	428	static inline uint32_t cfi_send_gen_cmd(u_char cmd, uint32_t cmd_addr, uint32_t base,
	429	struct map_info map, struct cfi_private cfi,
	430	int type, map_word *prev_val)
	431	{
	432	map_word val;
	433	uint32_t addr = base + cfi_build_cmd_addr(cmd_addr, cfi_interleave(cfi), type);
1da177e4 LT	434	val = cfi_build_cmd(cmd, map, cfi);
	435
	436	if (prev_val)
	437	*prev_val = map_read(map, addr);
	438
	439	map_write(map, val, addr);
	440
	441	return addr - base;
	442	}
	443
	444	static inline uint8_t cfi_read_query(struct map_info *map, uint32_t addr)
	445	{
	446	map_word val = map_read(map, addr);
	447
	448	if (map_bankwidth_is_1(map)) {
	449	return val.x[0];
	450	} else if (map_bankwidth_is_2(map)) {
	451	return cfi16_to_cpu(val.x[0]);
987d2401 TP	452	} else {
	453	/* No point in a 64-bit byteswap since that would just be
	454	swapping the responses from different chips, and we are
	455	only interested in one chip (a representative sample) */
	456	return cfi32_to_cpu(val.x[0]);
	457	}
	458	}
	459
	460	static inline uint16_t cfi_read_query16(struct map_info *map, uint32_t addr)
	461	{
	462	map_word val = map_read(map, addr);
	463
	464	if (map_bankwidth_is_1(map)) {
	465	return val.x[0] & 0xff;
	466	} else if (map_bankwidth_is_2(map)) {
	467	return cfi16_to_cpu(val.x[0]);
1da177e4 LT	468	} else {
	469	/* No point in a 64-bit byteswap since that would just be
	470	swapping the responses from different chips, and we are
	471	only interested in one chip (a representative sample) */
	472	return cfi32_to_cpu(val.x[0]);
	473	}
	474	}
	475
	476	static inline void cfi_udelay(int us)
	477	{
	478	if (us >= 1000) {
	479	msleep((us+999)/1000);
	480	} else {
	481	udelay(us);
	482	cond_resched();
	483	}
	484	}
	485
2e489e07 AK	486	int __xipram qry_present(struct map_info *map, __u32 base,
	487	struct cfi_private *cfi);
	488	int __xipram qry_mode_on(uint32_t base, struct map_info *map,
	489	struct cfi_private *cfi);
	490	void __xipram qry_mode_off(uint32_t base, struct map_info *map,
	491	struct cfi_private *cfi);
	492
1da177e4 LT	493	struct cfi_extquery cfi_read_pri(struct map_info map, uint16_t adr, uint16_t size,
	494	const char* name);
	495	struct cfi_fixup {
	496	uint16_t mfr;
	497	uint16_t id;
	498	void (fixup)(struct mtd_info mtd, void* param);
	499	void* param;
	500	};
	501
	502	#define CFI_MFR_ANY 0xffff
	503	#define CFI_ID_ANY 0xffff
	504
	505	#define CFI_MFR_AMD 0x0001
5b0c5c2c	506	#define CFI_MFR_ATMEL 0x001F
1da177e4 LT	507	#define CFI_MFR_ST 0x0020 /* STMicroelectronics */
	508
	509	void cfi_fixup(struct mtd_info mtd, struct cfi_fixup fixups);
	510
	511	typedef int (varsize_frob_t)(struct map_info map, struct flchip *chip,
	512	unsigned long adr, int len, void *thunk);
	513
	514	int cfi_varsize_frob(struct mtd_info *mtd, varsize_frob_t frob,
	515	loff_t ofs, size_t len, void *thunk);
	516
	517
	518	#endif /* __MTD_CFI_H__ */