[mirror_ubuntu-artful-kernel.git] / include / linux / mtd / fsmc.h

/*
 * incude/mtd/fsmc.h
 *
 * ST Microelectronics
 * Flexible Static Memory Controller (FSMC)
 * platform data interface and header file
 *
 * Copyright © 2010 ST Microelectronics
 * Vipin Kumar <vipin.kumar@st.com>
 *
 * This file is licensed under the terms of the GNU General Public
 * License version 2. This program is licensed "as is" without any
 * warranty of any kind, whether express or implied.
 */

#ifndef __MTD_FSMC_H
#define __MTD_FSMC_H

#include <linux/io.h>
#include <linux/platform_device.h>
#include <linux/mtd/physmap.h>
#include <linux/types.h>
#include <linux/mtd/partitions.h>
#include <asm/param.h>

#define FSMC_NAND_BW8		1
#define FSMC_NAND_BW16		2

#define FSMC_MAX_NOR_BANKS	4
#define FSMC_MAX_NAND_BANKS	4

#define FSMC_FLASH_WIDTH8	1
#define FSMC_FLASH_WIDTH16	2

/* fsmc controller registers for NOR flash */
#define CTRL			0x0
	/* ctrl register definitions */
	#define BANK_ENABLE		(1 << 0)
	#define MUXED			(1 << 1)
	#define NOR_DEV			(2 << 2)
	#define WIDTH_8			(0 << 4)
	#define WIDTH_16		(1 << 4)
	#define RSTPWRDWN		(1 << 6)
	#define WPROT			(1 << 7)
	#define WRT_ENABLE		(1 << 12)
	#define WAIT_ENB		(1 << 13)

#define CTRL_TIM		0x4
	/* ctrl_tim register definitions */

#define FSMC_NOR_BANK_SZ	0x8
#define FSMC_NOR_REG_SIZE	0x40

#define FSMC_NOR_REG(base, bank, reg)		(base + \
						FSMC_NOR_BANK_SZ * (bank) + \
						reg)

/* fsmc controller registers for NAND flash */
#define PC			0x00
	/* pc register definitions */
	#define FSMC_RESET		(1 << 0)
	#define FSMC_WAITON		(1 << 1)
	#define FSMC_ENABLE		(1 << 2)
	#define FSMC_DEVTYPE_NAND	(1 << 3)
	#define FSMC_DEVWID_8		(0 << 4)
	#define FSMC_DEVWID_16		(1 << 4)
	#define FSMC_ECCEN		(1 << 6)
	#define FSMC_ECCPLEN_512	(0 << 7)
	#define FSMC_ECCPLEN_256	(1 << 7)
	#define FSMC_TCLR_1		(1)
	#define FSMC_TCLR_SHIFT		(9)
	#define FSMC_TCLR_MASK		(0xF)
	#define FSMC_TAR_1		(1)
	#define FSMC_TAR_SHIFT		(13)
	#define FSMC_TAR_MASK		(0xF)
#define STS			0x04
	/* sts register definitions */
	#define FSMC_CODE_RDY		(1 << 15)
#define COMM			0x08
	/* comm register definitions */
	#define FSMC_TSET_0		0
	#define FSMC_TSET_SHIFT		0
	#define FSMC_TSET_MASK		0xFF
	#define FSMC_TWAIT_6		6
	#define FSMC_TWAIT_SHIFT	8
	#define FSMC_TWAIT_MASK		0xFF
	#define FSMC_THOLD_4		4
	#define FSMC_THOLD_SHIFT	16
	#define FSMC_THOLD_MASK		0xFF
	#define FSMC_THIZ_1		1
	#define FSMC_THIZ_SHIFT		24
	#define FSMC_THIZ_MASK		0xFF
#define ATTRIB			0x0C
#define IOATA			0x10
#define ECC1			0x14
#define ECC2			0x18
#define ECC3			0x1C
#define FSMC_NAND_BANK_SZ	0x20

#define FSMC_NAND_REG(base, bank, reg)		(base + FSMC_NOR_REG_SIZE + \
						(FSMC_NAND_BANK_SZ * (bank)) + \
						reg)

#define FSMC_BUSY_WAIT_TIMEOUT	(1 * HZ)

/*
 * There are 13 bytes of ecc for every 512 byte block in FSMC version 8
 * and it has to be read consecutively and immediately after the 512
 * byte data block for hardware to generate the error bit offsets
 * Managing the ecc bytes in the following way is easier. This way is
 * similar to oobfree structure maintained already in u-boot nand driver
 */
#define MAX_ECCPLACE_ENTRIES	32

struct fsmc_nand_eccplace {
	uint8_t offset;
	uint8_t length;
};

struct fsmc_eccplace {
	struct fsmc_nand_eccplace eccplace[MAX_ECCPLACE_ENTRIES];
};

struct fsmc_nand_timings {
	uint8_t tclr;
	uint8_t tar;
	uint8_t thiz;
	uint8_t thold;
	uint8_t twait;
	uint8_t tset;
};

enum access_mode {
	USE_DMA_ACCESS = 1,
	USE_WORD_ACCESS,
};

/**
 * fsmc_nand_platform_data - platform specific NAND controller config
 * @partitions: partition table for the platform, use a default fallback
 * if this is NULL
 * @nr_partitions: the number of partitions in the previous entry
 * @options: different options for the driver
 * @width: bus width
 * @bank: default bank
 * @select_bank: callback to select a certain bank, this is
 * platform-specific. If the controller only supports one bank
 * this may be set to NULL
 */
struct fsmc_nand_platform_data {
	struct fsmc_nand_timings *nand_timings;
	struct mtd_partition	*partitions;
	unsigned int		nr_partitions;
	unsigned int		options;
	unsigned int		width;
	unsigned int		bank;

	enum access_mode	mode;

	void			(*select_bank)(uint32_t bank, uint32_t busw);

	/* priv structures for dma accesses */
	void			*read_dma_priv;
	void			*write_dma_priv;
};

extern int __init fsmc_nor_init(struct platform_device *pdev,
		unsigned long base, uint32_t bank, uint32_t width);
extern void __init fsmc_init_board_info(struct platform_device *pdev,
		struct mtd_partition *partitions, unsigned int nr_partitions,
		unsigned int width);

#endif /* __MTD_FSMC_H */
Commit	Line	Data
6c009ab8 LW	1	/*
	2	* incude/mtd/fsmc.h
	3	*
	4	* ST Microelectronics
	5	* Flexible Static Memory Controller (FSMC)
	6	* platform data interface and header file
	7	*
	8	* Copyright © 2010 ST Microelectronics
	9	* Vipin Kumar <vipin.kumar@st.com>
	10	*
	11	* This file is licensed under the terms of the GNU General Public
	12	* License version 2. This program is licensed "as is" without any
	13	* warranty of any kind, whether express or implied.
	14	*/
	15
	16	#ifndef __MTD_FSMC_H
	17	#define __MTD_FSMC_H
	18
65ab220c	19	#include <linux/io.h>
6c009ab8 LW	20	#include <linux/platform_device.h>
	21	#include <linux/mtd/physmap.h>
	22	#include <linux/types.h>
	23	#include <linux/mtd/partitions.h>
	24	#include <asm/param.h>
	25
	26	#define FSMC_NAND_BW8 1
	27	#define FSMC_NAND_BW16 2
	28
6c009ab8 LW	29	#define FSMC_MAX_NOR_BANKS 4
	30	#define FSMC_MAX_NAND_BANKS 4
	31
	32	#define FSMC_FLASH_WIDTH8 1
	33	#define FSMC_FLASH_WIDTH16 2
	34
2a5dbead VK	35	/* fsmc controller registers for NOR flash */
	36	#define CTRL 0x0
	37	/* ctrl register definitions */
	38	#define BANK_ENABLE (1 << 0)
	39	#define MUXED (1 << 1)
	40	#define NOR_DEV (2 << 2)
	41	#define WIDTH_8 (0 << 4)
	42	#define WIDTH_16 (1 << 4)
	43	#define RSTPWRDWN (1 << 6)
	44	#define WPROT (1 << 7)
	45	#define WRT_ENABLE (1 << 12)
	46	#define WAIT_ENB (1 << 13)
	47
	48	#define CTRL_TIM 0x4
	49	/* ctrl_tim register definitions */
	50
	51	#define FSMC_NOR_BANK_SZ 0x8
6c009ab8 LW	52	#define FSMC_NOR_REG_SIZE 0x40
6c009ab8 LW	53
2a5dbead VK	54	#define FSMC_NOR_REG(base, bank, reg) (base + \
	55	FSMC_NOR_BANK_SZ * (bank) + \
	56	reg)
	57
	58	/* fsmc controller registers for NAND flash */
	59	#define PC 0x00
	60	/* pc register definitions */
	61	#define FSMC_RESET (1 << 0)
	62	#define FSMC_WAITON (1 << 1)
	63	#define FSMC_ENABLE (1 << 2)
	64	#define FSMC_DEVTYPE_NAND (1 << 3)
	65	#define FSMC_DEVWID_8 (0 << 4)
	66	#define FSMC_DEVWID_16 (1 << 4)
	67	#define FSMC_ECCEN (1 << 6)
	68	#define FSMC_ECCPLEN_512 (0 << 7)
	69	#define FSMC_ECCPLEN_256 (1 << 7)
	70	#define FSMC_TCLR_1 (1)
	71	#define FSMC_TCLR_SHIFT (9)
	72	#define FSMC_TCLR_MASK (0xF)
	73	#define FSMC_TAR_1 (1)
	74	#define FSMC_TAR_SHIFT (13)
	75	#define FSMC_TAR_MASK (0xF)
	76	#define STS 0x04
	77	/* sts register definitions */
	78	#define FSMC_CODE_RDY (1 << 15)
	79	#define COMM 0x08
	80	/* comm register definitions */
	81	#define FSMC_TSET_0 0
	82	#define FSMC_TSET_SHIFT 0
	83	#define FSMC_TSET_MASK 0xFF
	84	#define FSMC_TWAIT_6 6
	85	#define FSMC_TWAIT_SHIFT 8
	86	#define FSMC_TWAIT_MASK 0xFF
	87	#define FSMC_THOLD_4 4
	88	#define FSMC_THOLD_SHIFT 16
	89	#define FSMC_THOLD_MASK 0xFF
	90	#define FSMC_THIZ_1 1
	91	#define FSMC_THIZ_SHIFT 24
	92	#define FSMC_THIZ_MASK 0xFF
	93	#define ATTRIB 0x0C
	94	#define IOATA 0x10
	95	#define ECC1 0x14
	96	#define ECC2 0x18
	97	#define ECC3 0x1C
	98	#define FSMC_NAND_BANK_SZ 0x20
	99
	100	#define FSMC_NAND_REG(base, bank, reg) (base + FSMC_NOR_REG_SIZE + \
	101	(FSMC_NAND_BANK_SZ * (bank)) + \
	102	reg)
6c009ab8 LW	103
	104	#define FSMC_BUSY_WAIT_TIMEOUT (1 * HZ)
	105
6c009ab8 LW	106	/*
	107	* There are 13 bytes of ecc for every 512 byte block in FSMC version 8
	108	* and it has to be read consecutively and immediately after the 512
	109	* byte data block for hardware to generate the error bit offsets
	110	* Managing the ecc bytes in the following way is easier. This way is
	111	* similar to oobfree structure maintained already in u-boot nand driver
	112	*/
	113	#define MAX_ECCPLACE_ENTRIES 32
	114
	115	struct fsmc_nand_eccplace {
	116	uint8_t offset;
	117	uint8_t length;
	118	};
	119
	120	struct fsmc_eccplace {
	121	struct fsmc_nand_eccplace eccplace[MAX_ECCPLACE_ENTRIES];
	122	};
	123
e2f6bce8 VK	124	struct fsmc_nand_timings {
	125	uint8_t tclr;
	126	uint8_t tar;
	127	uint8_t thiz;
	128	uint8_t thold;
	129	uint8_t twait;
	130	uint8_t tset;
	131	};
	132
604e7544 VK	133	enum access_mode {
	134	USE_DMA_ACCESS = 1,
	135	USE_WORD_ACCESS,
	136	};
	137
6c009ab8 LW	138	/**
	139	* fsmc_nand_platform_data - platform specific NAND controller config
	140	* @partitions: partition table for the platform, use a default fallback
	141	* if this is NULL
	142	* @nr_partitions: the number of partitions in the previous entry
	143	* @options: different options for the driver
	144	* @width: bus width
	145	* @bank: default bank
	146	* @select_bank: callback to select a certain bank, this is
	147	* platform-specific. If the controller only supports one bank
	148	* this may be set to NULL
	149	*/
	150	struct fsmc_nand_platform_data {
e2f6bce8	151	struct fsmc_nand_timings *nand_timings;
6c009ab8 LW	152	struct mtd_partition *partitions;
	153	unsigned int nr_partitions;
	154	unsigned int options;
	155	unsigned int width;
	156	unsigned int bank;
b2acc92e	157
604e7544	158	enum access_mode mode;
b2acc92e	159
6c009ab8	160	void (*select_bank)(uint32_t bank, uint32_t busw);
4774fb0a VK	161
	162	/* priv structures for dma accesses */
	163	void *read_dma_priv;
	164	void *write_dma_priv;
6c009ab8 LW	165	};
	166
	167	extern int __init fsmc_nor_init(struct platform_device *pdev,
	168	unsigned long base, uint32_t bank, uint32_t width);
	169	extern void __init fsmc_init_board_info(struct platform_device *pdev,
	170	struct mtd_partition *partitions, unsigned int nr_partitions,
	171	unsigned int width);
	172
	173	#endif /* __MTD_FSMC_H */