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1da177e4 LT |
1 | /* |
2 | * linux/include/linux/mtd/nand.h | |
3 | * | |
4 | * Copyright (c) 2000 David Woodhouse <dwmw2@mvhi.com> | |
5 | * Steven J. Hill <sjhill@realitydiluted.com> | |
6 | * Thomas Gleixner <tglx@linutronix.de> | |
7 | * | |
962034f4 | 8 | * $Id: nand.h,v 1.74 2005/09/15 13:58:50 vwool Exp $ |
1da177e4 LT |
9 | * |
10 | * This program is free software; you can redistribute it and/or modify | |
11 | * it under the terms of the GNU General Public License version 2 as | |
12 | * published by the Free Software Foundation. | |
13 | * | |
2c0a2bed TG |
14 | * Info: |
15 | * Contains standard defines and IDs for NAND flash devices | |
1da177e4 | 16 | * |
2c0a2bed TG |
17 | * Changelog: |
18 | * See git changelog. | |
1da177e4 LT |
19 | */ |
20 | #ifndef __LINUX_MTD_NAND_H | |
21 | #define __LINUX_MTD_NAND_H | |
22 | ||
23 | #include <linux/config.h> | |
24 | #include <linux/wait.h> | |
25 | #include <linux/spinlock.h> | |
26 | #include <linux/mtd/mtd.h> | |
27 | ||
28 | struct mtd_info; | |
29 | /* Scan and identify a NAND device */ | |
30 | extern int nand_scan (struct mtd_info *mtd, int max_chips); | |
31 | /* Free resources held by the NAND device */ | |
32 | extern void nand_release (struct mtd_info *mtd); | |
33 | ||
34 | /* Read raw data from the device without ECC */ | |
2c0a2bed TG |
35 | extern int nand_read_raw (struct mtd_info *mtd, uint8_t *buf, loff_t from, |
36 | size_t len, size_t ooblen); | |
1da177e4 LT |
37 | |
38 | ||
9223a456 TG |
39 | extern int nand_write_raw(struct mtd_info *mtd, loff_t to, size_t len, |
40 | size_t *retlen, uint8_t *buf, uint8_t *oob); | |
41 | ||
1da177e4 LT |
42 | /* The maximum number of NAND chips in an array */ |
43 | #define NAND_MAX_CHIPS 8 | |
44 | ||
45 | /* This constant declares the max. oobsize / page, which | |
46 | * is supported now. If you add a chip with bigger oobsize/page | |
47 | * adjust this accordingly. | |
48 | */ | |
49 | #define NAND_MAX_OOBSIZE 64 | |
50 | ||
51 | /* | |
52 | * Constants for hardware specific CLE/ALE/NCE function | |
7abd3ef9 TG |
53 | * |
54 | * These are bits which can be or'ed to set/clear multiple | |
55 | * bits in one go. | |
56 | */ | |
1da177e4 | 57 | /* Select the chip by setting nCE to low */ |
7abd3ef9 | 58 | #define NAND_NCE 0x01 |
1da177e4 | 59 | /* Select the command latch by setting CLE to high */ |
7abd3ef9 | 60 | #define NAND_CLE 0x02 |
1da177e4 | 61 | /* Select the address latch by setting ALE to high */ |
7abd3ef9 TG |
62 | #define NAND_ALE 0x04 |
63 | ||
64 | #define NAND_CTRL_CLE (NAND_NCE | NAND_CLE) | |
65 | #define NAND_CTRL_ALE (NAND_NCE | NAND_ALE) | |
66 | #define NAND_CTRL_CHANGE 0x80 | |
1da177e4 LT |
67 | |
68 | /* | |
69 | * Standard NAND flash commands | |
70 | */ | |
71 | #define NAND_CMD_READ0 0 | |
72 | #define NAND_CMD_READ1 1 | |
73 | #define NAND_CMD_PAGEPROG 0x10 | |
74 | #define NAND_CMD_READOOB 0x50 | |
75 | #define NAND_CMD_ERASE1 0x60 | |
76 | #define NAND_CMD_STATUS 0x70 | |
77 | #define NAND_CMD_STATUS_MULTI 0x71 | |
78 | #define NAND_CMD_SEQIN 0x80 | |
79 | #define NAND_CMD_READID 0x90 | |
80 | #define NAND_CMD_ERASE2 0xd0 | |
81 | #define NAND_CMD_RESET 0xff | |
82 | ||
83 | /* Extended commands for large page devices */ | |
84 | #define NAND_CMD_READSTART 0x30 | |
85 | #define NAND_CMD_CACHEDPROG 0x15 | |
86 | ||
28a48de7 | 87 | /* Extended commands for AG-AND device */ |
61ecfa87 TG |
88 | /* |
89 | * Note: the command for NAND_CMD_DEPLETE1 is really 0x00 but | |
28a48de7 DM |
90 | * there is no way to distinguish that from NAND_CMD_READ0 |
91 | * until the remaining sequence of commands has been completed | |
92 | * so add a high order bit and mask it off in the command. | |
93 | */ | |
94 | #define NAND_CMD_DEPLETE1 0x100 | |
95 | #define NAND_CMD_DEPLETE2 0x38 | |
96 | #define NAND_CMD_STATUS_MULTI 0x71 | |
97 | #define NAND_CMD_STATUS_ERROR 0x72 | |
98 | /* multi-bank error status (banks 0-3) */ | |
99 | #define NAND_CMD_STATUS_ERROR0 0x73 | |
100 | #define NAND_CMD_STATUS_ERROR1 0x74 | |
101 | #define NAND_CMD_STATUS_ERROR2 0x75 | |
102 | #define NAND_CMD_STATUS_ERROR3 0x76 | |
103 | #define NAND_CMD_STATUS_RESET 0x7f | |
104 | #define NAND_CMD_STATUS_CLEAR 0xff | |
105 | ||
7abd3ef9 TG |
106 | #define NAND_CMD_NONE -1 |
107 | ||
1da177e4 LT |
108 | /* Status bits */ |
109 | #define NAND_STATUS_FAIL 0x01 | |
110 | #define NAND_STATUS_FAIL_N1 0x02 | |
111 | #define NAND_STATUS_TRUE_READY 0x20 | |
112 | #define NAND_STATUS_READY 0x40 | |
113 | #define NAND_STATUS_WP 0x80 | |
114 | ||
61ecfa87 | 115 | /* |
1da177e4 LT |
116 | * Constants for ECC_MODES |
117 | */ | |
6dfc6d25 TG |
118 | typedef enum { |
119 | NAND_ECC_NONE, | |
120 | NAND_ECC_SOFT, | |
121 | NAND_ECC_HW, | |
122 | NAND_ECC_HW_SYNDROME, | |
123 | } nand_ecc_modes_t; | |
1da177e4 LT |
124 | |
125 | /* | |
126 | * Constants for Hardware ECC | |
068e3c0a | 127 | */ |
1da177e4 LT |
128 | /* Reset Hardware ECC for read */ |
129 | #define NAND_ECC_READ 0 | |
130 | /* Reset Hardware ECC for write */ | |
131 | #define NAND_ECC_WRITE 1 | |
132 | /* Enable Hardware ECC before syndrom is read back from flash */ | |
133 | #define NAND_ECC_READSYN 2 | |
134 | ||
068e3c0a DM |
135 | /* Bit mask for flags passed to do_nand_read_ecc */ |
136 | #define NAND_GET_DEVICE 0x80 | |
137 | ||
138 | ||
1da177e4 LT |
139 | /* Option constants for bizarre disfunctionality and real |
140 | * features | |
141 | */ | |
142 | /* Chip can not auto increment pages */ | |
143 | #define NAND_NO_AUTOINCR 0x00000001 | |
144 | /* Buswitdh is 16 bit */ | |
145 | #define NAND_BUSWIDTH_16 0x00000002 | |
146 | /* Device supports partial programming without padding */ | |
147 | #define NAND_NO_PADDING 0x00000004 | |
148 | /* Chip has cache program function */ | |
149 | #define NAND_CACHEPRG 0x00000008 | |
150 | /* Chip has copy back function */ | |
151 | #define NAND_COPYBACK 0x00000010 | |
61ecfa87 | 152 | /* AND Chip which has 4 banks and a confusing page / block |
1da177e4 LT |
153 | * assignment. See Renesas datasheet for further information */ |
154 | #define NAND_IS_AND 0x00000020 | |
155 | /* Chip has a array of 4 pages which can be read without | |
156 | * additional ready /busy waits */ | |
61ecfa87 | 157 | #define NAND_4PAGE_ARRAY 0x00000040 |
28a48de7 DM |
158 | /* Chip requires that BBT is periodically rewritten to prevent |
159 | * bits from adjacent blocks from 'leaking' in altering data. | |
160 | * This happens with the Renesas AG-AND chips, possibly others. */ | |
161 | #define BBT_AUTO_REFRESH 0x00000080 | |
1da177e4 LT |
162 | |
163 | /* Options valid for Samsung large page devices */ | |
164 | #define NAND_SAMSUNG_LP_OPTIONS \ | |
165 | (NAND_NO_PADDING | NAND_CACHEPRG | NAND_COPYBACK) | |
166 | ||
167 | /* Macros to identify the above */ | |
168 | #define NAND_CANAUTOINCR(chip) (!(chip->options & NAND_NO_AUTOINCR)) | |
169 | #define NAND_MUST_PAD(chip) (!(chip->options & NAND_NO_PADDING)) | |
170 | #define NAND_HAS_CACHEPROG(chip) ((chip->options & NAND_CACHEPRG)) | |
171 | #define NAND_HAS_COPYBACK(chip) ((chip->options & NAND_COPYBACK)) | |
172 | ||
173 | /* Mask to zero out the chip options, which come from the id table */ | |
174 | #define NAND_CHIPOPTIONS_MSK (0x0000ffff & ~NAND_NO_AUTOINCR) | |
175 | ||
176 | /* Non chip related options */ | |
177 | /* Use a flash based bad block table. This option is passed to the | |
178 | * default bad block table function. */ | |
179 | #define NAND_USE_FLASH_BBT 0x00010000 | |
61ecfa87 TG |
180 | /* The hw ecc generator provides a syndrome instead a ecc value on read |
181 | * This can only work if we have the ecc bytes directly behind the | |
1da177e4 LT |
182 | * data bytes. Applies for DOC and AG-AND Renesas HW Reed Solomon generators */ |
183 | #define NAND_HWECC_SYNDROME 0x00020000 | |
0040bf38 TG |
184 | /* This option skips the bbt scan during initialization. */ |
185 | #define NAND_SKIP_BBTSCAN 0x00040000 | |
1da177e4 LT |
186 | |
187 | /* Options set by nand scan */ | |
a36ed299 TG |
188 | /* Nand scan has allocated controller struct */ |
189 | #define NAND_CONTROLLER_ALLOC 0x20000000 | |
1da177e4 LT |
190 | /* Nand scan has allocated oob_buf */ |
191 | #define NAND_OOBBUF_ALLOC 0x40000000 | |
192 | /* Nand scan has allocated data_buf */ | |
193 | #define NAND_DATABUF_ALLOC 0x80000000 | |
194 | ||
195 | ||
196 | /* | |
197 | * nand_state_t - chip states | |
198 | * Enumeration for NAND flash chip state | |
199 | */ | |
200 | typedef enum { | |
201 | FL_READY, | |
202 | FL_READING, | |
203 | FL_WRITING, | |
204 | FL_ERASING, | |
205 | FL_SYNCING, | |
206 | FL_CACHEDPRG, | |
962034f4 | 207 | FL_PM_SUSPENDED, |
1da177e4 LT |
208 | } nand_state_t; |
209 | ||
210 | /* Keep gcc happy */ | |
211 | struct nand_chip; | |
212 | ||
213 | /** | |
214 | * struct nand_hw_control - Control structure for hardware controller (e.g ECC generator) shared among independend devices | |
61ecfa87 | 215 | * @lock: protection lock |
1da177e4 | 216 | * @active: the mtd device which holds the controller currently |
0dfc6246 TG |
217 | * @wq: wait queue to sleep on if a NAND operation is in progress |
218 | * used instead of the per chip wait queue when a hw controller is available | |
1da177e4 LT |
219 | */ |
220 | struct nand_hw_control { | |
221 | spinlock_t lock; | |
222 | struct nand_chip *active; | |
0dfc6246 | 223 | wait_queue_head_t wq; |
1da177e4 LT |
224 | }; |
225 | ||
6dfc6d25 TG |
226 | /** |
227 | * struct nand_ecc_ctrl - Control structure for ecc | |
228 | * @mode: ecc mode | |
229 | * @steps: number of ecc steps per page | |
230 | * @size: data bytes per ecc step | |
231 | * @bytes: ecc bytes per step | |
232 | * @hwctl: function to control hardware ecc generator. Must only | |
233 | * be provided if an hardware ECC is available | |
234 | * @calculate: function for ecc calculation or readback from ecc hardware | |
235 | * @correct: function for ecc correction, matching to ecc generator (sw/hw) | |
236 | */ | |
237 | struct nand_ecc_ctrl { | |
238 | nand_ecc_modes_t mode; | |
239 | int steps; | |
240 | int size; | |
241 | int bytes; | |
9a57d470 | 242 | void (*hwctl)(struct mtd_info *mtd, int mode); |
6dfc6d25 TG |
243 | int (*calculate)(struct mtd_info *mtd, |
244 | const uint8_t *dat, | |
245 | uint8_t *ecc_code); | |
246 | int (*correct)(struct mtd_info *mtd, uint8_t *dat, | |
247 | uint8_t *read_ecc, | |
248 | uint8_t *calc_ecc); | |
249 | }; | |
250 | ||
1da177e4 LT |
251 | /** |
252 | * struct nand_chip - NAND Private Flash Chip Data | |
61ecfa87 TG |
253 | * @IO_ADDR_R: [BOARDSPECIFIC] address to read the 8 I/O lines of the flash device |
254 | * @IO_ADDR_W: [BOARDSPECIFIC] address to write the 8 I/O lines of the flash device | |
1da177e4 | 255 | * @read_byte: [REPLACEABLE] read one byte from the chip |
1da177e4 | 256 | * @read_word: [REPLACEABLE] read one word from the chip |
1da177e4 LT |
257 | * @write_buf: [REPLACEABLE] write data from the buffer to the chip |
258 | * @read_buf: [REPLACEABLE] read data from the chip into the buffer | |
259 | * @verify_buf: [REPLACEABLE] verify buffer contents against the chip data | |
260 | * @select_chip: [REPLACEABLE] select chip nr | |
261 | * @block_bad: [REPLACEABLE] check, if the block is bad | |
262 | * @block_markbad: [REPLACEABLE] mark the block bad | |
7abd3ef9 TG |
263 | * @cmd_ctrl: [BOARDSPECIFIC] hardwarespecific funtion for controlling |
264 | * ALE/CLE/nCE. Also used to write command and address | |
1da177e4 LT |
265 | * @dev_ready: [BOARDSPECIFIC] hardwarespecific function for accesing device ready/busy line |
266 | * If set to NULL no access to ready/busy is available and the ready/busy information | |
267 | * is read from the chip status register | |
268 | * @cmdfunc: [REPLACEABLE] hardwarespecific function for writing commands to the chip | |
269 | * @waitfunc: [REPLACEABLE] hardwarespecific function for wait on ready | |
6dfc6d25 | 270 | * @ecc: [BOARDSPECIFIC] ecc control ctructure |
1da177e4 LT |
271 | * @erase_cmd: [INTERN] erase command write function, selectable due to AND support |
272 | * @scan_bbt: [REPLACEABLE] function to scan bad block table | |
1da177e4 | 273 | * @chip_delay: [BOARDSPECIFIC] chip dependent delay for transfering data from array to read regs (tR) |
1da177e4 | 274 | * @wq: [INTERN] wait queue to sleep on if a NAND operation is in progress |
2c0a2bed | 275 | * @state: [INTERN] the current state of the NAND device |
1da177e4 LT |
276 | * @page_shift: [INTERN] number of address bits in a page (column address bits) |
277 | * @phys_erase_shift: [INTERN] number of address bits in a physical eraseblock | |
278 | * @bbt_erase_shift: [INTERN] number of address bits in a bbt entry | |
279 | * @chip_shift: [INTERN] number of address bits in one chip | |
61ecfa87 | 280 | * @data_buf: [INTERN] internal buffer for one page + oob |
1da177e4 LT |
281 | * @oob_buf: [INTERN] oob buffer for one eraseblock |
282 | * @oobdirty: [INTERN] indicates that oob_buf must be reinitialized | |
283 | * @data_poi: [INTERN] pointer to a data buffer | |
284 | * @options: [BOARDSPECIFIC] various chip options. They can partly be set to inform nand_scan about | |
285 | * special functionality. See the defines for further explanation | |
286 | * @badblockpos: [INTERN] position of the bad block marker in the oob area | |
287 | * @numchips: [INTERN] number of physical chips | |
288 | * @chipsize: [INTERN] the size of one chip for multichip arrays | |
289 | * @pagemask: [INTERN] page number mask = number of (pages / chip) - 1 | |
290 | * @pagebuf: [INTERN] holds the pagenumber which is currently in data_buf | |
291 | * @autooob: [REPLACEABLE] the default (auto)placement scheme | |
292 | * @bbt: [INTERN] bad block table pointer | |
293 | * @bbt_td: [REPLACEABLE] bad block table descriptor for flash lookup | |
294 | * @bbt_md: [REPLACEABLE] bad block table mirror descriptor | |
61ecfa87 | 295 | * @badblock_pattern: [REPLACEABLE] bad block scan pattern used for initial bad block scan |
a36ed299 TG |
296 | * @controller: [REPLACEABLE] a pointer to a hardware controller structure |
297 | * which is shared among multiple independend devices | |
1da177e4 | 298 | * @priv: [OPTIONAL] pointer to private chip date |
61ecfa87 | 299 | * @errstat: [OPTIONAL] hardware specific function to perform additional error status checks |
068e3c0a | 300 | * (determine if errors are correctable) |
1da177e4 | 301 | */ |
61ecfa87 | 302 | |
1da177e4 LT |
303 | struct nand_chip { |
304 | void __iomem *IO_ADDR_R; | |
2c0a2bed | 305 | void __iomem *IO_ADDR_W; |
61ecfa87 | 306 | |
58dd8f2b | 307 | uint8_t (*read_byte)(struct mtd_info *mtd); |
1da177e4 | 308 | u16 (*read_word)(struct mtd_info *mtd); |
58dd8f2b TG |
309 | void (*write_buf)(struct mtd_info *mtd, const uint8_t *buf, int len); |
310 | void (*read_buf)(struct mtd_info *mtd, uint8_t *buf, int len); | |
311 | int (*verify_buf)(struct mtd_info *mtd, const uint8_t *buf, int len); | |
1da177e4 LT |
312 | void (*select_chip)(struct mtd_info *mtd, int chip); |
313 | int (*block_bad)(struct mtd_info *mtd, loff_t ofs, int getchip); | |
314 | int (*block_markbad)(struct mtd_info *mtd, loff_t ofs); | |
7abd3ef9 TG |
315 | void (*cmd_ctrl)(struct mtd_info *mtd, int dat, |
316 | unsigned int ctrl); | |
2c0a2bed TG |
317 | int (*dev_ready)(struct mtd_info *mtd); |
318 | void (*cmdfunc)(struct mtd_info *mtd, unsigned command, int column, int page_addr); | |
319 | int (*waitfunc)(struct mtd_info *mtd, struct nand_chip *this, int state); | |
1da177e4 LT |
320 | void (*erase_cmd)(struct mtd_info *mtd, int page); |
321 | int (*scan_bbt)(struct mtd_info *mtd); | |
6dfc6d25 | 322 | struct nand_ecc_ctrl ecc; |
2c0a2bed | 323 | int chip_delay; |
1da177e4 | 324 | wait_queue_head_t wq; |
2c0a2bed TG |
325 | nand_state_t state; |
326 | int page_shift; | |
1da177e4 LT |
327 | int phys_erase_shift; |
328 | int bbt_erase_shift; | |
329 | int chip_shift; | |
58dd8f2b TG |
330 | uint8_t *data_buf; |
331 | uint8_t *oob_buf; | |
1da177e4 | 332 | int oobdirty; |
58dd8f2b | 333 | uint8_t *data_poi; |
1da177e4 LT |
334 | unsigned int options; |
335 | int badblockpos; | |
336 | int numchips; | |
337 | unsigned long chipsize; | |
338 | int pagemask; | |
339 | int pagebuf; | |
340 | struct nand_oobinfo *autooob; | |
341 | uint8_t *bbt; | |
342 | struct nand_bbt_descr *bbt_td; | |
343 | struct nand_bbt_descr *bbt_md; | |
344 | struct nand_bbt_descr *badblock_pattern; | |
345 | struct nand_hw_control *controller; | |
346 | void *priv; | |
068e3c0a | 347 | int (*errstat)(struct mtd_info *mtd, struct nand_chip *this, int state, int status, int page); |
1da177e4 LT |
348 | }; |
349 | ||
350 | /* | |
351 | * NAND Flash Manufacturer ID Codes | |
352 | */ | |
353 | #define NAND_MFR_TOSHIBA 0x98 | |
354 | #define NAND_MFR_SAMSUNG 0xec | |
355 | #define NAND_MFR_FUJITSU 0x04 | |
356 | #define NAND_MFR_NATIONAL 0x8f | |
357 | #define NAND_MFR_RENESAS 0x07 | |
358 | #define NAND_MFR_STMICRO 0x20 | |
2c0a2bed | 359 | #define NAND_MFR_HYNIX 0xad |
1da177e4 LT |
360 | |
361 | /** | |
362 | * struct nand_flash_dev - NAND Flash Device ID Structure | |
363 | * | |
2c0a2bed TG |
364 | * @name: Identify the device type |
365 | * @id: device ID code | |
366 | * @pagesize: Pagesize in bytes. Either 256 or 512 or 0 | |
61ecfa87 | 367 | * If the pagesize is 0, then the real pagesize |
1da177e4 LT |
368 | * and the eraseize are determined from the |
369 | * extended id bytes in the chip | |
2c0a2bed TG |
370 | * @erasesize: Size of an erase block in the flash device. |
371 | * @chipsize: Total chipsize in Mega Bytes | |
1da177e4 LT |
372 | * @options: Bitfield to store chip relevant options |
373 | */ | |
374 | struct nand_flash_dev { | |
375 | char *name; | |
376 | int id; | |
377 | unsigned long pagesize; | |
378 | unsigned long chipsize; | |
379 | unsigned long erasesize; | |
380 | unsigned long options; | |
381 | }; | |
382 | ||
383 | /** | |
384 | * struct nand_manufacturers - NAND Flash Manufacturer ID Structure | |
385 | * @name: Manufacturer name | |
2c0a2bed | 386 | * @id: manufacturer ID code of device. |
1da177e4 LT |
387 | */ |
388 | struct nand_manufacturers { | |
389 | int id; | |
390 | char * name; | |
391 | }; | |
392 | ||
393 | extern struct nand_flash_dev nand_flash_ids[]; | |
394 | extern struct nand_manufacturers nand_manuf_ids[]; | |
395 | ||
61ecfa87 | 396 | /** |
1da177e4 LT |
397 | * struct nand_bbt_descr - bad block table descriptor |
398 | * @options: options for this descriptor | |
399 | * @pages: the page(s) where we find the bbt, used with option BBT_ABSPAGE | |
400 | * when bbt is searched, then we store the found bbts pages here. | |
401 | * Its an array and supports up to 8 chips now | |
402 | * @offs: offset of the pattern in the oob area of the page | |
403 | * @veroffs: offset of the bbt version counter in the oob are of the page | |
404 | * @version: version read from the bbt page during scan | |
405 | * @len: length of the pattern, if 0 no pattern check is performed | |
406 | * @maxblocks: maximum number of blocks to search for a bbt. This number of | |
61ecfa87 | 407 | * blocks is reserved at the end of the device where the tables are |
1da177e4 LT |
408 | * written. |
409 | * @reserved_block_code: if non-0, this pattern denotes a reserved (rather than | |
410 | * bad) block in the stored bbt | |
61ecfa87 | 411 | * @pattern: pattern to identify bad block table or factory marked good / |
1da177e4 LT |
412 | * bad blocks, can be NULL, if len = 0 |
413 | * | |
61ecfa87 | 414 | * Descriptor for the bad block table marker and the descriptor for the |
1da177e4 LT |
415 | * pattern which identifies good and bad blocks. The assumption is made |
416 | * that the pattern and the version count are always located in the oob area | |
417 | * of the first block. | |
418 | */ | |
419 | struct nand_bbt_descr { | |
420 | int options; | |
421 | int pages[NAND_MAX_CHIPS]; | |
422 | int offs; | |
423 | int veroffs; | |
424 | uint8_t version[NAND_MAX_CHIPS]; | |
425 | int len; | |
2c0a2bed | 426 | int maxblocks; |
1da177e4 LT |
427 | int reserved_block_code; |
428 | uint8_t *pattern; | |
429 | }; | |
430 | ||
431 | /* Options for the bad block table descriptors */ | |
432 | ||
433 | /* The number of bits used per block in the bbt on the device */ | |
434 | #define NAND_BBT_NRBITS_MSK 0x0000000F | |
435 | #define NAND_BBT_1BIT 0x00000001 | |
436 | #define NAND_BBT_2BIT 0x00000002 | |
437 | #define NAND_BBT_4BIT 0x00000004 | |
438 | #define NAND_BBT_8BIT 0x00000008 | |
439 | /* The bad block table is in the last good block of the device */ | |
440 | #define NAND_BBT_LASTBLOCK 0x00000010 | |
441 | /* The bbt is at the given page, else we must scan for the bbt */ | |
442 | #define NAND_BBT_ABSPAGE 0x00000020 | |
443 | /* The bbt is at the given page, else we must scan for the bbt */ | |
444 | #define NAND_BBT_SEARCH 0x00000040 | |
445 | /* bbt is stored per chip on multichip devices */ | |
446 | #define NAND_BBT_PERCHIP 0x00000080 | |
447 | /* bbt has a version counter at offset veroffs */ | |
448 | #define NAND_BBT_VERSION 0x00000100 | |
449 | /* Create a bbt if none axists */ | |
450 | #define NAND_BBT_CREATE 0x00000200 | |
451 | /* Search good / bad pattern through all pages of a block */ | |
452 | #define NAND_BBT_SCANALLPAGES 0x00000400 | |
453 | /* Scan block empty during good / bad block scan */ | |
454 | #define NAND_BBT_SCANEMPTY 0x00000800 | |
455 | /* Write bbt if neccecary */ | |
456 | #define NAND_BBT_WRITE 0x00001000 | |
457 | /* Read and write back block contents when writing bbt */ | |
458 | #define NAND_BBT_SAVECONTENT 0x00002000 | |
459 | /* Search good / bad pattern on the first and the second page */ | |
460 | #define NAND_BBT_SCAN2NDPAGE 0x00004000 | |
461 | ||
462 | /* The maximum number of blocks to scan for a bbt */ | |
463 | #define NAND_BBT_SCAN_MAXBLOCKS 4 | |
464 | ||
465 | extern int nand_scan_bbt (struct mtd_info *mtd, struct nand_bbt_descr *bd); | |
466 | extern int nand_update_bbt (struct mtd_info *mtd, loff_t offs); | |
467 | extern int nand_default_bbt (struct mtd_info *mtd); | |
468 | extern int nand_isbad_bbt (struct mtd_info *mtd, loff_t offs, int allowbbt); | |
469 | extern int nand_erase_nand (struct mtd_info *mtd, struct erase_info *instr, int allowbbt); | |
068e3c0a | 470 | extern int nand_do_read_ecc (struct mtd_info *mtd, loff_t from, size_t len, |
58dd8f2b | 471 | size_t * retlen, uint8_t * buf, uint8_t * oob_buf, |
2c0a2bed | 472 | struct nand_oobinfo *oobsel, int flags); |
1da177e4 LT |
473 | |
474 | /* | |
475 | * Constants for oob configuration | |
476 | */ | |
477 | #define NAND_SMALL_BADBLOCK_POS 5 | |
478 | #define NAND_LARGE_BADBLOCK_POS 0 | |
479 | ||
41796c2e TG |
480 | /** |
481 | * struct platform_nand_chip - chip level device structure | |
482 | * | |
483 | * @nr_chips: max. number of chips to scan for | |
484 | * @chip_offs: chip number offset | |
485 | * @nr_partitions: number of partitions pointed to be partitoons (or zero) | |
486 | * @partitions: mtd partition list | |
487 | * @chip_delay: R/B delay value in us | |
488 | * @options: Option flags, e.g. 16bit buswidth | |
489 | * @priv: hardware controller specific settings | |
490 | */ | |
491 | struct platform_nand_chip { | |
492 | int nr_chips; | |
493 | int chip_offset; | |
494 | int nr_partitions; | |
495 | struct mtd_partition *partitions; | |
2c0a2bed | 496 | int chip_delay; |
41796c2e TG |
497 | unsigned int options; |
498 | void *priv; | |
499 | }; | |
500 | ||
501 | /** | |
502 | * struct platform_nand_ctrl - controller level device structure | |
503 | * | |
504 | * @hwcontrol: platform specific hardware control structure | |
505 | * @dev_ready: platform specific function to read ready/busy pin | |
506 | * @select_chip: platform specific chip select function | |
507 | * @priv_data: private data to transport driver specific settings | |
508 | * | |
509 | * All fields are optional and depend on the hardware driver requirements | |
510 | */ | |
511 | struct platform_nand_ctrl { | |
2c0a2bed TG |
512 | void (*hwcontrol)(struct mtd_info *mtd, int cmd); |
513 | int (*dev_ready)(struct mtd_info *mtd); | |
41796c2e TG |
514 | void (*select_chip)(struct mtd_info *mtd, int chip); |
515 | void *priv; | |
516 | }; | |
517 | ||
518 | /* Some helpers to access the data structures */ | |
519 | static inline | |
520 | struct platform_nand_chip *get_platform_nandchip(struct mtd_info *mtd) | |
521 | { | |
522 | struct nand_chip *chip = mtd->priv; | |
523 | ||
524 | return chip->priv; | |
525 | } | |
526 | ||
1da177e4 | 527 | #endif /* __LINUX_MTD_NAND_H */ |