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1da177e4
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1/*
2 * linux/include/linux/mtd/nand.h
3 *
4 * Copyright (c) 2000 David Woodhouse <dwmw2@mvhi.com>
5 * Steven J. Hill <sjhill@realitydiluted.com>
6 * Thomas Gleixner <tglx@linutronix.de>
7 *
962034f4 8 * $Id: nand.h,v 1.74 2005/09/15 13:58:50 vwool Exp $
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9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13 *
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14 * Info:
15 * Contains standard defines and IDs for NAND flash devices
1da177e4 16 *
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17 * Changelog:
18 * See git changelog.
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19 */
20#ifndef __LINUX_MTD_NAND_H
21#define __LINUX_MTD_NAND_H
22
23#include <linux/config.h>
24#include <linux/wait.h>
25#include <linux/spinlock.h>
26#include <linux/mtd/mtd.h>
27
28struct mtd_info;
29/* Scan and identify a NAND device */
30extern int nand_scan (struct mtd_info *mtd, int max_chips);
31/* Free resources held by the NAND device */
32extern void nand_release (struct mtd_info *mtd);
33
34/* Read raw data from the device without ECC */
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35extern int nand_read_raw (struct mtd_info *mtd, uint8_t *buf, loff_t from,
36 size_t len, size_t ooblen);
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37
38
9223a456 39extern int nand_write_raw(struct mtd_info *mtd, loff_t to, size_t len,
f75e5097 40 size_t *retlen, const uint8_t *buf, uint8_t *oob);
9223a456 41
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42/* The maximum number of NAND chips in an array */
43#define NAND_MAX_CHIPS 8
44
45/* This constant declares the max. oobsize / page, which
46 * is supported now. If you add a chip with bigger oobsize/page
47 * adjust this accordingly.
48 */
49#define NAND_MAX_OOBSIZE 64
f75e5097 50#define NAND_MAX_PAGESIZE 2048
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51
52/*
53 * Constants for hardware specific CLE/ALE/NCE function
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54 *
55 * These are bits which can be or'ed to set/clear multiple
56 * bits in one go.
57 */
1da177e4 58/* Select the chip by setting nCE to low */
7abd3ef9 59#define NAND_NCE 0x01
1da177e4 60/* Select the command latch by setting CLE to high */
7abd3ef9 61#define NAND_CLE 0x02
1da177e4 62/* Select the address latch by setting ALE to high */
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63#define NAND_ALE 0x04
64
65#define NAND_CTRL_CLE (NAND_NCE | NAND_CLE)
66#define NAND_CTRL_ALE (NAND_NCE | NAND_ALE)
67#define NAND_CTRL_CHANGE 0x80
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68
69/*
70 * Standard NAND flash commands
71 */
72#define NAND_CMD_READ0 0
73#define NAND_CMD_READ1 1
74#define NAND_CMD_PAGEPROG 0x10
75#define NAND_CMD_READOOB 0x50
76#define NAND_CMD_ERASE1 0x60
77#define NAND_CMD_STATUS 0x70
78#define NAND_CMD_STATUS_MULTI 0x71
79#define NAND_CMD_SEQIN 0x80
80#define NAND_CMD_READID 0x90
81#define NAND_CMD_ERASE2 0xd0
82#define NAND_CMD_RESET 0xff
83
84/* Extended commands for large page devices */
85#define NAND_CMD_READSTART 0x30
86#define NAND_CMD_CACHEDPROG 0x15
87
28a48de7 88/* Extended commands for AG-AND device */
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89/*
90 * Note: the command for NAND_CMD_DEPLETE1 is really 0x00 but
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91 * there is no way to distinguish that from NAND_CMD_READ0
92 * until the remaining sequence of commands has been completed
93 * so add a high order bit and mask it off in the command.
94 */
95#define NAND_CMD_DEPLETE1 0x100
96#define NAND_CMD_DEPLETE2 0x38
97#define NAND_CMD_STATUS_MULTI 0x71
98#define NAND_CMD_STATUS_ERROR 0x72
99/* multi-bank error status (banks 0-3) */
100#define NAND_CMD_STATUS_ERROR0 0x73
101#define NAND_CMD_STATUS_ERROR1 0x74
102#define NAND_CMD_STATUS_ERROR2 0x75
103#define NAND_CMD_STATUS_ERROR3 0x76
104#define NAND_CMD_STATUS_RESET 0x7f
105#define NAND_CMD_STATUS_CLEAR 0xff
106
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107#define NAND_CMD_NONE -1
108
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109/* Status bits */
110#define NAND_STATUS_FAIL 0x01
111#define NAND_STATUS_FAIL_N1 0x02
112#define NAND_STATUS_TRUE_READY 0x20
113#define NAND_STATUS_READY 0x40
114#define NAND_STATUS_WP 0x80
115
61ecfa87 116/*
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117 * Constants for ECC_MODES
118 */
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119typedef enum {
120 NAND_ECC_NONE,
121 NAND_ECC_SOFT,
122 NAND_ECC_HW,
123 NAND_ECC_HW_SYNDROME,
124} nand_ecc_modes_t;
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125
126/*
127 * Constants for Hardware ECC
068e3c0a 128 */
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129/* Reset Hardware ECC for read */
130#define NAND_ECC_READ 0
131/* Reset Hardware ECC for write */
132#define NAND_ECC_WRITE 1
133/* Enable Hardware ECC before syndrom is read back from flash */
134#define NAND_ECC_READSYN 2
135
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136/* Bit mask for flags passed to do_nand_read_ecc */
137#define NAND_GET_DEVICE 0x80
138
139
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140/* Option constants for bizarre disfunctionality and real
141* features
142*/
143/* Chip can not auto increment pages */
144#define NAND_NO_AUTOINCR 0x00000001
145/* Buswitdh is 16 bit */
146#define NAND_BUSWIDTH_16 0x00000002
147/* Device supports partial programming without padding */
148#define NAND_NO_PADDING 0x00000004
149/* Chip has cache program function */
150#define NAND_CACHEPRG 0x00000008
151/* Chip has copy back function */
152#define NAND_COPYBACK 0x00000010
61ecfa87 153/* AND Chip which has 4 banks and a confusing page / block
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154 * assignment. See Renesas datasheet for further information */
155#define NAND_IS_AND 0x00000020
156/* Chip has a array of 4 pages which can be read without
157 * additional ready /busy waits */
61ecfa87 158#define NAND_4PAGE_ARRAY 0x00000040
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DM
159/* Chip requires that BBT is periodically rewritten to prevent
160 * bits from adjacent blocks from 'leaking' in altering data.
161 * This happens with the Renesas AG-AND chips, possibly others. */
162#define BBT_AUTO_REFRESH 0x00000080
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TG
163/* Chip does not require ready check on read. True
164 * for all large page devices, as they do not support
165 * autoincrement.*/
166#define NAND_NO_READRDY 0x00000100
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167
168/* Options valid for Samsung large page devices */
169#define NAND_SAMSUNG_LP_OPTIONS \
170 (NAND_NO_PADDING | NAND_CACHEPRG | NAND_COPYBACK)
171
172/* Macros to identify the above */
173#define NAND_CANAUTOINCR(chip) (!(chip->options & NAND_NO_AUTOINCR))
174#define NAND_MUST_PAD(chip) (!(chip->options & NAND_NO_PADDING))
175#define NAND_HAS_CACHEPROG(chip) ((chip->options & NAND_CACHEPRG))
176#define NAND_HAS_COPYBACK(chip) ((chip->options & NAND_COPYBACK))
177
178/* Mask to zero out the chip options, which come from the id table */
179#define NAND_CHIPOPTIONS_MSK (0x0000ffff & ~NAND_NO_AUTOINCR)
180
181/* Non chip related options */
182/* Use a flash based bad block table. This option is passed to the
183 * default bad block table function. */
184#define NAND_USE_FLASH_BBT 0x00010000
0040bf38 185/* This option skips the bbt scan during initialization. */
f75e5097 186#define NAND_SKIP_BBTSCAN 0x00020000
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187
188/* Options set by nand scan */
a36ed299 189/* Nand scan has allocated controller struct */
f75e5097 190#define NAND_CONTROLLER_ALLOC 0x80000000
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191
192
193/*
194 * nand_state_t - chip states
195 * Enumeration for NAND flash chip state
196 */
197typedef enum {
198 FL_READY,
199 FL_READING,
200 FL_WRITING,
201 FL_ERASING,
202 FL_SYNCING,
203 FL_CACHEDPRG,
962034f4 204 FL_PM_SUSPENDED,
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205} nand_state_t;
206
207/* Keep gcc happy */
208struct nand_chip;
209
210/**
211 * struct nand_hw_control - Control structure for hardware controller (e.g ECC generator) shared among independend devices
61ecfa87 212 * @lock: protection lock
1da177e4 213 * @active: the mtd device which holds the controller currently
0dfc6246
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214 * @wq: wait queue to sleep on if a NAND operation is in progress
215 * used instead of the per chip wait queue when a hw controller is available
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216 */
217struct nand_hw_control {
218 spinlock_t lock;
219 struct nand_chip *active;
0dfc6246 220 wait_queue_head_t wq;
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221};
222
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TG
223/**
224 * struct nand_ecc_ctrl - Control structure for ecc
225 * @mode: ecc mode
226 * @steps: number of ecc steps per page
227 * @size: data bytes per ecc step
228 * @bytes: ecc bytes per step
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TG
229 * @total: total number of ecc bytes per page
230 * @prepad: padding information for syndrome based ecc generators
231 * @postpad: padding information for syndrome based ecc generators
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232 * @hwctl: function to control hardware ecc generator. Must only
233 * be provided if an hardware ECC is available
234 * @calculate: function for ecc calculation or readback from ecc hardware
235 * @correct: function for ecc correction, matching to ecc generator (sw/hw)
f75e5097 236 * @read_page: function to read a page according to the ecc generator requirements
9577f44a 237 * @write_page: function to write a page according to the ecc generator requirements
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TG
238 */
239struct nand_ecc_ctrl {
240 nand_ecc_modes_t mode;
241 int steps;
242 int size;
243 int bytes;
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TG
244 int total;
245 int prepad;
246 int postpad;
9a57d470 247 void (*hwctl)(struct mtd_info *mtd, int mode);
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248 int (*calculate)(struct mtd_info *mtd,
249 const uint8_t *dat,
250 uint8_t *ecc_code);
251 int (*correct)(struct mtd_info *mtd, uint8_t *dat,
252 uint8_t *read_ecc,
253 uint8_t *calc_ecc);
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TG
254 int (*read_page)(struct mtd_info *mtd,
255 struct nand_chip *chip,
256 uint8_t *buf);
f75e5097 257 void (*write_page)(struct mtd_info *mtd,
9577f44a 258 struct nand_chip *chip,
f75e5097
TG
259 const uint8_t *buf);
260};
261
262/**
263 * struct nand_buffers - buffer structure for read/write
264 * @ecccalc: buffer for calculated ecc
265 * @ecccode: buffer for ecc read from flash
266 * @oobwbuf: buffer for write oob data
267 * @databuf: buffer for data - dynamically sized
268 * @oobrbuf: buffer to read oob data
269 *
270 * Do not change the order of buffers. databuf and oobrbuf must be in
271 * consecutive order.
272 */
273struct nand_buffers {
274 uint8_t ecccalc[NAND_MAX_OOBSIZE];
275 uint8_t ecccode[NAND_MAX_OOBSIZE];
276 uint8_t oobwbuf[NAND_MAX_OOBSIZE];
277 uint8_t databuf[NAND_MAX_PAGESIZE];
278 uint8_t oobrbuf[NAND_MAX_OOBSIZE];
6dfc6d25
TG
279};
280
1da177e4
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281/**
282 * struct nand_chip - NAND Private Flash Chip Data
61ecfa87
TG
283 * @IO_ADDR_R: [BOARDSPECIFIC] address to read the 8 I/O lines of the flash device
284 * @IO_ADDR_W: [BOARDSPECIFIC] address to write the 8 I/O lines of the flash device
1da177e4 285 * @read_byte: [REPLACEABLE] read one byte from the chip
1da177e4 286 * @read_word: [REPLACEABLE] read one word from the chip
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287 * @write_buf: [REPLACEABLE] write data from the buffer to the chip
288 * @read_buf: [REPLACEABLE] read data from the chip into the buffer
289 * @verify_buf: [REPLACEABLE] verify buffer contents against the chip data
290 * @select_chip: [REPLACEABLE] select chip nr
291 * @block_bad: [REPLACEABLE] check, if the block is bad
292 * @block_markbad: [REPLACEABLE] mark the block bad
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TG
293 * @cmd_ctrl: [BOARDSPECIFIC] hardwarespecific funtion for controlling
294 * ALE/CLE/nCE. Also used to write command and address
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295 * @dev_ready: [BOARDSPECIFIC] hardwarespecific function for accesing device ready/busy line
296 * If set to NULL no access to ready/busy is available and the ready/busy information
297 * is read from the chip status register
298 * @cmdfunc: [REPLACEABLE] hardwarespecific function for writing commands to the chip
299 * @waitfunc: [REPLACEABLE] hardwarespecific function for wait on ready
6dfc6d25 300 * @ecc: [BOARDSPECIFIC] ecc control ctructure
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301 * @erase_cmd: [INTERN] erase command write function, selectable due to AND support
302 * @scan_bbt: [REPLACEABLE] function to scan bad block table
1da177e4 303 * @chip_delay: [BOARDSPECIFIC] chip dependent delay for transfering data from array to read regs (tR)
1da177e4 304 * @wq: [INTERN] wait queue to sleep on if a NAND operation is in progress
2c0a2bed 305 * @state: [INTERN] the current state of the NAND device
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306 * @page_shift: [INTERN] number of address bits in a page (column address bits)
307 * @phys_erase_shift: [INTERN] number of address bits in a physical eraseblock
308 * @bbt_erase_shift: [INTERN] number of address bits in a bbt entry
309 * @chip_shift: [INTERN] number of address bits in one chip
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TG
310 * @datbuf: [INTERN] internal buffer for one page + oob
311 * @oobbuf: [INTERN] oob buffer for one eraseblock
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312 * @oobdirty: [INTERN] indicates that oob_buf must be reinitialized
313 * @data_poi: [INTERN] pointer to a data buffer
314 * @options: [BOARDSPECIFIC] various chip options. They can partly be set to inform nand_scan about
315 * special functionality. See the defines for further explanation
316 * @badblockpos: [INTERN] position of the bad block marker in the oob area
317 * @numchips: [INTERN] number of physical chips
318 * @chipsize: [INTERN] the size of one chip for multichip arrays
319 * @pagemask: [INTERN] page number mask = number of (pages / chip) - 1
320 * @pagebuf: [INTERN] holds the pagenumber which is currently in data_buf
321 * @autooob: [REPLACEABLE] the default (auto)placement scheme
322 * @bbt: [INTERN] bad block table pointer
323 * @bbt_td: [REPLACEABLE] bad block table descriptor for flash lookup
324 * @bbt_md: [REPLACEABLE] bad block table mirror descriptor
61ecfa87 325 * @badblock_pattern: [REPLACEABLE] bad block scan pattern used for initial bad block scan
a36ed299
TG
326 * @controller: [REPLACEABLE] a pointer to a hardware controller structure
327 * which is shared among multiple independend devices
1da177e4 328 * @priv: [OPTIONAL] pointer to private chip date
61ecfa87 329 * @errstat: [OPTIONAL] hardware specific function to perform additional error status checks
068e3c0a 330 * (determine if errors are correctable)
1da177e4 331 */
61ecfa87 332
1da177e4
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333struct nand_chip {
334 void __iomem *IO_ADDR_R;
2c0a2bed 335 void __iomem *IO_ADDR_W;
61ecfa87 336
58dd8f2b 337 uint8_t (*read_byte)(struct mtd_info *mtd);
1da177e4 338 u16 (*read_word)(struct mtd_info *mtd);
58dd8f2b
TG
339 void (*write_buf)(struct mtd_info *mtd, const uint8_t *buf, int len);
340 void (*read_buf)(struct mtd_info *mtd, uint8_t *buf, int len);
341 int (*verify_buf)(struct mtd_info *mtd, const uint8_t *buf, int len);
1da177e4
LT
342 void (*select_chip)(struct mtd_info *mtd, int chip);
343 int (*block_bad)(struct mtd_info *mtd, loff_t ofs, int getchip);
344 int (*block_markbad)(struct mtd_info *mtd, loff_t ofs);
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TG
345 void (*cmd_ctrl)(struct mtd_info *mtd, int dat,
346 unsigned int ctrl);
2c0a2bed
TG
347 int (*dev_ready)(struct mtd_info *mtd);
348 void (*cmdfunc)(struct mtd_info *mtd, unsigned command, int column, int page_addr);
349 int (*waitfunc)(struct mtd_info *mtd, struct nand_chip *this, int state);
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350 void (*erase_cmd)(struct mtd_info *mtd, int page);
351 int (*scan_bbt)(struct mtd_info *mtd);
f75e5097
TG
352 int (*errstat)(struct mtd_info *mtd, struct nand_chip *this, int state, int status, int page);
353
2c0a2bed 354 int chip_delay;
f75e5097
TG
355 unsigned int options;
356
2c0a2bed 357 int page_shift;
1da177e4
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358 int phys_erase_shift;
359 int bbt_erase_shift;
360 int chip_shift;
1da177e4
LT
361 int numchips;
362 unsigned long chipsize;
363 int pagemask;
364 int pagebuf;
f75e5097
TG
365 int badblockpos;
366
367 nand_state_t state;
368
369 uint8_t *oob_poi;
370 struct nand_hw_control *controller;
1da177e4 371 struct nand_oobinfo *autooob;
f75e5097
TG
372
373 struct nand_ecc_ctrl ecc;
374 struct nand_buffers buffers;
375 struct nand_hw_control hwcontrol;
376
1da177e4
LT
377 uint8_t *bbt;
378 struct nand_bbt_descr *bbt_td;
379 struct nand_bbt_descr *bbt_md;
f75e5097 380
1da177e4 381 struct nand_bbt_descr *badblock_pattern;
f75e5097 382
1da177e4
LT
383 void *priv;
384};
385
386/*
387 * NAND Flash Manufacturer ID Codes
388 */
389#define NAND_MFR_TOSHIBA 0x98
390#define NAND_MFR_SAMSUNG 0xec
391#define NAND_MFR_FUJITSU 0x04
392#define NAND_MFR_NATIONAL 0x8f
393#define NAND_MFR_RENESAS 0x07
394#define NAND_MFR_STMICRO 0x20
2c0a2bed 395#define NAND_MFR_HYNIX 0xad
1da177e4
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396
397/**
398 * struct nand_flash_dev - NAND Flash Device ID Structure
399 *
2c0a2bed
TG
400 * @name: Identify the device type
401 * @id: device ID code
402 * @pagesize: Pagesize in bytes. Either 256 or 512 or 0
61ecfa87 403 * If the pagesize is 0, then the real pagesize
1da177e4
LT
404 * and the eraseize are determined from the
405 * extended id bytes in the chip
2c0a2bed
TG
406 * @erasesize: Size of an erase block in the flash device.
407 * @chipsize: Total chipsize in Mega Bytes
1da177e4
LT
408 * @options: Bitfield to store chip relevant options
409 */
410struct nand_flash_dev {
411 char *name;
412 int id;
413 unsigned long pagesize;
414 unsigned long chipsize;
415 unsigned long erasesize;
416 unsigned long options;
417};
418
419/**
420 * struct nand_manufacturers - NAND Flash Manufacturer ID Structure
421 * @name: Manufacturer name
2c0a2bed 422 * @id: manufacturer ID code of device.
1da177e4
LT
423*/
424struct nand_manufacturers {
425 int id;
426 char * name;
427};
428
429extern struct nand_flash_dev nand_flash_ids[];
430extern struct nand_manufacturers nand_manuf_ids[];
431
61ecfa87 432/**
1da177e4
LT
433 * struct nand_bbt_descr - bad block table descriptor
434 * @options: options for this descriptor
435 * @pages: the page(s) where we find the bbt, used with option BBT_ABSPAGE
436 * when bbt is searched, then we store the found bbts pages here.
437 * Its an array and supports up to 8 chips now
438 * @offs: offset of the pattern in the oob area of the page
439 * @veroffs: offset of the bbt version counter in the oob are of the page
440 * @version: version read from the bbt page during scan
441 * @len: length of the pattern, if 0 no pattern check is performed
442 * @maxblocks: maximum number of blocks to search for a bbt. This number of
61ecfa87 443 * blocks is reserved at the end of the device where the tables are
1da177e4
LT
444 * written.
445 * @reserved_block_code: if non-0, this pattern denotes a reserved (rather than
446 * bad) block in the stored bbt
61ecfa87 447 * @pattern: pattern to identify bad block table or factory marked good /
1da177e4
LT
448 * bad blocks, can be NULL, if len = 0
449 *
61ecfa87 450 * Descriptor for the bad block table marker and the descriptor for the
1da177e4
LT
451 * pattern which identifies good and bad blocks. The assumption is made
452 * that the pattern and the version count are always located in the oob area
453 * of the first block.
454 */
455struct nand_bbt_descr {
456 int options;
457 int pages[NAND_MAX_CHIPS];
458 int offs;
459 int veroffs;
460 uint8_t version[NAND_MAX_CHIPS];
461 int len;
2c0a2bed 462 int maxblocks;
1da177e4
LT
463 int reserved_block_code;
464 uint8_t *pattern;
465};
466
467/* Options for the bad block table descriptors */
468
469/* The number of bits used per block in the bbt on the device */
470#define NAND_BBT_NRBITS_MSK 0x0000000F
471#define NAND_BBT_1BIT 0x00000001
472#define NAND_BBT_2BIT 0x00000002
473#define NAND_BBT_4BIT 0x00000004
474#define NAND_BBT_8BIT 0x00000008
475/* The bad block table is in the last good block of the device */
476#define NAND_BBT_LASTBLOCK 0x00000010
477/* The bbt is at the given page, else we must scan for the bbt */
478#define NAND_BBT_ABSPAGE 0x00000020
479/* The bbt is at the given page, else we must scan for the bbt */
480#define NAND_BBT_SEARCH 0x00000040
481/* bbt is stored per chip on multichip devices */
482#define NAND_BBT_PERCHIP 0x00000080
483/* bbt has a version counter at offset veroffs */
484#define NAND_BBT_VERSION 0x00000100
485/* Create a bbt if none axists */
486#define NAND_BBT_CREATE 0x00000200
487/* Search good / bad pattern through all pages of a block */
488#define NAND_BBT_SCANALLPAGES 0x00000400
489/* Scan block empty during good / bad block scan */
490#define NAND_BBT_SCANEMPTY 0x00000800
491/* Write bbt if neccecary */
492#define NAND_BBT_WRITE 0x00001000
493/* Read and write back block contents when writing bbt */
494#define NAND_BBT_SAVECONTENT 0x00002000
495/* Search good / bad pattern on the first and the second page */
496#define NAND_BBT_SCAN2NDPAGE 0x00004000
497
498/* The maximum number of blocks to scan for a bbt */
499#define NAND_BBT_SCAN_MAXBLOCKS 4
500
f5bbdacc
TG
501extern int nand_scan_bbt(struct mtd_info *mtd, struct nand_bbt_descr *bd);
502extern int nand_update_bbt(struct mtd_info *mtd, loff_t offs);
503extern int nand_default_bbt(struct mtd_info *mtd);
504extern int nand_isbad_bbt(struct mtd_info *mtd, loff_t offs, int allowbbt);
505extern int nand_erase_nand(struct mtd_info *mtd, struct erase_info *instr,
506 int allowbbt);
507extern int nand_do_read(struct mtd_info *mtd, loff_t from, size_t len,
508 size_t * retlen, uint8_t * buf);
1da177e4
LT
509
510/*
511* Constants for oob configuration
512*/
513#define NAND_SMALL_BADBLOCK_POS 5
514#define NAND_LARGE_BADBLOCK_POS 0
515
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516/**
517 * struct platform_nand_chip - chip level device structure
518 *
519 * @nr_chips: max. number of chips to scan for
520 * @chip_offs: chip number offset
521 * @nr_partitions: number of partitions pointed to be partitoons (or zero)
522 * @partitions: mtd partition list
523 * @chip_delay: R/B delay value in us
524 * @options: Option flags, e.g. 16bit buswidth
525 * @priv: hardware controller specific settings
526 */
527struct platform_nand_chip {
528 int nr_chips;
529 int chip_offset;
530 int nr_partitions;
531 struct mtd_partition *partitions;
2c0a2bed 532 int chip_delay;
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533 unsigned int options;
534 void *priv;
535};
536
537/**
538 * struct platform_nand_ctrl - controller level device structure
539 *
540 * @hwcontrol: platform specific hardware control structure
541 * @dev_ready: platform specific function to read ready/busy pin
542 * @select_chip: platform specific chip select function
543 * @priv_data: private data to transport driver specific settings
544 *
545 * All fields are optional and depend on the hardware driver requirements
546 */
547struct platform_nand_ctrl {
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548 void (*hwcontrol)(struct mtd_info *mtd, int cmd);
549 int (*dev_ready)(struct mtd_info *mtd);
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550 void (*select_chip)(struct mtd_info *mtd, int chip);
551 void *priv;
552};
553
554/* Some helpers to access the data structures */
555static inline
556struct platform_nand_chip *get_platform_nandchip(struct mtd_info *mtd)
557{
558 struct nand_chip *chip = mtd->priv;
559
560 return chip->priv;
561}
562
1da177e4 563#endif /* __LINUX_MTD_NAND_H */