]>
Commit | Line | Data |
---|---|---|
1da177e4 LT |
1 | /* |
2 | * linux/include/linux/mtd/nand.h | |
3 | * | |
a1452a37 DW |
4 | * Copyright © 2000-2010 David Woodhouse <dwmw2@infradead.org> |
5 | * Steven J. Hill <sjhill@realitydiluted.com> | |
6 | * Thomas Gleixner <tglx@linutronix.de> | |
1da177e4 | 7 | * |
1da177e4 LT |
8 | * This program is free software; you can redistribute it and/or modify |
9 | * it under the terms of the GNU General Public License version 2 as | |
10 | * published by the Free Software Foundation. | |
11 | * | |
2c0a2bed TG |
12 | * Info: |
13 | * Contains standard defines and IDs for NAND flash devices | |
1da177e4 | 14 | * |
2c0a2bed TG |
15 | * Changelog: |
16 | * See git changelog. | |
1da177e4 LT |
17 | */ |
18 | #ifndef __LINUX_MTD_NAND_H | |
19 | #define __LINUX_MTD_NAND_H | |
20 | ||
1da177e4 LT |
21 | #include <linux/wait.h> |
22 | #include <linux/spinlock.h> | |
23 | #include <linux/mtd/mtd.h> | |
30631cb8 | 24 | #include <linux/mtd/flashchip.h> |
c62d81bc | 25 | #include <linux/mtd/bbm.h> |
1da177e4 LT |
26 | |
27 | struct mtd_info; | |
5e81e88a | 28 | struct nand_flash_dev; |
1da177e4 | 29 | /* Scan and identify a NAND device */ |
a0491fc4 SAS |
30 | extern int nand_scan(struct mtd_info *mtd, int max_chips); |
31 | /* | |
32 | * Separate phases of nand_scan(), allowing board driver to intervene | |
33 | * and override command or ECC setup according to flash type. | |
34 | */ | |
5e81e88a DW |
35 | extern int nand_scan_ident(struct mtd_info *mtd, int max_chips, |
36 | struct nand_flash_dev *table); | |
3b85c321 DW |
37 | extern int nand_scan_tail(struct mtd_info *mtd); |
38 | ||
1da177e4 | 39 | /* Free resources held by the NAND device */ |
a0491fc4 | 40 | extern void nand_release(struct mtd_info *mtd); |
1da177e4 | 41 | |
b77d95c7 DW |
42 | /* Internal helper for board drivers which need to override command function */ |
43 | extern void nand_wait_ready(struct mtd_info *mtd); | |
44 | ||
7854d3f7 | 45 | /* locks all blocks present in the device */ |
7d70f334 VS |
46 | extern int nand_lock(struct mtd_info *mtd, loff_t ofs, uint64_t len); |
47 | ||
7854d3f7 | 48 | /* unlocks specified locked blocks */ |
7d70f334 VS |
49 | extern int nand_unlock(struct mtd_info *mtd, loff_t ofs, uint64_t len); |
50 | ||
1da177e4 LT |
51 | /* The maximum number of NAND chips in an array */ |
52 | #define NAND_MAX_CHIPS 8 | |
53 | ||
a0491fc4 SAS |
54 | /* |
55 | * This constant declares the max. oobsize / page, which | |
1da177e4 LT |
56 | * is supported now. If you add a chip with bigger oobsize/page |
57 | * adjust this accordingly. | |
58 | */ | |
52778b2e | 59 | #define NAND_MAX_OOBSIZE 744 |
5c709ee9 | 60 | #define NAND_MAX_PAGESIZE 8192 |
1da177e4 LT |
61 | |
62 | /* | |
63 | * Constants for hardware specific CLE/ALE/NCE function | |
7abd3ef9 TG |
64 | * |
65 | * These are bits which can be or'ed to set/clear multiple | |
66 | * bits in one go. | |
67 | */ | |
1da177e4 | 68 | /* Select the chip by setting nCE to low */ |
7abd3ef9 | 69 | #define NAND_NCE 0x01 |
1da177e4 | 70 | /* Select the command latch by setting CLE to high */ |
7abd3ef9 | 71 | #define NAND_CLE 0x02 |
1da177e4 | 72 | /* Select the address latch by setting ALE to high */ |
7abd3ef9 TG |
73 | #define NAND_ALE 0x04 |
74 | ||
75 | #define NAND_CTRL_CLE (NAND_NCE | NAND_CLE) | |
76 | #define NAND_CTRL_ALE (NAND_NCE | NAND_ALE) | |
77 | #define NAND_CTRL_CHANGE 0x80 | |
1da177e4 LT |
78 | |
79 | /* | |
80 | * Standard NAND flash commands | |
81 | */ | |
82 | #define NAND_CMD_READ0 0 | |
83 | #define NAND_CMD_READ1 1 | |
7bc3312b | 84 | #define NAND_CMD_RNDOUT 5 |
1da177e4 LT |
85 | #define NAND_CMD_PAGEPROG 0x10 |
86 | #define NAND_CMD_READOOB 0x50 | |
87 | #define NAND_CMD_ERASE1 0x60 | |
88 | #define NAND_CMD_STATUS 0x70 | |
1da177e4 | 89 | #define NAND_CMD_SEQIN 0x80 |
7bc3312b | 90 | #define NAND_CMD_RNDIN 0x85 |
1da177e4 LT |
91 | #define NAND_CMD_READID 0x90 |
92 | #define NAND_CMD_ERASE2 0xd0 | |
caa4b6f2 | 93 | #define NAND_CMD_PARAM 0xec |
7db03ecc HS |
94 | #define NAND_CMD_GET_FEATURES 0xee |
95 | #define NAND_CMD_SET_FEATURES 0xef | |
1da177e4 LT |
96 | #define NAND_CMD_RESET 0xff |
97 | ||
7d70f334 VS |
98 | #define NAND_CMD_LOCK 0x2a |
99 | #define NAND_CMD_UNLOCK1 0x23 | |
100 | #define NAND_CMD_UNLOCK2 0x24 | |
101 | ||
1da177e4 LT |
102 | /* Extended commands for large page devices */ |
103 | #define NAND_CMD_READSTART 0x30 | |
7bc3312b | 104 | #define NAND_CMD_RNDOUTSTART 0xE0 |
1da177e4 LT |
105 | #define NAND_CMD_CACHEDPROG 0x15 |
106 | ||
7abd3ef9 TG |
107 | #define NAND_CMD_NONE -1 |
108 | ||
1da177e4 LT |
109 | /* Status bits */ |
110 | #define NAND_STATUS_FAIL 0x01 | |
111 | #define NAND_STATUS_FAIL_N1 0x02 | |
112 | #define NAND_STATUS_TRUE_READY 0x20 | |
113 | #define NAND_STATUS_READY 0x40 | |
114 | #define NAND_STATUS_WP 0x80 | |
115 | ||
61ecfa87 | 116 | /* |
1da177e4 LT |
117 | * Constants for ECC_MODES |
118 | */ | |
6dfc6d25 TG |
119 | typedef enum { |
120 | NAND_ECC_NONE, | |
121 | NAND_ECC_SOFT, | |
122 | NAND_ECC_HW, | |
123 | NAND_ECC_HW_SYNDROME, | |
6e0cb135 | 124 | NAND_ECC_HW_OOB_FIRST, |
193bd400 | 125 | NAND_ECC_SOFT_BCH, |
6dfc6d25 | 126 | } nand_ecc_modes_t; |
1da177e4 LT |
127 | |
128 | /* | |
129 | * Constants for Hardware ECC | |
068e3c0a | 130 | */ |
1da177e4 LT |
131 | /* Reset Hardware ECC for read */ |
132 | #define NAND_ECC_READ 0 | |
133 | /* Reset Hardware ECC for write */ | |
134 | #define NAND_ECC_WRITE 1 | |
7854d3f7 | 135 | /* Enable Hardware ECC before syndrome is read back from flash */ |
1da177e4 LT |
136 | #define NAND_ECC_READSYN 2 |
137 | ||
068e3c0a DM |
138 | /* Bit mask for flags passed to do_nand_read_ecc */ |
139 | #define NAND_GET_DEVICE 0x80 | |
140 | ||
141 | ||
a0491fc4 SAS |
142 | /* |
143 | * Option constants for bizarre disfunctionality and real | |
144 | * features. | |
145 | */ | |
7854d3f7 | 146 | /* Buswidth is 16 bit */ |
1da177e4 | 147 | #define NAND_BUSWIDTH_16 0x00000002 |
1da177e4 LT |
148 | /* Chip has cache program function */ |
149 | #define NAND_CACHEPRG 0x00000008 | |
5bc7c33c BN |
150 | /* |
151 | * Chip requires ready check on read (for auto-incremented sequential read). | |
152 | * True only for small page devices; large page devices do not support | |
153 | * autoincrement. | |
154 | */ | |
155 | #define NAND_NEED_READRDY 0x00000100 | |
156 | ||
29072b96 TG |
157 | /* Chip does not allow subpage writes */ |
158 | #define NAND_NO_SUBPAGE_WRITE 0x00000200 | |
159 | ||
93edbad6 ML |
160 | /* Device is one of 'new' xD cards that expose fake nand command set */ |
161 | #define NAND_BROKEN_XD 0x00000400 | |
162 | ||
163 | /* Device behaves just like nand, but is readonly */ | |
164 | #define NAND_ROM 0x00000800 | |
165 | ||
a5ff4f10 JW |
166 | /* Device supports subpage reads */ |
167 | #define NAND_SUBPAGE_READ 0x00001000 | |
168 | ||
1da177e4 | 169 | /* Options valid for Samsung large page devices */ |
3239a6cd | 170 | #define NAND_SAMSUNG_LP_OPTIONS NAND_CACHEPRG |
1da177e4 LT |
171 | |
172 | /* Macros to identify the above */ | |
1da177e4 | 173 | #define NAND_HAS_CACHEPROG(chip) ((chip->options & NAND_CACHEPRG)) |
a5ff4f10 | 174 | #define NAND_HAS_SUBPAGE_READ(chip) ((chip->options & NAND_SUBPAGE_READ)) |
1da177e4 | 175 | |
1da177e4 | 176 | /* Non chip related options */ |
0040bf38 | 177 | /* This option skips the bbt scan during initialization. */ |
b4dc53e1 | 178 | #define NAND_SKIP_BBTSCAN 0x00010000 |
a0491fc4 SAS |
179 | /* |
180 | * This option is defined if the board driver allocates its own buffers | |
181 | * (e.g. because it needs them DMA-coherent). | |
182 | */ | |
b4dc53e1 | 183 | #define NAND_OWN_BUFFERS 0x00020000 |
b1c6e6db | 184 | /* Chip may not exist, so silence any errors in scan */ |
b4dc53e1 | 185 | #define NAND_SCAN_SILENT_NODEV 0x00040000 |
64b37b2a MC |
186 | /* |
187 | * Autodetect nand buswidth with readid/onfi. | |
188 | * This suppose the driver will configure the hardware in 8 bits mode | |
189 | * when calling nand_scan_ident, and update its configuration | |
190 | * before calling nand_scan_tail. | |
191 | */ | |
192 | #define NAND_BUSWIDTH_AUTO 0x00080000 | |
b1c6e6db | 193 | |
1da177e4 | 194 | /* Options set by nand scan */ |
a36ed299 | 195 | /* Nand scan has allocated controller struct */ |
f75e5097 | 196 | #define NAND_CONTROLLER_ALLOC 0x80000000 |
1da177e4 | 197 | |
29072b96 TG |
198 | /* Cell info constants */ |
199 | #define NAND_CI_CHIPNR_MSK 0x03 | |
200 | #define NAND_CI_CELLTYPE_MSK 0x0C | |
7db906b7 | 201 | #define NAND_CI_CELLTYPE_SHIFT 2 |
1da177e4 | 202 | |
1da177e4 LT |
203 | /* Keep gcc happy */ |
204 | struct nand_chip; | |
205 | ||
5b40db68 HS |
206 | /* ONFI features */ |
207 | #define ONFI_FEATURE_16_BIT_BUS (1 << 0) | |
208 | #define ONFI_FEATURE_EXT_PARAM_PAGE (1 << 7) | |
209 | ||
3e70192c HS |
210 | /* ONFI timing mode, used in both asynchronous and synchronous mode */ |
211 | #define ONFI_TIMING_MODE_0 (1 << 0) | |
212 | #define ONFI_TIMING_MODE_1 (1 << 1) | |
213 | #define ONFI_TIMING_MODE_2 (1 << 2) | |
214 | #define ONFI_TIMING_MODE_3 (1 << 3) | |
215 | #define ONFI_TIMING_MODE_4 (1 << 4) | |
216 | #define ONFI_TIMING_MODE_5 (1 << 5) | |
217 | #define ONFI_TIMING_MODE_UNKNOWN (1 << 6) | |
218 | ||
7db03ecc HS |
219 | /* ONFI feature address */ |
220 | #define ONFI_FEATURE_ADDR_TIMING_MODE 0x1 | |
221 | ||
222 | /* ONFI subfeature parameters length */ | |
223 | #define ONFI_SUBFEATURE_PARAM_LEN 4 | |
224 | ||
d914c932 DM |
225 | /* ONFI optional commands SET/GET FEATURES supported? */ |
226 | #define ONFI_OPT_CMD_SET_GET_FEATURES (1 << 2) | |
227 | ||
d1e1f4e4 FF |
228 | struct nand_onfi_params { |
229 | /* rev info and features block */ | |
b46daf7e SAS |
230 | /* 'O' 'N' 'F' 'I' */ |
231 | u8 sig[4]; | |
232 | __le16 revision; | |
233 | __le16 features; | |
234 | __le16 opt_cmd; | |
5138a98f HS |
235 | u8 reserved0[2]; |
236 | __le16 ext_param_page_length; /* since ONFI 2.1 */ | |
237 | u8 num_of_param_pages; /* since ONFI 2.1 */ | |
238 | u8 reserved1[17]; | |
d1e1f4e4 FF |
239 | |
240 | /* manufacturer information block */ | |
b46daf7e SAS |
241 | char manufacturer[12]; |
242 | char model[20]; | |
243 | u8 jedec_id; | |
244 | __le16 date_code; | |
245 | u8 reserved2[13]; | |
d1e1f4e4 FF |
246 | |
247 | /* memory organization block */ | |
b46daf7e SAS |
248 | __le32 byte_per_page; |
249 | __le16 spare_bytes_per_page; | |
250 | __le32 data_bytes_per_ppage; | |
251 | __le16 spare_bytes_per_ppage; | |
252 | __le32 pages_per_block; | |
253 | __le32 blocks_per_lun; | |
254 | u8 lun_count; | |
255 | u8 addr_cycles; | |
256 | u8 bits_per_cell; | |
257 | __le16 bb_per_lun; | |
258 | __le16 block_endurance; | |
259 | u8 guaranteed_good_blocks; | |
260 | __le16 guaranteed_block_endurance; | |
261 | u8 programs_per_page; | |
262 | u8 ppage_attr; | |
263 | u8 ecc_bits; | |
264 | u8 interleaved_bits; | |
265 | u8 interleaved_ops; | |
266 | u8 reserved3[13]; | |
d1e1f4e4 FF |
267 | |
268 | /* electrical parameter block */ | |
b46daf7e SAS |
269 | u8 io_pin_capacitance_max; |
270 | __le16 async_timing_mode; | |
271 | __le16 program_cache_timing_mode; | |
272 | __le16 t_prog; | |
273 | __le16 t_bers; | |
274 | __le16 t_r; | |
275 | __le16 t_ccs; | |
276 | __le16 src_sync_timing_mode; | |
277 | __le16 src_ssync_features; | |
278 | __le16 clk_pin_capacitance_typ; | |
279 | __le16 io_pin_capacitance_typ; | |
280 | __le16 input_pin_capacitance_typ; | |
281 | u8 input_pin_capacitance_max; | |
282 | u8 driver_strenght_support; | |
283 | __le16 t_int_r; | |
284 | __le16 t_ald; | |
285 | u8 reserved4[7]; | |
d1e1f4e4 FF |
286 | |
287 | /* vendor */ | |
b46daf7e | 288 | u8 reserved5[90]; |
d1e1f4e4 FF |
289 | |
290 | __le16 crc; | |
291 | } __attribute__((packed)); | |
292 | ||
293 | #define ONFI_CRC_BASE 0x4F4E | |
294 | ||
5138a98f HS |
295 | /* Extended ECC information Block Definition (since ONFI 2.1) */ |
296 | struct onfi_ext_ecc_info { | |
297 | u8 ecc_bits; | |
298 | u8 codeword_size; | |
299 | __le16 bb_per_lun; | |
300 | __le16 block_endurance; | |
301 | u8 reserved[2]; | |
302 | } __packed; | |
303 | ||
304 | #define ONFI_SECTION_TYPE_0 0 /* Unused section. */ | |
305 | #define ONFI_SECTION_TYPE_1 1 /* for additional sections. */ | |
306 | #define ONFI_SECTION_TYPE_2 2 /* for ECC information. */ | |
307 | struct onfi_ext_section { | |
308 | u8 type; | |
309 | u8 length; | |
310 | } __packed; | |
311 | ||
312 | #define ONFI_EXT_SECTION_MAX 8 | |
313 | ||
314 | /* Extended Parameter Page Definition (since ONFI 2.1) */ | |
315 | struct onfi_ext_param_page { | |
316 | __le16 crc; | |
317 | u8 sig[4]; /* 'E' 'P' 'P' 'S' */ | |
318 | u8 reserved0[10]; | |
319 | struct onfi_ext_section sections[ONFI_EXT_SECTION_MAX]; | |
320 | ||
321 | /* | |
322 | * The actual size of the Extended Parameter Page is in | |
323 | * @ext_param_page_length of nand_onfi_params{}. | |
324 | * The following are the variable length sections. | |
325 | * So we do not add any fields below. Please see the ONFI spec. | |
326 | */ | |
327 | } __packed; | |
328 | ||
1da177e4 | 329 | /** |
844d3b42 | 330 | * struct nand_hw_control - Control structure for hardware controller (e.g ECC generator) shared among independent devices |
61ecfa87 | 331 | * @lock: protection lock |
1da177e4 | 332 | * @active: the mtd device which holds the controller currently |
a0491fc4 SAS |
333 | * @wq: wait queue to sleep on if a NAND operation is in |
334 | * progress used instead of the per chip wait queue | |
335 | * when a hw controller is available. | |
1da177e4 LT |
336 | */ |
337 | struct nand_hw_control { | |
b46daf7e | 338 | spinlock_t lock; |
1da177e4 | 339 | struct nand_chip *active; |
0dfc6246 | 340 | wait_queue_head_t wq; |
1da177e4 LT |
341 | }; |
342 | ||
6dfc6d25 | 343 | /** |
7854d3f7 BN |
344 | * struct nand_ecc_ctrl - Control structure for ECC |
345 | * @mode: ECC mode | |
346 | * @steps: number of ECC steps per page | |
347 | * @size: data bytes per ECC step | |
348 | * @bytes: ECC bytes per step | |
1d0b95b0 | 349 | * @strength: max number of correctible bits per ECC step |
7854d3f7 BN |
350 | * @total: total number of ECC bytes per page |
351 | * @prepad: padding information for syndrome based ECC generators | |
352 | * @postpad: padding information for syndrome based ECC generators | |
844d3b42 | 353 | * @layout: ECC layout control struct pointer |
7854d3f7 BN |
354 | * @priv: pointer to private ECC control data |
355 | * @hwctl: function to control hardware ECC generator. Must only | |
6dfc6d25 | 356 | * be provided if an hardware ECC is available |
7854d3f7 BN |
357 | * @calculate: function for ECC calculation or readback from ECC hardware |
358 | * @correct: function for ECC correction, matching to ECC generator (sw/hw) | |
956e944c DW |
359 | * @read_page_raw: function to read a raw page without ECC |
360 | * @write_page_raw: function to write a raw page without ECC | |
7854d3f7 | 361 | * @read_page: function to read a page according to the ECC generator |
5ca7f415 MD |
362 | * requirements; returns maximum number of bitflips corrected in |
363 | * any single ECC step, 0 if bitflips uncorrectable, -EIO hw error | |
364 | * @read_subpage: function to read parts of the page covered by ECC; | |
365 | * returns same as read_page() | |
837a6ba4 | 366 | * @write_subpage: function to write parts of the page covered by ECC. |
7854d3f7 | 367 | * @write_page: function to write a page according to the ECC generator |
a0491fc4 | 368 | * requirements. |
9ce244b3 | 369 | * @write_oob_raw: function to write chip OOB data without ECC |
c46f6483 | 370 | * @read_oob_raw: function to read chip OOB data without ECC |
844d3b42 RD |
371 | * @read_oob: function to read chip OOB data |
372 | * @write_oob: function to write chip OOB data | |
6dfc6d25 TG |
373 | */ |
374 | struct nand_ecc_ctrl { | |
b46daf7e SAS |
375 | nand_ecc_modes_t mode; |
376 | int steps; | |
377 | int size; | |
378 | int bytes; | |
379 | int total; | |
1d0b95b0 | 380 | int strength; |
b46daf7e SAS |
381 | int prepad; |
382 | int postpad; | |
5bd34c09 | 383 | struct nand_ecclayout *layout; |
193bd400 | 384 | void *priv; |
b46daf7e SAS |
385 | void (*hwctl)(struct mtd_info *mtd, int mode); |
386 | int (*calculate)(struct mtd_info *mtd, const uint8_t *dat, | |
387 | uint8_t *ecc_code); | |
388 | int (*correct)(struct mtd_info *mtd, uint8_t *dat, uint8_t *read_ecc, | |
389 | uint8_t *calc_ecc); | |
390 | int (*read_page_raw)(struct mtd_info *mtd, struct nand_chip *chip, | |
1fbb938d | 391 | uint8_t *buf, int oob_required, int page); |
fdbad98d | 392 | int (*write_page_raw)(struct mtd_info *mtd, struct nand_chip *chip, |
1fbb938d | 393 | const uint8_t *buf, int oob_required); |
b46daf7e | 394 | int (*read_page)(struct mtd_info *mtd, struct nand_chip *chip, |
1fbb938d | 395 | uint8_t *buf, int oob_required, int page); |
b46daf7e SAS |
396 | int (*read_subpage)(struct mtd_info *mtd, struct nand_chip *chip, |
397 | uint32_t offs, uint32_t len, uint8_t *buf); | |
837a6ba4 GP |
398 | int (*write_subpage)(struct mtd_info *mtd, struct nand_chip *chip, |
399 | uint32_t offset, uint32_t data_len, | |
400 | const uint8_t *data_buf, int oob_required); | |
fdbad98d | 401 | int (*write_page)(struct mtd_info *mtd, struct nand_chip *chip, |
1fbb938d | 402 | const uint8_t *buf, int oob_required); |
9ce244b3 BN |
403 | int (*write_oob_raw)(struct mtd_info *mtd, struct nand_chip *chip, |
404 | int page); | |
c46f6483 | 405 | int (*read_oob_raw)(struct mtd_info *mtd, struct nand_chip *chip, |
5c2ffb11 SL |
406 | int page); |
407 | int (*read_oob)(struct mtd_info *mtd, struct nand_chip *chip, int page); | |
b46daf7e SAS |
408 | int (*write_oob)(struct mtd_info *mtd, struct nand_chip *chip, |
409 | int page); | |
f75e5097 TG |
410 | }; |
411 | ||
412 | /** | |
413 | * struct nand_buffers - buffer structure for read/write | |
7854d3f7 BN |
414 | * @ecccalc: buffer for calculated ECC |
415 | * @ecccode: buffer for ECC read from flash | |
f75e5097 | 416 | * @databuf: buffer for data - dynamically sized |
f75e5097 TG |
417 | * |
418 | * Do not change the order of buffers. databuf and oobrbuf must be in | |
419 | * consecutive order. | |
420 | */ | |
421 | struct nand_buffers { | |
422 | uint8_t ecccalc[NAND_MAX_OOBSIZE]; | |
423 | uint8_t ecccode[NAND_MAX_OOBSIZE]; | |
7dcdcbef | 424 | uint8_t databuf[NAND_MAX_PAGESIZE + NAND_MAX_OOBSIZE]; |
6dfc6d25 TG |
425 | }; |
426 | ||
1da177e4 LT |
427 | /** |
428 | * struct nand_chip - NAND Private Flash Chip Data | |
a0491fc4 SAS |
429 | * @IO_ADDR_R: [BOARDSPECIFIC] address to read the 8 I/O lines of the |
430 | * flash device | |
431 | * @IO_ADDR_W: [BOARDSPECIFIC] address to write the 8 I/O lines of the | |
432 | * flash device. | |
1da177e4 | 433 | * @read_byte: [REPLACEABLE] read one byte from the chip |
1da177e4 | 434 | * @read_word: [REPLACEABLE] read one word from the chip |
1da177e4 LT |
435 | * @write_buf: [REPLACEABLE] write data from the buffer to the chip |
436 | * @read_buf: [REPLACEABLE] read data from the chip into the buffer | |
1da177e4 | 437 | * @select_chip: [REPLACEABLE] select chip nr |
ce157510 BN |
438 | * @block_bad: [REPLACEABLE] check if a block is bad, using OOB markers |
439 | * @block_markbad: [REPLACEABLE] mark a block bad | |
25985edc | 440 | * @cmd_ctrl: [BOARDSPECIFIC] hardwarespecific function for controlling |
7abd3ef9 | 441 | * ALE/CLE/nCE. Also used to write command and address |
25985edc | 442 | * @init_size: [BOARDSPECIFIC] hardwarespecific function for setting |
12a40a57 HS |
443 | * mtd->oobsize, mtd->writesize and so on. |
444 | * @id_data contains the 8 bytes values of NAND_CMD_READID. | |
445 | * Return with the bus width. | |
7854d3f7 | 446 | * @dev_ready: [BOARDSPECIFIC] hardwarespecific function for accessing |
a0491fc4 SAS |
447 | * device ready/busy line. If set to NULL no access to |
448 | * ready/busy is available and the ready/busy information | |
449 | * is read from the chip status register. | |
450 | * @cmdfunc: [REPLACEABLE] hardwarespecific function for writing | |
451 | * commands to the chip. | |
452 | * @waitfunc: [REPLACEABLE] hardwarespecific function for wait on | |
453 | * ready. | |
7854d3f7 | 454 | * @ecc: [BOARDSPECIFIC] ECC control structure |
844d3b42 RD |
455 | * @buffers: buffer structure for read/write |
456 | * @hwcontrol: platform-specific hardware control structure | |
a0491fc4 SAS |
457 | * @erase_cmd: [INTERN] erase command write function, selectable due |
458 | * to AND support. | |
1da177e4 | 459 | * @scan_bbt: [REPLACEABLE] function to scan bad block table |
25985edc | 460 | * @chip_delay: [BOARDSPECIFIC] chip dependent delay for transferring |
a0491fc4 | 461 | * data from array to read regs (tR). |
2c0a2bed | 462 | * @state: [INTERN] the current state of the NAND device |
e9195edc BN |
463 | * @oob_poi: "poison value buffer," used for laying out OOB data |
464 | * before writing | |
a0491fc4 SAS |
465 | * @page_shift: [INTERN] number of address bits in a page (column |
466 | * address bits). | |
1da177e4 LT |
467 | * @phys_erase_shift: [INTERN] number of address bits in a physical eraseblock |
468 | * @bbt_erase_shift: [INTERN] number of address bits in a bbt entry | |
469 | * @chip_shift: [INTERN] number of address bits in one chip | |
a0491fc4 SAS |
470 | * @options: [BOARDSPECIFIC] various chip options. They can partly |
471 | * be set to inform nand_scan about special functionality. | |
472 | * See the defines for further explanation. | |
5fb1549d BN |
473 | * @bbt_options: [INTERN] bad block specific options. All options used |
474 | * here must come from bbm.h. By default, these options | |
475 | * will be copied to the appropriate nand_bbt_descr's. | |
a0491fc4 SAS |
476 | * @badblockpos: [INTERN] position of the bad block marker in the oob |
477 | * area. | |
661a0832 BN |
478 | * @badblockbits: [INTERN] minimum number of set bits in a good block's |
479 | * bad block marker position; i.e., BBM == 11110111b is | |
480 | * not bad when badblockbits == 7 | |
7db906b7 | 481 | * @bits_per_cell: [INTERN] number of bits per cell. i.e., 1 means SLC. |
4cfeca2d HS |
482 | * @ecc_strength_ds: [INTERN] ECC correctability from the datasheet. |
483 | * Minimum amount of bit errors per @ecc_step_ds guaranteed | |
484 | * to be correctable. If unknown, set to zero. | |
485 | * @ecc_step_ds: [INTERN] ECC step required by the @ecc_strength_ds, | |
486 | * also from the datasheet. It is the recommended ECC step | |
487 | * size, if known; if unknown, set to zero. | |
1da177e4 LT |
488 | * @numchips: [INTERN] number of physical chips |
489 | * @chipsize: [INTERN] the size of one chip for multichip arrays | |
490 | * @pagemask: [INTERN] page number mask = number of (pages / chip) - 1 | |
a0491fc4 SAS |
491 | * @pagebuf: [INTERN] holds the pagenumber which is currently in |
492 | * data_buf. | |
edbc4540 MD |
493 | * @pagebuf_bitflips: [INTERN] holds the bitflip count for the page which is |
494 | * currently in data_buf. | |
29072b96 | 495 | * @subpagesize: [INTERN] holds the subpagesize |
a0491fc4 SAS |
496 | * @onfi_version: [INTERN] holds the chip ONFI version (BCD encoded), |
497 | * non 0 if ONFI supported. | |
498 | * @onfi_params: [INTERN] holds the ONFI page parameter when ONFI is | |
499 | * supported, 0 otherwise. | |
9ef525a9 RD |
500 | * @onfi_set_features: [REPLACEABLE] set the features for ONFI nand |
501 | * @onfi_get_features: [REPLACEABLE] get the features for ONFI nand | |
1da177e4 | 502 | * @bbt: [INTERN] bad block table pointer |
a0491fc4 SAS |
503 | * @bbt_td: [REPLACEABLE] bad block table descriptor for flash |
504 | * lookup. | |
1da177e4 | 505 | * @bbt_md: [REPLACEABLE] bad block table mirror descriptor |
a0491fc4 SAS |
506 | * @badblock_pattern: [REPLACEABLE] bad block scan pattern used for initial |
507 | * bad block scan. | |
508 | * @controller: [REPLACEABLE] a pointer to a hardware controller | |
7854d3f7 | 509 | * structure which is shared among multiple independent |
a0491fc4 | 510 | * devices. |
32c8db8f | 511 | * @priv: [OPTIONAL] pointer to private chip data |
a0491fc4 SAS |
512 | * @errstat: [OPTIONAL] hardware specific function to perform |
513 | * additional error status checks (determine if errors are | |
514 | * correctable). | |
351edd24 | 515 | * @write_page: [REPLACEABLE] High-level page write function |
1da177e4 | 516 | */ |
61ecfa87 | 517 | |
1da177e4 | 518 | struct nand_chip { |
b46daf7e SAS |
519 | void __iomem *IO_ADDR_R; |
520 | void __iomem *IO_ADDR_W; | |
521 | ||
522 | uint8_t (*read_byte)(struct mtd_info *mtd); | |
523 | u16 (*read_word)(struct mtd_info *mtd); | |
524 | void (*write_buf)(struct mtd_info *mtd, const uint8_t *buf, int len); | |
525 | void (*read_buf)(struct mtd_info *mtd, uint8_t *buf, int len); | |
b46daf7e SAS |
526 | void (*select_chip)(struct mtd_info *mtd, int chip); |
527 | int (*block_bad)(struct mtd_info *mtd, loff_t ofs, int getchip); | |
528 | int (*block_markbad)(struct mtd_info *mtd, loff_t ofs); | |
529 | void (*cmd_ctrl)(struct mtd_info *mtd, int dat, unsigned int ctrl); | |
530 | int (*init_size)(struct mtd_info *mtd, struct nand_chip *this, | |
531 | u8 *id_data); | |
532 | int (*dev_ready)(struct mtd_info *mtd); | |
533 | void (*cmdfunc)(struct mtd_info *mtd, unsigned command, int column, | |
534 | int page_addr); | |
535 | int(*waitfunc)(struct mtd_info *mtd, struct nand_chip *this); | |
536 | void (*erase_cmd)(struct mtd_info *mtd, int page); | |
537 | int (*scan_bbt)(struct mtd_info *mtd); | |
538 | int (*errstat)(struct mtd_info *mtd, struct nand_chip *this, int state, | |
539 | int status, int page); | |
540 | int (*write_page)(struct mtd_info *mtd, struct nand_chip *chip, | |
837a6ba4 GP |
541 | uint32_t offset, int data_len, const uint8_t *buf, |
542 | int oob_required, int page, int cached, int raw); | |
7db03ecc HS |
543 | int (*onfi_set_features)(struct mtd_info *mtd, struct nand_chip *chip, |
544 | int feature_addr, uint8_t *subfeature_para); | |
545 | int (*onfi_get_features)(struct mtd_info *mtd, struct nand_chip *chip, | |
546 | int feature_addr, uint8_t *subfeature_para); | |
b46daf7e SAS |
547 | |
548 | int chip_delay; | |
549 | unsigned int options; | |
5fb1549d | 550 | unsigned int bbt_options; |
b46daf7e SAS |
551 | |
552 | int page_shift; | |
553 | int phys_erase_shift; | |
554 | int bbt_erase_shift; | |
555 | int chip_shift; | |
556 | int numchips; | |
557 | uint64_t chipsize; | |
558 | int pagemask; | |
559 | int pagebuf; | |
edbc4540 | 560 | unsigned int pagebuf_bitflips; |
b46daf7e | 561 | int subpagesize; |
7db906b7 | 562 | uint8_t bits_per_cell; |
4cfeca2d HS |
563 | uint16_t ecc_strength_ds; |
564 | uint16_t ecc_step_ds; | |
b46daf7e SAS |
565 | int badblockpos; |
566 | int badblockbits; | |
567 | ||
568 | int onfi_version; | |
d1e1f4e4 FF |
569 | struct nand_onfi_params onfi_params; |
570 | ||
b46daf7e | 571 | flstate_t state; |
f75e5097 | 572 | |
b46daf7e SAS |
573 | uint8_t *oob_poi; |
574 | struct nand_hw_control *controller; | |
f75e5097 TG |
575 | |
576 | struct nand_ecc_ctrl ecc; | |
4bf63fcb | 577 | struct nand_buffers *buffers; |
f75e5097 TG |
578 | struct nand_hw_control hwcontrol; |
579 | ||
b46daf7e SAS |
580 | uint8_t *bbt; |
581 | struct nand_bbt_descr *bbt_td; | |
582 | struct nand_bbt_descr *bbt_md; | |
f75e5097 | 583 | |
b46daf7e | 584 | struct nand_bbt_descr *badblock_pattern; |
f75e5097 | 585 | |
b46daf7e | 586 | void *priv; |
1da177e4 LT |
587 | }; |
588 | ||
589 | /* | |
590 | * NAND Flash Manufacturer ID Codes | |
591 | */ | |
592 | #define NAND_MFR_TOSHIBA 0x98 | |
593 | #define NAND_MFR_SAMSUNG 0xec | |
594 | #define NAND_MFR_FUJITSU 0x04 | |
595 | #define NAND_MFR_NATIONAL 0x8f | |
596 | #define NAND_MFR_RENESAS 0x07 | |
597 | #define NAND_MFR_STMICRO 0x20 | |
2c0a2bed | 598 | #define NAND_MFR_HYNIX 0xad |
8c60e547 | 599 | #define NAND_MFR_MICRON 0x2c |
30eb0db0 | 600 | #define NAND_MFR_AMD 0x01 |
c1257b47 | 601 | #define NAND_MFR_MACRONIX 0xc2 |
b1ccfab3 | 602 | #define NAND_MFR_EON 0x92 |
1da177e4 | 603 | |
53552d22 AB |
604 | /* The maximum expected count of bytes in the NAND ID sequence */ |
605 | #define NAND_MAX_ID_LEN 8 | |
606 | ||
8dbfae1e AB |
607 | /* |
608 | * A helper for defining older NAND chips where the second ID byte fully | |
609 | * defined the chip, including the geometry (chip size, eraseblock size, page | |
5bfa9b71 | 610 | * size). All these chips have 512 bytes NAND page size. |
8dbfae1e | 611 | */ |
5bfa9b71 AB |
612 | #define LEGACY_ID_NAND(nm, devid, chipsz, erasesz, opts) \ |
613 | { .name = (nm), {{ .dev_id = (devid) }}, .pagesize = 512, \ | |
614 | .chipsize = (chipsz), .erasesize = (erasesz), .options = (opts) } | |
8dbfae1e AB |
615 | |
616 | /* | |
617 | * A helper for defining newer chips which report their page size and | |
618 | * eraseblock size via the extended ID bytes. | |
619 | * | |
620 | * The real difference between LEGACY_ID_NAND and EXTENDED_ID_NAND is that with | |
621 | * EXTENDED_ID_NAND, manufacturers overloaded the same device ID so that the | |
622 | * device ID now only represented a particular total chip size (and voltage, | |
623 | * buswidth), and the page size, eraseblock size, and OOB size could vary while | |
624 | * using the same device ID. | |
625 | */ | |
8e12b474 AB |
626 | #define EXTENDED_ID_NAND(nm, devid, chipsz, opts) \ |
627 | { .name = (nm), {{ .dev_id = (devid) }}, .chipsize = (chipsz), \ | |
8dbfae1e AB |
628 | .options = (opts) } |
629 | ||
2dc0bdd9 HS |
630 | #define NAND_ECC_INFO(_strength, _step) \ |
631 | { .strength_ds = (_strength), .step_ds = (_step) } | |
632 | #define NAND_ECC_STRENGTH(type) ((type)->ecc.strength_ds) | |
633 | #define NAND_ECC_STEP(type) ((type)->ecc.step_ds) | |
634 | ||
1da177e4 LT |
635 | /** |
636 | * struct nand_flash_dev - NAND Flash Device ID Structure | |
68aa352d AB |
637 | * @name: a human-readable name of the NAND chip |
638 | * @dev_id: the device ID (the second byte of the full chip ID array) | |
8e12b474 AB |
639 | * @mfr_id: manufecturer ID part of the full chip ID array (refers the same |
640 | * memory address as @id[0]) | |
641 | * @dev_id: device ID part of the full chip ID array (refers the same memory | |
642 | * address as @id[1]) | |
643 | * @id: full device ID array | |
68aa352d AB |
644 | * @pagesize: size of the NAND page in bytes; if 0, then the real page size (as |
645 | * well as the eraseblock size) is determined from the extended NAND | |
646 | * chip ID array) | |
68aa352d | 647 | * @chipsize: total chip size in MiB |
ecb42fea | 648 | * @erasesize: eraseblock size in bytes (determined from the extended ID if 0) |
68aa352d | 649 | * @options: stores various chip bit options |
f22d5f63 HS |
650 | * @id_len: The valid length of the @id. |
651 | * @oobsize: OOB size | |
2dc0bdd9 HS |
652 | * @ecc.strength_ds: The ECC correctability from the datasheet, same as the |
653 | * @ecc_strength_ds in nand_chip{}. | |
654 | * @ecc.step_ds: The ECC step required by the @ecc.strength_ds, same as the | |
655 | * @ecc_step_ds in nand_chip{}, also from the datasheet. | |
656 | * For example, the "4bit ECC for each 512Byte" can be set with | |
657 | * NAND_ECC_INFO(4, 512). | |
1da177e4 LT |
658 | */ |
659 | struct nand_flash_dev { | |
660 | char *name; | |
8e12b474 AB |
661 | union { |
662 | struct { | |
663 | uint8_t mfr_id; | |
664 | uint8_t dev_id; | |
665 | }; | |
53552d22 | 666 | uint8_t id[NAND_MAX_ID_LEN]; |
8e12b474 | 667 | }; |
ecb42fea AB |
668 | unsigned int pagesize; |
669 | unsigned int chipsize; | |
670 | unsigned int erasesize; | |
671 | unsigned int options; | |
f22d5f63 HS |
672 | uint16_t id_len; |
673 | uint16_t oobsize; | |
2dc0bdd9 HS |
674 | struct { |
675 | uint16_t strength_ds; | |
676 | uint16_t step_ds; | |
677 | } ecc; | |
1da177e4 LT |
678 | }; |
679 | ||
680 | /** | |
681 | * struct nand_manufacturers - NAND Flash Manufacturer ID Structure | |
682 | * @name: Manufacturer name | |
2c0a2bed | 683 | * @id: manufacturer ID code of device. |
1da177e4 LT |
684 | */ |
685 | struct nand_manufacturers { | |
686 | int id; | |
a0491fc4 | 687 | char *name; |
1da177e4 LT |
688 | }; |
689 | ||
690 | extern struct nand_flash_dev nand_flash_ids[]; | |
691 | extern struct nand_manufacturers nand_manuf_ids[]; | |
692 | ||
f5bbdacc | 693 | extern int nand_scan_bbt(struct mtd_info *mtd, struct nand_bbt_descr *bd); |
f5bbdacc | 694 | extern int nand_default_bbt(struct mtd_info *mtd); |
b32843b7 | 695 | extern int nand_markbad_bbt(struct mtd_info *mtd, loff_t offs); |
f5bbdacc TG |
696 | extern int nand_isbad_bbt(struct mtd_info *mtd, loff_t offs, int allowbbt); |
697 | extern int nand_erase_nand(struct mtd_info *mtd, struct erase_info *instr, | |
698 | int allowbbt); | |
699 | extern int nand_do_read(struct mtd_info *mtd, loff_t from, size_t len, | |
a0491fc4 | 700 | size_t *retlen, uint8_t *buf); |
1da177e4 | 701 | |
41796c2e TG |
702 | /** |
703 | * struct platform_nand_chip - chip level device structure | |
41796c2e | 704 | * @nr_chips: max. number of chips to scan for |
844d3b42 | 705 | * @chip_offset: chip number offset |
8be834f7 | 706 | * @nr_partitions: number of partitions pointed to by partitions (or zero) |
41796c2e TG |
707 | * @partitions: mtd partition list |
708 | * @chip_delay: R/B delay value in us | |
709 | * @options: Option flags, e.g. 16bit buswidth | |
a40f7341 | 710 | * @bbt_options: BBT option flags, e.g. NAND_BBT_USE_FLASH |
7854d3f7 | 711 | * @ecclayout: ECC layout info structure |
972edcb7 | 712 | * @part_probe_types: NULL-terminated array of probe types |
41796c2e TG |
713 | */ |
714 | struct platform_nand_chip { | |
b46daf7e SAS |
715 | int nr_chips; |
716 | int chip_offset; | |
717 | int nr_partitions; | |
718 | struct mtd_partition *partitions; | |
719 | struct nand_ecclayout *ecclayout; | |
720 | int chip_delay; | |
721 | unsigned int options; | |
a40f7341 | 722 | unsigned int bbt_options; |
b46daf7e | 723 | const char **part_probe_types; |
41796c2e TG |
724 | }; |
725 | ||
bf95efd4 HS |
726 | /* Keep gcc happy */ |
727 | struct platform_device; | |
728 | ||
41796c2e TG |
729 | /** |
730 | * struct platform_nand_ctrl - controller level device structure | |
bf95efd4 HS |
731 | * @probe: platform specific function to probe/setup hardware |
732 | * @remove: platform specific function to remove/teardown hardware | |
41796c2e TG |
733 | * @hwcontrol: platform specific hardware control structure |
734 | * @dev_ready: platform specific function to read ready/busy pin | |
735 | * @select_chip: platform specific chip select function | |
972edcb7 VW |
736 | * @cmd_ctrl: platform specific function for controlling |
737 | * ALE/CLE/nCE. Also used to write command and address | |
d6fed9e9 AC |
738 | * @write_buf: platform specific function for write buffer |
739 | * @read_buf: platform specific function for read buffer | |
25806d3c | 740 | * @read_byte: platform specific function to read one byte from chip |
844d3b42 | 741 | * @priv: private data to transport driver specific settings |
41796c2e TG |
742 | * |
743 | * All fields are optional and depend on the hardware driver requirements | |
744 | */ | |
745 | struct platform_nand_ctrl { | |
b46daf7e SAS |
746 | int (*probe)(struct platform_device *pdev); |
747 | void (*remove)(struct platform_device *pdev); | |
748 | void (*hwcontrol)(struct mtd_info *mtd, int cmd); | |
749 | int (*dev_ready)(struct mtd_info *mtd); | |
750 | void (*select_chip)(struct mtd_info *mtd, int chip); | |
751 | void (*cmd_ctrl)(struct mtd_info *mtd, int dat, unsigned int ctrl); | |
752 | void (*write_buf)(struct mtd_info *mtd, const uint8_t *buf, int len); | |
753 | void (*read_buf)(struct mtd_info *mtd, uint8_t *buf, int len); | |
b4f7aa84 | 754 | unsigned char (*read_byte)(struct mtd_info *mtd); |
b46daf7e | 755 | void *priv; |
41796c2e TG |
756 | }; |
757 | ||
972edcb7 VW |
758 | /** |
759 | * struct platform_nand_data - container structure for platform-specific data | |
760 | * @chip: chip level chip structure | |
761 | * @ctrl: controller level device structure | |
762 | */ | |
763 | struct platform_nand_data { | |
b46daf7e SAS |
764 | struct platform_nand_chip chip; |
765 | struct platform_nand_ctrl ctrl; | |
972edcb7 VW |
766 | }; |
767 | ||
41796c2e TG |
768 | /* Some helpers to access the data structures */ |
769 | static inline | |
770 | struct platform_nand_chip *get_platform_nandchip(struct mtd_info *mtd) | |
771 | { | |
772 | struct nand_chip *chip = mtd->priv; | |
773 | ||
774 | return chip->priv; | |
775 | } | |
776 | ||
5b40db68 HS |
777 | /* return the supported features. */ |
778 | static inline int onfi_feature(struct nand_chip *chip) | |
779 | { | |
780 | return chip->onfi_version ? le16_to_cpu(chip->onfi_params.features) : 0; | |
781 | } | |
782 | ||
3e70192c HS |
783 | /* return the supported asynchronous timing mode. */ |
784 | static inline int onfi_get_async_timing_mode(struct nand_chip *chip) | |
785 | { | |
786 | if (!chip->onfi_version) | |
787 | return ONFI_TIMING_MODE_UNKNOWN; | |
788 | return le16_to_cpu(chip->onfi_params.async_timing_mode); | |
789 | } | |
790 | ||
791 | /* return the supported synchronous timing mode. */ | |
792 | static inline int onfi_get_sync_timing_mode(struct nand_chip *chip) | |
793 | { | |
794 | if (!chip->onfi_version) | |
795 | return ONFI_TIMING_MODE_UNKNOWN; | |
796 | return le16_to_cpu(chip->onfi_params.src_sync_timing_mode); | |
797 | } | |
798 | ||
1d0ed69d HS |
799 | /* |
800 | * Check if it is a SLC nand. | |
801 | * The !nand_is_slc() can be used to check the MLC/TLC nand chips. | |
802 | * We do not distinguish the MLC and TLC now. | |
803 | */ | |
804 | static inline bool nand_is_slc(struct nand_chip *chip) | |
805 | { | |
7db906b7 | 806 | return chip->bits_per_cell == 1; |
1d0ed69d | 807 | } |
1da177e4 | 808 | #endif /* __LINUX_MTD_NAND_H */ |