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1da177e4 LT |
1 | /* |
2 | * linux/include/linux/mtd/nand.h | |
3 | * | |
a1452a37 DW |
4 | * Copyright © 2000-2010 David Woodhouse <dwmw2@infradead.org> |
5 | * Steven J. Hill <sjhill@realitydiluted.com> | |
6 | * Thomas Gleixner <tglx@linutronix.de> | |
1da177e4 | 7 | * |
1da177e4 LT |
8 | * This program is free software; you can redistribute it and/or modify |
9 | * it under the terms of the GNU General Public License version 2 as | |
10 | * published by the Free Software Foundation. | |
11 | * | |
2c0a2bed TG |
12 | * Info: |
13 | * Contains standard defines and IDs for NAND flash devices | |
1da177e4 | 14 | * |
2c0a2bed TG |
15 | * Changelog: |
16 | * See git changelog. | |
1da177e4 LT |
17 | */ |
18 | #ifndef __LINUX_MTD_NAND_H | |
19 | #define __LINUX_MTD_NAND_H | |
20 | ||
1da177e4 LT |
21 | #include <linux/wait.h> |
22 | #include <linux/spinlock.h> | |
23 | #include <linux/mtd/mtd.h> | |
30631cb8 | 24 | #include <linux/mtd/flashchip.h> |
c62d81bc | 25 | #include <linux/mtd/bbm.h> |
1da177e4 LT |
26 | |
27 | struct mtd_info; | |
5e81e88a | 28 | struct nand_flash_dev; |
1da177e4 | 29 | /* Scan and identify a NAND device */ |
a0491fc4 SAS |
30 | extern int nand_scan(struct mtd_info *mtd, int max_chips); |
31 | /* | |
32 | * Separate phases of nand_scan(), allowing board driver to intervene | |
33 | * and override command or ECC setup according to flash type. | |
34 | */ | |
5e81e88a DW |
35 | extern int nand_scan_ident(struct mtd_info *mtd, int max_chips, |
36 | struct nand_flash_dev *table); | |
3b85c321 DW |
37 | extern int nand_scan_tail(struct mtd_info *mtd); |
38 | ||
1da177e4 | 39 | /* Free resources held by the NAND device */ |
a0491fc4 | 40 | extern void nand_release(struct mtd_info *mtd); |
1da177e4 | 41 | |
b77d95c7 DW |
42 | /* Internal helper for board drivers which need to override command function */ |
43 | extern void nand_wait_ready(struct mtd_info *mtd); | |
44 | ||
7854d3f7 | 45 | /* locks all blocks present in the device */ |
7d70f334 VS |
46 | extern int nand_lock(struct mtd_info *mtd, loff_t ofs, uint64_t len); |
47 | ||
7854d3f7 | 48 | /* unlocks specified locked blocks */ |
7d70f334 VS |
49 | extern int nand_unlock(struct mtd_info *mtd, loff_t ofs, uint64_t len); |
50 | ||
1da177e4 LT |
51 | /* The maximum number of NAND chips in an array */ |
52 | #define NAND_MAX_CHIPS 8 | |
53 | ||
a0491fc4 SAS |
54 | /* |
55 | * This constant declares the max. oobsize / page, which | |
1da177e4 LT |
56 | * is supported now. If you add a chip with bigger oobsize/page |
57 | * adjust this accordingly. | |
58 | */ | |
b9e48534 | 59 | #define NAND_MAX_OOBSIZE 640 |
5c709ee9 | 60 | #define NAND_MAX_PAGESIZE 8192 |
1da177e4 LT |
61 | |
62 | /* | |
63 | * Constants for hardware specific CLE/ALE/NCE function | |
7abd3ef9 TG |
64 | * |
65 | * These are bits which can be or'ed to set/clear multiple | |
66 | * bits in one go. | |
67 | */ | |
1da177e4 | 68 | /* Select the chip by setting nCE to low */ |
7abd3ef9 | 69 | #define NAND_NCE 0x01 |
1da177e4 | 70 | /* Select the command latch by setting CLE to high */ |
7abd3ef9 | 71 | #define NAND_CLE 0x02 |
1da177e4 | 72 | /* Select the address latch by setting ALE to high */ |
7abd3ef9 TG |
73 | #define NAND_ALE 0x04 |
74 | ||
75 | #define NAND_CTRL_CLE (NAND_NCE | NAND_CLE) | |
76 | #define NAND_CTRL_ALE (NAND_NCE | NAND_ALE) | |
77 | #define NAND_CTRL_CHANGE 0x80 | |
1da177e4 LT |
78 | |
79 | /* | |
80 | * Standard NAND flash commands | |
81 | */ | |
82 | #define NAND_CMD_READ0 0 | |
83 | #define NAND_CMD_READ1 1 | |
7bc3312b | 84 | #define NAND_CMD_RNDOUT 5 |
1da177e4 LT |
85 | #define NAND_CMD_PAGEPROG 0x10 |
86 | #define NAND_CMD_READOOB 0x50 | |
87 | #define NAND_CMD_ERASE1 0x60 | |
88 | #define NAND_CMD_STATUS 0x70 | |
1da177e4 | 89 | #define NAND_CMD_SEQIN 0x80 |
7bc3312b | 90 | #define NAND_CMD_RNDIN 0x85 |
1da177e4 LT |
91 | #define NAND_CMD_READID 0x90 |
92 | #define NAND_CMD_ERASE2 0xd0 | |
caa4b6f2 | 93 | #define NAND_CMD_PARAM 0xec |
7db03ecc HS |
94 | #define NAND_CMD_GET_FEATURES 0xee |
95 | #define NAND_CMD_SET_FEATURES 0xef | |
1da177e4 LT |
96 | #define NAND_CMD_RESET 0xff |
97 | ||
7d70f334 VS |
98 | #define NAND_CMD_LOCK 0x2a |
99 | #define NAND_CMD_UNLOCK1 0x23 | |
100 | #define NAND_CMD_UNLOCK2 0x24 | |
101 | ||
1da177e4 LT |
102 | /* Extended commands for large page devices */ |
103 | #define NAND_CMD_READSTART 0x30 | |
7bc3312b | 104 | #define NAND_CMD_RNDOUTSTART 0xE0 |
1da177e4 LT |
105 | #define NAND_CMD_CACHEDPROG 0x15 |
106 | ||
7abd3ef9 TG |
107 | #define NAND_CMD_NONE -1 |
108 | ||
1da177e4 LT |
109 | /* Status bits */ |
110 | #define NAND_STATUS_FAIL 0x01 | |
111 | #define NAND_STATUS_FAIL_N1 0x02 | |
112 | #define NAND_STATUS_TRUE_READY 0x20 | |
113 | #define NAND_STATUS_READY 0x40 | |
114 | #define NAND_STATUS_WP 0x80 | |
115 | ||
61ecfa87 | 116 | /* |
1da177e4 LT |
117 | * Constants for ECC_MODES |
118 | */ | |
6dfc6d25 TG |
119 | typedef enum { |
120 | NAND_ECC_NONE, | |
121 | NAND_ECC_SOFT, | |
122 | NAND_ECC_HW, | |
123 | NAND_ECC_HW_SYNDROME, | |
6e0cb135 | 124 | NAND_ECC_HW_OOB_FIRST, |
193bd400 | 125 | NAND_ECC_SOFT_BCH, |
6dfc6d25 | 126 | } nand_ecc_modes_t; |
1da177e4 LT |
127 | |
128 | /* | |
129 | * Constants for Hardware ECC | |
068e3c0a | 130 | */ |
1da177e4 LT |
131 | /* Reset Hardware ECC for read */ |
132 | #define NAND_ECC_READ 0 | |
133 | /* Reset Hardware ECC for write */ | |
134 | #define NAND_ECC_WRITE 1 | |
7854d3f7 | 135 | /* Enable Hardware ECC before syndrome is read back from flash */ |
1da177e4 LT |
136 | #define NAND_ECC_READSYN 2 |
137 | ||
068e3c0a DM |
138 | /* Bit mask for flags passed to do_nand_read_ecc */ |
139 | #define NAND_GET_DEVICE 0x80 | |
140 | ||
141 | ||
a0491fc4 SAS |
142 | /* |
143 | * Option constants for bizarre disfunctionality and real | |
144 | * features. | |
145 | */ | |
7854d3f7 | 146 | /* Buswidth is 16 bit */ |
1da177e4 | 147 | #define NAND_BUSWIDTH_16 0x00000002 |
1da177e4 LT |
148 | /* Chip has cache program function */ |
149 | #define NAND_CACHEPRG 0x00000008 | |
5bc7c33c BN |
150 | /* |
151 | * Chip requires ready check on read (for auto-incremented sequential read). | |
152 | * True only for small page devices; large page devices do not support | |
153 | * autoincrement. | |
154 | */ | |
155 | #define NAND_NEED_READRDY 0x00000100 | |
156 | ||
29072b96 TG |
157 | /* Chip does not allow subpage writes */ |
158 | #define NAND_NO_SUBPAGE_WRITE 0x00000200 | |
159 | ||
93edbad6 ML |
160 | /* Device is one of 'new' xD cards that expose fake nand command set */ |
161 | #define NAND_BROKEN_XD 0x00000400 | |
162 | ||
163 | /* Device behaves just like nand, but is readonly */ | |
164 | #define NAND_ROM 0x00000800 | |
165 | ||
a5ff4f10 JW |
166 | /* Device supports subpage reads */ |
167 | #define NAND_SUBPAGE_READ 0x00001000 | |
168 | ||
1da177e4 | 169 | /* Options valid for Samsung large page devices */ |
3239a6cd | 170 | #define NAND_SAMSUNG_LP_OPTIONS NAND_CACHEPRG |
1da177e4 LT |
171 | |
172 | /* Macros to identify the above */ | |
1da177e4 | 173 | #define NAND_HAS_CACHEPROG(chip) ((chip->options & NAND_CACHEPRG)) |
a5ff4f10 | 174 | #define NAND_HAS_SUBPAGE_READ(chip) ((chip->options & NAND_SUBPAGE_READ)) |
1da177e4 | 175 | |
1da177e4 | 176 | /* Non chip related options */ |
0040bf38 | 177 | /* This option skips the bbt scan during initialization. */ |
b4dc53e1 | 178 | #define NAND_SKIP_BBTSCAN 0x00010000 |
a0491fc4 SAS |
179 | /* |
180 | * This option is defined if the board driver allocates its own buffers | |
181 | * (e.g. because it needs them DMA-coherent). | |
182 | */ | |
b4dc53e1 | 183 | #define NAND_OWN_BUFFERS 0x00020000 |
b1c6e6db | 184 | /* Chip may not exist, so silence any errors in scan */ |
b4dc53e1 | 185 | #define NAND_SCAN_SILENT_NODEV 0x00040000 |
64b37b2a MC |
186 | /* |
187 | * Autodetect nand buswidth with readid/onfi. | |
188 | * This suppose the driver will configure the hardware in 8 bits mode | |
189 | * when calling nand_scan_ident, and update its configuration | |
190 | * before calling nand_scan_tail. | |
191 | */ | |
192 | #define NAND_BUSWIDTH_AUTO 0x00080000 | |
b1c6e6db | 193 | |
1da177e4 | 194 | /* Options set by nand scan */ |
a36ed299 | 195 | /* Nand scan has allocated controller struct */ |
f75e5097 | 196 | #define NAND_CONTROLLER_ALLOC 0x80000000 |
1da177e4 | 197 | |
29072b96 TG |
198 | /* Cell info constants */ |
199 | #define NAND_CI_CHIPNR_MSK 0x03 | |
200 | #define NAND_CI_CELLTYPE_MSK 0x0C | |
1da177e4 | 201 | |
1da177e4 LT |
202 | /* Keep gcc happy */ |
203 | struct nand_chip; | |
204 | ||
3e70192c HS |
205 | /* ONFI timing mode, used in both asynchronous and synchronous mode */ |
206 | #define ONFI_TIMING_MODE_0 (1 << 0) | |
207 | #define ONFI_TIMING_MODE_1 (1 << 1) | |
208 | #define ONFI_TIMING_MODE_2 (1 << 2) | |
209 | #define ONFI_TIMING_MODE_3 (1 << 3) | |
210 | #define ONFI_TIMING_MODE_4 (1 << 4) | |
211 | #define ONFI_TIMING_MODE_5 (1 << 5) | |
212 | #define ONFI_TIMING_MODE_UNKNOWN (1 << 6) | |
213 | ||
7db03ecc HS |
214 | /* ONFI feature address */ |
215 | #define ONFI_FEATURE_ADDR_TIMING_MODE 0x1 | |
216 | ||
217 | /* ONFI subfeature parameters length */ | |
218 | #define ONFI_SUBFEATURE_PARAM_LEN 4 | |
219 | ||
d1e1f4e4 FF |
220 | struct nand_onfi_params { |
221 | /* rev info and features block */ | |
b46daf7e SAS |
222 | /* 'O' 'N' 'F' 'I' */ |
223 | u8 sig[4]; | |
224 | __le16 revision; | |
225 | __le16 features; | |
226 | __le16 opt_cmd; | |
227 | u8 reserved[22]; | |
d1e1f4e4 FF |
228 | |
229 | /* manufacturer information block */ | |
b46daf7e SAS |
230 | char manufacturer[12]; |
231 | char model[20]; | |
232 | u8 jedec_id; | |
233 | __le16 date_code; | |
234 | u8 reserved2[13]; | |
d1e1f4e4 FF |
235 | |
236 | /* memory organization block */ | |
b46daf7e SAS |
237 | __le32 byte_per_page; |
238 | __le16 spare_bytes_per_page; | |
239 | __le32 data_bytes_per_ppage; | |
240 | __le16 spare_bytes_per_ppage; | |
241 | __le32 pages_per_block; | |
242 | __le32 blocks_per_lun; | |
243 | u8 lun_count; | |
244 | u8 addr_cycles; | |
245 | u8 bits_per_cell; | |
246 | __le16 bb_per_lun; | |
247 | __le16 block_endurance; | |
248 | u8 guaranteed_good_blocks; | |
249 | __le16 guaranteed_block_endurance; | |
250 | u8 programs_per_page; | |
251 | u8 ppage_attr; | |
252 | u8 ecc_bits; | |
253 | u8 interleaved_bits; | |
254 | u8 interleaved_ops; | |
255 | u8 reserved3[13]; | |
d1e1f4e4 FF |
256 | |
257 | /* electrical parameter block */ | |
b46daf7e SAS |
258 | u8 io_pin_capacitance_max; |
259 | __le16 async_timing_mode; | |
260 | __le16 program_cache_timing_mode; | |
261 | __le16 t_prog; | |
262 | __le16 t_bers; | |
263 | __le16 t_r; | |
264 | __le16 t_ccs; | |
265 | __le16 src_sync_timing_mode; | |
266 | __le16 src_ssync_features; | |
267 | __le16 clk_pin_capacitance_typ; | |
268 | __le16 io_pin_capacitance_typ; | |
269 | __le16 input_pin_capacitance_typ; | |
270 | u8 input_pin_capacitance_max; | |
271 | u8 driver_strenght_support; | |
272 | __le16 t_int_r; | |
273 | __le16 t_ald; | |
274 | u8 reserved4[7]; | |
d1e1f4e4 FF |
275 | |
276 | /* vendor */ | |
b46daf7e | 277 | u8 reserved5[90]; |
d1e1f4e4 FF |
278 | |
279 | __le16 crc; | |
280 | } __attribute__((packed)); | |
281 | ||
282 | #define ONFI_CRC_BASE 0x4F4E | |
283 | ||
1da177e4 | 284 | /** |
844d3b42 | 285 | * struct nand_hw_control - Control structure for hardware controller (e.g ECC generator) shared among independent devices |
61ecfa87 | 286 | * @lock: protection lock |
1da177e4 | 287 | * @active: the mtd device which holds the controller currently |
a0491fc4 SAS |
288 | * @wq: wait queue to sleep on if a NAND operation is in |
289 | * progress used instead of the per chip wait queue | |
290 | * when a hw controller is available. | |
1da177e4 LT |
291 | */ |
292 | struct nand_hw_control { | |
b46daf7e | 293 | spinlock_t lock; |
1da177e4 | 294 | struct nand_chip *active; |
0dfc6246 | 295 | wait_queue_head_t wq; |
1da177e4 LT |
296 | }; |
297 | ||
6dfc6d25 | 298 | /** |
7854d3f7 BN |
299 | * struct nand_ecc_ctrl - Control structure for ECC |
300 | * @mode: ECC mode | |
301 | * @steps: number of ECC steps per page | |
302 | * @size: data bytes per ECC step | |
303 | * @bytes: ECC bytes per step | |
1d0b95b0 | 304 | * @strength: max number of correctible bits per ECC step |
7854d3f7 BN |
305 | * @total: total number of ECC bytes per page |
306 | * @prepad: padding information for syndrome based ECC generators | |
307 | * @postpad: padding information for syndrome based ECC generators | |
844d3b42 | 308 | * @layout: ECC layout control struct pointer |
7854d3f7 BN |
309 | * @priv: pointer to private ECC control data |
310 | * @hwctl: function to control hardware ECC generator. Must only | |
6dfc6d25 | 311 | * be provided if an hardware ECC is available |
7854d3f7 BN |
312 | * @calculate: function for ECC calculation or readback from ECC hardware |
313 | * @correct: function for ECC correction, matching to ECC generator (sw/hw) | |
956e944c DW |
314 | * @read_page_raw: function to read a raw page without ECC |
315 | * @write_page_raw: function to write a raw page without ECC | |
7854d3f7 | 316 | * @read_page: function to read a page according to the ECC generator |
5ca7f415 MD |
317 | * requirements; returns maximum number of bitflips corrected in |
318 | * any single ECC step, 0 if bitflips uncorrectable, -EIO hw error | |
319 | * @read_subpage: function to read parts of the page covered by ECC; | |
320 | * returns same as read_page() | |
7854d3f7 | 321 | * @write_page: function to write a page according to the ECC generator |
a0491fc4 | 322 | * requirements. |
9ce244b3 | 323 | * @write_oob_raw: function to write chip OOB data without ECC |
c46f6483 | 324 | * @read_oob_raw: function to read chip OOB data without ECC |
844d3b42 RD |
325 | * @read_oob: function to read chip OOB data |
326 | * @write_oob: function to write chip OOB data | |
6dfc6d25 TG |
327 | */ |
328 | struct nand_ecc_ctrl { | |
b46daf7e SAS |
329 | nand_ecc_modes_t mode; |
330 | int steps; | |
331 | int size; | |
332 | int bytes; | |
333 | int total; | |
1d0b95b0 | 334 | int strength; |
b46daf7e SAS |
335 | int prepad; |
336 | int postpad; | |
5bd34c09 | 337 | struct nand_ecclayout *layout; |
193bd400 | 338 | void *priv; |
b46daf7e SAS |
339 | void (*hwctl)(struct mtd_info *mtd, int mode); |
340 | int (*calculate)(struct mtd_info *mtd, const uint8_t *dat, | |
341 | uint8_t *ecc_code); | |
342 | int (*correct)(struct mtd_info *mtd, uint8_t *dat, uint8_t *read_ecc, | |
343 | uint8_t *calc_ecc); | |
344 | int (*read_page_raw)(struct mtd_info *mtd, struct nand_chip *chip, | |
1fbb938d | 345 | uint8_t *buf, int oob_required, int page); |
fdbad98d | 346 | int (*write_page_raw)(struct mtd_info *mtd, struct nand_chip *chip, |
1fbb938d | 347 | const uint8_t *buf, int oob_required); |
b46daf7e | 348 | int (*read_page)(struct mtd_info *mtd, struct nand_chip *chip, |
1fbb938d | 349 | uint8_t *buf, int oob_required, int page); |
b46daf7e SAS |
350 | int (*read_subpage)(struct mtd_info *mtd, struct nand_chip *chip, |
351 | uint32_t offs, uint32_t len, uint8_t *buf); | |
fdbad98d | 352 | int (*write_page)(struct mtd_info *mtd, struct nand_chip *chip, |
1fbb938d | 353 | const uint8_t *buf, int oob_required); |
9ce244b3 BN |
354 | int (*write_oob_raw)(struct mtd_info *mtd, struct nand_chip *chip, |
355 | int page); | |
c46f6483 | 356 | int (*read_oob_raw)(struct mtd_info *mtd, struct nand_chip *chip, |
5c2ffb11 SL |
357 | int page); |
358 | int (*read_oob)(struct mtd_info *mtd, struct nand_chip *chip, int page); | |
b46daf7e SAS |
359 | int (*write_oob)(struct mtd_info *mtd, struct nand_chip *chip, |
360 | int page); | |
f75e5097 TG |
361 | }; |
362 | ||
363 | /** | |
364 | * struct nand_buffers - buffer structure for read/write | |
7854d3f7 BN |
365 | * @ecccalc: buffer for calculated ECC |
366 | * @ecccode: buffer for ECC read from flash | |
f75e5097 | 367 | * @databuf: buffer for data - dynamically sized |
f75e5097 TG |
368 | * |
369 | * Do not change the order of buffers. databuf and oobrbuf must be in | |
370 | * consecutive order. | |
371 | */ | |
372 | struct nand_buffers { | |
373 | uint8_t ecccalc[NAND_MAX_OOBSIZE]; | |
374 | uint8_t ecccode[NAND_MAX_OOBSIZE]; | |
7dcdcbef | 375 | uint8_t databuf[NAND_MAX_PAGESIZE + NAND_MAX_OOBSIZE]; |
6dfc6d25 TG |
376 | }; |
377 | ||
1da177e4 LT |
378 | /** |
379 | * struct nand_chip - NAND Private Flash Chip Data | |
a0491fc4 SAS |
380 | * @IO_ADDR_R: [BOARDSPECIFIC] address to read the 8 I/O lines of the |
381 | * flash device | |
382 | * @IO_ADDR_W: [BOARDSPECIFIC] address to write the 8 I/O lines of the | |
383 | * flash device. | |
1da177e4 | 384 | * @read_byte: [REPLACEABLE] read one byte from the chip |
1da177e4 | 385 | * @read_word: [REPLACEABLE] read one word from the chip |
1da177e4 LT |
386 | * @write_buf: [REPLACEABLE] write data from the buffer to the chip |
387 | * @read_buf: [REPLACEABLE] read data from the chip into the buffer | |
1da177e4 LT |
388 | * @select_chip: [REPLACEABLE] select chip nr |
389 | * @block_bad: [REPLACEABLE] check, if the block is bad | |
390 | * @block_markbad: [REPLACEABLE] mark the block bad | |
25985edc | 391 | * @cmd_ctrl: [BOARDSPECIFIC] hardwarespecific function for controlling |
7abd3ef9 | 392 | * ALE/CLE/nCE. Also used to write command and address |
25985edc | 393 | * @init_size: [BOARDSPECIFIC] hardwarespecific function for setting |
12a40a57 HS |
394 | * mtd->oobsize, mtd->writesize and so on. |
395 | * @id_data contains the 8 bytes values of NAND_CMD_READID. | |
396 | * Return with the bus width. | |
7854d3f7 | 397 | * @dev_ready: [BOARDSPECIFIC] hardwarespecific function for accessing |
a0491fc4 SAS |
398 | * device ready/busy line. If set to NULL no access to |
399 | * ready/busy is available and the ready/busy information | |
400 | * is read from the chip status register. | |
401 | * @cmdfunc: [REPLACEABLE] hardwarespecific function for writing | |
402 | * commands to the chip. | |
403 | * @waitfunc: [REPLACEABLE] hardwarespecific function for wait on | |
404 | * ready. | |
7854d3f7 | 405 | * @ecc: [BOARDSPECIFIC] ECC control structure |
844d3b42 RD |
406 | * @buffers: buffer structure for read/write |
407 | * @hwcontrol: platform-specific hardware control structure | |
a0491fc4 SAS |
408 | * @erase_cmd: [INTERN] erase command write function, selectable due |
409 | * to AND support. | |
1da177e4 | 410 | * @scan_bbt: [REPLACEABLE] function to scan bad block table |
25985edc | 411 | * @chip_delay: [BOARDSPECIFIC] chip dependent delay for transferring |
a0491fc4 | 412 | * data from array to read regs (tR). |
2c0a2bed | 413 | * @state: [INTERN] the current state of the NAND device |
e9195edc BN |
414 | * @oob_poi: "poison value buffer," used for laying out OOB data |
415 | * before writing | |
a0491fc4 SAS |
416 | * @page_shift: [INTERN] number of address bits in a page (column |
417 | * address bits). | |
1da177e4 LT |
418 | * @phys_erase_shift: [INTERN] number of address bits in a physical eraseblock |
419 | * @bbt_erase_shift: [INTERN] number of address bits in a bbt entry | |
420 | * @chip_shift: [INTERN] number of address bits in one chip | |
a0491fc4 SAS |
421 | * @options: [BOARDSPECIFIC] various chip options. They can partly |
422 | * be set to inform nand_scan about special functionality. | |
423 | * See the defines for further explanation. | |
5fb1549d BN |
424 | * @bbt_options: [INTERN] bad block specific options. All options used |
425 | * here must come from bbm.h. By default, these options | |
426 | * will be copied to the appropriate nand_bbt_descr's. | |
a0491fc4 SAS |
427 | * @badblockpos: [INTERN] position of the bad block marker in the oob |
428 | * area. | |
661a0832 BN |
429 | * @badblockbits: [INTERN] minimum number of set bits in a good block's |
430 | * bad block marker position; i.e., BBM == 11110111b is | |
431 | * not bad when badblockbits == 7 | |
552a8278 | 432 | * @cellinfo: [INTERN] MLC/multichip data from chip ident |
1da177e4 LT |
433 | * @numchips: [INTERN] number of physical chips |
434 | * @chipsize: [INTERN] the size of one chip for multichip arrays | |
435 | * @pagemask: [INTERN] page number mask = number of (pages / chip) - 1 | |
a0491fc4 SAS |
436 | * @pagebuf: [INTERN] holds the pagenumber which is currently in |
437 | * data_buf. | |
edbc4540 MD |
438 | * @pagebuf_bitflips: [INTERN] holds the bitflip count for the page which is |
439 | * currently in data_buf. | |
29072b96 | 440 | * @subpagesize: [INTERN] holds the subpagesize |
a0491fc4 SAS |
441 | * @onfi_version: [INTERN] holds the chip ONFI version (BCD encoded), |
442 | * non 0 if ONFI supported. | |
443 | * @onfi_params: [INTERN] holds the ONFI page parameter when ONFI is | |
444 | * supported, 0 otherwise. | |
9ef525a9 RD |
445 | * @onfi_set_features: [REPLACEABLE] set the features for ONFI nand |
446 | * @onfi_get_features: [REPLACEABLE] get the features for ONFI nand | |
7854d3f7 | 447 | * @ecclayout: [REPLACEABLE] the default ECC placement scheme |
1da177e4 | 448 | * @bbt: [INTERN] bad block table pointer |
a0491fc4 SAS |
449 | * @bbt_td: [REPLACEABLE] bad block table descriptor for flash |
450 | * lookup. | |
1da177e4 | 451 | * @bbt_md: [REPLACEABLE] bad block table mirror descriptor |
a0491fc4 SAS |
452 | * @badblock_pattern: [REPLACEABLE] bad block scan pattern used for initial |
453 | * bad block scan. | |
454 | * @controller: [REPLACEABLE] a pointer to a hardware controller | |
7854d3f7 | 455 | * structure which is shared among multiple independent |
a0491fc4 | 456 | * devices. |
32c8db8f | 457 | * @priv: [OPTIONAL] pointer to private chip data |
a0491fc4 SAS |
458 | * @errstat: [OPTIONAL] hardware specific function to perform |
459 | * additional error status checks (determine if errors are | |
460 | * correctable). | |
351edd24 | 461 | * @write_page: [REPLACEABLE] High-level page write function |
1da177e4 | 462 | */ |
61ecfa87 | 463 | |
1da177e4 | 464 | struct nand_chip { |
b46daf7e SAS |
465 | void __iomem *IO_ADDR_R; |
466 | void __iomem *IO_ADDR_W; | |
467 | ||
468 | uint8_t (*read_byte)(struct mtd_info *mtd); | |
469 | u16 (*read_word)(struct mtd_info *mtd); | |
470 | void (*write_buf)(struct mtd_info *mtd, const uint8_t *buf, int len); | |
471 | void (*read_buf)(struct mtd_info *mtd, uint8_t *buf, int len); | |
b46daf7e SAS |
472 | void (*select_chip)(struct mtd_info *mtd, int chip); |
473 | int (*block_bad)(struct mtd_info *mtd, loff_t ofs, int getchip); | |
474 | int (*block_markbad)(struct mtd_info *mtd, loff_t ofs); | |
475 | void (*cmd_ctrl)(struct mtd_info *mtd, int dat, unsigned int ctrl); | |
476 | int (*init_size)(struct mtd_info *mtd, struct nand_chip *this, | |
477 | u8 *id_data); | |
478 | int (*dev_ready)(struct mtd_info *mtd); | |
479 | void (*cmdfunc)(struct mtd_info *mtd, unsigned command, int column, | |
480 | int page_addr); | |
481 | int(*waitfunc)(struct mtd_info *mtd, struct nand_chip *this); | |
482 | void (*erase_cmd)(struct mtd_info *mtd, int page); | |
483 | int (*scan_bbt)(struct mtd_info *mtd); | |
484 | int (*errstat)(struct mtd_info *mtd, struct nand_chip *this, int state, | |
485 | int status, int page); | |
486 | int (*write_page)(struct mtd_info *mtd, struct nand_chip *chip, | |
1fbb938d BN |
487 | const uint8_t *buf, int oob_required, int page, |
488 | int cached, int raw); | |
7db03ecc HS |
489 | int (*onfi_set_features)(struct mtd_info *mtd, struct nand_chip *chip, |
490 | int feature_addr, uint8_t *subfeature_para); | |
491 | int (*onfi_get_features)(struct mtd_info *mtd, struct nand_chip *chip, | |
492 | int feature_addr, uint8_t *subfeature_para); | |
b46daf7e SAS |
493 | |
494 | int chip_delay; | |
495 | unsigned int options; | |
5fb1549d | 496 | unsigned int bbt_options; |
b46daf7e SAS |
497 | |
498 | int page_shift; | |
499 | int phys_erase_shift; | |
500 | int bbt_erase_shift; | |
501 | int chip_shift; | |
502 | int numchips; | |
503 | uint64_t chipsize; | |
504 | int pagemask; | |
505 | int pagebuf; | |
edbc4540 | 506 | unsigned int pagebuf_bitflips; |
b46daf7e SAS |
507 | int subpagesize; |
508 | uint8_t cellinfo; | |
509 | int badblockpos; | |
510 | int badblockbits; | |
511 | ||
512 | int onfi_version; | |
d1e1f4e4 FF |
513 | struct nand_onfi_params onfi_params; |
514 | ||
b46daf7e | 515 | flstate_t state; |
f75e5097 | 516 | |
b46daf7e SAS |
517 | uint8_t *oob_poi; |
518 | struct nand_hw_control *controller; | |
519 | struct nand_ecclayout *ecclayout; | |
f75e5097 TG |
520 | |
521 | struct nand_ecc_ctrl ecc; | |
4bf63fcb | 522 | struct nand_buffers *buffers; |
f75e5097 TG |
523 | struct nand_hw_control hwcontrol; |
524 | ||
b46daf7e SAS |
525 | uint8_t *bbt; |
526 | struct nand_bbt_descr *bbt_td; | |
527 | struct nand_bbt_descr *bbt_md; | |
f75e5097 | 528 | |
b46daf7e | 529 | struct nand_bbt_descr *badblock_pattern; |
f75e5097 | 530 | |
b46daf7e | 531 | void *priv; |
1da177e4 LT |
532 | }; |
533 | ||
534 | /* | |
535 | * NAND Flash Manufacturer ID Codes | |
536 | */ | |
537 | #define NAND_MFR_TOSHIBA 0x98 | |
538 | #define NAND_MFR_SAMSUNG 0xec | |
539 | #define NAND_MFR_FUJITSU 0x04 | |
540 | #define NAND_MFR_NATIONAL 0x8f | |
541 | #define NAND_MFR_RENESAS 0x07 | |
542 | #define NAND_MFR_STMICRO 0x20 | |
2c0a2bed | 543 | #define NAND_MFR_HYNIX 0xad |
8c60e547 | 544 | #define NAND_MFR_MICRON 0x2c |
30eb0db0 | 545 | #define NAND_MFR_AMD 0x01 |
c1257b47 | 546 | #define NAND_MFR_MACRONIX 0xc2 |
b1ccfab3 | 547 | #define NAND_MFR_EON 0x92 |
1da177e4 LT |
548 | |
549 | /** | |
550 | * struct nand_flash_dev - NAND Flash Device ID Structure | |
68aa352d AB |
551 | * @name: a human-readable name of the NAND chip |
552 | * @dev_id: the device ID (the second byte of the full chip ID array) | |
553 | * @pagesize: size of the NAND page in bytes; if 0, then the real page size (as | |
554 | * well as the eraseblock size) is determined from the extended NAND | |
555 | * chip ID array) | |
556 | * @erasesize: eraseblock size in bytes (determined from the extended ID if 0) | |
557 | * @chipsize: total chip size in MiB | |
558 | * @options: stores various chip bit options | |
1da177e4 LT |
559 | */ |
560 | struct nand_flash_dev { | |
561 | char *name; | |
68aa352d | 562 | int dev_id; |
1da177e4 LT |
563 | unsigned long pagesize; |
564 | unsigned long chipsize; | |
565 | unsigned long erasesize; | |
566 | unsigned long options; | |
567 | }; | |
568 | ||
569 | /** | |
570 | * struct nand_manufacturers - NAND Flash Manufacturer ID Structure | |
571 | * @name: Manufacturer name | |
2c0a2bed | 572 | * @id: manufacturer ID code of device. |
1da177e4 LT |
573 | */ |
574 | struct nand_manufacturers { | |
575 | int id; | |
a0491fc4 | 576 | char *name; |
1da177e4 LT |
577 | }; |
578 | ||
579 | extern struct nand_flash_dev nand_flash_ids[]; | |
580 | extern struct nand_manufacturers nand_manuf_ids[]; | |
581 | ||
f5bbdacc TG |
582 | extern int nand_scan_bbt(struct mtd_info *mtd, struct nand_bbt_descr *bd); |
583 | extern int nand_update_bbt(struct mtd_info *mtd, loff_t offs); | |
584 | extern int nand_default_bbt(struct mtd_info *mtd); | |
585 | extern int nand_isbad_bbt(struct mtd_info *mtd, loff_t offs, int allowbbt); | |
586 | extern int nand_erase_nand(struct mtd_info *mtd, struct erase_info *instr, | |
587 | int allowbbt); | |
588 | extern int nand_do_read(struct mtd_info *mtd, loff_t from, size_t len, | |
a0491fc4 | 589 | size_t *retlen, uint8_t *buf); |
1da177e4 | 590 | |
41796c2e TG |
591 | /** |
592 | * struct platform_nand_chip - chip level device structure | |
41796c2e | 593 | * @nr_chips: max. number of chips to scan for |
844d3b42 | 594 | * @chip_offset: chip number offset |
8be834f7 | 595 | * @nr_partitions: number of partitions pointed to by partitions (or zero) |
41796c2e TG |
596 | * @partitions: mtd partition list |
597 | * @chip_delay: R/B delay value in us | |
598 | * @options: Option flags, e.g. 16bit buswidth | |
a40f7341 | 599 | * @bbt_options: BBT option flags, e.g. NAND_BBT_USE_FLASH |
7854d3f7 | 600 | * @ecclayout: ECC layout info structure |
972edcb7 | 601 | * @part_probe_types: NULL-terminated array of probe types |
41796c2e TG |
602 | */ |
603 | struct platform_nand_chip { | |
b46daf7e SAS |
604 | int nr_chips; |
605 | int chip_offset; | |
606 | int nr_partitions; | |
607 | struct mtd_partition *partitions; | |
608 | struct nand_ecclayout *ecclayout; | |
609 | int chip_delay; | |
610 | unsigned int options; | |
a40f7341 | 611 | unsigned int bbt_options; |
b46daf7e | 612 | const char **part_probe_types; |
41796c2e TG |
613 | }; |
614 | ||
bf95efd4 HS |
615 | /* Keep gcc happy */ |
616 | struct platform_device; | |
617 | ||
41796c2e TG |
618 | /** |
619 | * struct platform_nand_ctrl - controller level device structure | |
bf95efd4 HS |
620 | * @probe: platform specific function to probe/setup hardware |
621 | * @remove: platform specific function to remove/teardown hardware | |
41796c2e TG |
622 | * @hwcontrol: platform specific hardware control structure |
623 | * @dev_ready: platform specific function to read ready/busy pin | |
624 | * @select_chip: platform specific chip select function | |
972edcb7 VW |
625 | * @cmd_ctrl: platform specific function for controlling |
626 | * ALE/CLE/nCE. Also used to write command and address | |
d6fed9e9 AC |
627 | * @write_buf: platform specific function for write buffer |
628 | * @read_buf: platform specific function for read buffer | |
25806d3c | 629 | * @read_byte: platform specific function to read one byte from chip |
844d3b42 | 630 | * @priv: private data to transport driver specific settings |
41796c2e TG |
631 | * |
632 | * All fields are optional and depend on the hardware driver requirements | |
633 | */ | |
634 | struct platform_nand_ctrl { | |
b46daf7e SAS |
635 | int (*probe)(struct platform_device *pdev); |
636 | void (*remove)(struct platform_device *pdev); | |
637 | void (*hwcontrol)(struct mtd_info *mtd, int cmd); | |
638 | int (*dev_ready)(struct mtd_info *mtd); | |
639 | void (*select_chip)(struct mtd_info *mtd, int chip); | |
640 | void (*cmd_ctrl)(struct mtd_info *mtd, int dat, unsigned int ctrl); | |
641 | void (*write_buf)(struct mtd_info *mtd, const uint8_t *buf, int len); | |
642 | void (*read_buf)(struct mtd_info *mtd, uint8_t *buf, int len); | |
b4f7aa84 | 643 | unsigned char (*read_byte)(struct mtd_info *mtd); |
b46daf7e | 644 | void *priv; |
41796c2e TG |
645 | }; |
646 | ||
972edcb7 VW |
647 | /** |
648 | * struct platform_nand_data - container structure for platform-specific data | |
649 | * @chip: chip level chip structure | |
650 | * @ctrl: controller level device structure | |
651 | */ | |
652 | struct platform_nand_data { | |
b46daf7e SAS |
653 | struct platform_nand_chip chip; |
654 | struct platform_nand_ctrl ctrl; | |
972edcb7 VW |
655 | }; |
656 | ||
41796c2e TG |
657 | /* Some helpers to access the data structures */ |
658 | static inline | |
659 | struct platform_nand_chip *get_platform_nandchip(struct mtd_info *mtd) | |
660 | { | |
661 | struct nand_chip *chip = mtd->priv; | |
662 | ||
663 | return chip->priv; | |
664 | } | |
665 | ||
3e70192c HS |
666 | /* return the supported asynchronous timing mode. */ |
667 | static inline int onfi_get_async_timing_mode(struct nand_chip *chip) | |
668 | { | |
669 | if (!chip->onfi_version) | |
670 | return ONFI_TIMING_MODE_UNKNOWN; | |
671 | return le16_to_cpu(chip->onfi_params.async_timing_mode); | |
672 | } | |
673 | ||
674 | /* return the supported synchronous timing mode. */ | |
675 | static inline int onfi_get_sync_timing_mode(struct nand_chip *chip) | |
676 | { | |
677 | if (!chip->onfi_version) | |
678 | return ONFI_TIMING_MODE_UNKNOWN; | |
679 | return le16_to_cpu(chip->onfi_params.src_sync_timing_mode); | |
680 | } | |
681 | ||
1da177e4 | 682 | #endif /* __LINUX_MTD_NAND_H */ |