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1da177e4 LT |
1 | /* |
2 | * linux/include/linux/mtd/nand.h | |
3 | * | |
4 | * Copyright (c) 2000 David Woodhouse <dwmw2@mvhi.com> | |
5 | * Steven J. Hill <sjhill@realitydiluted.com> | |
6 | * Thomas Gleixner <tglx@linutronix.de> | |
7 | * | |
0040bf38 | 8 | * $Id: nand.h,v 1.71 2005/02/09 12:12:59 gleixner Exp $ |
1da177e4 LT |
9 | * |
10 | * This program is free software; you can redistribute it and/or modify | |
11 | * it under the terms of the GNU General Public License version 2 as | |
12 | * published by the Free Software Foundation. | |
13 | * | |
14 | * Info: | |
15 | * Contains standard defines and IDs for NAND flash devices | |
16 | * | |
17 | * Changelog: | |
18 | * 01-31-2000 DMW Created | |
19 | * 09-18-2000 SJH Moved structure out of the Disk-On-Chip drivers | |
20 | * so it can be used by other NAND flash device | |
21 | * drivers. I also changed the copyright since none | |
22 | * of the original contents of this file are specific | |
23 | * to DoC devices. David can whack me with a baseball | |
24 | * bat later if I did something naughty. | |
25 | * 10-11-2000 SJH Added private NAND flash structure for driver | |
26 | * 10-24-2000 SJH Added prototype for 'nand_scan' function | |
27 | * 10-29-2001 TG changed nand_chip structure to support | |
28 | * hardwarespecific function for accessing control lines | |
29 | * 02-21-2002 TG added support for different read/write adress and | |
30 | * ready/busy line access function | |
31 | * 02-26-2002 TG added chip_delay to nand_chip structure to optimize | |
32 | * command delay times for different chips | |
33 | * 04-28-2002 TG OOB config defines moved from nand.c to avoid duplicate | |
34 | * defines in jffs2/wbuf.c | |
35 | * 08-07-2002 TG forced bad block location to byte 5 of OOB, even if | |
36 | * CONFIG_MTD_NAND_ECC_JFFS2 is not set | |
37 | * 08-10-2002 TG extensions to nand_chip structure to support HW-ECC | |
38 | * | |
39 | * 08-29-2002 tglx nand_chip structure: data_poi for selecting | |
40 | * internal / fs-driver buffer | |
41 | * support for 6byte/512byte hardware ECC | |
42 | * read_ecc, write_ecc extended for different oob-layout | |
43 | * oob layout selections: NAND_NONE_OOB, NAND_JFFS2_OOB, | |
44 | * NAND_YAFFS_OOB | |
45 | * 11-25-2002 tglx Added Manufacturer code FUJITSU, NATIONAL | |
46 | * Split manufacturer and device ID structures | |
47 | * | |
48 | * 02-08-2004 tglx added option field to nand structure for chip anomalities | |
49 | * 05-25-2004 tglx added bad block table support, ST-MICRO manufacturer id | |
50 | * update of nand_chip structure description | |
28a48de7 DM |
51 | * 01-17-2005 dmarlin added extended commands for AG-AND device and added option |
52 | * for BBT_AUTO_REFRESH. | |
068e3c0a DM |
53 | * 01-20-2005 dmarlin added optional pointer to hardware specific callback for |
54 | * extra error status checks. | |
1da177e4 LT |
55 | */ |
56 | #ifndef __LINUX_MTD_NAND_H | |
57 | #define __LINUX_MTD_NAND_H | |
58 | ||
59 | #include <linux/config.h> | |
60 | #include <linux/wait.h> | |
61 | #include <linux/spinlock.h> | |
62 | #include <linux/mtd/mtd.h> | |
63 | ||
64 | struct mtd_info; | |
65 | /* Scan and identify a NAND device */ | |
66 | extern int nand_scan (struct mtd_info *mtd, int max_chips); | |
67 | /* Free resources held by the NAND device */ | |
68 | extern void nand_release (struct mtd_info *mtd); | |
69 | ||
70 | /* Read raw data from the device without ECC */ | |
71 | extern int nand_read_raw (struct mtd_info *mtd, uint8_t *buf, loff_t from, size_t len, size_t ooblen); | |
72 | ||
73 | ||
74 | /* The maximum number of NAND chips in an array */ | |
75 | #define NAND_MAX_CHIPS 8 | |
76 | ||
77 | /* This constant declares the max. oobsize / page, which | |
78 | * is supported now. If you add a chip with bigger oobsize/page | |
79 | * adjust this accordingly. | |
80 | */ | |
81 | #define NAND_MAX_OOBSIZE 64 | |
82 | ||
83 | /* | |
84 | * Constants for hardware specific CLE/ALE/NCE function | |
85 | */ | |
86 | /* Select the chip by setting nCE to low */ | |
87 | #define NAND_CTL_SETNCE 1 | |
88 | /* Deselect the chip by setting nCE to high */ | |
89 | #define NAND_CTL_CLRNCE 2 | |
90 | /* Select the command latch by setting CLE to high */ | |
91 | #define NAND_CTL_SETCLE 3 | |
92 | /* Deselect the command latch by setting CLE to low */ | |
93 | #define NAND_CTL_CLRCLE 4 | |
94 | /* Select the address latch by setting ALE to high */ | |
95 | #define NAND_CTL_SETALE 5 | |
96 | /* Deselect the address latch by setting ALE to low */ | |
97 | #define NAND_CTL_CLRALE 6 | |
98 | /* Set write protection by setting WP to high. Not used! */ | |
99 | #define NAND_CTL_SETWP 7 | |
100 | /* Clear write protection by setting WP to low. Not used! */ | |
101 | #define NAND_CTL_CLRWP 8 | |
102 | ||
103 | /* | |
104 | * Standard NAND flash commands | |
105 | */ | |
106 | #define NAND_CMD_READ0 0 | |
107 | #define NAND_CMD_READ1 1 | |
108 | #define NAND_CMD_PAGEPROG 0x10 | |
109 | #define NAND_CMD_READOOB 0x50 | |
110 | #define NAND_CMD_ERASE1 0x60 | |
111 | #define NAND_CMD_STATUS 0x70 | |
112 | #define NAND_CMD_STATUS_MULTI 0x71 | |
113 | #define NAND_CMD_SEQIN 0x80 | |
114 | #define NAND_CMD_READID 0x90 | |
115 | #define NAND_CMD_ERASE2 0xd0 | |
116 | #define NAND_CMD_RESET 0xff | |
117 | ||
118 | /* Extended commands for large page devices */ | |
119 | #define NAND_CMD_READSTART 0x30 | |
120 | #define NAND_CMD_CACHEDPROG 0x15 | |
121 | ||
28a48de7 DM |
122 | /* Extended commands for AG-AND device */ |
123 | /* | |
124 | * Note: the command for NAND_CMD_DEPLETE1 is really 0x00 but | |
125 | * there is no way to distinguish that from NAND_CMD_READ0 | |
126 | * until the remaining sequence of commands has been completed | |
127 | * so add a high order bit and mask it off in the command. | |
128 | */ | |
129 | #define NAND_CMD_DEPLETE1 0x100 | |
130 | #define NAND_CMD_DEPLETE2 0x38 | |
131 | #define NAND_CMD_STATUS_MULTI 0x71 | |
132 | #define NAND_CMD_STATUS_ERROR 0x72 | |
133 | /* multi-bank error status (banks 0-3) */ | |
134 | #define NAND_CMD_STATUS_ERROR0 0x73 | |
135 | #define NAND_CMD_STATUS_ERROR1 0x74 | |
136 | #define NAND_CMD_STATUS_ERROR2 0x75 | |
137 | #define NAND_CMD_STATUS_ERROR3 0x76 | |
138 | #define NAND_CMD_STATUS_RESET 0x7f | |
139 | #define NAND_CMD_STATUS_CLEAR 0xff | |
140 | ||
1da177e4 LT |
141 | /* Status bits */ |
142 | #define NAND_STATUS_FAIL 0x01 | |
143 | #define NAND_STATUS_FAIL_N1 0x02 | |
144 | #define NAND_STATUS_TRUE_READY 0x20 | |
145 | #define NAND_STATUS_READY 0x40 | |
146 | #define NAND_STATUS_WP 0x80 | |
147 | ||
148 | /* | |
149 | * Constants for ECC_MODES | |
150 | */ | |
151 | ||
152 | /* No ECC. Usage is not recommended ! */ | |
153 | #define NAND_ECC_NONE 0 | |
154 | /* Software ECC 3 byte ECC per 256 Byte data */ | |
155 | #define NAND_ECC_SOFT 1 | |
156 | /* Hardware ECC 3 byte ECC per 256 Byte data */ | |
157 | #define NAND_ECC_HW3_256 2 | |
158 | /* Hardware ECC 3 byte ECC per 512 Byte data */ | |
159 | #define NAND_ECC_HW3_512 3 | |
160 | /* Hardware ECC 3 byte ECC per 512 Byte data */ | |
161 | #define NAND_ECC_HW6_512 4 | |
162 | /* Hardware ECC 8 byte ECC per 512 Byte data */ | |
163 | #define NAND_ECC_HW8_512 6 | |
164 | /* Hardware ECC 12 byte ECC per 2048 Byte data */ | |
165 | #define NAND_ECC_HW12_2048 7 | |
166 | ||
167 | /* | |
168 | * Constants for Hardware ECC | |
068e3c0a | 169 | */ |
1da177e4 LT |
170 | /* Reset Hardware ECC for read */ |
171 | #define NAND_ECC_READ 0 | |
172 | /* Reset Hardware ECC for write */ | |
173 | #define NAND_ECC_WRITE 1 | |
174 | /* Enable Hardware ECC before syndrom is read back from flash */ | |
175 | #define NAND_ECC_READSYN 2 | |
176 | ||
068e3c0a DM |
177 | /* Bit mask for flags passed to do_nand_read_ecc */ |
178 | #define NAND_GET_DEVICE 0x80 | |
179 | ||
180 | ||
1da177e4 LT |
181 | /* Option constants for bizarre disfunctionality and real |
182 | * features | |
183 | */ | |
184 | /* Chip can not auto increment pages */ | |
185 | #define NAND_NO_AUTOINCR 0x00000001 | |
186 | /* Buswitdh is 16 bit */ | |
187 | #define NAND_BUSWIDTH_16 0x00000002 | |
188 | /* Device supports partial programming without padding */ | |
189 | #define NAND_NO_PADDING 0x00000004 | |
190 | /* Chip has cache program function */ | |
191 | #define NAND_CACHEPRG 0x00000008 | |
192 | /* Chip has copy back function */ | |
193 | #define NAND_COPYBACK 0x00000010 | |
194 | /* AND Chip which has 4 banks and a confusing page / block | |
195 | * assignment. See Renesas datasheet for further information */ | |
196 | #define NAND_IS_AND 0x00000020 | |
197 | /* Chip has a array of 4 pages which can be read without | |
198 | * additional ready /busy waits */ | |
199 | #define NAND_4PAGE_ARRAY 0x00000040 | |
28a48de7 DM |
200 | /* Chip requires that BBT is periodically rewritten to prevent |
201 | * bits from adjacent blocks from 'leaking' in altering data. | |
202 | * This happens with the Renesas AG-AND chips, possibly others. */ | |
203 | #define BBT_AUTO_REFRESH 0x00000080 | |
1da177e4 LT |
204 | |
205 | /* Options valid for Samsung large page devices */ | |
206 | #define NAND_SAMSUNG_LP_OPTIONS \ | |
207 | (NAND_NO_PADDING | NAND_CACHEPRG | NAND_COPYBACK) | |
208 | ||
209 | /* Macros to identify the above */ | |
210 | #define NAND_CANAUTOINCR(chip) (!(chip->options & NAND_NO_AUTOINCR)) | |
211 | #define NAND_MUST_PAD(chip) (!(chip->options & NAND_NO_PADDING)) | |
212 | #define NAND_HAS_CACHEPROG(chip) ((chip->options & NAND_CACHEPRG)) | |
213 | #define NAND_HAS_COPYBACK(chip) ((chip->options & NAND_COPYBACK)) | |
214 | ||
215 | /* Mask to zero out the chip options, which come from the id table */ | |
216 | #define NAND_CHIPOPTIONS_MSK (0x0000ffff & ~NAND_NO_AUTOINCR) | |
217 | ||
218 | /* Non chip related options */ | |
219 | /* Use a flash based bad block table. This option is passed to the | |
220 | * default bad block table function. */ | |
221 | #define NAND_USE_FLASH_BBT 0x00010000 | |
222 | /* The hw ecc generator provides a syndrome instead a ecc value on read | |
223 | * This can only work if we have the ecc bytes directly behind the | |
224 | * data bytes. Applies for DOC and AG-AND Renesas HW Reed Solomon generators */ | |
225 | #define NAND_HWECC_SYNDROME 0x00020000 | |
0040bf38 TG |
226 | /* This option skips the bbt scan during initialization. */ |
227 | #define NAND_SKIP_BBTSCAN 0x00040000 | |
1da177e4 LT |
228 | |
229 | /* Options set by nand scan */ | |
230 | /* Nand scan has allocated oob_buf */ | |
231 | #define NAND_OOBBUF_ALLOC 0x40000000 | |
232 | /* Nand scan has allocated data_buf */ | |
233 | #define NAND_DATABUF_ALLOC 0x80000000 | |
234 | ||
235 | ||
236 | /* | |
237 | * nand_state_t - chip states | |
238 | * Enumeration for NAND flash chip state | |
239 | */ | |
240 | typedef enum { | |
241 | FL_READY, | |
242 | FL_READING, | |
243 | FL_WRITING, | |
244 | FL_ERASING, | |
245 | FL_SYNCING, | |
246 | FL_CACHEDPRG, | |
247 | } nand_state_t; | |
248 | ||
249 | /* Keep gcc happy */ | |
250 | struct nand_chip; | |
251 | ||
252 | /** | |
253 | * struct nand_hw_control - Control structure for hardware controller (e.g ECC generator) shared among independend devices | |
254 | * @lock: protection lock | |
255 | * @active: the mtd device which holds the controller currently | |
256 | */ | |
257 | struct nand_hw_control { | |
258 | spinlock_t lock; | |
259 | struct nand_chip *active; | |
260 | }; | |
261 | ||
262 | /** | |
263 | * struct nand_chip - NAND Private Flash Chip Data | |
264 | * @IO_ADDR_R: [BOARDSPECIFIC] address to read the 8 I/O lines of the flash device | |
265 | * @IO_ADDR_W: [BOARDSPECIFIC] address to write the 8 I/O lines of the flash device | |
266 | * @read_byte: [REPLACEABLE] read one byte from the chip | |
267 | * @write_byte: [REPLACEABLE] write one byte to the chip | |
268 | * @read_word: [REPLACEABLE] read one word from the chip | |
269 | * @write_word: [REPLACEABLE] write one word to the chip | |
270 | * @write_buf: [REPLACEABLE] write data from the buffer to the chip | |
271 | * @read_buf: [REPLACEABLE] read data from the chip into the buffer | |
272 | * @verify_buf: [REPLACEABLE] verify buffer contents against the chip data | |
273 | * @select_chip: [REPLACEABLE] select chip nr | |
274 | * @block_bad: [REPLACEABLE] check, if the block is bad | |
275 | * @block_markbad: [REPLACEABLE] mark the block bad | |
276 | * @hwcontrol: [BOARDSPECIFIC] hardwarespecific function for accesing control-lines | |
277 | * @dev_ready: [BOARDSPECIFIC] hardwarespecific function for accesing device ready/busy line | |
278 | * If set to NULL no access to ready/busy is available and the ready/busy information | |
279 | * is read from the chip status register | |
280 | * @cmdfunc: [REPLACEABLE] hardwarespecific function for writing commands to the chip | |
281 | * @waitfunc: [REPLACEABLE] hardwarespecific function for wait on ready | |
282 | * @calculate_ecc: [REPLACEABLE] function for ecc calculation or readback from ecc hardware | |
283 | * @correct_data: [REPLACEABLE] function for ecc correction, matching to ecc generator (sw/hw) | |
284 | * @enable_hwecc: [BOARDSPECIFIC] function to enable (reset) hardware ecc generator. Must only | |
285 | * be provided if a hardware ECC is available | |
286 | * @erase_cmd: [INTERN] erase command write function, selectable due to AND support | |
287 | * @scan_bbt: [REPLACEABLE] function to scan bad block table | |
288 | * @eccmode: [BOARDSPECIFIC] mode of ecc, see defines | |
289 | * @eccsize: [INTERN] databytes used per ecc-calculation | |
290 | * @eccbytes: [INTERN] number of ecc bytes per ecc-calculation step | |
291 | * @eccsteps: [INTERN] number of ecc calculation steps per page | |
292 | * @chip_delay: [BOARDSPECIFIC] chip dependent delay for transfering data from array to read regs (tR) | |
293 | * @chip_lock: [INTERN] spinlock used to protect access to this structure and the chip | |
294 | * @wq: [INTERN] wait queue to sleep on if a NAND operation is in progress | |
295 | * @state: [INTERN] the current state of the NAND device | |
296 | * @page_shift: [INTERN] number of address bits in a page (column address bits) | |
297 | * @phys_erase_shift: [INTERN] number of address bits in a physical eraseblock | |
298 | * @bbt_erase_shift: [INTERN] number of address bits in a bbt entry | |
299 | * @chip_shift: [INTERN] number of address bits in one chip | |
300 | * @data_buf: [INTERN] internal buffer for one page + oob | |
301 | * @oob_buf: [INTERN] oob buffer for one eraseblock | |
302 | * @oobdirty: [INTERN] indicates that oob_buf must be reinitialized | |
303 | * @data_poi: [INTERN] pointer to a data buffer | |
304 | * @options: [BOARDSPECIFIC] various chip options. They can partly be set to inform nand_scan about | |
305 | * special functionality. See the defines for further explanation | |
306 | * @badblockpos: [INTERN] position of the bad block marker in the oob area | |
307 | * @numchips: [INTERN] number of physical chips | |
308 | * @chipsize: [INTERN] the size of one chip for multichip arrays | |
309 | * @pagemask: [INTERN] page number mask = number of (pages / chip) - 1 | |
310 | * @pagebuf: [INTERN] holds the pagenumber which is currently in data_buf | |
311 | * @autooob: [REPLACEABLE] the default (auto)placement scheme | |
312 | * @bbt: [INTERN] bad block table pointer | |
313 | * @bbt_td: [REPLACEABLE] bad block table descriptor for flash lookup | |
314 | * @bbt_md: [REPLACEABLE] bad block table mirror descriptor | |
315 | * @badblock_pattern: [REPLACEABLE] bad block scan pattern used for initial bad block scan | |
316 | * @controller: [OPTIONAL] a pointer to a hardware controller structure which is shared among multiple independend devices | |
317 | * @priv: [OPTIONAL] pointer to private chip date | |
068e3c0a DM |
318 | * @errstat: [OPTIONAL] hardware specific function to perform additional error status checks |
319 | * (determine if errors are correctable) | |
1da177e4 LT |
320 | */ |
321 | ||
322 | struct nand_chip { | |
323 | void __iomem *IO_ADDR_R; | |
324 | void __iomem *IO_ADDR_W; | |
325 | ||
326 | u_char (*read_byte)(struct mtd_info *mtd); | |
327 | void (*write_byte)(struct mtd_info *mtd, u_char byte); | |
328 | u16 (*read_word)(struct mtd_info *mtd); | |
329 | void (*write_word)(struct mtd_info *mtd, u16 word); | |
330 | ||
331 | void (*write_buf)(struct mtd_info *mtd, const u_char *buf, int len); | |
332 | void (*read_buf)(struct mtd_info *mtd, u_char *buf, int len); | |
333 | int (*verify_buf)(struct mtd_info *mtd, const u_char *buf, int len); | |
334 | void (*select_chip)(struct mtd_info *mtd, int chip); | |
335 | int (*block_bad)(struct mtd_info *mtd, loff_t ofs, int getchip); | |
336 | int (*block_markbad)(struct mtd_info *mtd, loff_t ofs); | |
337 | void (*hwcontrol)(struct mtd_info *mtd, int cmd); | |
338 | int (*dev_ready)(struct mtd_info *mtd); | |
339 | void (*cmdfunc)(struct mtd_info *mtd, unsigned command, int column, int page_addr); | |
340 | int (*waitfunc)(struct mtd_info *mtd, struct nand_chip *this, int state); | |
341 | int (*calculate_ecc)(struct mtd_info *mtd, const u_char *dat, u_char *ecc_code); | |
342 | int (*correct_data)(struct mtd_info *mtd, u_char *dat, u_char *read_ecc, u_char *calc_ecc); | |
343 | void (*enable_hwecc)(struct mtd_info *mtd, int mode); | |
344 | void (*erase_cmd)(struct mtd_info *mtd, int page); | |
345 | int (*scan_bbt)(struct mtd_info *mtd); | |
346 | int eccmode; | |
347 | int eccsize; | |
348 | int eccbytes; | |
349 | int eccsteps; | |
350 | int chip_delay; | |
351 | spinlock_t chip_lock; | |
352 | wait_queue_head_t wq; | |
353 | nand_state_t state; | |
354 | int page_shift; | |
355 | int phys_erase_shift; | |
356 | int bbt_erase_shift; | |
357 | int chip_shift; | |
358 | u_char *data_buf; | |
359 | u_char *oob_buf; | |
360 | int oobdirty; | |
361 | u_char *data_poi; | |
362 | unsigned int options; | |
363 | int badblockpos; | |
364 | int numchips; | |
365 | unsigned long chipsize; | |
366 | int pagemask; | |
367 | int pagebuf; | |
368 | struct nand_oobinfo *autooob; | |
369 | uint8_t *bbt; | |
370 | struct nand_bbt_descr *bbt_td; | |
371 | struct nand_bbt_descr *bbt_md; | |
372 | struct nand_bbt_descr *badblock_pattern; | |
373 | struct nand_hw_control *controller; | |
374 | void *priv; | |
068e3c0a | 375 | int (*errstat)(struct mtd_info *mtd, struct nand_chip *this, int state, int status, int page); |
1da177e4 LT |
376 | }; |
377 | ||
378 | /* | |
379 | * NAND Flash Manufacturer ID Codes | |
380 | */ | |
381 | #define NAND_MFR_TOSHIBA 0x98 | |
382 | #define NAND_MFR_SAMSUNG 0xec | |
383 | #define NAND_MFR_FUJITSU 0x04 | |
384 | #define NAND_MFR_NATIONAL 0x8f | |
385 | #define NAND_MFR_RENESAS 0x07 | |
386 | #define NAND_MFR_STMICRO 0x20 | |
f1f67a98 | 387 | #define NAND_MFR_HYNIX 0xad |
1da177e4 LT |
388 | |
389 | /** | |
390 | * struct nand_flash_dev - NAND Flash Device ID Structure | |
391 | * | |
392 | * @name: Identify the device type | |
393 | * @id: device ID code | |
394 | * @pagesize: Pagesize in bytes. Either 256 or 512 or 0 | |
395 | * If the pagesize is 0, then the real pagesize | |
396 | * and the eraseize are determined from the | |
397 | * extended id bytes in the chip | |
398 | * @erasesize: Size of an erase block in the flash device. | |
399 | * @chipsize: Total chipsize in Mega Bytes | |
400 | * @options: Bitfield to store chip relevant options | |
401 | */ | |
402 | struct nand_flash_dev { | |
403 | char *name; | |
404 | int id; | |
405 | unsigned long pagesize; | |
406 | unsigned long chipsize; | |
407 | unsigned long erasesize; | |
408 | unsigned long options; | |
409 | }; | |
410 | ||
411 | /** | |
412 | * struct nand_manufacturers - NAND Flash Manufacturer ID Structure | |
413 | * @name: Manufacturer name | |
414 | * @id: manufacturer ID code of device. | |
415 | */ | |
416 | struct nand_manufacturers { | |
417 | int id; | |
418 | char * name; | |
419 | }; | |
420 | ||
421 | extern struct nand_flash_dev nand_flash_ids[]; | |
422 | extern struct nand_manufacturers nand_manuf_ids[]; | |
423 | ||
424 | /** | |
425 | * struct nand_bbt_descr - bad block table descriptor | |
426 | * @options: options for this descriptor | |
427 | * @pages: the page(s) where we find the bbt, used with option BBT_ABSPAGE | |
428 | * when bbt is searched, then we store the found bbts pages here. | |
429 | * Its an array and supports up to 8 chips now | |
430 | * @offs: offset of the pattern in the oob area of the page | |
431 | * @veroffs: offset of the bbt version counter in the oob are of the page | |
432 | * @version: version read from the bbt page during scan | |
433 | * @len: length of the pattern, if 0 no pattern check is performed | |
434 | * @maxblocks: maximum number of blocks to search for a bbt. This number of | |
435 | * blocks is reserved at the end of the device where the tables are | |
436 | * written. | |
437 | * @reserved_block_code: if non-0, this pattern denotes a reserved (rather than | |
438 | * bad) block in the stored bbt | |
439 | * @pattern: pattern to identify bad block table or factory marked good / | |
440 | * bad blocks, can be NULL, if len = 0 | |
441 | * | |
442 | * Descriptor for the bad block table marker and the descriptor for the | |
443 | * pattern which identifies good and bad blocks. The assumption is made | |
444 | * that the pattern and the version count are always located in the oob area | |
445 | * of the first block. | |
446 | */ | |
447 | struct nand_bbt_descr { | |
448 | int options; | |
449 | int pages[NAND_MAX_CHIPS]; | |
450 | int offs; | |
451 | int veroffs; | |
452 | uint8_t version[NAND_MAX_CHIPS]; | |
453 | int len; | |
454 | int maxblocks; | |
455 | int reserved_block_code; | |
456 | uint8_t *pattern; | |
457 | }; | |
458 | ||
459 | /* Options for the bad block table descriptors */ | |
460 | ||
461 | /* The number of bits used per block in the bbt on the device */ | |
462 | #define NAND_BBT_NRBITS_MSK 0x0000000F | |
463 | #define NAND_BBT_1BIT 0x00000001 | |
464 | #define NAND_BBT_2BIT 0x00000002 | |
465 | #define NAND_BBT_4BIT 0x00000004 | |
466 | #define NAND_BBT_8BIT 0x00000008 | |
467 | /* The bad block table is in the last good block of the device */ | |
468 | #define NAND_BBT_LASTBLOCK 0x00000010 | |
469 | /* The bbt is at the given page, else we must scan for the bbt */ | |
470 | #define NAND_BBT_ABSPAGE 0x00000020 | |
471 | /* The bbt is at the given page, else we must scan for the bbt */ | |
472 | #define NAND_BBT_SEARCH 0x00000040 | |
473 | /* bbt is stored per chip on multichip devices */ | |
474 | #define NAND_BBT_PERCHIP 0x00000080 | |
475 | /* bbt has a version counter at offset veroffs */ | |
476 | #define NAND_BBT_VERSION 0x00000100 | |
477 | /* Create a bbt if none axists */ | |
478 | #define NAND_BBT_CREATE 0x00000200 | |
479 | /* Search good / bad pattern through all pages of a block */ | |
480 | #define NAND_BBT_SCANALLPAGES 0x00000400 | |
481 | /* Scan block empty during good / bad block scan */ | |
482 | #define NAND_BBT_SCANEMPTY 0x00000800 | |
483 | /* Write bbt if neccecary */ | |
484 | #define NAND_BBT_WRITE 0x00001000 | |
485 | /* Read and write back block contents when writing bbt */ | |
486 | #define NAND_BBT_SAVECONTENT 0x00002000 | |
487 | /* Search good / bad pattern on the first and the second page */ | |
488 | #define NAND_BBT_SCAN2NDPAGE 0x00004000 | |
489 | ||
490 | /* The maximum number of blocks to scan for a bbt */ | |
491 | #define NAND_BBT_SCAN_MAXBLOCKS 4 | |
492 | ||
493 | extern int nand_scan_bbt (struct mtd_info *mtd, struct nand_bbt_descr *bd); | |
494 | extern int nand_update_bbt (struct mtd_info *mtd, loff_t offs); | |
495 | extern int nand_default_bbt (struct mtd_info *mtd); | |
496 | extern int nand_isbad_bbt (struct mtd_info *mtd, loff_t offs, int allowbbt); | |
497 | extern int nand_erase_nand (struct mtd_info *mtd, struct erase_info *instr, int allowbbt); | |
068e3c0a DM |
498 | extern int nand_do_read_ecc (struct mtd_info *mtd, loff_t from, size_t len, |
499 | size_t * retlen, u_char * buf, u_char * oob_buf, | |
500 | struct nand_oobinfo *oobsel, int flags); | |
1da177e4 LT |
501 | |
502 | /* | |
503 | * Constants for oob configuration | |
504 | */ | |
505 | #define NAND_SMALL_BADBLOCK_POS 5 | |
506 | #define NAND_LARGE_BADBLOCK_POS 0 | |
507 | ||
508 | #endif /* __LINUX_MTD_NAND_H */ |