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mtd: add SST39SF040 chip to jedec_probe
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1da177e4
LT
1/*
2 * linux/include/linux/mtd/nand.h
3 *
44d1b980 4 * Copyright (c) 2000 David Woodhouse <dwmw2@infradead.org>
1da177e4
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5 * Steven J. Hill <sjhill@realitydiluted.com>
6 * Thomas Gleixner <tglx@linutronix.de>
7 *
1da177e4
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8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 *
2c0a2bed
TG
12 * Info:
13 * Contains standard defines and IDs for NAND flash devices
1da177e4 14 *
2c0a2bed
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15 * Changelog:
16 * See git changelog.
1da177e4
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17 */
18#ifndef __LINUX_MTD_NAND_H
19#define __LINUX_MTD_NAND_H
20
1da177e4
LT
21#include <linux/wait.h>
22#include <linux/spinlock.h>
23#include <linux/mtd/mtd.h>
24
25struct mtd_info;
26/* Scan and identify a NAND device */
27extern int nand_scan (struct mtd_info *mtd, int max_chips);
3b85c321
DW
28/* Separate phases of nand_scan(), allowing board driver to intervene
29 * and override command or ECC setup according to flash type */
30extern int nand_scan_ident(struct mtd_info *mtd, int max_chips);
31extern int nand_scan_tail(struct mtd_info *mtd);
32
1da177e4
LT
33/* Free resources held by the NAND device */
34extern void nand_release (struct mtd_info *mtd);
35
b77d95c7
DW
36/* Internal helper for board drivers which need to override command function */
37extern void nand_wait_ready(struct mtd_info *mtd);
38
1da177e4
LT
39/* The maximum number of NAND chips in an array */
40#define NAND_MAX_CHIPS 8
41
42/* This constant declares the max. oobsize / page, which
43 * is supported now. If you add a chip with bigger oobsize/page
44 * adjust this accordingly.
45 */
81ec5364
TG
46#define NAND_MAX_OOBSIZE 128
47#define NAND_MAX_PAGESIZE 4096
1da177e4
LT
48
49/*
50 * Constants for hardware specific CLE/ALE/NCE function
7abd3ef9
TG
51 *
52 * These are bits which can be or'ed to set/clear multiple
53 * bits in one go.
54 */
1da177e4 55/* Select the chip by setting nCE to low */
7abd3ef9 56#define NAND_NCE 0x01
1da177e4 57/* Select the command latch by setting CLE to high */
7abd3ef9 58#define NAND_CLE 0x02
1da177e4 59/* Select the address latch by setting ALE to high */
7abd3ef9
TG
60#define NAND_ALE 0x04
61
62#define NAND_CTRL_CLE (NAND_NCE | NAND_CLE)
63#define NAND_CTRL_ALE (NAND_NCE | NAND_ALE)
64#define NAND_CTRL_CHANGE 0x80
1da177e4
LT
65
66/*
67 * Standard NAND flash commands
68 */
69#define NAND_CMD_READ0 0
70#define NAND_CMD_READ1 1
7bc3312b 71#define NAND_CMD_RNDOUT 5
1da177e4
LT
72#define NAND_CMD_PAGEPROG 0x10
73#define NAND_CMD_READOOB 0x50
74#define NAND_CMD_ERASE1 0x60
75#define NAND_CMD_STATUS 0x70
76#define NAND_CMD_STATUS_MULTI 0x71
77#define NAND_CMD_SEQIN 0x80
7bc3312b 78#define NAND_CMD_RNDIN 0x85
1da177e4
LT
79#define NAND_CMD_READID 0x90
80#define NAND_CMD_ERASE2 0xd0
81#define NAND_CMD_RESET 0xff
82
83/* Extended commands for large page devices */
84#define NAND_CMD_READSTART 0x30
7bc3312b 85#define NAND_CMD_RNDOUTSTART 0xE0
1da177e4
LT
86#define NAND_CMD_CACHEDPROG 0x15
87
28a48de7 88/* Extended commands for AG-AND device */
61ecfa87
TG
89/*
90 * Note: the command for NAND_CMD_DEPLETE1 is really 0x00 but
28a48de7
DM
91 * there is no way to distinguish that from NAND_CMD_READ0
92 * until the remaining sequence of commands has been completed
93 * so add a high order bit and mask it off in the command.
94 */
95#define NAND_CMD_DEPLETE1 0x100
96#define NAND_CMD_DEPLETE2 0x38
97#define NAND_CMD_STATUS_MULTI 0x71
98#define NAND_CMD_STATUS_ERROR 0x72
99/* multi-bank error status (banks 0-3) */
100#define NAND_CMD_STATUS_ERROR0 0x73
101#define NAND_CMD_STATUS_ERROR1 0x74
102#define NAND_CMD_STATUS_ERROR2 0x75
103#define NAND_CMD_STATUS_ERROR3 0x76
104#define NAND_CMD_STATUS_RESET 0x7f
105#define NAND_CMD_STATUS_CLEAR 0xff
106
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TG
107#define NAND_CMD_NONE -1
108
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109/* Status bits */
110#define NAND_STATUS_FAIL 0x01
111#define NAND_STATUS_FAIL_N1 0x02
112#define NAND_STATUS_TRUE_READY 0x20
113#define NAND_STATUS_READY 0x40
114#define NAND_STATUS_WP 0x80
115
61ecfa87 116/*
1da177e4
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117 * Constants for ECC_MODES
118 */
6dfc6d25
TG
119typedef enum {
120 NAND_ECC_NONE,
121 NAND_ECC_SOFT,
122 NAND_ECC_HW,
123 NAND_ECC_HW_SYNDROME,
124} nand_ecc_modes_t;
1da177e4
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125
126/*
127 * Constants for Hardware ECC
068e3c0a 128 */
1da177e4
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129/* Reset Hardware ECC for read */
130#define NAND_ECC_READ 0
131/* Reset Hardware ECC for write */
132#define NAND_ECC_WRITE 1
133/* Enable Hardware ECC before syndrom is read back from flash */
134#define NAND_ECC_READSYN 2
135
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DM
136/* Bit mask for flags passed to do_nand_read_ecc */
137#define NAND_GET_DEVICE 0x80
138
139
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140/* Option constants for bizarre disfunctionality and real
141* features
142*/
143/* Chip can not auto increment pages */
144#define NAND_NO_AUTOINCR 0x00000001
145/* Buswitdh is 16 bit */
146#define NAND_BUSWIDTH_16 0x00000002
147/* Device supports partial programming without padding */
148#define NAND_NO_PADDING 0x00000004
149/* Chip has cache program function */
150#define NAND_CACHEPRG 0x00000008
151/* Chip has copy back function */
152#define NAND_COPYBACK 0x00000010
61ecfa87 153/* AND Chip which has 4 banks and a confusing page / block
1da177e4
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154 * assignment. See Renesas datasheet for further information */
155#define NAND_IS_AND 0x00000020
156/* Chip has a array of 4 pages which can be read without
157 * additional ready /busy waits */
61ecfa87 158#define NAND_4PAGE_ARRAY 0x00000040
28a48de7
DM
159/* Chip requires that BBT is periodically rewritten to prevent
160 * bits from adjacent blocks from 'leaking' in altering data.
161 * This happens with the Renesas AG-AND chips, possibly others. */
162#define BBT_AUTO_REFRESH 0x00000080
7a30601b
TG
163/* Chip does not require ready check on read. True
164 * for all large page devices, as they do not support
165 * autoincrement.*/
166#define NAND_NO_READRDY 0x00000100
29072b96
TG
167/* Chip does not allow subpage writes */
168#define NAND_NO_SUBPAGE_WRITE 0x00000200
169
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LT
170
171/* Options valid for Samsung large page devices */
172#define NAND_SAMSUNG_LP_OPTIONS \
173 (NAND_NO_PADDING | NAND_CACHEPRG | NAND_COPYBACK)
174
175/* Macros to identify the above */
176#define NAND_CANAUTOINCR(chip) (!(chip->options & NAND_NO_AUTOINCR))
177#define NAND_MUST_PAD(chip) (!(chip->options & NAND_NO_PADDING))
178#define NAND_HAS_CACHEPROG(chip) ((chip->options & NAND_CACHEPRG))
179#define NAND_HAS_COPYBACK(chip) ((chip->options & NAND_COPYBACK))
96d8b647
AK
180/* Large page NAND with SOFT_ECC should support subpage reads */
181#define NAND_SUBPAGE_READ(chip) ((chip->ecc.mode == NAND_ECC_SOFT) \
182 && (chip->page_shift > 9))
1da177e4
LT
183
184/* Mask to zero out the chip options, which come from the id table */
185#define NAND_CHIPOPTIONS_MSK (0x0000ffff & ~NAND_NO_AUTOINCR)
186
187/* Non chip related options */
188/* Use a flash based bad block table. This option is passed to the
189 * default bad block table function. */
190#define NAND_USE_FLASH_BBT 0x00010000
0040bf38 191/* This option skips the bbt scan during initialization. */
f75e5097 192#define NAND_SKIP_BBTSCAN 0x00020000
4bf63fcb
DW
193/* This option is defined if the board driver allocates its own buffers
194 (e.g. because it needs them DMA-coherent */
195#define NAND_OWN_BUFFERS 0x00040000
1da177e4 196/* Options set by nand scan */
a36ed299 197/* Nand scan has allocated controller struct */
f75e5097 198#define NAND_CONTROLLER_ALLOC 0x80000000
1da177e4 199
29072b96
TG
200/* Cell info constants */
201#define NAND_CI_CHIPNR_MSK 0x03
202#define NAND_CI_CELLTYPE_MSK 0x0C
1da177e4
LT
203
204/*
205 * nand_state_t - chip states
206 * Enumeration for NAND flash chip state
207 */
208typedef enum {
209 FL_READY,
210 FL_READING,
211 FL_WRITING,
212 FL_ERASING,
213 FL_SYNCING,
214 FL_CACHEDPRG,
962034f4 215 FL_PM_SUSPENDED,
1da177e4
LT
216} nand_state_t;
217
218/* Keep gcc happy */
219struct nand_chip;
220
221/**
844d3b42 222 * struct nand_hw_control - Control structure for hardware controller (e.g ECC generator) shared among independent devices
61ecfa87 223 * @lock: protection lock
1da177e4 224 * @active: the mtd device which holds the controller currently
0dfc6246
TG
225 * @wq: wait queue to sleep on if a NAND operation is in progress
226 * used instead of the per chip wait queue when a hw controller is available
1da177e4
LT
227 */
228struct nand_hw_control {
229 spinlock_t lock;
230 struct nand_chip *active;
0dfc6246 231 wait_queue_head_t wq;
1da177e4
LT
232};
233
6dfc6d25
TG
234/**
235 * struct nand_ecc_ctrl - Control structure for ecc
236 * @mode: ecc mode
237 * @steps: number of ecc steps per page
238 * @size: data bytes per ecc step
239 * @bytes: ecc bytes per step
9577f44a
TG
240 * @total: total number of ecc bytes per page
241 * @prepad: padding information for syndrome based ecc generators
242 * @postpad: padding information for syndrome based ecc generators
844d3b42 243 * @layout: ECC layout control struct pointer
6dfc6d25
TG
244 * @hwctl: function to control hardware ecc generator. Must only
245 * be provided if an hardware ECC is available
246 * @calculate: function for ecc calculation or readback from ecc hardware
247 * @correct: function for ecc correction, matching to ecc generator (sw/hw)
956e944c
DW
248 * @read_page_raw: function to read a raw page without ECC
249 * @write_page_raw: function to write a raw page without ECC
f75e5097 250 * @read_page: function to read a page according to the ecc generator requirements
17c1d2be 251 * @read_subpage: function to read parts of the page covered by ECC.
9577f44a 252 * @write_page: function to write a page according to the ecc generator requirements
844d3b42
RD
253 * @read_oob: function to read chip OOB data
254 * @write_oob: function to write chip OOB data
6dfc6d25
TG
255 */
256struct nand_ecc_ctrl {
257 nand_ecc_modes_t mode;
258 int steps;
259 int size;
260 int bytes;
9577f44a
TG
261 int total;
262 int prepad;
263 int postpad;
5bd34c09 264 struct nand_ecclayout *layout;
9a57d470 265 void (*hwctl)(struct mtd_info *mtd, int mode);
6dfc6d25
TG
266 int (*calculate)(struct mtd_info *mtd,
267 const uint8_t *dat,
268 uint8_t *ecc_code);
269 int (*correct)(struct mtd_info *mtd, uint8_t *dat,
270 uint8_t *read_ecc,
271 uint8_t *calc_ecc);
956e944c
DW
272 int (*read_page_raw)(struct mtd_info *mtd,
273 struct nand_chip *chip,
274 uint8_t *buf);
275 void (*write_page_raw)(struct mtd_info *mtd,
276 struct nand_chip *chip,
277 const uint8_t *buf);
9577f44a
TG
278 int (*read_page)(struct mtd_info *mtd,
279 struct nand_chip *chip,
280 uint8_t *buf);
3d459559
AK
281 int (*read_subpage)(struct mtd_info *mtd,
282 struct nand_chip *chip,
283 uint32_t offs, uint32_t len,
284 uint8_t *buf);
f75e5097 285 void (*write_page)(struct mtd_info *mtd,
9577f44a 286 struct nand_chip *chip,
f75e5097 287 const uint8_t *buf);
7bc3312b
TG
288 int (*read_oob)(struct mtd_info *mtd,
289 struct nand_chip *chip,
290 int page,
291 int sndcmd);
292 int (*write_oob)(struct mtd_info *mtd,
293 struct nand_chip *chip,
294 int page);
f75e5097
TG
295};
296
297/**
298 * struct nand_buffers - buffer structure for read/write
299 * @ecccalc: buffer for calculated ecc
300 * @ecccode: buffer for ecc read from flash
f75e5097 301 * @databuf: buffer for data - dynamically sized
f75e5097
TG
302 *
303 * Do not change the order of buffers. databuf and oobrbuf must be in
304 * consecutive order.
305 */
306struct nand_buffers {
307 uint8_t ecccalc[NAND_MAX_OOBSIZE];
308 uint8_t ecccode[NAND_MAX_OOBSIZE];
7dcdcbef 309 uint8_t databuf[NAND_MAX_PAGESIZE + NAND_MAX_OOBSIZE];
6dfc6d25
TG
310};
311
1da177e4
LT
312/**
313 * struct nand_chip - NAND Private Flash Chip Data
61ecfa87
TG
314 * @IO_ADDR_R: [BOARDSPECIFIC] address to read the 8 I/O lines of the flash device
315 * @IO_ADDR_W: [BOARDSPECIFIC] address to write the 8 I/O lines of the flash device
1da177e4 316 * @read_byte: [REPLACEABLE] read one byte from the chip
1da177e4 317 * @read_word: [REPLACEABLE] read one word from the chip
1da177e4
LT
318 * @write_buf: [REPLACEABLE] write data from the buffer to the chip
319 * @read_buf: [REPLACEABLE] read data from the chip into the buffer
320 * @verify_buf: [REPLACEABLE] verify buffer contents against the chip data
321 * @select_chip: [REPLACEABLE] select chip nr
322 * @block_bad: [REPLACEABLE] check, if the block is bad
323 * @block_markbad: [REPLACEABLE] mark the block bad
7abd3ef9
TG
324 * @cmd_ctrl: [BOARDSPECIFIC] hardwarespecific funtion for controlling
325 * ALE/CLE/nCE. Also used to write command and address
1da177e4
LT
326 * @dev_ready: [BOARDSPECIFIC] hardwarespecific function for accesing device ready/busy line
327 * If set to NULL no access to ready/busy is available and the ready/busy information
328 * is read from the chip status register
329 * @cmdfunc: [REPLACEABLE] hardwarespecific function for writing commands to the chip
330 * @waitfunc: [REPLACEABLE] hardwarespecific function for wait on ready
6dfc6d25 331 * @ecc: [BOARDSPECIFIC] ecc control ctructure
844d3b42
RD
332 * @buffers: buffer structure for read/write
333 * @hwcontrol: platform-specific hardware control structure
334 * @ops: oob operation operands
1da177e4
LT
335 * @erase_cmd: [INTERN] erase command write function, selectable due to AND support
336 * @scan_bbt: [REPLACEABLE] function to scan bad block table
1da177e4 337 * @chip_delay: [BOARDSPECIFIC] chip dependent delay for transfering data from array to read regs (tR)
2c0a2bed 338 * @state: [INTERN] the current state of the NAND device
844d3b42 339 * @oob_poi: poison value buffer
1da177e4
LT
340 * @page_shift: [INTERN] number of address bits in a page (column address bits)
341 * @phys_erase_shift: [INTERN] number of address bits in a physical eraseblock
342 * @bbt_erase_shift: [INTERN] number of address bits in a bbt entry
343 * @chip_shift: [INTERN] number of address bits in one chip
1da177e4
LT
344 * @options: [BOARDSPECIFIC] various chip options. They can partly be set to inform nand_scan about
345 * special functionality. See the defines for further explanation
346 * @badblockpos: [INTERN] position of the bad block marker in the oob area
552a8278 347 * @cellinfo: [INTERN] MLC/multichip data from chip ident
1da177e4
LT
348 * @numchips: [INTERN] number of physical chips
349 * @chipsize: [INTERN] the size of one chip for multichip arrays
350 * @pagemask: [INTERN] page number mask = number of (pages / chip) - 1
351 * @pagebuf: [INTERN] holds the pagenumber which is currently in data_buf
29072b96 352 * @subpagesize: [INTERN] holds the subpagesize
5bd34c09 353 * @ecclayout: [REPLACEABLE] the default ecc placement scheme
1da177e4
LT
354 * @bbt: [INTERN] bad block table pointer
355 * @bbt_td: [REPLACEABLE] bad block table descriptor for flash lookup
356 * @bbt_md: [REPLACEABLE] bad block table mirror descriptor
61ecfa87 357 * @badblock_pattern: [REPLACEABLE] bad block scan pattern used for initial bad block scan
a36ed299
TG
358 * @controller: [REPLACEABLE] a pointer to a hardware controller structure
359 * which is shared among multiple independend devices
1da177e4 360 * @priv: [OPTIONAL] pointer to private chip date
61ecfa87 361 * @errstat: [OPTIONAL] hardware specific function to perform additional error status checks
068e3c0a 362 * (determine if errors are correctable)
351edd24 363 * @write_page: [REPLACEABLE] High-level page write function
1da177e4 364 */
61ecfa87 365
1da177e4
LT
366struct nand_chip {
367 void __iomem *IO_ADDR_R;
2c0a2bed 368 void __iomem *IO_ADDR_W;
61ecfa87 369
58dd8f2b 370 uint8_t (*read_byte)(struct mtd_info *mtd);
1da177e4 371 u16 (*read_word)(struct mtd_info *mtd);
58dd8f2b
TG
372 void (*write_buf)(struct mtd_info *mtd, const uint8_t *buf, int len);
373 void (*read_buf)(struct mtd_info *mtd, uint8_t *buf, int len);
374 int (*verify_buf)(struct mtd_info *mtd, const uint8_t *buf, int len);
1da177e4
LT
375 void (*select_chip)(struct mtd_info *mtd, int chip);
376 int (*block_bad)(struct mtd_info *mtd, loff_t ofs, int getchip);
377 int (*block_markbad)(struct mtd_info *mtd, loff_t ofs);
7abd3ef9
TG
378 void (*cmd_ctrl)(struct mtd_info *mtd, int dat,
379 unsigned int ctrl);
2c0a2bed
TG
380 int (*dev_ready)(struct mtd_info *mtd);
381 void (*cmdfunc)(struct mtd_info *mtd, unsigned command, int column, int page_addr);
7bc3312b 382 int (*waitfunc)(struct mtd_info *mtd, struct nand_chip *this);
1da177e4
LT
383 void (*erase_cmd)(struct mtd_info *mtd, int page);
384 int (*scan_bbt)(struct mtd_info *mtd);
f75e5097 385 int (*errstat)(struct mtd_info *mtd, struct nand_chip *this, int state, int status, int page);
956e944c
DW
386 int (*write_page)(struct mtd_info *mtd, struct nand_chip *chip,
387 const uint8_t *buf, int page, int cached, int raw);
f75e5097 388
2c0a2bed 389 int chip_delay;
f75e5097
TG
390 unsigned int options;
391
2c0a2bed 392 int page_shift;
1da177e4
LT
393 int phys_erase_shift;
394 int bbt_erase_shift;
395 int chip_shift;
1da177e4 396 int numchips;
69423d99 397 uint64_t chipsize;
1da177e4
LT
398 int pagemask;
399 int pagebuf;
29072b96
TG
400 int subpagesize;
401 uint8_t cellinfo;
f75e5097
TG
402 int badblockpos;
403
404 nand_state_t state;
405
406 uint8_t *oob_poi;
407 struct nand_hw_control *controller;
5bd34c09 408 struct nand_ecclayout *ecclayout;
f75e5097
TG
409
410 struct nand_ecc_ctrl ecc;
4bf63fcb 411 struct nand_buffers *buffers;
f75e5097
TG
412 struct nand_hw_control hwcontrol;
413
8593fbc6
TG
414 struct mtd_oob_ops ops;
415
1da177e4
LT
416 uint8_t *bbt;
417 struct nand_bbt_descr *bbt_td;
418 struct nand_bbt_descr *bbt_md;
f75e5097 419
1da177e4 420 struct nand_bbt_descr *badblock_pattern;
f75e5097 421
1da177e4
LT
422 void *priv;
423};
424
425/*
426 * NAND Flash Manufacturer ID Codes
427 */
428#define NAND_MFR_TOSHIBA 0x98
429#define NAND_MFR_SAMSUNG 0xec
430#define NAND_MFR_FUJITSU 0x04
431#define NAND_MFR_NATIONAL 0x8f
432#define NAND_MFR_RENESAS 0x07
433#define NAND_MFR_STMICRO 0x20
2c0a2bed 434#define NAND_MFR_HYNIX 0xad
8c60e547 435#define NAND_MFR_MICRON 0x2c
30eb0db0 436#define NAND_MFR_AMD 0x01
1da177e4
LT
437
438/**
439 * struct nand_flash_dev - NAND Flash Device ID Structure
2c0a2bed
TG
440 * @name: Identify the device type
441 * @id: device ID code
442 * @pagesize: Pagesize in bytes. Either 256 or 512 or 0
61ecfa87 443 * If the pagesize is 0, then the real pagesize
1da177e4
LT
444 * and the eraseize are determined from the
445 * extended id bytes in the chip
2c0a2bed
TG
446 * @erasesize: Size of an erase block in the flash device.
447 * @chipsize: Total chipsize in Mega Bytes
1da177e4
LT
448 * @options: Bitfield to store chip relevant options
449 */
450struct nand_flash_dev {
451 char *name;
452 int id;
453 unsigned long pagesize;
454 unsigned long chipsize;
455 unsigned long erasesize;
456 unsigned long options;
457};
458
459/**
460 * struct nand_manufacturers - NAND Flash Manufacturer ID Structure
461 * @name: Manufacturer name
2c0a2bed 462 * @id: manufacturer ID code of device.
1da177e4
LT
463*/
464struct nand_manufacturers {
465 int id;
466 char * name;
467};
468
469extern struct nand_flash_dev nand_flash_ids[];
470extern struct nand_manufacturers nand_manuf_ids[];
471
61ecfa87 472/**
1da177e4
LT
473 * struct nand_bbt_descr - bad block table descriptor
474 * @options: options for this descriptor
475 * @pages: the page(s) where we find the bbt, used with option BBT_ABSPAGE
476 * when bbt is searched, then we store the found bbts pages here.
477 * Its an array and supports up to 8 chips now
478 * @offs: offset of the pattern in the oob area of the page
479 * @veroffs: offset of the bbt version counter in the oob are of the page
480 * @version: version read from the bbt page during scan
481 * @len: length of the pattern, if 0 no pattern check is performed
482 * @maxblocks: maximum number of blocks to search for a bbt. This number of
61ecfa87 483 * blocks is reserved at the end of the device where the tables are
1da177e4
LT
484 * written.
485 * @reserved_block_code: if non-0, this pattern denotes a reserved (rather than
486 * bad) block in the stored bbt
61ecfa87 487 * @pattern: pattern to identify bad block table or factory marked good /
1da177e4
LT
488 * bad blocks, can be NULL, if len = 0
489 *
61ecfa87 490 * Descriptor for the bad block table marker and the descriptor for the
1da177e4
LT
491 * pattern which identifies good and bad blocks. The assumption is made
492 * that the pattern and the version count are always located in the oob area
493 * of the first block.
494 */
495struct nand_bbt_descr {
496 int options;
497 int pages[NAND_MAX_CHIPS];
498 int offs;
499 int veroffs;
500 uint8_t version[NAND_MAX_CHIPS];
501 int len;
2c0a2bed 502 int maxblocks;
1da177e4
LT
503 int reserved_block_code;
504 uint8_t *pattern;
505};
506
507/* Options for the bad block table descriptors */
508
509/* The number of bits used per block in the bbt on the device */
510#define NAND_BBT_NRBITS_MSK 0x0000000F
511#define NAND_BBT_1BIT 0x00000001
512#define NAND_BBT_2BIT 0x00000002
513#define NAND_BBT_4BIT 0x00000004
514#define NAND_BBT_8BIT 0x00000008
515/* The bad block table is in the last good block of the device */
516#define NAND_BBT_LASTBLOCK 0x00000010
517/* The bbt is at the given page, else we must scan for the bbt */
518#define NAND_BBT_ABSPAGE 0x00000020
519/* The bbt is at the given page, else we must scan for the bbt */
520#define NAND_BBT_SEARCH 0x00000040
521/* bbt is stored per chip on multichip devices */
522#define NAND_BBT_PERCHIP 0x00000080
523/* bbt has a version counter at offset veroffs */
524#define NAND_BBT_VERSION 0x00000100
525/* Create a bbt if none axists */
526#define NAND_BBT_CREATE 0x00000200
527/* Search good / bad pattern through all pages of a block */
528#define NAND_BBT_SCANALLPAGES 0x00000400
529/* Scan block empty during good / bad block scan */
530#define NAND_BBT_SCANEMPTY 0x00000800
531/* Write bbt if neccecary */
532#define NAND_BBT_WRITE 0x00001000
533/* Read and write back block contents when writing bbt */
534#define NAND_BBT_SAVECONTENT 0x00002000
535/* Search good / bad pattern on the first and the second page */
536#define NAND_BBT_SCAN2NDPAGE 0x00004000
537
538/* The maximum number of blocks to scan for a bbt */
539#define NAND_BBT_SCAN_MAXBLOCKS 4
540
f5bbdacc
TG
541extern int nand_scan_bbt(struct mtd_info *mtd, struct nand_bbt_descr *bd);
542extern int nand_update_bbt(struct mtd_info *mtd, loff_t offs);
543extern int nand_default_bbt(struct mtd_info *mtd);
544extern int nand_isbad_bbt(struct mtd_info *mtd, loff_t offs, int allowbbt);
545extern int nand_erase_nand(struct mtd_info *mtd, struct erase_info *instr,
546 int allowbbt);
547extern int nand_do_read(struct mtd_info *mtd, loff_t from, size_t len,
548 size_t * retlen, uint8_t * buf);
1da177e4
LT
549
550/*
551* Constants for oob configuration
552*/
553#define NAND_SMALL_BADBLOCK_POS 5
554#define NAND_LARGE_BADBLOCK_POS 0
555
41796c2e
TG
556/**
557 * struct platform_nand_chip - chip level device structure
41796c2e 558 * @nr_chips: max. number of chips to scan for
844d3b42 559 * @chip_offset: chip number offset
8be834f7 560 * @nr_partitions: number of partitions pointed to by partitions (or zero)
41796c2e
TG
561 * @partitions: mtd partition list
562 * @chip_delay: R/B delay value in us
563 * @options: Option flags, e.g. 16bit buswidth
5bd34c09 564 * @ecclayout: ecc layout info structure
972edcb7 565 * @part_probe_types: NULL-terminated array of probe types
41796c2e
TG
566 * @priv: hardware controller specific settings
567 */
568struct platform_nand_chip {
569 int nr_chips;
570 int chip_offset;
571 int nr_partitions;
572 struct mtd_partition *partitions;
5bd34c09 573 struct nand_ecclayout *ecclayout;
2c0a2bed 574 int chip_delay;
41796c2e 575 unsigned int options;
972edcb7 576 const char **part_probe_types;
41796c2e
TG
577 void *priv;
578};
579
580/**
581 * struct platform_nand_ctrl - controller level device structure
41796c2e
TG
582 * @hwcontrol: platform specific hardware control structure
583 * @dev_ready: platform specific function to read ready/busy pin
584 * @select_chip: platform specific chip select function
972edcb7
VW
585 * @cmd_ctrl: platform specific function for controlling
586 * ALE/CLE/nCE. Also used to write command and address
844d3b42 587 * @priv: private data to transport driver specific settings
41796c2e
TG
588 *
589 * All fields are optional and depend on the hardware driver requirements
590 */
591struct platform_nand_ctrl {
2c0a2bed
TG
592 void (*hwcontrol)(struct mtd_info *mtd, int cmd);
593 int (*dev_ready)(struct mtd_info *mtd);
41796c2e 594 void (*select_chip)(struct mtd_info *mtd, int chip);
972edcb7
VW
595 void (*cmd_ctrl)(struct mtd_info *mtd, int dat,
596 unsigned int ctrl);
41796c2e
TG
597 void *priv;
598};
599
972edcb7
VW
600/**
601 * struct platform_nand_data - container structure for platform-specific data
602 * @chip: chip level chip structure
603 * @ctrl: controller level device structure
604 */
605struct platform_nand_data {
606 struct platform_nand_chip chip;
607 struct platform_nand_ctrl ctrl;
608};
609
41796c2e
TG
610/* Some helpers to access the data structures */
611static inline
612struct platform_nand_chip *get_platform_nandchip(struct mtd_info *mtd)
613{
614 struct nand_chip *chip = mtd->priv;
615
616 return chip->priv;
617}
618
1da177e4 619#endif /* __LINUX_MTD_NAND_H */