]>
Commit | Line | Data |
---|---|---|
1da177e4 LT |
1 | /* |
2 | * linux/include/linux/mtd/nand.h | |
3 | * | |
a1452a37 DW |
4 | * Copyright © 2000-2010 David Woodhouse <dwmw2@infradead.org> |
5 | * Steven J. Hill <sjhill@realitydiluted.com> | |
6 | * Thomas Gleixner <tglx@linutronix.de> | |
1da177e4 | 7 | * |
1da177e4 LT |
8 | * This program is free software; you can redistribute it and/or modify |
9 | * it under the terms of the GNU General Public License version 2 as | |
10 | * published by the Free Software Foundation. | |
11 | * | |
2c0a2bed TG |
12 | * Info: |
13 | * Contains standard defines and IDs for NAND flash devices | |
1da177e4 | 14 | * |
2c0a2bed TG |
15 | * Changelog: |
16 | * See git changelog. | |
1da177e4 LT |
17 | */ |
18 | #ifndef __LINUX_MTD_NAND_H | |
19 | #define __LINUX_MTD_NAND_H | |
20 | ||
1da177e4 LT |
21 | #include <linux/wait.h> |
22 | #include <linux/spinlock.h> | |
23 | #include <linux/mtd/mtd.h> | |
30631cb8 | 24 | #include <linux/mtd/flashchip.h> |
c62d81bc | 25 | #include <linux/mtd/bbm.h> |
1da177e4 LT |
26 | |
27 | struct mtd_info; | |
5e81e88a | 28 | struct nand_flash_dev; |
5844feea BN |
29 | struct device_node; |
30 | ||
1da177e4 | 31 | /* Scan and identify a NAND device */ |
79022591 | 32 | int nand_scan(struct mtd_info *mtd, int max_chips); |
a0491fc4 SAS |
33 | /* |
34 | * Separate phases of nand_scan(), allowing board driver to intervene | |
35 | * and override command or ECC setup according to flash type. | |
36 | */ | |
79022591 | 37 | int nand_scan_ident(struct mtd_info *mtd, int max_chips, |
5e81e88a | 38 | struct nand_flash_dev *table); |
79022591 | 39 | int nand_scan_tail(struct mtd_info *mtd); |
3b85c321 | 40 | |
1da177e4 | 41 | /* Free resources held by the NAND device */ |
79022591 | 42 | void nand_release(struct mtd_info *mtd); |
1da177e4 | 43 | |
b77d95c7 | 44 | /* Internal helper for board drivers which need to override command function */ |
79022591 | 45 | void nand_wait_ready(struct mtd_info *mtd); |
b77d95c7 | 46 | |
7854d3f7 | 47 | /* locks all blocks present in the device */ |
79022591 | 48 | int nand_lock(struct mtd_info *mtd, loff_t ofs, uint64_t len); |
7d70f334 | 49 | |
7854d3f7 | 50 | /* unlocks specified locked blocks */ |
79022591 | 51 | int nand_unlock(struct mtd_info *mtd, loff_t ofs, uint64_t len); |
7d70f334 | 52 | |
1da177e4 LT |
53 | /* The maximum number of NAND chips in an array */ |
54 | #define NAND_MAX_CHIPS 8 | |
55 | ||
1da177e4 LT |
56 | /* |
57 | * Constants for hardware specific CLE/ALE/NCE function | |
7abd3ef9 TG |
58 | * |
59 | * These are bits which can be or'ed to set/clear multiple | |
60 | * bits in one go. | |
61 | */ | |
1da177e4 | 62 | /* Select the chip by setting nCE to low */ |
7abd3ef9 | 63 | #define NAND_NCE 0x01 |
1da177e4 | 64 | /* Select the command latch by setting CLE to high */ |
7abd3ef9 | 65 | #define NAND_CLE 0x02 |
1da177e4 | 66 | /* Select the address latch by setting ALE to high */ |
7abd3ef9 TG |
67 | #define NAND_ALE 0x04 |
68 | ||
69 | #define NAND_CTRL_CLE (NAND_NCE | NAND_CLE) | |
70 | #define NAND_CTRL_ALE (NAND_NCE | NAND_ALE) | |
71 | #define NAND_CTRL_CHANGE 0x80 | |
1da177e4 LT |
72 | |
73 | /* | |
74 | * Standard NAND flash commands | |
75 | */ | |
76 | #define NAND_CMD_READ0 0 | |
77 | #define NAND_CMD_READ1 1 | |
7bc3312b | 78 | #define NAND_CMD_RNDOUT 5 |
1da177e4 LT |
79 | #define NAND_CMD_PAGEPROG 0x10 |
80 | #define NAND_CMD_READOOB 0x50 | |
81 | #define NAND_CMD_ERASE1 0x60 | |
82 | #define NAND_CMD_STATUS 0x70 | |
1da177e4 | 83 | #define NAND_CMD_SEQIN 0x80 |
7bc3312b | 84 | #define NAND_CMD_RNDIN 0x85 |
1da177e4 LT |
85 | #define NAND_CMD_READID 0x90 |
86 | #define NAND_CMD_ERASE2 0xd0 | |
caa4b6f2 | 87 | #define NAND_CMD_PARAM 0xec |
7db03ecc HS |
88 | #define NAND_CMD_GET_FEATURES 0xee |
89 | #define NAND_CMD_SET_FEATURES 0xef | |
1da177e4 LT |
90 | #define NAND_CMD_RESET 0xff |
91 | ||
7d70f334 VS |
92 | #define NAND_CMD_LOCK 0x2a |
93 | #define NAND_CMD_UNLOCK1 0x23 | |
94 | #define NAND_CMD_UNLOCK2 0x24 | |
95 | ||
1da177e4 LT |
96 | /* Extended commands for large page devices */ |
97 | #define NAND_CMD_READSTART 0x30 | |
7bc3312b | 98 | #define NAND_CMD_RNDOUTSTART 0xE0 |
1da177e4 LT |
99 | #define NAND_CMD_CACHEDPROG 0x15 |
100 | ||
7abd3ef9 TG |
101 | #define NAND_CMD_NONE -1 |
102 | ||
1da177e4 LT |
103 | /* Status bits */ |
104 | #define NAND_STATUS_FAIL 0x01 | |
105 | #define NAND_STATUS_FAIL_N1 0x02 | |
106 | #define NAND_STATUS_TRUE_READY 0x20 | |
107 | #define NAND_STATUS_READY 0x40 | |
108 | #define NAND_STATUS_WP 0x80 | |
109 | ||
61ecfa87 | 110 | /* |
1da177e4 LT |
111 | * Constants for ECC_MODES |
112 | */ | |
6dfc6d25 TG |
113 | typedef enum { |
114 | NAND_ECC_NONE, | |
115 | NAND_ECC_SOFT, | |
116 | NAND_ECC_HW, | |
117 | NAND_ECC_HW_SYNDROME, | |
6e0cb135 | 118 | NAND_ECC_HW_OOB_FIRST, |
6dfc6d25 | 119 | } nand_ecc_modes_t; |
1da177e4 | 120 | |
b0fcd8ab RM |
121 | enum nand_ecc_algo { |
122 | NAND_ECC_UNKNOWN, | |
123 | NAND_ECC_HAMMING, | |
124 | NAND_ECC_BCH, | |
125 | }; | |
126 | ||
1da177e4 LT |
127 | /* |
128 | * Constants for Hardware ECC | |
068e3c0a | 129 | */ |
1da177e4 LT |
130 | /* Reset Hardware ECC for read */ |
131 | #define NAND_ECC_READ 0 | |
132 | /* Reset Hardware ECC for write */ | |
133 | #define NAND_ECC_WRITE 1 | |
7854d3f7 | 134 | /* Enable Hardware ECC before syndrome is read back from flash */ |
1da177e4 LT |
135 | #define NAND_ECC_READSYN 2 |
136 | ||
40cbe6ee BB |
137 | /* |
138 | * Enable generic NAND 'page erased' check. This check is only done when | |
139 | * ecc.correct() returns -EBADMSG. | |
140 | * Set this flag if your implementation does not fix bitflips in erased | |
141 | * pages and you want to rely on the default implementation. | |
142 | */ | |
143 | #define NAND_ECC_GENERIC_ERASED_CHECK BIT(0) | |
144 | ||
068e3c0a DM |
145 | /* Bit mask for flags passed to do_nand_read_ecc */ |
146 | #define NAND_GET_DEVICE 0x80 | |
147 | ||
148 | ||
a0491fc4 SAS |
149 | /* |
150 | * Option constants for bizarre disfunctionality and real | |
151 | * features. | |
152 | */ | |
7854d3f7 | 153 | /* Buswidth is 16 bit */ |
1da177e4 | 154 | #define NAND_BUSWIDTH_16 0x00000002 |
1da177e4 LT |
155 | /* Chip has cache program function */ |
156 | #define NAND_CACHEPRG 0x00000008 | |
5bc7c33c BN |
157 | /* |
158 | * Chip requires ready check on read (for auto-incremented sequential read). | |
159 | * True only for small page devices; large page devices do not support | |
160 | * autoincrement. | |
161 | */ | |
162 | #define NAND_NEED_READRDY 0x00000100 | |
163 | ||
29072b96 TG |
164 | /* Chip does not allow subpage writes */ |
165 | #define NAND_NO_SUBPAGE_WRITE 0x00000200 | |
166 | ||
93edbad6 ML |
167 | /* Device is one of 'new' xD cards that expose fake nand command set */ |
168 | #define NAND_BROKEN_XD 0x00000400 | |
169 | ||
170 | /* Device behaves just like nand, but is readonly */ | |
171 | #define NAND_ROM 0x00000800 | |
172 | ||
a5ff4f10 JW |
173 | /* Device supports subpage reads */ |
174 | #define NAND_SUBPAGE_READ 0x00001000 | |
175 | ||
c03d9969 BB |
176 | /* |
177 | * Some MLC NANDs need data scrambling to limit bitflips caused by repeated | |
178 | * patterns. | |
179 | */ | |
180 | #define NAND_NEED_SCRAMBLING 0x00002000 | |
181 | ||
1da177e4 | 182 | /* Options valid for Samsung large page devices */ |
3239a6cd | 183 | #define NAND_SAMSUNG_LP_OPTIONS NAND_CACHEPRG |
1da177e4 LT |
184 | |
185 | /* Macros to identify the above */ | |
1da177e4 | 186 | #define NAND_HAS_CACHEPROG(chip) ((chip->options & NAND_CACHEPRG)) |
a5ff4f10 | 187 | #define NAND_HAS_SUBPAGE_READ(chip) ((chip->options & NAND_SUBPAGE_READ)) |
1da177e4 | 188 | |
1da177e4 | 189 | /* Non chip related options */ |
0040bf38 | 190 | /* This option skips the bbt scan during initialization. */ |
b4dc53e1 | 191 | #define NAND_SKIP_BBTSCAN 0x00010000 |
a0491fc4 SAS |
192 | /* |
193 | * This option is defined if the board driver allocates its own buffers | |
194 | * (e.g. because it needs them DMA-coherent). | |
195 | */ | |
b4dc53e1 | 196 | #define NAND_OWN_BUFFERS 0x00020000 |
b1c6e6db | 197 | /* Chip may not exist, so silence any errors in scan */ |
b4dc53e1 | 198 | #define NAND_SCAN_SILENT_NODEV 0x00040000 |
64b37b2a MC |
199 | /* |
200 | * Autodetect nand buswidth with readid/onfi. | |
201 | * This suppose the driver will configure the hardware in 8 bits mode | |
202 | * when calling nand_scan_ident, and update its configuration | |
203 | * before calling nand_scan_tail. | |
204 | */ | |
205 | #define NAND_BUSWIDTH_AUTO 0x00080000 | |
5f867db6 SW |
206 | /* |
207 | * This option could be defined by controller drivers to protect against | |
208 | * kmap'ed, vmalloc'ed highmem buffers being passed from upper layers | |
209 | */ | |
210 | #define NAND_USE_BOUNCE_BUFFER 0x00100000 | |
b1c6e6db | 211 | |
1da177e4 | 212 | /* Options set by nand scan */ |
a36ed299 | 213 | /* Nand scan has allocated controller struct */ |
f75e5097 | 214 | #define NAND_CONTROLLER_ALLOC 0x80000000 |
1da177e4 | 215 | |
29072b96 TG |
216 | /* Cell info constants */ |
217 | #define NAND_CI_CHIPNR_MSK 0x03 | |
218 | #define NAND_CI_CELLTYPE_MSK 0x0C | |
7db906b7 | 219 | #define NAND_CI_CELLTYPE_SHIFT 2 |
1da177e4 | 220 | |
1da177e4 LT |
221 | /* Keep gcc happy */ |
222 | struct nand_chip; | |
223 | ||
5b40db68 HS |
224 | /* ONFI features */ |
225 | #define ONFI_FEATURE_16_BIT_BUS (1 << 0) | |
226 | #define ONFI_FEATURE_EXT_PARAM_PAGE (1 << 7) | |
227 | ||
3e70192c HS |
228 | /* ONFI timing mode, used in both asynchronous and synchronous mode */ |
229 | #define ONFI_TIMING_MODE_0 (1 << 0) | |
230 | #define ONFI_TIMING_MODE_1 (1 << 1) | |
231 | #define ONFI_TIMING_MODE_2 (1 << 2) | |
232 | #define ONFI_TIMING_MODE_3 (1 << 3) | |
233 | #define ONFI_TIMING_MODE_4 (1 << 4) | |
234 | #define ONFI_TIMING_MODE_5 (1 << 5) | |
235 | #define ONFI_TIMING_MODE_UNKNOWN (1 << 6) | |
236 | ||
7db03ecc HS |
237 | /* ONFI feature address */ |
238 | #define ONFI_FEATURE_ADDR_TIMING_MODE 0x1 | |
239 | ||
8429bb39 BN |
240 | /* Vendor-specific feature address (Micron) */ |
241 | #define ONFI_FEATURE_ADDR_READ_RETRY 0x89 | |
242 | ||
7db03ecc HS |
243 | /* ONFI subfeature parameters length */ |
244 | #define ONFI_SUBFEATURE_PARAM_LEN 4 | |
245 | ||
d914c932 DM |
246 | /* ONFI optional commands SET/GET FEATURES supported? */ |
247 | #define ONFI_OPT_CMD_SET_GET_FEATURES (1 << 2) | |
248 | ||
d1e1f4e4 FF |
249 | struct nand_onfi_params { |
250 | /* rev info and features block */ | |
b46daf7e SAS |
251 | /* 'O' 'N' 'F' 'I' */ |
252 | u8 sig[4]; | |
253 | __le16 revision; | |
254 | __le16 features; | |
255 | __le16 opt_cmd; | |
5138a98f HS |
256 | u8 reserved0[2]; |
257 | __le16 ext_param_page_length; /* since ONFI 2.1 */ | |
258 | u8 num_of_param_pages; /* since ONFI 2.1 */ | |
259 | u8 reserved1[17]; | |
d1e1f4e4 FF |
260 | |
261 | /* manufacturer information block */ | |
b46daf7e SAS |
262 | char manufacturer[12]; |
263 | char model[20]; | |
264 | u8 jedec_id; | |
265 | __le16 date_code; | |
266 | u8 reserved2[13]; | |
d1e1f4e4 FF |
267 | |
268 | /* memory organization block */ | |
b46daf7e SAS |
269 | __le32 byte_per_page; |
270 | __le16 spare_bytes_per_page; | |
271 | __le32 data_bytes_per_ppage; | |
272 | __le16 spare_bytes_per_ppage; | |
273 | __le32 pages_per_block; | |
274 | __le32 blocks_per_lun; | |
275 | u8 lun_count; | |
276 | u8 addr_cycles; | |
277 | u8 bits_per_cell; | |
278 | __le16 bb_per_lun; | |
279 | __le16 block_endurance; | |
280 | u8 guaranteed_good_blocks; | |
281 | __le16 guaranteed_block_endurance; | |
282 | u8 programs_per_page; | |
283 | u8 ppage_attr; | |
284 | u8 ecc_bits; | |
285 | u8 interleaved_bits; | |
286 | u8 interleaved_ops; | |
287 | u8 reserved3[13]; | |
d1e1f4e4 FF |
288 | |
289 | /* electrical parameter block */ | |
b46daf7e SAS |
290 | u8 io_pin_capacitance_max; |
291 | __le16 async_timing_mode; | |
292 | __le16 program_cache_timing_mode; | |
293 | __le16 t_prog; | |
294 | __le16 t_bers; | |
295 | __le16 t_r; | |
296 | __le16 t_ccs; | |
297 | __le16 src_sync_timing_mode; | |
de64aa9e | 298 | u8 src_ssync_features; |
b46daf7e SAS |
299 | __le16 clk_pin_capacitance_typ; |
300 | __le16 io_pin_capacitance_typ; | |
301 | __le16 input_pin_capacitance_typ; | |
302 | u8 input_pin_capacitance_max; | |
a55e85ce | 303 | u8 driver_strength_support; |
b46daf7e | 304 | __le16 t_int_r; |
74e98be4 | 305 | __le16 t_adl; |
de64aa9e | 306 | u8 reserved4[8]; |
d1e1f4e4 FF |
307 | |
308 | /* vendor */ | |
6f0065b0 BN |
309 | __le16 vendor_revision; |
310 | u8 vendor[88]; | |
d1e1f4e4 FF |
311 | |
312 | __le16 crc; | |
e2e6b7b7 | 313 | } __packed; |
d1e1f4e4 FF |
314 | |
315 | #define ONFI_CRC_BASE 0x4F4E | |
316 | ||
5138a98f HS |
317 | /* Extended ECC information Block Definition (since ONFI 2.1) */ |
318 | struct onfi_ext_ecc_info { | |
319 | u8 ecc_bits; | |
320 | u8 codeword_size; | |
321 | __le16 bb_per_lun; | |
322 | __le16 block_endurance; | |
323 | u8 reserved[2]; | |
324 | } __packed; | |
325 | ||
326 | #define ONFI_SECTION_TYPE_0 0 /* Unused section. */ | |
327 | #define ONFI_SECTION_TYPE_1 1 /* for additional sections. */ | |
328 | #define ONFI_SECTION_TYPE_2 2 /* for ECC information. */ | |
329 | struct onfi_ext_section { | |
330 | u8 type; | |
331 | u8 length; | |
332 | } __packed; | |
333 | ||
334 | #define ONFI_EXT_SECTION_MAX 8 | |
335 | ||
336 | /* Extended Parameter Page Definition (since ONFI 2.1) */ | |
337 | struct onfi_ext_param_page { | |
338 | __le16 crc; | |
339 | u8 sig[4]; /* 'E' 'P' 'P' 'S' */ | |
340 | u8 reserved0[10]; | |
341 | struct onfi_ext_section sections[ONFI_EXT_SECTION_MAX]; | |
342 | ||
343 | /* | |
344 | * The actual size of the Extended Parameter Page is in | |
345 | * @ext_param_page_length of nand_onfi_params{}. | |
346 | * The following are the variable length sections. | |
347 | * So we do not add any fields below. Please see the ONFI spec. | |
348 | */ | |
349 | } __packed; | |
350 | ||
6f0065b0 BN |
351 | struct nand_onfi_vendor_micron { |
352 | u8 two_plane_read; | |
353 | u8 read_cache; | |
354 | u8 read_unique_id; | |
355 | u8 dq_imped; | |
356 | u8 dq_imped_num_settings; | |
357 | u8 dq_imped_feat_addr; | |
358 | u8 rb_pulldown_strength; | |
359 | u8 rb_pulldown_strength_feat_addr; | |
360 | u8 rb_pulldown_strength_num_settings; | |
361 | u8 otp_mode; | |
362 | u8 otp_page_start; | |
363 | u8 otp_data_prot_addr; | |
364 | u8 otp_num_pages; | |
365 | u8 otp_feat_addr; | |
366 | u8 read_retry_options; | |
367 | u8 reserved[72]; | |
368 | u8 param_revision; | |
369 | } __packed; | |
370 | ||
afbfff03 HS |
371 | struct jedec_ecc_info { |
372 | u8 ecc_bits; | |
373 | u8 codeword_size; | |
374 | __le16 bb_per_lun; | |
375 | __le16 block_endurance; | |
376 | u8 reserved[2]; | |
377 | } __packed; | |
378 | ||
7852f896 HS |
379 | /* JEDEC features */ |
380 | #define JEDEC_FEATURE_16_BIT_BUS (1 << 0) | |
381 | ||
afbfff03 HS |
382 | struct nand_jedec_params { |
383 | /* rev info and features block */ | |
384 | /* 'J' 'E' 'S' 'D' */ | |
385 | u8 sig[4]; | |
386 | __le16 revision; | |
387 | __le16 features; | |
388 | u8 opt_cmd[3]; | |
389 | __le16 sec_cmd; | |
390 | u8 num_of_param_pages; | |
391 | u8 reserved0[18]; | |
392 | ||
393 | /* manufacturer information block */ | |
394 | char manufacturer[12]; | |
395 | char model[20]; | |
396 | u8 jedec_id[6]; | |
397 | u8 reserved1[10]; | |
398 | ||
399 | /* memory organization block */ | |
400 | __le32 byte_per_page; | |
401 | __le16 spare_bytes_per_page; | |
402 | u8 reserved2[6]; | |
403 | __le32 pages_per_block; | |
404 | __le32 blocks_per_lun; | |
405 | u8 lun_count; | |
406 | u8 addr_cycles; | |
407 | u8 bits_per_cell; | |
408 | u8 programs_per_page; | |
409 | u8 multi_plane_addr; | |
410 | u8 multi_plane_op_attr; | |
411 | u8 reserved3[38]; | |
412 | ||
413 | /* electrical parameter block */ | |
414 | __le16 async_sdr_speed_grade; | |
415 | __le16 toggle_ddr_speed_grade; | |
416 | __le16 sync_ddr_speed_grade; | |
417 | u8 async_sdr_features; | |
418 | u8 toggle_ddr_features; | |
419 | u8 sync_ddr_features; | |
420 | __le16 t_prog; | |
421 | __le16 t_bers; | |
422 | __le16 t_r; | |
423 | __le16 t_r_multi_plane; | |
424 | __le16 t_ccs; | |
425 | __le16 io_pin_capacitance_typ; | |
426 | __le16 input_pin_capacitance_typ; | |
427 | __le16 clk_pin_capacitance_typ; | |
428 | u8 driver_strength_support; | |
74e98be4 | 429 | __le16 t_adl; |
afbfff03 HS |
430 | u8 reserved4[36]; |
431 | ||
432 | /* ECC and endurance block */ | |
433 | u8 guaranteed_good_blocks; | |
434 | __le16 guaranteed_block_endurance; | |
435 | struct jedec_ecc_info ecc_info[4]; | |
436 | u8 reserved5[29]; | |
437 | ||
438 | /* reserved */ | |
439 | u8 reserved6[148]; | |
440 | ||
441 | /* vendor */ | |
442 | __le16 vendor_rev_num; | |
443 | u8 reserved7[88]; | |
444 | ||
445 | /* CRC for Parameter Page */ | |
446 | __le16 crc; | |
447 | } __packed; | |
448 | ||
1da177e4 | 449 | /** |
844d3b42 | 450 | * struct nand_hw_control - Control structure for hardware controller (e.g ECC generator) shared among independent devices |
61ecfa87 | 451 | * @lock: protection lock |
1da177e4 | 452 | * @active: the mtd device which holds the controller currently |
a0491fc4 SAS |
453 | * @wq: wait queue to sleep on if a NAND operation is in |
454 | * progress used instead of the per chip wait queue | |
455 | * when a hw controller is available. | |
1da177e4 LT |
456 | */ |
457 | struct nand_hw_control { | |
b46daf7e | 458 | spinlock_t lock; |
1da177e4 | 459 | struct nand_chip *active; |
0dfc6246 | 460 | wait_queue_head_t wq; |
1da177e4 LT |
461 | }; |
462 | ||
d45bc58d MG |
463 | static inline void nand_hw_control_init(struct nand_hw_control *nfc) |
464 | { | |
465 | nfc->active = NULL; | |
466 | spin_lock_init(&nfc->lock); | |
467 | init_waitqueue_head(&nfc->wq); | |
468 | } | |
469 | ||
6dfc6d25 | 470 | /** |
7854d3f7 BN |
471 | * struct nand_ecc_ctrl - Control structure for ECC |
472 | * @mode: ECC mode | |
b0fcd8ab | 473 | * @algo: ECC algorithm |
7854d3f7 BN |
474 | * @steps: number of ECC steps per page |
475 | * @size: data bytes per ECC step | |
476 | * @bytes: ECC bytes per step | |
1d0b95b0 | 477 | * @strength: max number of correctible bits per ECC step |
7854d3f7 BN |
478 | * @total: total number of ECC bytes per page |
479 | * @prepad: padding information for syndrome based ECC generators | |
480 | * @postpad: padding information for syndrome based ECC generators | |
40cbe6ee | 481 | * @options: ECC specific options (see NAND_ECC_XXX flags defined above) |
7854d3f7 BN |
482 | * @priv: pointer to private ECC control data |
483 | * @hwctl: function to control hardware ECC generator. Must only | |
6dfc6d25 | 484 | * be provided if an hardware ECC is available |
7854d3f7 | 485 | * @calculate: function for ECC calculation or readback from ECC hardware |
6e941192 BB |
486 | * @correct: function for ECC correction, matching to ECC generator (sw/hw). |
487 | * Should return a positive number representing the number of | |
488 | * corrected bitflips, -EBADMSG if the number of bitflips exceed | |
489 | * ECC strength, or any other error code if the error is not | |
490 | * directly related to correction. | |
491 | * If -EBADMSG is returned the input buffers should be left | |
492 | * untouched. | |
62d956dc BB |
493 | * @read_page_raw: function to read a raw page without ECC. This function |
494 | * should hide the specific layout used by the ECC | |
495 | * controller and always return contiguous in-band and | |
496 | * out-of-band data even if they're not stored | |
497 | * contiguously on the NAND chip (e.g. | |
498 | * NAND_ECC_HW_SYNDROME interleaves in-band and | |
499 | * out-of-band data). | |
500 | * @write_page_raw: function to write a raw page without ECC. This function | |
501 | * should hide the specific layout used by the ECC | |
502 | * controller and consider the passed data as contiguous | |
503 | * in-band and out-of-band data. ECC controller is | |
504 | * responsible for doing the appropriate transformations | |
505 | * to adapt to its specific layout (e.g. | |
506 | * NAND_ECC_HW_SYNDROME interleaves in-band and | |
507 | * out-of-band data). | |
7854d3f7 | 508 | * @read_page: function to read a page according to the ECC generator |
5ca7f415 MD |
509 | * requirements; returns maximum number of bitflips corrected in |
510 | * any single ECC step, 0 if bitflips uncorrectable, -EIO hw error | |
511 | * @read_subpage: function to read parts of the page covered by ECC; | |
512 | * returns same as read_page() | |
837a6ba4 | 513 | * @write_subpage: function to write parts of the page covered by ECC. |
7854d3f7 | 514 | * @write_page: function to write a page according to the ECC generator |
a0491fc4 | 515 | * requirements. |
9ce244b3 | 516 | * @write_oob_raw: function to write chip OOB data without ECC |
c46f6483 | 517 | * @read_oob_raw: function to read chip OOB data without ECC |
844d3b42 RD |
518 | * @read_oob: function to read chip OOB data |
519 | * @write_oob: function to write chip OOB data | |
6dfc6d25 TG |
520 | */ |
521 | struct nand_ecc_ctrl { | |
b46daf7e | 522 | nand_ecc_modes_t mode; |
b0fcd8ab | 523 | enum nand_ecc_algo algo; |
b46daf7e SAS |
524 | int steps; |
525 | int size; | |
526 | int bytes; | |
527 | int total; | |
1d0b95b0 | 528 | int strength; |
b46daf7e SAS |
529 | int prepad; |
530 | int postpad; | |
40cbe6ee | 531 | unsigned int options; |
193bd400 | 532 | void *priv; |
b46daf7e SAS |
533 | void (*hwctl)(struct mtd_info *mtd, int mode); |
534 | int (*calculate)(struct mtd_info *mtd, const uint8_t *dat, | |
535 | uint8_t *ecc_code); | |
536 | int (*correct)(struct mtd_info *mtd, uint8_t *dat, uint8_t *read_ecc, | |
537 | uint8_t *calc_ecc); | |
538 | int (*read_page_raw)(struct mtd_info *mtd, struct nand_chip *chip, | |
1fbb938d | 539 | uint8_t *buf, int oob_required, int page); |
fdbad98d | 540 | int (*write_page_raw)(struct mtd_info *mtd, struct nand_chip *chip, |
45aaeff9 | 541 | const uint8_t *buf, int oob_required, int page); |
b46daf7e | 542 | int (*read_page)(struct mtd_info *mtd, struct nand_chip *chip, |
1fbb938d | 543 | uint8_t *buf, int oob_required, int page); |
b46daf7e | 544 | int (*read_subpage)(struct mtd_info *mtd, struct nand_chip *chip, |
e004debd | 545 | uint32_t offs, uint32_t len, uint8_t *buf, int page); |
837a6ba4 GP |
546 | int (*write_subpage)(struct mtd_info *mtd, struct nand_chip *chip, |
547 | uint32_t offset, uint32_t data_len, | |
45aaeff9 | 548 | const uint8_t *data_buf, int oob_required, int page); |
fdbad98d | 549 | int (*write_page)(struct mtd_info *mtd, struct nand_chip *chip, |
45aaeff9 | 550 | const uint8_t *buf, int oob_required, int page); |
9ce244b3 BN |
551 | int (*write_oob_raw)(struct mtd_info *mtd, struct nand_chip *chip, |
552 | int page); | |
c46f6483 | 553 | int (*read_oob_raw)(struct mtd_info *mtd, struct nand_chip *chip, |
5c2ffb11 SL |
554 | int page); |
555 | int (*read_oob)(struct mtd_info *mtd, struct nand_chip *chip, int page); | |
b46daf7e SAS |
556 | int (*write_oob)(struct mtd_info *mtd, struct nand_chip *chip, |
557 | int page); | |
f75e5097 TG |
558 | }; |
559 | ||
560 | /** | |
561 | * struct nand_buffers - buffer structure for read/write | |
f02ea4e6 HS |
562 | * @ecccalc: buffer pointer for calculated ECC, size is oobsize. |
563 | * @ecccode: buffer pointer for ECC read from flash, size is oobsize. | |
564 | * @databuf: buffer pointer for data, size is (page size + oobsize). | |
f75e5097 TG |
565 | * |
566 | * Do not change the order of buffers. databuf and oobrbuf must be in | |
567 | * consecutive order. | |
568 | */ | |
569 | struct nand_buffers { | |
f02ea4e6 HS |
570 | uint8_t *ecccalc; |
571 | uint8_t *ecccode; | |
572 | uint8_t *databuf; | |
6dfc6d25 TG |
573 | }; |
574 | ||
eee64b70 SH |
575 | /** |
576 | * struct nand_sdr_timings - SDR NAND chip timings | |
577 | * | |
578 | * This struct defines the timing requirements of a SDR NAND chip. | |
579 | * These information can be found in every NAND datasheets and the timings | |
580 | * meaning are described in the ONFI specifications: | |
581 | * www.onfi.org/~/media/ONFI/specs/onfi_3_1_spec.pdf (chapter 4.15 Timing | |
582 | * Parameters) | |
583 | * | |
584 | * All these timings are expressed in picoseconds. | |
585 | * | |
586 | * @tALH_min: ALE hold time | |
587 | * @tADL_min: ALE to data loading time | |
588 | * @tALS_min: ALE setup time | |
589 | * @tAR_min: ALE to RE# delay | |
590 | * @tCEA_max: CE# access time | |
591 | * @tCEH_min: | |
592 | * @tCH_min: CE# hold time | |
593 | * @tCHZ_max: CE# high to output hi-Z | |
594 | * @tCLH_min: CLE hold time | |
595 | * @tCLR_min: CLE to RE# delay | |
596 | * @tCLS_min: CLE setup time | |
597 | * @tCOH_min: CE# high to output hold | |
598 | * @tCS_min: CE# setup time | |
599 | * @tDH_min: Data hold time | |
600 | * @tDS_min: Data setup time | |
601 | * @tFEAT_max: Busy time for Set Features and Get Features | |
602 | * @tIR_min: Output hi-Z to RE# low | |
603 | * @tITC_max: Interface and Timing Mode Change time | |
604 | * @tRC_min: RE# cycle time | |
605 | * @tREA_max: RE# access time | |
606 | * @tREH_min: RE# high hold time | |
607 | * @tRHOH_min: RE# high to output hold | |
608 | * @tRHW_min: RE# high to WE# low | |
609 | * @tRHZ_max: RE# high to output hi-Z | |
610 | * @tRLOH_min: RE# low to output hold | |
611 | * @tRP_min: RE# pulse width | |
612 | * @tRR_min: Ready to RE# low (data only) | |
613 | * @tRST_max: Device reset time, measured from the falling edge of R/B# to the | |
614 | * rising edge of R/B#. | |
615 | * @tWB_max: WE# high to SR[6] low | |
616 | * @tWC_min: WE# cycle time | |
617 | * @tWH_min: WE# high hold time | |
618 | * @tWHR_min: WE# high to RE# low | |
619 | * @tWP_min: WE# pulse width | |
620 | * @tWW_min: WP# transition to WE# low | |
621 | */ | |
622 | struct nand_sdr_timings { | |
623 | u32 tALH_min; | |
624 | u32 tADL_min; | |
625 | u32 tALS_min; | |
626 | u32 tAR_min; | |
627 | u32 tCEA_max; | |
628 | u32 tCEH_min; | |
629 | u32 tCH_min; | |
630 | u32 tCHZ_max; | |
631 | u32 tCLH_min; | |
632 | u32 tCLR_min; | |
633 | u32 tCLS_min; | |
634 | u32 tCOH_min; | |
635 | u32 tCS_min; | |
636 | u32 tDH_min; | |
637 | u32 tDS_min; | |
638 | u32 tFEAT_max; | |
639 | u32 tIR_min; | |
640 | u32 tITC_max; | |
641 | u32 tRC_min; | |
642 | u32 tREA_max; | |
643 | u32 tREH_min; | |
644 | u32 tRHOH_min; | |
645 | u32 tRHW_min; | |
646 | u32 tRHZ_max; | |
647 | u32 tRLOH_min; | |
648 | u32 tRP_min; | |
649 | u32 tRR_min; | |
650 | u64 tRST_max; | |
651 | u32 tWB_max; | |
652 | u32 tWC_min; | |
653 | u32 tWH_min; | |
654 | u32 tWHR_min; | |
655 | u32 tWP_min; | |
656 | u32 tWW_min; | |
657 | }; | |
658 | ||
659 | /** | |
660 | * enum nand_data_interface_type - NAND interface timing type | |
661 | * @NAND_SDR_IFACE: Single Data Rate interface | |
662 | */ | |
663 | enum nand_data_interface_type { | |
664 | NAND_SDR_IFACE, | |
665 | }; | |
666 | ||
667 | /** | |
668 | * struct nand_data_interface - NAND interface timing | |
669 | * @type: type of the timing | |
670 | * @timings: The timing, type according to @type | |
671 | */ | |
672 | struct nand_data_interface { | |
673 | enum nand_data_interface_type type; | |
674 | union { | |
675 | struct nand_sdr_timings sdr; | |
676 | } timings; | |
677 | }; | |
678 | ||
679 | /** | |
680 | * nand_get_sdr_timings - get SDR timing from data interface | |
681 | * @conf: The data interface | |
682 | */ | |
683 | static inline const struct nand_sdr_timings * | |
684 | nand_get_sdr_timings(const struct nand_data_interface *conf) | |
685 | { | |
686 | if (conf->type != NAND_SDR_IFACE) | |
687 | return ERR_PTR(-EINVAL); | |
688 | ||
689 | return &conf->timings.sdr; | |
690 | } | |
691 | ||
1da177e4 LT |
692 | /** |
693 | * struct nand_chip - NAND Private Flash Chip Data | |
ed4f85c0 | 694 | * @mtd: MTD device registered to the MTD framework |
a0491fc4 SAS |
695 | * @IO_ADDR_R: [BOARDSPECIFIC] address to read the 8 I/O lines of the |
696 | * flash device | |
697 | * @IO_ADDR_W: [BOARDSPECIFIC] address to write the 8 I/O lines of the | |
698 | * flash device. | |
1da177e4 | 699 | * @read_byte: [REPLACEABLE] read one byte from the chip |
1da177e4 | 700 | * @read_word: [REPLACEABLE] read one word from the chip |
05f78359 UKK |
701 | * @write_byte: [REPLACEABLE] write a single byte to the chip on the |
702 | * low 8 I/O lines | |
1da177e4 LT |
703 | * @write_buf: [REPLACEABLE] write data from the buffer to the chip |
704 | * @read_buf: [REPLACEABLE] read data from the chip into the buffer | |
1da177e4 | 705 | * @select_chip: [REPLACEABLE] select chip nr |
ce157510 BN |
706 | * @block_bad: [REPLACEABLE] check if a block is bad, using OOB markers |
707 | * @block_markbad: [REPLACEABLE] mark a block bad | |
25985edc | 708 | * @cmd_ctrl: [BOARDSPECIFIC] hardwarespecific function for controlling |
7abd3ef9 | 709 | * ALE/CLE/nCE. Also used to write command and address |
7854d3f7 | 710 | * @dev_ready: [BOARDSPECIFIC] hardwarespecific function for accessing |
a0491fc4 SAS |
711 | * device ready/busy line. If set to NULL no access to |
712 | * ready/busy is available and the ready/busy information | |
713 | * is read from the chip status register. | |
714 | * @cmdfunc: [REPLACEABLE] hardwarespecific function for writing | |
715 | * commands to the chip. | |
716 | * @waitfunc: [REPLACEABLE] hardwarespecific function for wait on | |
717 | * ready. | |
ba84fb59 BN |
718 | * @setup_read_retry: [FLASHSPECIFIC] flash (vendor) specific function for |
719 | * setting the read-retry mode. Mostly needed for MLC NAND. | |
7854d3f7 | 720 | * @ecc: [BOARDSPECIFIC] ECC control structure |
844d3b42 RD |
721 | * @buffers: buffer structure for read/write |
722 | * @hwcontrol: platform-specific hardware control structure | |
49c50b97 | 723 | * @erase: [REPLACEABLE] erase function |
1da177e4 | 724 | * @scan_bbt: [REPLACEABLE] function to scan bad block table |
25985edc | 725 | * @chip_delay: [BOARDSPECIFIC] chip dependent delay for transferring |
a0491fc4 | 726 | * data from array to read regs (tR). |
2c0a2bed | 727 | * @state: [INTERN] the current state of the NAND device |
e9195edc BN |
728 | * @oob_poi: "poison value buffer," used for laying out OOB data |
729 | * before writing | |
a0491fc4 SAS |
730 | * @page_shift: [INTERN] number of address bits in a page (column |
731 | * address bits). | |
1da177e4 LT |
732 | * @phys_erase_shift: [INTERN] number of address bits in a physical eraseblock |
733 | * @bbt_erase_shift: [INTERN] number of address bits in a bbt entry | |
734 | * @chip_shift: [INTERN] number of address bits in one chip | |
a0491fc4 SAS |
735 | * @options: [BOARDSPECIFIC] various chip options. They can partly |
736 | * be set to inform nand_scan about special functionality. | |
737 | * See the defines for further explanation. | |
5fb1549d BN |
738 | * @bbt_options: [INTERN] bad block specific options. All options used |
739 | * here must come from bbm.h. By default, these options | |
740 | * will be copied to the appropriate nand_bbt_descr's. | |
a0491fc4 SAS |
741 | * @badblockpos: [INTERN] position of the bad block marker in the oob |
742 | * area. | |
661a0832 BN |
743 | * @badblockbits: [INTERN] minimum number of set bits in a good block's |
744 | * bad block marker position; i.e., BBM == 11110111b is | |
745 | * not bad when badblockbits == 7 | |
7db906b7 | 746 | * @bits_per_cell: [INTERN] number of bits per cell. i.e., 1 means SLC. |
4cfeca2d HS |
747 | * @ecc_strength_ds: [INTERN] ECC correctability from the datasheet. |
748 | * Minimum amount of bit errors per @ecc_step_ds guaranteed | |
749 | * to be correctable. If unknown, set to zero. | |
750 | * @ecc_step_ds: [INTERN] ECC step required by the @ecc_strength_ds, | |
751 | * also from the datasheet. It is the recommended ECC step | |
752 | * size, if known; if unknown, set to zero. | |
57a94e24 BB |
753 | * @onfi_timing_mode_default: [INTERN] default ONFI timing mode. This field is |
754 | * either deduced from the datasheet if the NAND | |
755 | * chip is not ONFI compliant or set to 0 if it is | |
756 | * (an ONFI chip is always configured in mode 0 | |
757 | * after a NAND reset) | |
1da177e4 LT |
758 | * @numchips: [INTERN] number of physical chips |
759 | * @chipsize: [INTERN] the size of one chip for multichip arrays | |
760 | * @pagemask: [INTERN] page number mask = number of (pages / chip) - 1 | |
a0491fc4 SAS |
761 | * @pagebuf: [INTERN] holds the pagenumber which is currently in |
762 | * data_buf. | |
edbc4540 MD |
763 | * @pagebuf_bitflips: [INTERN] holds the bitflip count for the page which is |
764 | * currently in data_buf. | |
29072b96 | 765 | * @subpagesize: [INTERN] holds the subpagesize |
a0491fc4 SAS |
766 | * @onfi_version: [INTERN] holds the chip ONFI version (BCD encoded), |
767 | * non 0 if ONFI supported. | |
d94abba7 HS |
768 | * @jedec_version: [INTERN] holds the chip JEDEC version (BCD encoded), |
769 | * non 0 if JEDEC supported. | |
a0491fc4 SAS |
770 | * @onfi_params: [INTERN] holds the ONFI page parameter when ONFI is |
771 | * supported, 0 otherwise. | |
d94abba7 HS |
772 | * @jedec_params: [INTERN] holds the JEDEC parameter page when JEDEC is |
773 | * supported, 0 otherwise. | |
ba84fb59 | 774 | * @read_retries: [INTERN] the number of read retry modes supported |
9ef525a9 RD |
775 | * @onfi_set_features: [REPLACEABLE] set the features for ONFI nand |
776 | * @onfi_get_features: [REPLACEABLE] get the features for ONFI nand | |
1da177e4 | 777 | * @bbt: [INTERN] bad block table pointer |
a0491fc4 SAS |
778 | * @bbt_td: [REPLACEABLE] bad block table descriptor for flash |
779 | * lookup. | |
1da177e4 | 780 | * @bbt_md: [REPLACEABLE] bad block table mirror descriptor |
a0491fc4 SAS |
781 | * @badblock_pattern: [REPLACEABLE] bad block scan pattern used for initial |
782 | * bad block scan. | |
783 | * @controller: [REPLACEABLE] a pointer to a hardware controller | |
7854d3f7 | 784 | * structure which is shared among multiple independent |
a0491fc4 | 785 | * devices. |
32c8db8f | 786 | * @priv: [OPTIONAL] pointer to private chip data |
a0491fc4 SAS |
787 | * @errstat: [OPTIONAL] hardware specific function to perform |
788 | * additional error status checks (determine if errors are | |
789 | * correctable). | |
351edd24 | 790 | * @write_page: [REPLACEABLE] High-level page write function |
1da177e4 | 791 | */ |
61ecfa87 | 792 | |
1da177e4 | 793 | struct nand_chip { |
ed4f85c0 | 794 | struct mtd_info mtd; |
b46daf7e SAS |
795 | void __iomem *IO_ADDR_R; |
796 | void __iomem *IO_ADDR_W; | |
797 | ||
798 | uint8_t (*read_byte)(struct mtd_info *mtd); | |
799 | u16 (*read_word)(struct mtd_info *mtd); | |
05f78359 | 800 | void (*write_byte)(struct mtd_info *mtd, uint8_t byte); |
b46daf7e SAS |
801 | void (*write_buf)(struct mtd_info *mtd, const uint8_t *buf, int len); |
802 | void (*read_buf)(struct mtd_info *mtd, uint8_t *buf, int len); | |
b46daf7e | 803 | void (*select_chip)(struct mtd_info *mtd, int chip); |
9f3e0429 | 804 | int (*block_bad)(struct mtd_info *mtd, loff_t ofs); |
b46daf7e SAS |
805 | int (*block_markbad)(struct mtd_info *mtd, loff_t ofs); |
806 | void (*cmd_ctrl)(struct mtd_info *mtd, int dat, unsigned int ctrl); | |
b46daf7e SAS |
807 | int (*dev_ready)(struct mtd_info *mtd); |
808 | void (*cmdfunc)(struct mtd_info *mtd, unsigned command, int column, | |
809 | int page_addr); | |
810 | int(*waitfunc)(struct mtd_info *mtd, struct nand_chip *this); | |
49c50b97 | 811 | int (*erase)(struct mtd_info *mtd, int page); |
b46daf7e SAS |
812 | int (*scan_bbt)(struct mtd_info *mtd); |
813 | int (*errstat)(struct mtd_info *mtd, struct nand_chip *this, int state, | |
814 | int status, int page); | |
815 | int (*write_page)(struct mtd_info *mtd, struct nand_chip *chip, | |
837a6ba4 GP |
816 | uint32_t offset, int data_len, const uint8_t *buf, |
817 | int oob_required, int page, int cached, int raw); | |
7db03ecc HS |
818 | int (*onfi_set_features)(struct mtd_info *mtd, struct nand_chip *chip, |
819 | int feature_addr, uint8_t *subfeature_para); | |
820 | int (*onfi_get_features)(struct mtd_info *mtd, struct nand_chip *chip, | |
821 | int feature_addr, uint8_t *subfeature_para); | |
ba84fb59 | 822 | int (*setup_read_retry)(struct mtd_info *mtd, int retry_mode); |
b46daf7e SAS |
823 | |
824 | int chip_delay; | |
825 | unsigned int options; | |
5fb1549d | 826 | unsigned int bbt_options; |
b46daf7e SAS |
827 | |
828 | int page_shift; | |
829 | int phys_erase_shift; | |
830 | int bbt_erase_shift; | |
831 | int chip_shift; | |
832 | int numchips; | |
833 | uint64_t chipsize; | |
834 | int pagemask; | |
835 | int pagebuf; | |
edbc4540 | 836 | unsigned int pagebuf_bitflips; |
b46daf7e | 837 | int subpagesize; |
7db906b7 | 838 | uint8_t bits_per_cell; |
4cfeca2d HS |
839 | uint16_t ecc_strength_ds; |
840 | uint16_t ecc_step_ds; | |
57a94e24 | 841 | int onfi_timing_mode_default; |
b46daf7e SAS |
842 | int badblockpos; |
843 | int badblockbits; | |
844 | ||
845 | int onfi_version; | |
d94abba7 HS |
846 | int jedec_version; |
847 | union { | |
848 | struct nand_onfi_params onfi_params; | |
849 | struct nand_jedec_params jedec_params; | |
850 | }; | |
d1e1f4e4 | 851 | |
ba84fb59 BN |
852 | int read_retries; |
853 | ||
b46daf7e | 854 | flstate_t state; |
f75e5097 | 855 | |
b46daf7e SAS |
856 | uint8_t *oob_poi; |
857 | struct nand_hw_control *controller; | |
f75e5097 TG |
858 | |
859 | struct nand_ecc_ctrl ecc; | |
4bf63fcb | 860 | struct nand_buffers *buffers; |
f75e5097 TG |
861 | struct nand_hw_control hwcontrol; |
862 | ||
b46daf7e SAS |
863 | uint8_t *bbt; |
864 | struct nand_bbt_descr *bbt_td; | |
865 | struct nand_bbt_descr *bbt_md; | |
f75e5097 | 866 | |
b46daf7e | 867 | struct nand_bbt_descr *badblock_pattern; |
f75e5097 | 868 | |
b46daf7e | 869 | void *priv; |
1da177e4 LT |
870 | }; |
871 | ||
41b207a7 BB |
872 | extern const struct mtd_ooblayout_ops nand_ooblayout_sp_ops; |
873 | extern const struct mtd_ooblayout_ops nand_ooblayout_lp_ops; | |
874 | ||
28b8b26b BN |
875 | static inline void nand_set_flash_node(struct nand_chip *chip, |
876 | struct device_node *np) | |
877 | { | |
29574ede | 878 | mtd_set_of_node(&chip->mtd, np); |
28b8b26b BN |
879 | } |
880 | ||
881 | static inline struct device_node *nand_get_flash_node(struct nand_chip *chip) | |
882 | { | |
29574ede | 883 | return mtd_get_of_node(&chip->mtd); |
28b8b26b BN |
884 | } |
885 | ||
9eba47dd BB |
886 | static inline struct nand_chip *mtd_to_nand(struct mtd_info *mtd) |
887 | { | |
2d3b77ba | 888 | return container_of(mtd, struct nand_chip, mtd); |
9eba47dd BB |
889 | } |
890 | ||
ffd014f4 BB |
891 | static inline struct mtd_info *nand_to_mtd(struct nand_chip *chip) |
892 | { | |
893 | return &chip->mtd; | |
894 | } | |
895 | ||
d39ddbd9 BB |
896 | static inline void *nand_get_controller_data(struct nand_chip *chip) |
897 | { | |
898 | return chip->priv; | |
899 | } | |
900 | ||
901 | static inline void nand_set_controller_data(struct nand_chip *chip, void *priv) | |
902 | { | |
903 | chip->priv = priv; | |
904 | } | |
905 | ||
1da177e4 LT |
906 | /* |
907 | * NAND Flash Manufacturer ID Codes | |
908 | */ | |
909 | #define NAND_MFR_TOSHIBA 0x98 | |
1c7fe6b4 | 910 | #define NAND_MFR_ESMT 0xc8 |
1da177e4 LT |
911 | #define NAND_MFR_SAMSUNG 0xec |
912 | #define NAND_MFR_FUJITSU 0x04 | |
913 | #define NAND_MFR_NATIONAL 0x8f | |
914 | #define NAND_MFR_RENESAS 0x07 | |
915 | #define NAND_MFR_STMICRO 0x20 | |
2c0a2bed | 916 | #define NAND_MFR_HYNIX 0xad |
8c60e547 | 917 | #define NAND_MFR_MICRON 0x2c |
30eb0db0 | 918 | #define NAND_MFR_AMD 0x01 |
c1257b47 | 919 | #define NAND_MFR_MACRONIX 0xc2 |
b1ccfab3 | 920 | #define NAND_MFR_EON 0x92 |
3f97c6ff | 921 | #define NAND_MFR_SANDISK 0x45 |
4968a412 | 922 | #define NAND_MFR_INTEL 0x89 |
641519cb | 923 | #define NAND_MFR_ATO 0x9b |
1da177e4 | 924 | |
53552d22 AB |
925 | /* The maximum expected count of bytes in the NAND ID sequence */ |
926 | #define NAND_MAX_ID_LEN 8 | |
927 | ||
8dbfae1e AB |
928 | /* |
929 | * A helper for defining older NAND chips where the second ID byte fully | |
930 | * defined the chip, including the geometry (chip size, eraseblock size, page | |
5bfa9b71 | 931 | * size). All these chips have 512 bytes NAND page size. |
8dbfae1e | 932 | */ |
5bfa9b71 AB |
933 | #define LEGACY_ID_NAND(nm, devid, chipsz, erasesz, opts) \ |
934 | { .name = (nm), {{ .dev_id = (devid) }}, .pagesize = 512, \ | |
935 | .chipsize = (chipsz), .erasesize = (erasesz), .options = (opts) } | |
8dbfae1e AB |
936 | |
937 | /* | |
938 | * A helper for defining newer chips which report their page size and | |
939 | * eraseblock size via the extended ID bytes. | |
940 | * | |
941 | * The real difference between LEGACY_ID_NAND and EXTENDED_ID_NAND is that with | |
942 | * EXTENDED_ID_NAND, manufacturers overloaded the same device ID so that the | |
943 | * device ID now only represented a particular total chip size (and voltage, | |
944 | * buswidth), and the page size, eraseblock size, and OOB size could vary while | |
945 | * using the same device ID. | |
946 | */ | |
8e12b474 AB |
947 | #define EXTENDED_ID_NAND(nm, devid, chipsz, opts) \ |
948 | { .name = (nm), {{ .dev_id = (devid) }}, .chipsize = (chipsz), \ | |
8dbfae1e AB |
949 | .options = (opts) } |
950 | ||
2dc0bdd9 HS |
951 | #define NAND_ECC_INFO(_strength, _step) \ |
952 | { .strength_ds = (_strength), .step_ds = (_step) } | |
953 | #define NAND_ECC_STRENGTH(type) ((type)->ecc.strength_ds) | |
954 | #define NAND_ECC_STEP(type) ((type)->ecc.step_ds) | |
955 | ||
1da177e4 LT |
956 | /** |
957 | * struct nand_flash_dev - NAND Flash Device ID Structure | |
68aa352d AB |
958 | * @name: a human-readable name of the NAND chip |
959 | * @dev_id: the device ID (the second byte of the full chip ID array) | |
8e12b474 AB |
960 | * @mfr_id: manufecturer ID part of the full chip ID array (refers the same |
961 | * memory address as @id[0]) | |
962 | * @dev_id: device ID part of the full chip ID array (refers the same memory | |
963 | * address as @id[1]) | |
964 | * @id: full device ID array | |
68aa352d AB |
965 | * @pagesize: size of the NAND page in bytes; if 0, then the real page size (as |
966 | * well as the eraseblock size) is determined from the extended NAND | |
967 | * chip ID array) | |
68aa352d | 968 | * @chipsize: total chip size in MiB |
ecb42fea | 969 | * @erasesize: eraseblock size in bytes (determined from the extended ID if 0) |
68aa352d | 970 | * @options: stores various chip bit options |
f22d5f63 HS |
971 | * @id_len: The valid length of the @id. |
972 | * @oobsize: OOB size | |
7b7d8982 | 973 | * @ecc: ECC correctability and step information from the datasheet. |
2dc0bdd9 HS |
974 | * @ecc.strength_ds: The ECC correctability from the datasheet, same as the |
975 | * @ecc_strength_ds in nand_chip{}. | |
976 | * @ecc.step_ds: The ECC step required by the @ecc.strength_ds, same as the | |
977 | * @ecc_step_ds in nand_chip{}, also from the datasheet. | |
978 | * For example, the "4bit ECC for each 512Byte" can be set with | |
979 | * NAND_ECC_INFO(4, 512). | |
57a94e24 BB |
980 | * @onfi_timing_mode_default: the default ONFI timing mode entered after a NAND |
981 | * reset. Should be deduced from timings described | |
982 | * in the datasheet. | |
983 | * | |
1da177e4 LT |
984 | */ |
985 | struct nand_flash_dev { | |
986 | char *name; | |
8e12b474 AB |
987 | union { |
988 | struct { | |
989 | uint8_t mfr_id; | |
990 | uint8_t dev_id; | |
991 | }; | |
53552d22 | 992 | uint8_t id[NAND_MAX_ID_LEN]; |
8e12b474 | 993 | }; |
ecb42fea AB |
994 | unsigned int pagesize; |
995 | unsigned int chipsize; | |
996 | unsigned int erasesize; | |
997 | unsigned int options; | |
f22d5f63 HS |
998 | uint16_t id_len; |
999 | uint16_t oobsize; | |
2dc0bdd9 HS |
1000 | struct { |
1001 | uint16_t strength_ds; | |
1002 | uint16_t step_ds; | |
1003 | } ecc; | |
57a94e24 | 1004 | int onfi_timing_mode_default; |
1da177e4 LT |
1005 | }; |
1006 | ||
1007 | /** | |
1008 | * struct nand_manufacturers - NAND Flash Manufacturer ID Structure | |
1009 | * @name: Manufacturer name | |
2c0a2bed | 1010 | * @id: manufacturer ID code of device. |
1da177e4 LT |
1011 | */ |
1012 | struct nand_manufacturers { | |
1013 | int id; | |
a0491fc4 | 1014 | char *name; |
1da177e4 LT |
1015 | }; |
1016 | ||
1017 | extern struct nand_flash_dev nand_flash_ids[]; | |
1018 | extern struct nand_manufacturers nand_manuf_ids[]; | |
1019 | ||
79022591 SH |
1020 | int nand_default_bbt(struct mtd_info *mtd); |
1021 | int nand_markbad_bbt(struct mtd_info *mtd, loff_t offs); | |
1022 | int nand_isreserved_bbt(struct mtd_info *mtd, loff_t offs); | |
1023 | int nand_isbad_bbt(struct mtd_info *mtd, loff_t offs, int allowbbt); | |
1024 | int nand_erase_nand(struct mtd_info *mtd, struct erase_info *instr, | |
1025 | int allowbbt); | |
1026 | int nand_do_read(struct mtd_info *mtd, loff_t from, size_t len, | |
1027 | size_t *retlen, uint8_t *buf); | |
1da177e4 | 1028 | |
41796c2e TG |
1029 | /** |
1030 | * struct platform_nand_chip - chip level device structure | |
41796c2e | 1031 | * @nr_chips: max. number of chips to scan for |
844d3b42 | 1032 | * @chip_offset: chip number offset |
8be834f7 | 1033 | * @nr_partitions: number of partitions pointed to by partitions (or zero) |
41796c2e TG |
1034 | * @partitions: mtd partition list |
1035 | * @chip_delay: R/B delay value in us | |
1036 | * @options: Option flags, e.g. 16bit buswidth | |
a40f7341 | 1037 | * @bbt_options: BBT option flags, e.g. NAND_BBT_USE_FLASH |
972edcb7 | 1038 | * @part_probe_types: NULL-terminated array of probe types |
41796c2e TG |
1039 | */ |
1040 | struct platform_nand_chip { | |
b46daf7e SAS |
1041 | int nr_chips; |
1042 | int chip_offset; | |
1043 | int nr_partitions; | |
1044 | struct mtd_partition *partitions; | |
b46daf7e SAS |
1045 | int chip_delay; |
1046 | unsigned int options; | |
a40f7341 | 1047 | unsigned int bbt_options; |
b46daf7e | 1048 | const char **part_probe_types; |
41796c2e TG |
1049 | }; |
1050 | ||
bf95efd4 HS |
1051 | /* Keep gcc happy */ |
1052 | struct platform_device; | |
1053 | ||
41796c2e TG |
1054 | /** |
1055 | * struct platform_nand_ctrl - controller level device structure | |
bf95efd4 HS |
1056 | * @probe: platform specific function to probe/setup hardware |
1057 | * @remove: platform specific function to remove/teardown hardware | |
41796c2e TG |
1058 | * @hwcontrol: platform specific hardware control structure |
1059 | * @dev_ready: platform specific function to read ready/busy pin | |
1060 | * @select_chip: platform specific chip select function | |
972edcb7 VW |
1061 | * @cmd_ctrl: platform specific function for controlling |
1062 | * ALE/CLE/nCE. Also used to write command and address | |
d6fed9e9 AC |
1063 | * @write_buf: platform specific function for write buffer |
1064 | * @read_buf: platform specific function for read buffer | |
25806d3c | 1065 | * @read_byte: platform specific function to read one byte from chip |
844d3b42 | 1066 | * @priv: private data to transport driver specific settings |
41796c2e TG |
1067 | * |
1068 | * All fields are optional and depend on the hardware driver requirements | |
1069 | */ | |
1070 | struct platform_nand_ctrl { | |
b46daf7e SAS |
1071 | int (*probe)(struct platform_device *pdev); |
1072 | void (*remove)(struct platform_device *pdev); | |
1073 | void (*hwcontrol)(struct mtd_info *mtd, int cmd); | |
1074 | int (*dev_ready)(struct mtd_info *mtd); | |
1075 | void (*select_chip)(struct mtd_info *mtd, int chip); | |
1076 | void (*cmd_ctrl)(struct mtd_info *mtd, int dat, unsigned int ctrl); | |
1077 | void (*write_buf)(struct mtd_info *mtd, const uint8_t *buf, int len); | |
1078 | void (*read_buf)(struct mtd_info *mtd, uint8_t *buf, int len); | |
b4f7aa84 | 1079 | unsigned char (*read_byte)(struct mtd_info *mtd); |
b46daf7e | 1080 | void *priv; |
41796c2e TG |
1081 | }; |
1082 | ||
972edcb7 VW |
1083 | /** |
1084 | * struct platform_nand_data - container structure for platform-specific data | |
1085 | * @chip: chip level chip structure | |
1086 | * @ctrl: controller level device structure | |
1087 | */ | |
1088 | struct platform_nand_data { | |
b46daf7e SAS |
1089 | struct platform_nand_chip chip; |
1090 | struct platform_nand_ctrl ctrl; | |
972edcb7 VW |
1091 | }; |
1092 | ||
5b40db68 HS |
1093 | /* return the supported features. */ |
1094 | static inline int onfi_feature(struct nand_chip *chip) | |
1095 | { | |
1096 | return chip->onfi_version ? le16_to_cpu(chip->onfi_params.features) : 0; | |
1097 | } | |
1098 | ||
3e70192c HS |
1099 | /* return the supported asynchronous timing mode. */ |
1100 | static inline int onfi_get_async_timing_mode(struct nand_chip *chip) | |
1101 | { | |
1102 | if (!chip->onfi_version) | |
1103 | return ONFI_TIMING_MODE_UNKNOWN; | |
1104 | return le16_to_cpu(chip->onfi_params.async_timing_mode); | |
1105 | } | |
1106 | ||
1107 | /* return the supported synchronous timing mode. */ | |
1108 | static inline int onfi_get_sync_timing_mode(struct nand_chip *chip) | |
1109 | { | |
1110 | if (!chip->onfi_version) | |
1111 | return ONFI_TIMING_MODE_UNKNOWN; | |
1112 | return le16_to_cpu(chip->onfi_params.src_sync_timing_mode); | |
1113 | } | |
1114 | ||
1d0ed69d HS |
1115 | /* |
1116 | * Check if it is a SLC nand. | |
1117 | * The !nand_is_slc() can be used to check the MLC/TLC nand chips. | |
1118 | * We do not distinguish the MLC and TLC now. | |
1119 | */ | |
1120 | static inline bool nand_is_slc(struct nand_chip *chip) | |
1121 | { | |
7db906b7 | 1122 | return chip->bits_per_cell == 1; |
1d0ed69d | 1123 | } |
3dad2344 BN |
1124 | |
1125 | /** | |
1126 | * Check if the opcode's address should be sent only on the lower 8 bits | |
1127 | * @command: opcode to check | |
1128 | */ | |
1129 | static inline int nand_opcode_8bits(unsigned int command) | |
1130 | { | |
e34fcb07 DM |
1131 | switch (command) { |
1132 | case NAND_CMD_READID: | |
1133 | case NAND_CMD_PARAM: | |
1134 | case NAND_CMD_GET_FEATURES: | |
1135 | case NAND_CMD_SET_FEATURES: | |
1136 | return 1; | |
1137 | default: | |
1138 | break; | |
1139 | } | |
1140 | return 0; | |
3dad2344 BN |
1141 | } |
1142 | ||
7852f896 HS |
1143 | /* return the supported JEDEC features. */ |
1144 | static inline int jedec_feature(struct nand_chip *chip) | |
1145 | { | |
1146 | return chip->jedec_version ? le16_to_cpu(chip->jedec_params.features) | |
1147 | : 0; | |
1148 | } | |
bb5fd0b6 | 1149 | |
974647ea BB |
1150 | /* get timing characteristics from ONFI timing mode. */ |
1151 | const struct nand_sdr_timings *onfi_async_timing_mode_to_sdr_timings(int mode); | |
730a43fb BB |
1152 | |
1153 | int nand_check_erased_ecc_chunk(void *data, int datalen, | |
1154 | void *ecc, int ecclen, | |
1155 | void *extraoob, int extraooblen, | |
1156 | int threshold); | |
9d02fc2a BB |
1157 | |
1158 | /* Default write_oob implementation */ | |
1159 | int nand_write_oob_std(struct mtd_info *mtd, struct nand_chip *chip, int page); | |
1160 | ||
1161 | /* Default write_oob syndrome implementation */ | |
1162 | int nand_write_oob_syndrome(struct mtd_info *mtd, struct nand_chip *chip, | |
1163 | int page); | |
1164 | ||
1165 | /* Default read_oob implementation */ | |
1166 | int nand_read_oob_std(struct mtd_info *mtd, struct nand_chip *chip, int page); | |
1167 | ||
1168 | /* Default read_oob syndrome implementation */ | |
1169 | int nand_read_oob_syndrome(struct mtd_info *mtd, struct nand_chip *chip, | |
1170 | int page); | |
2f94abfe SH |
1171 | |
1172 | /* Reset and initialize a NAND device */ | |
1173 | int nand_reset(struct nand_chip *chip); | |
1174 | ||
1da177e4 | 1175 | #endif /* __LINUX_MTD_NAND_H */ |