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Commit | Line | Data |
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1da177e4 LT |
1 | /* |
2 | * linux/include/linux/mtd/nand.h | |
3 | * | |
a1452a37 DW |
4 | * Copyright © 2000-2010 David Woodhouse <dwmw2@infradead.org> |
5 | * Steven J. Hill <sjhill@realitydiluted.com> | |
6 | * Thomas Gleixner <tglx@linutronix.de> | |
1da177e4 | 7 | * |
1da177e4 LT |
8 | * This program is free software; you can redistribute it and/or modify |
9 | * it under the terms of the GNU General Public License version 2 as | |
10 | * published by the Free Software Foundation. | |
11 | * | |
2c0a2bed TG |
12 | * Info: |
13 | * Contains standard defines and IDs for NAND flash devices | |
1da177e4 | 14 | * |
2c0a2bed TG |
15 | * Changelog: |
16 | * See git changelog. | |
1da177e4 LT |
17 | */ |
18 | #ifndef __LINUX_MTD_NAND_H | |
19 | #define __LINUX_MTD_NAND_H | |
20 | ||
1da177e4 LT |
21 | #include <linux/wait.h> |
22 | #include <linux/spinlock.h> | |
23 | #include <linux/mtd/mtd.h> | |
30631cb8 | 24 | #include <linux/mtd/flashchip.h> |
c62d81bc | 25 | #include <linux/mtd/bbm.h> |
1da177e4 LT |
26 | |
27 | struct mtd_info; | |
5e81e88a | 28 | struct nand_flash_dev; |
5844feea BN |
29 | struct device_node; |
30 | ||
1da177e4 | 31 | /* Scan and identify a NAND device */ |
79022591 | 32 | int nand_scan(struct mtd_info *mtd, int max_chips); |
a0491fc4 SAS |
33 | /* |
34 | * Separate phases of nand_scan(), allowing board driver to intervene | |
35 | * and override command or ECC setup according to flash type. | |
36 | */ | |
79022591 | 37 | int nand_scan_ident(struct mtd_info *mtd, int max_chips, |
5e81e88a | 38 | struct nand_flash_dev *table); |
79022591 | 39 | int nand_scan_tail(struct mtd_info *mtd); |
3b85c321 | 40 | |
d44154f9 | 41 | /* Unregister the MTD device and free resources held by the NAND device */ |
79022591 | 42 | void nand_release(struct mtd_info *mtd); |
1da177e4 | 43 | |
b77d95c7 | 44 | /* Internal helper for board drivers which need to override command function */ |
79022591 | 45 | void nand_wait_ready(struct mtd_info *mtd); |
b77d95c7 | 46 | |
1da177e4 LT |
47 | /* The maximum number of NAND chips in an array */ |
48 | #define NAND_MAX_CHIPS 8 | |
49 | ||
1da177e4 LT |
50 | /* |
51 | * Constants for hardware specific CLE/ALE/NCE function | |
7abd3ef9 TG |
52 | * |
53 | * These are bits which can be or'ed to set/clear multiple | |
54 | * bits in one go. | |
55 | */ | |
1da177e4 | 56 | /* Select the chip by setting nCE to low */ |
7abd3ef9 | 57 | #define NAND_NCE 0x01 |
1da177e4 | 58 | /* Select the command latch by setting CLE to high */ |
7abd3ef9 | 59 | #define NAND_CLE 0x02 |
1da177e4 | 60 | /* Select the address latch by setting ALE to high */ |
7abd3ef9 TG |
61 | #define NAND_ALE 0x04 |
62 | ||
63 | #define NAND_CTRL_CLE (NAND_NCE | NAND_CLE) | |
64 | #define NAND_CTRL_ALE (NAND_NCE | NAND_ALE) | |
65 | #define NAND_CTRL_CHANGE 0x80 | |
1da177e4 LT |
66 | |
67 | /* | |
68 | * Standard NAND flash commands | |
69 | */ | |
70 | #define NAND_CMD_READ0 0 | |
71 | #define NAND_CMD_READ1 1 | |
7bc3312b | 72 | #define NAND_CMD_RNDOUT 5 |
1da177e4 LT |
73 | #define NAND_CMD_PAGEPROG 0x10 |
74 | #define NAND_CMD_READOOB 0x50 | |
75 | #define NAND_CMD_ERASE1 0x60 | |
76 | #define NAND_CMD_STATUS 0x70 | |
1da177e4 | 77 | #define NAND_CMD_SEQIN 0x80 |
7bc3312b | 78 | #define NAND_CMD_RNDIN 0x85 |
1da177e4 LT |
79 | #define NAND_CMD_READID 0x90 |
80 | #define NAND_CMD_ERASE2 0xd0 | |
caa4b6f2 | 81 | #define NAND_CMD_PARAM 0xec |
7db03ecc HS |
82 | #define NAND_CMD_GET_FEATURES 0xee |
83 | #define NAND_CMD_SET_FEATURES 0xef | |
1da177e4 LT |
84 | #define NAND_CMD_RESET 0xff |
85 | ||
86 | /* Extended commands for large page devices */ | |
87 | #define NAND_CMD_READSTART 0x30 | |
7bc3312b | 88 | #define NAND_CMD_RNDOUTSTART 0xE0 |
1da177e4 LT |
89 | #define NAND_CMD_CACHEDPROG 0x15 |
90 | ||
7abd3ef9 TG |
91 | #define NAND_CMD_NONE -1 |
92 | ||
1da177e4 LT |
93 | /* Status bits */ |
94 | #define NAND_STATUS_FAIL 0x01 | |
95 | #define NAND_STATUS_FAIL_N1 0x02 | |
96 | #define NAND_STATUS_TRUE_READY 0x20 | |
97 | #define NAND_STATUS_READY 0x40 | |
98 | #define NAND_STATUS_WP 0x80 | |
99 | ||
104e442a BB |
100 | #define NAND_DATA_IFACE_CHECK_ONLY -1 |
101 | ||
61ecfa87 | 102 | /* |
1da177e4 LT |
103 | * Constants for ECC_MODES |
104 | */ | |
6dfc6d25 TG |
105 | typedef enum { |
106 | NAND_ECC_NONE, | |
107 | NAND_ECC_SOFT, | |
108 | NAND_ECC_HW, | |
109 | NAND_ECC_HW_SYNDROME, | |
6e0cb135 | 110 | NAND_ECC_HW_OOB_FIRST, |
785818fa | 111 | NAND_ECC_ON_DIE, |
6dfc6d25 | 112 | } nand_ecc_modes_t; |
1da177e4 | 113 | |
b0fcd8ab RM |
114 | enum nand_ecc_algo { |
115 | NAND_ECC_UNKNOWN, | |
116 | NAND_ECC_HAMMING, | |
117 | NAND_ECC_BCH, | |
118 | }; | |
119 | ||
1da177e4 LT |
120 | /* |
121 | * Constants for Hardware ECC | |
068e3c0a | 122 | */ |
1da177e4 LT |
123 | /* Reset Hardware ECC for read */ |
124 | #define NAND_ECC_READ 0 | |
125 | /* Reset Hardware ECC for write */ | |
126 | #define NAND_ECC_WRITE 1 | |
7854d3f7 | 127 | /* Enable Hardware ECC before syndrome is read back from flash */ |
1da177e4 LT |
128 | #define NAND_ECC_READSYN 2 |
129 | ||
40cbe6ee BB |
130 | /* |
131 | * Enable generic NAND 'page erased' check. This check is only done when | |
132 | * ecc.correct() returns -EBADMSG. | |
133 | * Set this flag if your implementation does not fix bitflips in erased | |
134 | * pages and you want to rely on the default implementation. | |
135 | */ | |
136 | #define NAND_ECC_GENERIC_ERASED_CHECK BIT(0) | |
ba78ee00 | 137 | #define NAND_ECC_MAXIMIZE BIT(1) |
3371d663 MG |
138 | /* |
139 | * If your controller already sends the required NAND commands when | |
140 | * reading or writing a page, then the framework is not supposed to | |
141 | * send READ0 and SEQIN/PAGEPROG respectively. | |
142 | */ | |
143 | #define NAND_ECC_CUSTOM_PAGE_ACCESS BIT(2) | |
40cbe6ee | 144 | |
068e3c0a DM |
145 | /* Bit mask for flags passed to do_nand_read_ecc */ |
146 | #define NAND_GET_DEVICE 0x80 | |
147 | ||
148 | ||
a0491fc4 SAS |
149 | /* |
150 | * Option constants for bizarre disfunctionality and real | |
151 | * features. | |
152 | */ | |
7854d3f7 | 153 | /* Buswidth is 16 bit */ |
1da177e4 | 154 | #define NAND_BUSWIDTH_16 0x00000002 |
1da177e4 LT |
155 | /* Chip has cache program function */ |
156 | #define NAND_CACHEPRG 0x00000008 | |
5bc7c33c BN |
157 | /* |
158 | * Chip requires ready check on read (for auto-incremented sequential read). | |
159 | * True only for small page devices; large page devices do not support | |
160 | * autoincrement. | |
161 | */ | |
162 | #define NAND_NEED_READRDY 0x00000100 | |
163 | ||
29072b96 TG |
164 | /* Chip does not allow subpage writes */ |
165 | #define NAND_NO_SUBPAGE_WRITE 0x00000200 | |
166 | ||
93edbad6 ML |
167 | /* Device is one of 'new' xD cards that expose fake nand command set */ |
168 | #define NAND_BROKEN_XD 0x00000400 | |
169 | ||
170 | /* Device behaves just like nand, but is readonly */ | |
171 | #define NAND_ROM 0x00000800 | |
172 | ||
a5ff4f10 JW |
173 | /* Device supports subpage reads */ |
174 | #define NAND_SUBPAGE_READ 0x00001000 | |
175 | ||
c03d9969 BB |
176 | /* |
177 | * Some MLC NANDs need data scrambling to limit bitflips caused by repeated | |
178 | * patterns. | |
179 | */ | |
180 | #define NAND_NEED_SCRAMBLING 0x00002000 | |
181 | ||
1da177e4 | 182 | /* Options valid for Samsung large page devices */ |
3239a6cd | 183 | #define NAND_SAMSUNG_LP_OPTIONS NAND_CACHEPRG |
1da177e4 LT |
184 | |
185 | /* Macros to identify the above */ | |
1da177e4 | 186 | #define NAND_HAS_CACHEPROG(chip) ((chip->options & NAND_CACHEPRG)) |
a5ff4f10 | 187 | #define NAND_HAS_SUBPAGE_READ(chip) ((chip->options & NAND_SUBPAGE_READ)) |
3371d663 | 188 | #define NAND_HAS_SUBPAGE_WRITE(chip) !((chip)->options & NAND_NO_SUBPAGE_WRITE) |
1da177e4 | 189 | |
1da177e4 | 190 | /* Non chip related options */ |
0040bf38 | 191 | /* This option skips the bbt scan during initialization. */ |
b4dc53e1 | 192 | #define NAND_SKIP_BBTSCAN 0x00010000 |
a0491fc4 SAS |
193 | /* |
194 | * This option is defined if the board driver allocates its own buffers | |
195 | * (e.g. because it needs them DMA-coherent). | |
196 | */ | |
b4dc53e1 | 197 | #define NAND_OWN_BUFFERS 0x00020000 |
b1c6e6db | 198 | /* Chip may not exist, so silence any errors in scan */ |
b4dc53e1 | 199 | #define NAND_SCAN_SILENT_NODEV 0x00040000 |
64b37b2a MC |
200 | /* |
201 | * Autodetect nand buswidth with readid/onfi. | |
202 | * This suppose the driver will configure the hardware in 8 bits mode | |
203 | * when calling nand_scan_ident, and update its configuration | |
204 | * before calling nand_scan_tail. | |
205 | */ | |
206 | #define NAND_BUSWIDTH_AUTO 0x00080000 | |
5f867db6 SW |
207 | /* |
208 | * This option could be defined by controller drivers to protect against | |
209 | * kmap'ed, vmalloc'ed highmem buffers being passed from upper layers | |
210 | */ | |
211 | #define NAND_USE_BOUNCE_BUFFER 0x00100000 | |
b1c6e6db | 212 | |
6ea40a3b BB |
213 | /* |
214 | * In case your controller is implementing ->cmd_ctrl() and is relying on the | |
215 | * default ->cmdfunc() implementation, you may want to let the core handle the | |
216 | * tCCS delay which is required when a column change (RNDIN or RNDOUT) is | |
217 | * requested. | |
218 | * If your controller already takes care of this delay, you don't need to set | |
219 | * this flag. | |
220 | */ | |
221 | #define NAND_WAIT_TCCS 0x00200000 | |
222 | ||
1da177e4 | 223 | /* Options set by nand scan */ |
a36ed299 | 224 | /* Nand scan has allocated controller struct */ |
f75e5097 | 225 | #define NAND_CONTROLLER_ALLOC 0x80000000 |
1da177e4 | 226 | |
29072b96 TG |
227 | /* Cell info constants */ |
228 | #define NAND_CI_CHIPNR_MSK 0x03 | |
229 | #define NAND_CI_CELLTYPE_MSK 0x0C | |
7db906b7 | 230 | #define NAND_CI_CELLTYPE_SHIFT 2 |
1da177e4 | 231 | |
1da177e4 LT |
232 | /* Keep gcc happy */ |
233 | struct nand_chip; | |
234 | ||
5b40db68 HS |
235 | /* ONFI features */ |
236 | #define ONFI_FEATURE_16_BIT_BUS (1 << 0) | |
237 | #define ONFI_FEATURE_EXT_PARAM_PAGE (1 << 7) | |
238 | ||
3e70192c HS |
239 | /* ONFI timing mode, used in both asynchronous and synchronous mode */ |
240 | #define ONFI_TIMING_MODE_0 (1 << 0) | |
241 | #define ONFI_TIMING_MODE_1 (1 << 1) | |
242 | #define ONFI_TIMING_MODE_2 (1 << 2) | |
243 | #define ONFI_TIMING_MODE_3 (1 << 3) | |
244 | #define ONFI_TIMING_MODE_4 (1 << 4) | |
245 | #define ONFI_TIMING_MODE_5 (1 << 5) | |
246 | #define ONFI_TIMING_MODE_UNKNOWN (1 << 6) | |
247 | ||
7db03ecc HS |
248 | /* ONFI feature address */ |
249 | #define ONFI_FEATURE_ADDR_TIMING_MODE 0x1 | |
250 | ||
8429bb39 BN |
251 | /* Vendor-specific feature address (Micron) */ |
252 | #define ONFI_FEATURE_ADDR_READ_RETRY 0x89 | |
9748e1d8 TP |
253 | #define ONFI_FEATURE_ON_DIE_ECC 0x90 |
254 | #define ONFI_FEATURE_ON_DIE_ECC_EN BIT(3) | |
8429bb39 | 255 | |
7db03ecc HS |
256 | /* ONFI subfeature parameters length */ |
257 | #define ONFI_SUBFEATURE_PARAM_LEN 4 | |
258 | ||
d914c932 DM |
259 | /* ONFI optional commands SET/GET FEATURES supported? */ |
260 | #define ONFI_OPT_CMD_SET_GET_FEATURES (1 << 2) | |
261 | ||
d1e1f4e4 FF |
262 | struct nand_onfi_params { |
263 | /* rev info and features block */ | |
b46daf7e SAS |
264 | /* 'O' 'N' 'F' 'I' */ |
265 | u8 sig[4]; | |
266 | __le16 revision; | |
267 | __le16 features; | |
268 | __le16 opt_cmd; | |
5138a98f HS |
269 | u8 reserved0[2]; |
270 | __le16 ext_param_page_length; /* since ONFI 2.1 */ | |
271 | u8 num_of_param_pages; /* since ONFI 2.1 */ | |
272 | u8 reserved1[17]; | |
d1e1f4e4 FF |
273 | |
274 | /* manufacturer information block */ | |
b46daf7e SAS |
275 | char manufacturer[12]; |
276 | char model[20]; | |
277 | u8 jedec_id; | |
278 | __le16 date_code; | |
279 | u8 reserved2[13]; | |
d1e1f4e4 FF |
280 | |
281 | /* memory organization block */ | |
b46daf7e SAS |
282 | __le32 byte_per_page; |
283 | __le16 spare_bytes_per_page; | |
284 | __le32 data_bytes_per_ppage; | |
285 | __le16 spare_bytes_per_ppage; | |
286 | __le32 pages_per_block; | |
287 | __le32 blocks_per_lun; | |
288 | u8 lun_count; | |
289 | u8 addr_cycles; | |
290 | u8 bits_per_cell; | |
291 | __le16 bb_per_lun; | |
292 | __le16 block_endurance; | |
293 | u8 guaranteed_good_blocks; | |
294 | __le16 guaranteed_block_endurance; | |
295 | u8 programs_per_page; | |
296 | u8 ppage_attr; | |
297 | u8 ecc_bits; | |
298 | u8 interleaved_bits; | |
299 | u8 interleaved_ops; | |
300 | u8 reserved3[13]; | |
d1e1f4e4 FF |
301 | |
302 | /* electrical parameter block */ | |
b46daf7e SAS |
303 | u8 io_pin_capacitance_max; |
304 | __le16 async_timing_mode; | |
305 | __le16 program_cache_timing_mode; | |
306 | __le16 t_prog; | |
307 | __le16 t_bers; | |
308 | __le16 t_r; | |
309 | __le16 t_ccs; | |
310 | __le16 src_sync_timing_mode; | |
de64aa9e | 311 | u8 src_ssync_features; |
b46daf7e SAS |
312 | __le16 clk_pin_capacitance_typ; |
313 | __le16 io_pin_capacitance_typ; | |
314 | __le16 input_pin_capacitance_typ; | |
315 | u8 input_pin_capacitance_max; | |
a55e85ce | 316 | u8 driver_strength_support; |
b46daf7e | 317 | __le16 t_int_r; |
74e98be4 | 318 | __le16 t_adl; |
de64aa9e | 319 | u8 reserved4[8]; |
d1e1f4e4 FF |
320 | |
321 | /* vendor */ | |
6f0065b0 BN |
322 | __le16 vendor_revision; |
323 | u8 vendor[88]; | |
d1e1f4e4 FF |
324 | |
325 | __le16 crc; | |
e2e6b7b7 | 326 | } __packed; |
d1e1f4e4 FF |
327 | |
328 | #define ONFI_CRC_BASE 0x4F4E | |
329 | ||
5138a98f HS |
330 | /* Extended ECC information Block Definition (since ONFI 2.1) */ |
331 | struct onfi_ext_ecc_info { | |
332 | u8 ecc_bits; | |
333 | u8 codeword_size; | |
334 | __le16 bb_per_lun; | |
335 | __le16 block_endurance; | |
336 | u8 reserved[2]; | |
337 | } __packed; | |
338 | ||
339 | #define ONFI_SECTION_TYPE_0 0 /* Unused section. */ | |
340 | #define ONFI_SECTION_TYPE_1 1 /* for additional sections. */ | |
341 | #define ONFI_SECTION_TYPE_2 2 /* for ECC information. */ | |
342 | struct onfi_ext_section { | |
343 | u8 type; | |
344 | u8 length; | |
345 | } __packed; | |
346 | ||
347 | #define ONFI_EXT_SECTION_MAX 8 | |
348 | ||
349 | /* Extended Parameter Page Definition (since ONFI 2.1) */ | |
350 | struct onfi_ext_param_page { | |
351 | __le16 crc; | |
352 | u8 sig[4]; /* 'E' 'P' 'P' 'S' */ | |
353 | u8 reserved0[10]; | |
354 | struct onfi_ext_section sections[ONFI_EXT_SECTION_MAX]; | |
355 | ||
356 | /* | |
357 | * The actual size of the Extended Parameter Page is in | |
358 | * @ext_param_page_length of nand_onfi_params{}. | |
359 | * The following are the variable length sections. | |
360 | * So we do not add any fields below. Please see the ONFI spec. | |
361 | */ | |
362 | } __packed; | |
363 | ||
afbfff03 HS |
364 | struct jedec_ecc_info { |
365 | u8 ecc_bits; | |
366 | u8 codeword_size; | |
367 | __le16 bb_per_lun; | |
368 | __le16 block_endurance; | |
369 | u8 reserved[2]; | |
370 | } __packed; | |
371 | ||
7852f896 HS |
372 | /* JEDEC features */ |
373 | #define JEDEC_FEATURE_16_BIT_BUS (1 << 0) | |
374 | ||
afbfff03 HS |
375 | struct nand_jedec_params { |
376 | /* rev info and features block */ | |
377 | /* 'J' 'E' 'S' 'D' */ | |
378 | u8 sig[4]; | |
379 | __le16 revision; | |
380 | __le16 features; | |
381 | u8 opt_cmd[3]; | |
382 | __le16 sec_cmd; | |
383 | u8 num_of_param_pages; | |
384 | u8 reserved0[18]; | |
385 | ||
386 | /* manufacturer information block */ | |
387 | char manufacturer[12]; | |
388 | char model[20]; | |
389 | u8 jedec_id[6]; | |
390 | u8 reserved1[10]; | |
391 | ||
392 | /* memory organization block */ | |
393 | __le32 byte_per_page; | |
394 | __le16 spare_bytes_per_page; | |
395 | u8 reserved2[6]; | |
396 | __le32 pages_per_block; | |
397 | __le32 blocks_per_lun; | |
398 | u8 lun_count; | |
399 | u8 addr_cycles; | |
400 | u8 bits_per_cell; | |
401 | u8 programs_per_page; | |
402 | u8 multi_plane_addr; | |
403 | u8 multi_plane_op_attr; | |
404 | u8 reserved3[38]; | |
405 | ||
406 | /* electrical parameter block */ | |
407 | __le16 async_sdr_speed_grade; | |
408 | __le16 toggle_ddr_speed_grade; | |
409 | __le16 sync_ddr_speed_grade; | |
410 | u8 async_sdr_features; | |
411 | u8 toggle_ddr_features; | |
412 | u8 sync_ddr_features; | |
413 | __le16 t_prog; | |
414 | __le16 t_bers; | |
415 | __le16 t_r; | |
416 | __le16 t_r_multi_plane; | |
417 | __le16 t_ccs; | |
418 | __le16 io_pin_capacitance_typ; | |
419 | __le16 input_pin_capacitance_typ; | |
420 | __le16 clk_pin_capacitance_typ; | |
421 | u8 driver_strength_support; | |
74e98be4 | 422 | __le16 t_adl; |
afbfff03 HS |
423 | u8 reserved4[36]; |
424 | ||
425 | /* ECC and endurance block */ | |
426 | u8 guaranteed_good_blocks; | |
427 | __le16 guaranteed_block_endurance; | |
428 | struct jedec_ecc_info ecc_info[4]; | |
429 | u8 reserved5[29]; | |
430 | ||
431 | /* reserved */ | |
432 | u8 reserved6[148]; | |
433 | ||
434 | /* vendor */ | |
435 | __le16 vendor_rev_num; | |
436 | u8 reserved7[88]; | |
437 | ||
438 | /* CRC for Parameter Page */ | |
439 | __le16 crc; | |
440 | } __packed; | |
441 | ||
7f501f0a BB |
442 | /** |
443 | * struct nand_id - NAND id structure | |
444 | * @data: buffer containing the id bytes. Currently 8 bytes large, but can | |
445 | * be extended if required. | |
446 | * @len: ID length. | |
447 | */ | |
448 | struct nand_id { | |
449 | u8 data[8]; | |
450 | int len; | |
451 | }; | |
452 | ||
1da177e4 | 453 | /** |
844d3b42 | 454 | * struct nand_hw_control - Control structure for hardware controller (e.g ECC generator) shared among independent devices |
61ecfa87 | 455 | * @lock: protection lock |
1da177e4 | 456 | * @active: the mtd device which holds the controller currently |
a0491fc4 SAS |
457 | * @wq: wait queue to sleep on if a NAND operation is in |
458 | * progress used instead of the per chip wait queue | |
459 | * when a hw controller is available. | |
1da177e4 LT |
460 | */ |
461 | struct nand_hw_control { | |
b46daf7e | 462 | spinlock_t lock; |
1da177e4 | 463 | struct nand_chip *active; |
0dfc6246 | 464 | wait_queue_head_t wq; |
1da177e4 LT |
465 | }; |
466 | ||
d45bc58d MG |
467 | static inline void nand_hw_control_init(struct nand_hw_control *nfc) |
468 | { | |
469 | nfc->active = NULL; | |
470 | spin_lock_init(&nfc->lock); | |
471 | init_waitqueue_head(&nfc->wq); | |
472 | } | |
473 | ||
2c8f8afa MY |
474 | /** |
475 | * struct nand_ecc_step_info - ECC step information of ECC engine | |
476 | * @stepsize: data bytes per ECC step | |
477 | * @strengths: array of supported strengths | |
478 | * @nstrengths: number of supported strengths | |
479 | */ | |
480 | struct nand_ecc_step_info { | |
481 | int stepsize; | |
482 | const int *strengths; | |
483 | int nstrengths; | |
484 | }; | |
485 | ||
486 | /** | |
487 | * struct nand_ecc_caps - capability of ECC engine | |
488 | * @stepinfos: array of ECC step information | |
489 | * @nstepinfos: number of ECC step information | |
490 | * @calc_ecc_bytes: driver's hook to calculate ECC bytes per step | |
491 | */ | |
492 | struct nand_ecc_caps { | |
493 | const struct nand_ecc_step_info *stepinfos; | |
494 | int nstepinfos; | |
495 | int (*calc_ecc_bytes)(int step_size, int strength); | |
496 | }; | |
497 | ||
a03c6017 MY |
498 | /* a shorthand to generate struct nand_ecc_caps with only one ECC stepsize */ |
499 | #define NAND_ECC_CAPS_SINGLE(__name, __calc, __step, ...) \ | |
500 | static const int __name##_strengths[] = { __VA_ARGS__ }; \ | |
501 | static const struct nand_ecc_step_info __name##_stepinfo = { \ | |
502 | .stepsize = __step, \ | |
503 | .strengths = __name##_strengths, \ | |
504 | .nstrengths = ARRAY_SIZE(__name##_strengths), \ | |
505 | }; \ | |
506 | static const struct nand_ecc_caps __name = { \ | |
507 | .stepinfos = &__name##_stepinfo, \ | |
508 | .nstepinfos = 1, \ | |
509 | .calc_ecc_bytes = __calc, \ | |
510 | } | |
511 | ||
6dfc6d25 | 512 | /** |
7854d3f7 BN |
513 | * struct nand_ecc_ctrl - Control structure for ECC |
514 | * @mode: ECC mode | |
b0fcd8ab | 515 | * @algo: ECC algorithm |
7854d3f7 BN |
516 | * @steps: number of ECC steps per page |
517 | * @size: data bytes per ECC step | |
518 | * @bytes: ECC bytes per step | |
1d0b95b0 | 519 | * @strength: max number of correctible bits per ECC step |
7854d3f7 BN |
520 | * @total: total number of ECC bytes per page |
521 | * @prepad: padding information for syndrome based ECC generators | |
522 | * @postpad: padding information for syndrome based ECC generators | |
40cbe6ee | 523 | * @options: ECC specific options (see NAND_ECC_XXX flags defined above) |
7854d3f7 BN |
524 | * @priv: pointer to private ECC control data |
525 | * @hwctl: function to control hardware ECC generator. Must only | |
6dfc6d25 | 526 | * be provided if an hardware ECC is available |
7854d3f7 | 527 | * @calculate: function for ECC calculation or readback from ECC hardware |
6e941192 BB |
528 | * @correct: function for ECC correction, matching to ECC generator (sw/hw). |
529 | * Should return a positive number representing the number of | |
530 | * corrected bitflips, -EBADMSG if the number of bitflips exceed | |
531 | * ECC strength, or any other error code if the error is not | |
532 | * directly related to correction. | |
533 | * If -EBADMSG is returned the input buffers should be left | |
534 | * untouched. | |
62d956dc BB |
535 | * @read_page_raw: function to read a raw page without ECC. This function |
536 | * should hide the specific layout used by the ECC | |
537 | * controller and always return contiguous in-band and | |
538 | * out-of-band data even if they're not stored | |
539 | * contiguously on the NAND chip (e.g. | |
540 | * NAND_ECC_HW_SYNDROME interleaves in-band and | |
541 | * out-of-band data). | |
542 | * @write_page_raw: function to write a raw page without ECC. This function | |
543 | * should hide the specific layout used by the ECC | |
544 | * controller and consider the passed data as contiguous | |
545 | * in-band and out-of-band data. ECC controller is | |
546 | * responsible for doing the appropriate transformations | |
547 | * to adapt to its specific layout (e.g. | |
548 | * NAND_ECC_HW_SYNDROME interleaves in-band and | |
549 | * out-of-band data). | |
7854d3f7 | 550 | * @read_page: function to read a page according to the ECC generator |
5ca7f415 | 551 | * requirements; returns maximum number of bitflips corrected in |
07604686 | 552 | * any single ECC step, -EIO hw error |
5ca7f415 MD |
553 | * @read_subpage: function to read parts of the page covered by ECC; |
554 | * returns same as read_page() | |
837a6ba4 | 555 | * @write_subpage: function to write parts of the page covered by ECC. |
7854d3f7 | 556 | * @write_page: function to write a page according to the ECC generator |
a0491fc4 | 557 | * requirements. |
9ce244b3 | 558 | * @write_oob_raw: function to write chip OOB data without ECC |
c46f6483 | 559 | * @read_oob_raw: function to read chip OOB data without ECC |
844d3b42 RD |
560 | * @read_oob: function to read chip OOB data |
561 | * @write_oob: function to write chip OOB data | |
6dfc6d25 TG |
562 | */ |
563 | struct nand_ecc_ctrl { | |
b46daf7e | 564 | nand_ecc_modes_t mode; |
b0fcd8ab | 565 | enum nand_ecc_algo algo; |
b46daf7e SAS |
566 | int steps; |
567 | int size; | |
568 | int bytes; | |
569 | int total; | |
1d0b95b0 | 570 | int strength; |
b46daf7e SAS |
571 | int prepad; |
572 | int postpad; | |
40cbe6ee | 573 | unsigned int options; |
193bd400 | 574 | void *priv; |
b46daf7e SAS |
575 | void (*hwctl)(struct mtd_info *mtd, int mode); |
576 | int (*calculate)(struct mtd_info *mtd, const uint8_t *dat, | |
577 | uint8_t *ecc_code); | |
578 | int (*correct)(struct mtd_info *mtd, uint8_t *dat, uint8_t *read_ecc, | |
579 | uint8_t *calc_ecc); | |
580 | int (*read_page_raw)(struct mtd_info *mtd, struct nand_chip *chip, | |
1fbb938d | 581 | uint8_t *buf, int oob_required, int page); |
fdbad98d | 582 | int (*write_page_raw)(struct mtd_info *mtd, struct nand_chip *chip, |
45aaeff9 | 583 | const uint8_t *buf, int oob_required, int page); |
b46daf7e | 584 | int (*read_page)(struct mtd_info *mtd, struct nand_chip *chip, |
1fbb938d | 585 | uint8_t *buf, int oob_required, int page); |
b46daf7e | 586 | int (*read_subpage)(struct mtd_info *mtd, struct nand_chip *chip, |
e004debd | 587 | uint32_t offs, uint32_t len, uint8_t *buf, int page); |
837a6ba4 GP |
588 | int (*write_subpage)(struct mtd_info *mtd, struct nand_chip *chip, |
589 | uint32_t offset, uint32_t data_len, | |
45aaeff9 | 590 | const uint8_t *data_buf, int oob_required, int page); |
fdbad98d | 591 | int (*write_page)(struct mtd_info *mtd, struct nand_chip *chip, |
45aaeff9 | 592 | const uint8_t *buf, int oob_required, int page); |
9ce244b3 BN |
593 | int (*write_oob_raw)(struct mtd_info *mtd, struct nand_chip *chip, |
594 | int page); | |
c46f6483 | 595 | int (*read_oob_raw)(struct mtd_info *mtd, struct nand_chip *chip, |
5c2ffb11 SL |
596 | int page); |
597 | int (*read_oob)(struct mtd_info *mtd, struct nand_chip *chip, int page); | |
b46daf7e SAS |
598 | int (*write_oob)(struct mtd_info *mtd, struct nand_chip *chip, |
599 | int page); | |
f75e5097 TG |
600 | }; |
601 | ||
3371d663 MG |
602 | static inline int nand_standard_page_accessors(struct nand_ecc_ctrl *ecc) |
603 | { | |
604 | return !(ecc->options & NAND_ECC_CUSTOM_PAGE_ACCESS); | |
605 | } | |
606 | ||
f75e5097 TG |
607 | /** |
608 | * struct nand_buffers - buffer structure for read/write | |
f02ea4e6 HS |
609 | * @ecccalc: buffer pointer for calculated ECC, size is oobsize. |
610 | * @ecccode: buffer pointer for ECC read from flash, size is oobsize. | |
611 | * @databuf: buffer pointer for data, size is (page size + oobsize). | |
f75e5097 TG |
612 | * |
613 | * Do not change the order of buffers. databuf and oobrbuf must be in | |
614 | * consecutive order. | |
615 | */ | |
616 | struct nand_buffers { | |
f02ea4e6 HS |
617 | uint8_t *ecccalc; |
618 | uint8_t *ecccode; | |
619 | uint8_t *databuf; | |
6dfc6d25 TG |
620 | }; |
621 | ||
eee64b70 SH |
622 | /** |
623 | * struct nand_sdr_timings - SDR NAND chip timings | |
624 | * | |
625 | * This struct defines the timing requirements of a SDR NAND chip. | |
626 | * These information can be found in every NAND datasheets and the timings | |
627 | * meaning are described in the ONFI specifications: | |
628 | * www.onfi.org/~/media/ONFI/specs/onfi_3_1_spec.pdf (chapter 4.15 Timing | |
629 | * Parameters) | |
630 | * | |
631 | * All these timings are expressed in picoseconds. | |
632 | * | |
204e7ecd BB |
633 | * @tBERS_max: Block erase time |
634 | * @tCCS_min: Change column setup time | |
635 | * @tPROG_max: Page program time | |
636 | * @tR_max: Page read time | |
eee64b70 SH |
637 | * @tALH_min: ALE hold time |
638 | * @tADL_min: ALE to data loading time | |
639 | * @tALS_min: ALE setup time | |
640 | * @tAR_min: ALE to RE# delay | |
641 | * @tCEA_max: CE# access time | |
61babe94 | 642 | * @tCEH_min: CE# high hold time |
eee64b70 SH |
643 | * @tCH_min: CE# hold time |
644 | * @tCHZ_max: CE# high to output hi-Z | |
645 | * @tCLH_min: CLE hold time | |
646 | * @tCLR_min: CLE to RE# delay | |
647 | * @tCLS_min: CLE setup time | |
648 | * @tCOH_min: CE# high to output hold | |
649 | * @tCS_min: CE# setup time | |
650 | * @tDH_min: Data hold time | |
651 | * @tDS_min: Data setup time | |
652 | * @tFEAT_max: Busy time for Set Features and Get Features | |
653 | * @tIR_min: Output hi-Z to RE# low | |
654 | * @tITC_max: Interface and Timing Mode Change time | |
655 | * @tRC_min: RE# cycle time | |
656 | * @tREA_max: RE# access time | |
657 | * @tREH_min: RE# high hold time | |
658 | * @tRHOH_min: RE# high to output hold | |
659 | * @tRHW_min: RE# high to WE# low | |
660 | * @tRHZ_max: RE# high to output hi-Z | |
661 | * @tRLOH_min: RE# low to output hold | |
662 | * @tRP_min: RE# pulse width | |
663 | * @tRR_min: Ready to RE# low (data only) | |
664 | * @tRST_max: Device reset time, measured from the falling edge of R/B# to the | |
665 | * rising edge of R/B#. | |
666 | * @tWB_max: WE# high to SR[6] low | |
667 | * @tWC_min: WE# cycle time | |
668 | * @tWH_min: WE# high hold time | |
669 | * @tWHR_min: WE# high to RE# low | |
670 | * @tWP_min: WE# pulse width | |
671 | * @tWW_min: WP# transition to WE# low | |
672 | */ | |
673 | struct nand_sdr_timings { | |
204e7ecd BB |
674 | u32 tBERS_max; |
675 | u32 tCCS_min; | |
676 | u32 tPROG_max; | |
677 | u32 tR_max; | |
eee64b70 SH |
678 | u32 tALH_min; |
679 | u32 tADL_min; | |
680 | u32 tALS_min; | |
681 | u32 tAR_min; | |
682 | u32 tCEA_max; | |
683 | u32 tCEH_min; | |
684 | u32 tCH_min; | |
685 | u32 tCHZ_max; | |
686 | u32 tCLH_min; | |
687 | u32 tCLR_min; | |
688 | u32 tCLS_min; | |
689 | u32 tCOH_min; | |
690 | u32 tCS_min; | |
691 | u32 tDH_min; | |
692 | u32 tDS_min; | |
693 | u32 tFEAT_max; | |
694 | u32 tIR_min; | |
695 | u32 tITC_max; | |
696 | u32 tRC_min; | |
697 | u32 tREA_max; | |
698 | u32 tREH_min; | |
699 | u32 tRHOH_min; | |
700 | u32 tRHW_min; | |
701 | u32 tRHZ_max; | |
702 | u32 tRLOH_min; | |
703 | u32 tRP_min; | |
704 | u32 tRR_min; | |
705 | u64 tRST_max; | |
706 | u32 tWB_max; | |
707 | u32 tWC_min; | |
708 | u32 tWH_min; | |
709 | u32 tWHR_min; | |
710 | u32 tWP_min; | |
711 | u32 tWW_min; | |
712 | }; | |
713 | ||
714 | /** | |
715 | * enum nand_data_interface_type - NAND interface timing type | |
716 | * @NAND_SDR_IFACE: Single Data Rate interface | |
717 | */ | |
718 | enum nand_data_interface_type { | |
719 | NAND_SDR_IFACE, | |
720 | }; | |
721 | ||
722 | /** | |
723 | * struct nand_data_interface - NAND interface timing | |
724 | * @type: type of the timing | |
725 | * @timings: The timing, type according to @type | |
726 | */ | |
727 | struct nand_data_interface { | |
728 | enum nand_data_interface_type type; | |
729 | union { | |
730 | struct nand_sdr_timings sdr; | |
731 | } timings; | |
732 | }; | |
733 | ||
734 | /** | |
735 | * nand_get_sdr_timings - get SDR timing from data interface | |
736 | * @conf: The data interface | |
737 | */ | |
738 | static inline const struct nand_sdr_timings * | |
739 | nand_get_sdr_timings(const struct nand_data_interface *conf) | |
740 | { | |
741 | if (conf->type != NAND_SDR_IFACE) | |
742 | return ERR_PTR(-EINVAL); | |
743 | ||
744 | return &conf->timings.sdr; | |
745 | } | |
746 | ||
abbe26d1 BB |
747 | /** |
748 | * struct nand_manufacturer_ops - NAND Manufacturer operations | |
749 | * @detect: detect the NAND memory organization and capabilities | |
750 | * @init: initialize all vendor specific fields (like the ->read_retry() | |
751 | * implementation) if any. | |
752 | * @cleanup: the ->init() function may have allocated resources, ->cleanup() | |
753 | * is here to let vendor specific code release those resources. | |
754 | */ | |
755 | struct nand_manufacturer_ops { | |
756 | void (*detect)(struct nand_chip *chip); | |
757 | int (*init)(struct nand_chip *chip); | |
758 | void (*cleanup)(struct nand_chip *chip); | |
759 | }; | |
760 | ||
1da177e4 LT |
761 | /** |
762 | * struct nand_chip - NAND Private Flash Chip Data | |
ed4f85c0 | 763 | * @mtd: MTD device registered to the MTD framework |
a0491fc4 SAS |
764 | * @IO_ADDR_R: [BOARDSPECIFIC] address to read the 8 I/O lines of the |
765 | * flash device | |
766 | * @IO_ADDR_W: [BOARDSPECIFIC] address to write the 8 I/O lines of the | |
767 | * flash device. | |
1da177e4 | 768 | * @read_byte: [REPLACEABLE] read one byte from the chip |
1da177e4 | 769 | * @read_word: [REPLACEABLE] read one word from the chip |
05f78359 UKK |
770 | * @write_byte: [REPLACEABLE] write a single byte to the chip on the |
771 | * low 8 I/O lines | |
1da177e4 LT |
772 | * @write_buf: [REPLACEABLE] write data from the buffer to the chip |
773 | * @read_buf: [REPLACEABLE] read data from the chip into the buffer | |
1da177e4 | 774 | * @select_chip: [REPLACEABLE] select chip nr |
ce157510 BN |
775 | * @block_bad: [REPLACEABLE] check if a block is bad, using OOB markers |
776 | * @block_markbad: [REPLACEABLE] mark a block bad | |
25985edc | 777 | * @cmd_ctrl: [BOARDSPECIFIC] hardwarespecific function for controlling |
7abd3ef9 | 778 | * ALE/CLE/nCE. Also used to write command and address |
7854d3f7 | 779 | * @dev_ready: [BOARDSPECIFIC] hardwarespecific function for accessing |
a0491fc4 SAS |
780 | * device ready/busy line. If set to NULL no access to |
781 | * ready/busy is available and the ready/busy information | |
782 | * is read from the chip status register. | |
783 | * @cmdfunc: [REPLACEABLE] hardwarespecific function for writing | |
784 | * commands to the chip. | |
785 | * @waitfunc: [REPLACEABLE] hardwarespecific function for wait on | |
786 | * ready. | |
ba84fb59 BN |
787 | * @setup_read_retry: [FLASHSPECIFIC] flash (vendor) specific function for |
788 | * setting the read-retry mode. Mostly needed for MLC NAND. | |
7854d3f7 | 789 | * @ecc: [BOARDSPECIFIC] ECC control structure |
844d3b42 | 790 | * @buffers: buffer structure for read/write |
477544c6 | 791 | * @buf_align: minimum buffer alignment required by a platform |
844d3b42 | 792 | * @hwcontrol: platform-specific hardware control structure |
49c50b97 | 793 | * @erase: [REPLACEABLE] erase function |
1da177e4 | 794 | * @scan_bbt: [REPLACEABLE] function to scan bad block table |
25985edc | 795 | * @chip_delay: [BOARDSPECIFIC] chip dependent delay for transferring |
a0491fc4 | 796 | * data from array to read regs (tR). |
2c0a2bed | 797 | * @state: [INTERN] the current state of the NAND device |
e9195edc BN |
798 | * @oob_poi: "poison value buffer," used for laying out OOB data |
799 | * before writing | |
a0491fc4 SAS |
800 | * @page_shift: [INTERN] number of address bits in a page (column |
801 | * address bits). | |
1da177e4 LT |
802 | * @phys_erase_shift: [INTERN] number of address bits in a physical eraseblock |
803 | * @bbt_erase_shift: [INTERN] number of address bits in a bbt entry | |
804 | * @chip_shift: [INTERN] number of address bits in one chip | |
a0491fc4 SAS |
805 | * @options: [BOARDSPECIFIC] various chip options. They can partly |
806 | * be set to inform nand_scan about special functionality. | |
807 | * See the defines for further explanation. | |
5fb1549d BN |
808 | * @bbt_options: [INTERN] bad block specific options. All options used |
809 | * here must come from bbm.h. By default, these options | |
810 | * will be copied to the appropriate nand_bbt_descr's. | |
a0491fc4 SAS |
811 | * @badblockpos: [INTERN] position of the bad block marker in the oob |
812 | * area. | |
661a0832 BN |
813 | * @badblockbits: [INTERN] minimum number of set bits in a good block's |
814 | * bad block marker position; i.e., BBM == 11110111b is | |
815 | * not bad when badblockbits == 7 | |
7db906b7 | 816 | * @bits_per_cell: [INTERN] number of bits per cell. i.e., 1 means SLC. |
4cfeca2d HS |
817 | * @ecc_strength_ds: [INTERN] ECC correctability from the datasheet. |
818 | * Minimum amount of bit errors per @ecc_step_ds guaranteed | |
819 | * to be correctable. If unknown, set to zero. | |
820 | * @ecc_step_ds: [INTERN] ECC step required by the @ecc_strength_ds, | |
b6f6c294 | 821 | * also from the datasheet. It is the recommended ECC step |
4cfeca2d | 822 | * size, if known; if unknown, set to zero. |
57a94e24 | 823 | * @onfi_timing_mode_default: [INTERN] default ONFI timing mode. This field is |
d8e725dd BB |
824 | * set to the actually used ONFI mode if the chip is |
825 | * ONFI compliant or deduced from the datasheet if | |
826 | * the NAND chip is not ONFI compliant. | |
1da177e4 LT |
827 | * @numchips: [INTERN] number of physical chips |
828 | * @chipsize: [INTERN] the size of one chip for multichip arrays | |
829 | * @pagemask: [INTERN] page number mask = number of (pages / chip) - 1 | |
a0491fc4 SAS |
830 | * @pagebuf: [INTERN] holds the pagenumber which is currently in |
831 | * data_buf. | |
edbc4540 MD |
832 | * @pagebuf_bitflips: [INTERN] holds the bitflip count for the page which is |
833 | * currently in data_buf. | |
29072b96 | 834 | * @subpagesize: [INTERN] holds the subpagesize |
7f501f0a | 835 | * @id: [INTERN] holds NAND ID |
a0491fc4 SAS |
836 | * @onfi_version: [INTERN] holds the chip ONFI version (BCD encoded), |
837 | * non 0 if ONFI supported. | |
d94abba7 HS |
838 | * @jedec_version: [INTERN] holds the chip JEDEC version (BCD encoded), |
839 | * non 0 if JEDEC supported. | |
a0491fc4 SAS |
840 | * @onfi_params: [INTERN] holds the ONFI page parameter when ONFI is |
841 | * supported, 0 otherwise. | |
d94abba7 HS |
842 | * @jedec_params: [INTERN] holds the JEDEC parameter page when JEDEC is |
843 | * supported, 0 otherwise. | |
ceb374eb ZB |
844 | * @max_bb_per_die: [INTERN] the max number of bad blocks each die of a |
845 | * this nand device will encounter their life times. | |
846 | * @blocks_per_die: [INTERN] The number of PEBs in a die | |
61babe94 | 847 | * @data_interface: [INTERN] NAND interface timing information |
ba84fb59 | 848 | * @read_retries: [INTERN] the number of read retry modes supported |
9ef525a9 RD |
849 | * @onfi_set_features: [REPLACEABLE] set the features for ONFI nand |
850 | * @onfi_get_features: [REPLACEABLE] get the features for ONFI nand | |
104e442a BB |
851 | * @setup_data_interface: [OPTIONAL] setup the data interface and timing. If |
852 | * chipnr is set to %NAND_DATA_IFACE_CHECK_ONLY this | |
853 | * means the configuration should not be applied but | |
854 | * only checked. | |
1da177e4 | 855 | * @bbt: [INTERN] bad block table pointer |
a0491fc4 SAS |
856 | * @bbt_td: [REPLACEABLE] bad block table descriptor for flash |
857 | * lookup. | |
1da177e4 | 858 | * @bbt_md: [REPLACEABLE] bad block table mirror descriptor |
a0491fc4 SAS |
859 | * @badblock_pattern: [REPLACEABLE] bad block scan pattern used for initial |
860 | * bad block scan. | |
861 | * @controller: [REPLACEABLE] a pointer to a hardware controller | |
7854d3f7 | 862 | * structure which is shared among multiple independent |
a0491fc4 | 863 | * devices. |
32c8db8f | 864 | * @priv: [OPTIONAL] pointer to private chip data |
abbe26d1 | 865 | * @manufacturer: [INTERN] Contains manufacturer information |
1da177e4 | 866 | */ |
61ecfa87 | 867 | |
1da177e4 | 868 | struct nand_chip { |
ed4f85c0 | 869 | struct mtd_info mtd; |
b46daf7e SAS |
870 | void __iomem *IO_ADDR_R; |
871 | void __iomem *IO_ADDR_W; | |
872 | ||
873 | uint8_t (*read_byte)(struct mtd_info *mtd); | |
874 | u16 (*read_word)(struct mtd_info *mtd); | |
05f78359 | 875 | void (*write_byte)(struct mtd_info *mtd, uint8_t byte); |
b46daf7e SAS |
876 | void (*write_buf)(struct mtd_info *mtd, const uint8_t *buf, int len); |
877 | void (*read_buf)(struct mtd_info *mtd, uint8_t *buf, int len); | |
b46daf7e | 878 | void (*select_chip)(struct mtd_info *mtd, int chip); |
9f3e0429 | 879 | int (*block_bad)(struct mtd_info *mtd, loff_t ofs); |
b46daf7e SAS |
880 | int (*block_markbad)(struct mtd_info *mtd, loff_t ofs); |
881 | void (*cmd_ctrl)(struct mtd_info *mtd, int dat, unsigned int ctrl); | |
b46daf7e SAS |
882 | int (*dev_ready)(struct mtd_info *mtd); |
883 | void (*cmdfunc)(struct mtd_info *mtd, unsigned command, int column, | |
884 | int page_addr); | |
885 | int(*waitfunc)(struct mtd_info *mtd, struct nand_chip *this); | |
49c50b97 | 886 | int (*erase)(struct mtd_info *mtd, int page); |
b46daf7e | 887 | int (*scan_bbt)(struct mtd_info *mtd); |
7db03ecc HS |
888 | int (*onfi_set_features)(struct mtd_info *mtd, struct nand_chip *chip, |
889 | int feature_addr, uint8_t *subfeature_para); | |
890 | int (*onfi_get_features)(struct mtd_info *mtd, struct nand_chip *chip, | |
891 | int feature_addr, uint8_t *subfeature_para); | |
ba84fb59 | 892 | int (*setup_read_retry)(struct mtd_info *mtd, int retry_mode); |
104e442a BB |
893 | int (*setup_data_interface)(struct mtd_info *mtd, int chipnr, |
894 | const struct nand_data_interface *conf); | |
d8e725dd | 895 | |
b46daf7e SAS |
896 | |
897 | int chip_delay; | |
898 | unsigned int options; | |
5fb1549d | 899 | unsigned int bbt_options; |
b46daf7e SAS |
900 | |
901 | int page_shift; | |
902 | int phys_erase_shift; | |
903 | int bbt_erase_shift; | |
904 | int chip_shift; | |
905 | int numchips; | |
906 | uint64_t chipsize; | |
907 | int pagemask; | |
908 | int pagebuf; | |
edbc4540 | 909 | unsigned int pagebuf_bitflips; |
b46daf7e | 910 | int subpagesize; |
7db906b7 | 911 | uint8_t bits_per_cell; |
4cfeca2d HS |
912 | uint16_t ecc_strength_ds; |
913 | uint16_t ecc_step_ds; | |
57a94e24 | 914 | int onfi_timing_mode_default; |
b46daf7e SAS |
915 | int badblockpos; |
916 | int badblockbits; | |
917 | ||
7f501f0a | 918 | struct nand_id id; |
b46daf7e | 919 | int onfi_version; |
d94abba7 HS |
920 | int jedec_version; |
921 | union { | |
922 | struct nand_onfi_params onfi_params; | |
923 | struct nand_jedec_params jedec_params; | |
924 | }; | |
ceb374eb ZB |
925 | u16 max_bb_per_die; |
926 | u32 blocks_per_die; | |
d1e1f4e4 | 927 | |
d8e725dd BB |
928 | struct nand_data_interface *data_interface; |
929 | ||
ba84fb59 BN |
930 | int read_retries; |
931 | ||
b46daf7e | 932 | flstate_t state; |
f75e5097 | 933 | |
b46daf7e SAS |
934 | uint8_t *oob_poi; |
935 | struct nand_hw_control *controller; | |
f75e5097 TG |
936 | |
937 | struct nand_ecc_ctrl ecc; | |
4bf63fcb | 938 | struct nand_buffers *buffers; |
477544c6 | 939 | unsigned long buf_align; |
f75e5097 TG |
940 | struct nand_hw_control hwcontrol; |
941 | ||
b46daf7e SAS |
942 | uint8_t *bbt; |
943 | struct nand_bbt_descr *bbt_td; | |
944 | struct nand_bbt_descr *bbt_md; | |
f75e5097 | 945 | |
b46daf7e | 946 | struct nand_bbt_descr *badblock_pattern; |
f75e5097 | 947 | |
b46daf7e | 948 | void *priv; |
abbe26d1 BB |
949 | |
950 | struct { | |
951 | const struct nand_manufacturer *desc; | |
952 | void *priv; | |
953 | } manufacturer; | |
1da177e4 LT |
954 | }; |
955 | ||
41b207a7 BB |
956 | extern const struct mtd_ooblayout_ops nand_ooblayout_sp_ops; |
957 | extern const struct mtd_ooblayout_ops nand_ooblayout_lp_ops; | |
958 | ||
28b8b26b BN |
959 | static inline void nand_set_flash_node(struct nand_chip *chip, |
960 | struct device_node *np) | |
961 | { | |
29574ede | 962 | mtd_set_of_node(&chip->mtd, np); |
28b8b26b BN |
963 | } |
964 | ||
965 | static inline struct device_node *nand_get_flash_node(struct nand_chip *chip) | |
966 | { | |
29574ede | 967 | return mtd_get_of_node(&chip->mtd); |
28b8b26b BN |
968 | } |
969 | ||
9eba47dd BB |
970 | static inline struct nand_chip *mtd_to_nand(struct mtd_info *mtd) |
971 | { | |
2d3b77ba | 972 | return container_of(mtd, struct nand_chip, mtd); |
9eba47dd BB |
973 | } |
974 | ||
ffd014f4 BB |
975 | static inline struct mtd_info *nand_to_mtd(struct nand_chip *chip) |
976 | { | |
977 | return &chip->mtd; | |
978 | } | |
979 | ||
d39ddbd9 BB |
980 | static inline void *nand_get_controller_data(struct nand_chip *chip) |
981 | { | |
982 | return chip->priv; | |
983 | } | |
984 | ||
985 | static inline void nand_set_controller_data(struct nand_chip *chip, void *priv) | |
986 | { | |
987 | chip->priv = priv; | |
988 | } | |
989 | ||
abbe26d1 BB |
990 | static inline void nand_set_manufacturer_data(struct nand_chip *chip, |
991 | void *priv) | |
992 | { | |
993 | chip->manufacturer.priv = priv; | |
994 | } | |
995 | ||
996 | static inline void *nand_get_manufacturer_data(struct nand_chip *chip) | |
997 | { | |
998 | return chip->manufacturer.priv; | |
999 | } | |
1000 | ||
1da177e4 LT |
1001 | /* |
1002 | * NAND Flash Manufacturer ID Codes | |
1003 | */ | |
1004 | #define NAND_MFR_TOSHIBA 0x98 | |
1c7fe6b4 | 1005 | #define NAND_MFR_ESMT 0xc8 |
1da177e4 LT |
1006 | #define NAND_MFR_SAMSUNG 0xec |
1007 | #define NAND_MFR_FUJITSU 0x04 | |
1008 | #define NAND_MFR_NATIONAL 0x8f | |
1009 | #define NAND_MFR_RENESAS 0x07 | |
1010 | #define NAND_MFR_STMICRO 0x20 | |
2c0a2bed | 1011 | #define NAND_MFR_HYNIX 0xad |
8c60e547 | 1012 | #define NAND_MFR_MICRON 0x2c |
30eb0db0 | 1013 | #define NAND_MFR_AMD 0x01 |
c1257b47 | 1014 | #define NAND_MFR_MACRONIX 0xc2 |
b1ccfab3 | 1015 | #define NAND_MFR_EON 0x92 |
3f97c6ff | 1016 | #define NAND_MFR_SANDISK 0x45 |
4968a412 | 1017 | #define NAND_MFR_INTEL 0x89 |
641519cb | 1018 | #define NAND_MFR_ATO 0x9b |
a4077ce5 | 1019 | #define NAND_MFR_WINBOND 0xef |
1da177e4 | 1020 | |
53552d22 AB |
1021 | /* The maximum expected count of bytes in the NAND ID sequence */ |
1022 | #define NAND_MAX_ID_LEN 8 | |
1023 | ||
8dbfae1e AB |
1024 | /* |
1025 | * A helper for defining older NAND chips where the second ID byte fully | |
1026 | * defined the chip, including the geometry (chip size, eraseblock size, page | |
5bfa9b71 | 1027 | * size). All these chips have 512 bytes NAND page size. |
8dbfae1e | 1028 | */ |
5bfa9b71 AB |
1029 | #define LEGACY_ID_NAND(nm, devid, chipsz, erasesz, opts) \ |
1030 | { .name = (nm), {{ .dev_id = (devid) }}, .pagesize = 512, \ | |
1031 | .chipsize = (chipsz), .erasesize = (erasesz), .options = (opts) } | |
8dbfae1e AB |
1032 | |
1033 | /* | |
1034 | * A helper for defining newer chips which report their page size and | |
1035 | * eraseblock size via the extended ID bytes. | |
1036 | * | |
1037 | * The real difference between LEGACY_ID_NAND and EXTENDED_ID_NAND is that with | |
1038 | * EXTENDED_ID_NAND, manufacturers overloaded the same device ID so that the | |
1039 | * device ID now only represented a particular total chip size (and voltage, | |
1040 | * buswidth), and the page size, eraseblock size, and OOB size could vary while | |
1041 | * using the same device ID. | |
1042 | */ | |
8e12b474 AB |
1043 | #define EXTENDED_ID_NAND(nm, devid, chipsz, opts) \ |
1044 | { .name = (nm), {{ .dev_id = (devid) }}, .chipsize = (chipsz), \ | |
8dbfae1e AB |
1045 | .options = (opts) } |
1046 | ||
2dc0bdd9 HS |
1047 | #define NAND_ECC_INFO(_strength, _step) \ |
1048 | { .strength_ds = (_strength), .step_ds = (_step) } | |
1049 | #define NAND_ECC_STRENGTH(type) ((type)->ecc.strength_ds) | |
1050 | #define NAND_ECC_STEP(type) ((type)->ecc.step_ds) | |
1051 | ||
1da177e4 LT |
1052 | /** |
1053 | * struct nand_flash_dev - NAND Flash Device ID Structure | |
68aa352d AB |
1054 | * @name: a human-readable name of the NAND chip |
1055 | * @dev_id: the device ID (the second byte of the full chip ID array) | |
8e12b474 AB |
1056 | * @mfr_id: manufecturer ID part of the full chip ID array (refers the same |
1057 | * memory address as @id[0]) | |
1058 | * @dev_id: device ID part of the full chip ID array (refers the same memory | |
1059 | * address as @id[1]) | |
1060 | * @id: full device ID array | |
68aa352d AB |
1061 | * @pagesize: size of the NAND page in bytes; if 0, then the real page size (as |
1062 | * well as the eraseblock size) is determined from the extended NAND | |
1063 | * chip ID array) | |
68aa352d | 1064 | * @chipsize: total chip size in MiB |
ecb42fea | 1065 | * @erasesize: eraseblock size in bytes (determined from the extended ID if 0) |
68aa352d | 1066 | * @options: stores various chip bit options |
f22d5f63 HS |
1067 | * @id_len: The valid length of the @id. |
1068 | * @oobsize: OOB size | |
7b7d8982 | 1069 | * @ecc: ECC correctability and step information from the datasheet. |
2dc0bdd9 HS |
1070 | * @ecc.strength_ds: The ECC correctability from the datasheet, same as the |
1071 | * @ecc_strength_ds in nand_chip{}. | |
1072 | * @ecc.step_ds: The ECC step required by the @ecc.strength_ds, same as the | |
1073 | * @ecc_step_ds in nand_chip{}, also from the datasheet. | |
1074 | * For example, the "4bit ECC for each 512Byte" can be set with | |
1075 | * NAND_ECC_INFO(4, 512). | |
57a94e24 BB |
1076 | * @onfi_timing_mode_default: the default ONFI timing mode entered after a NAND |
1077 | * reset. Should be deduced from timings described | |
1078 | * in the datasheet. | |
1079 | * | |
1da177e4 LT |
1080 | */ |
1081 | struct nand_flash_dev { | |
1082 | char *name; | |
8e12b474 AB |
1083 | union { |
1084 | struct { | |
1085 | uint8_t mfr_id; | |
1086 | uint8_t dev_id; | |
1087 | }; | |
53552d22 | 1088 | uint8_t id[NAND_MAX_ID_LEN]; |
8e12b474 | 1089 | }; |
ecb42fea AB |
1090 | unsigned int pagesize; |
1091 | unsigned int chipsize; | |
1092 | unsigned int erasesize; | |
1093 | unsigned int options; | |
f22d5f63 HS |
1094 | uint16_t id_len; |
1095 | uint16_t oobsize; | |
2dc0bdd9 HS |
1096 | struct { |
1097 | uint16_t strength_ds; | |
1098 | uint16_t step_ds; | |
1099 | } ecc; | |
57a94e24 | 1100 | int onfi_timing_mode_default; |
1da177e4 LT |
1101 | }; |
1102 | ||
1103 | /** | |
8cfb9ab6 | 1104 | * struct nand_manufacturer - NAND Flash Manufacturer structure |
1da177e4 | 1105 | * @name: Manufacturer name |
2c0a2bed | 1106 | * @id: manufacturer ID code of device. |
abbe26d1 | 1107 | * @ops: manufacturer operations |
1da177e4 | 1108 | */ |
8cfb9ab6 | 1109 | struct nand_manufacturer { |
1da177e4 | 1110 | int id; |
a0491fc4 | 1111 | char *name; |
abbe26d1 | 1112 | const struct nand_manufacturer_ops *ops; |
1da177e4 LT |
1113 | }; |
1114 | ||
bcc678c2 BB |
1115 | const struct nand_manufacturer *nand_get_manufacturer(u8 id); |
1116 | ||
1117 | static inline const char * | |
1118 | nand_manufacturer_name(const struct nand_manufacturer *manufacturer) | |
1119 | { | |
1120 | return manufacturer ? manufacturer->name : "Unknown"; | |
1121 | } | |
1122 | ||
1da177e4 | 1123 | extern struct nand_flash_dev nand_flash_ids[]; |
1da177e4 | 1124 | |
9b2d61f8 | 1125 | extern const struct nand_manufacturer_ops toshiba_nand_manuf_ops; |
c51d0ac5 | 1126 | extern const struct nand_manufacturer_ops samsung_nand_manuf_ops; |
01389b6b | 1127 | extern const struct nand_manufacturer_ops hynix_nand_manuf_ops; |
10d4e75c | 1128 | extern const struct nand_manufacturer_ops micron_nand_manuf_ops; |
229204da | 1129 | extern const struct nand_manufacturer_ops amd_nand_manuf_ops; |
3b5206f4 | 1130 | extern const struct nand_manufacturer_ops macronix_nand_manuf_ops; |
c51d0ac5 | 1131 | |
79022591 SH |
1132 | int nand_default_bbt(struct mtd_info *mtd); |
1133 | int nand_markbad_bbt(struct mtd_info *mtd, loff_t offs); | |
1134 | int nand_isreserved_bbt(struct mtd_info *mtd, loff_t offs); | |
1135 | int nand_isbad_bbt(struct mtd_info *mtd, loff_t offs, int allowbbt); | |
1136 | int nand_erase_nand(struct mtd_info *mtd, struct erase_info *instr, | |
1137 | int allowbbt); | |
1138 | int nand_do_read(struct mtd_info *mtd, loff_t from, size_t len, | |
1139 | size_t *retlen, uint8_t *buf); | |
1da177e4 | 1140 | |
41796c2e TG |
1141 | /** |
1142 | * struct platform_nand_chip - chip level device structure | |
41796c2e | 1143 | * @nr_chips: max. number of chips to scan for |
844d3b42 | 1144 | * @chip_offset: chip number offset |
8be834f7 | 1145 | * @nr_partitions: number of partitions pointed to by partitions (or zero) |
41796c2e TG |
1146 | * @partitions: mtd partition list |
1147 | * @chip_delay: R/B delay value in us | |
1148 | * @options: Option flags, e.g. 16bit buswidth | |
a40f7341 | 1149 | * @bbt_options: BBT option flags, e.g. NAND_BBT_USE_FLASH |
972edcb7 | 1150 | * @part_probe_types: NULL-terminated array of probe types |
41796c2e TG |
1151 | */ |
1152 | struct platform_nand_chip { | |
b46daf7e SAS |
1153 | int nr_chips; |
1154 | int chip_offset; | |
1155 | int nr_partitions; | |
1156 | struct mtd_partition *partitions; | |
b46daf7e SAS |
1157 | int chip_delay; |
1158 | unsigned int options; | |
a40f7341 | 1159 | unsigned int bbt_options; |
b46daf7e | 1160 | const char **part_probe_types; |
41796c2e TG |
1161 | }; |
1162 | ||
bf95efd4 HS |
1163 | /* Keep gcc happy */ |
1164 | struct platform_device; | |
1165 | ||
41796c2e TG |
1166 | /** |
1167 | * struct platform_nand_ctrl - controller level device structure | |
bf95efd4 HS |
1168 | * @probe: platform specific function to probe/setup hardware |
1169 | * @remove: platform specific function to remove/teardown hardware | |
41796c2e TG |
1170 | * @hwcontrol: platform specific hardware control structure |
1171 | * @dev_ready: platform specific function to read ready/busy pin | |
1172 | * @select_chip: platform specific chip select function | |
972edcb7 VW |
1173 | * @cmd_ctrl: platform specific function for controlling |
1174 | * ALE/CLE/nCE. Also used to write command and address | |
d6fed9e9 AC |
1175 | * @write_buf: platform specific function for write buffer |
1176 | * @read_buf: platform specific function for read buffer | |
25806d3c | 1177 | * @read_byte: platform specific function to read one byte from chip |
844d3b42 | 1178 | * @priv: private data to transport driver specific settings |
41796c2e TG |
1179 | * |
1180 | * All fields are optional and depend on the hardware driver requirements | |
1181 | */ | |
1182 | struct platform_nand_ctrl { | |
b46daf7e SAS |
1183 | int (*probe)(struct platform_device *pdev); |
1184 | void (*remove)(struct platform_device *pdev); | |
1185 | void (*hwcontrol)(struct mtd_info *mtd, int cmd); | |
1186 | int (*dev_ready)(struct mtd_info *mtd); | |
1187 | void (*select_chip)(struct mtd_info *mtd, int chip); | |
1188 | void (*cmd_ctrl)(struct mtd_info *mtd, int dat, unsigned int ctrl); | |
1189 | void (*write_buf)(struct mtd_info *mtd, const uint8_t *buf, int len); | |
1190 | void (*read_buf)(struct mtd_info *mtd, uint8_t *buf, int len); | |
b4f7aa84 | 1191 | unsigned char (*read_byte)(struct mtd_info *mtd); |
b46daf7e | 1192 | void *priv; |
41796c2e TG |
1193 | }; |
1194 | ||
972edcb7 VW |
1195 | /** |
1196 | * struct platform_nand_data - container structure for platform-specific data | |
1197 | * @chip: chip level chip structure | |
1198 | * @ctrl: controller level device structure | |
1199 | */ | |
1200 | struct platform_nand_data { | |
b46daf7e SAS |
1201 | struct platform_nand_chip chip; |
1202 | struct platform_nand_ctrl ctrl; | |
972edcb7 VW |
1203 | }; |
1204 | ||
5b40db68 HS |
1205 | /* return the supported features. */ |
1206 | static inline int onfi_feature(struct nand_chip *chip) | |
1207 | { | |
1208 | return chip->onfi_version ? le16_to_cpu(chip->onfi_params.features) : 0; | |
1209 | } | |
1210 | ||
3e70192c HS |
1211 | /* return the supported asynchronous timing mode. */ |
1212 | static inline int onfi_get_async_timing_mode(struct nand_chip *chip) | |
1213 | { | |
1214 | if (!chip->onfi_version) | |
1215 | return ONFI_TIMING_MODE_UNKNOWN; | |
1216 | return le16_to_cpu(chip->onfi_params.async_timing_mode); | |
1217 | } | |
1218 | ||
1219 | /* return the supported synchronous timing mode. */ | |
1220 | static inline int onfi_get_sync_timing_mode(struct nand_chip *chip) | |
1221 | { | |
1222 | if (!chip->onfi_version) | |
1223 | return ONFI_TIMING_MODE_UNKNOWN; | |
1224 | return le16_to_cpu(chip->onfi_params.src_sync_timing_mode); | |
1225 | } | |
1226 | ||
b88730ad SH |
1227 | int onfi_init_data_interface(struct nand_chip *chip, |
1228 | struct nand_data_interface *iface, | |
1229 | enum nand_data_interface_type type, | |
1230 | int timing_mode); | |
1231 | ||
1d0ed69d HS |
1232 | /* |
1233 | * Check if it is a SLC nand. | |
1234 | * The !nand_is_slc() can be used to check the MLC/TLC nand chips. | |
1235 | * We do not distinguish the MLC and TLC now. | |
1236 | */ | |
1237 | static inline bool nand_is_slc(struct nand_chip *chip) | |
1238 | { | |
7db906b7 | 1239 | return chip->bits_per_cell == 1; |
1d0ed69d | 1240 | } |
3dad2344 BN |
1241 | |
1242 | /** | |
1243 | * Check if the opcode's address should be sent only on the lower 8 bits | |
1244 | * @command: opcode to check | |
1245 | */ | |
1246 | static inline int nand_opcode_8bits(unsigned int command) | |
1247 | { | |
e34fcb07 DM |
1248 | switch (command) { |
1249 | case NAND_CMD_READID: | |
1250 | case NAND_CMD_PARAM: | |
1251 | case NAND_CMD_GET_FEATURES: | |
1252 | case NAND_CMD_SET_FEATURES: | |
1253 | return 1; | |
1254 | default: | |
1255 | break; | |
1256 | } | |
1257 | return 0; | |
3dad2344 BN |
1258 | } |
1259 | ||
7852f896 HS |
1260 | /* return the supported JEDEC features. */ |
1261 | static inline int jedec_feature(struct nand_chip *chip) | |
1262 | { | |
1263 | return chip->jedec_version ? le16_to_cpu(chip->jedec_params.features) | |
1264 | : 0; | |
1265 | } | |
bb5fd0b6 | 1266 | |
974647ea BB |
1267 | /* get timing characteristics from ONFI timing mode. */ |
1268 | const struct nand_sdr_timings *onfi_async_timing_mode_to_sdr_timings(int mode); | |
6e1f9708 SH |
1269 | /* get data interface from ONFI timing mode 0, used after reset. */ |
1270 | const struct nand_data_interface *nand_get_default_data_interface(void); | |
730a43fb BB |
1271 | |
1272 | int nand_check_erased_ecc_chunk(void *data, int datalen, | |
1273 | void *ecc, int ecclen, | |
1274 | void *extraoob, int extraooblen, | |
1275 | int threshold); | |
9d02fc2a | 1276 | |
2c8f8afa MY |
1277 | int nand_check_ecc_caps(struct nand_chip *chip, |
1278 | const struct nand_ecc_caps *caps, int oobavail); | |
1279 | ||
1280 | int nand_match_ecc_req(struct nand_chip *chip, | |
1281 | const struct nand_ecc_caps *caps, int oobavail); | |
1282 | ||
1283 | int nand_maximize_ecc(struct nand_chip *chip, | |
1284 | const struct nand_ecc_caps *caps, int oobavail); | |
1285 | ||
9d02fc2a BB |
1286 | /* Default write_oob implementation */ |
1287 | int nand_write_oob_std(struct mtd_info *mtd, struct nand_chip *chip, int page); | |
1288 | ||
1289 | /* Default write_oob syndrome implementation */ | |
1290 | int nand_write_oob_syndrome(struct mtd_info *mtd, struct nand_chip *chip, | |
1291 | int page); | |
1292 | ||
1293 | /* Default read_oob implementation */ | |
1294 | int nand_read_oob_std(struct mtd_info *mtd, struct nand_chip *chip, int page); | |
1295 | ||
1296 | /* Default read_oob syndrome implementation */ | |
1297 | int nand_read_oob_syndrome(struct mtd_info *mtd, struct nand_chip *chip, | |
1298 | int page); | |
2f94abfe | 1299 | |
4a78cc64 BB |
1300 | /* Stub used by drivers that do not support GET/SET FEATURES operations */ |
1301 | int nand_onfi_get_set_features_notsupp(struct mtd_info *mtd, | |
1302 | struct nand_chip *chip, int addr, | |
1303 | u8 *subfeature_param); | |
1304 | ||
cc0f51ec TP |
1305 | /* Default read_page_raw implementation */ |
1306 | int nand_read_page_raw(struct mtd_info *mtd, struct nand_chip *chip, | |
1307 | uint8_t *buf, int oob_required, int page); | |
1308 | ||
1309 | /* Default write_page_raw implementation */ | |
1310 | int nand_write_page_raw(struct mtd_info *mtd, struct nand_chip *chip, | |
1311 | const uint8_t *buf, int oob_required, int page); | |
1312 | ||
2f94abfe | 1313 | /* Reset and initialize a NAND device */ |
73f907fd | 1314 | int nand_reset(struct nand_chip *chip, int chipnr); |
2f94abfe | 1315 | |
d44154f9 RW |
1316 | /* Free resources held by the NAND device */ |
1317 | void nand_cleanup(struct nand_chip *chip); | |
1318 | ||
abbe26d1 BB |
1319 | /* Default extended ID decoding function */ |
1320 | void nand_decode_ext_id(struct nand_chip *chip); | |
1da177e4 | 1321 | #endif /* __LINUX_MTD_NAND_H */ |