[mirror_ubuntu-bionic-kernel.git] / include / linux / mtd / spi-nor.h

/*
 * Copyright (C) 2014 Freescale Semiconductor, Inc.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 */

#ifndef __LINUX_MTD_SPI_NOR_H
#define __LINUX_MTD_SPI_NOR_H

#include <linux/bitops.h>
#include <linux/mtd/cfi.h>
#include <linux/mtd/mtd.h>

/*
 * Manufacturer IDs
 *
 * The first byte returned from the flash after sending opcode SPINOR_OP_RDID.
 * Sometimes these are the same as CFI IDs, but sometimes they aren't.
 */
#define SNOR_MFR_ATMEL		CFI_MFR_ATMEL
#define SNOR_MFR_GIGADEVICE	0xc8
#define SNOR_MFR_INTEL		CFI_MFR_INTEL
#define SNOR_MFR_MICRON		CFI_MFR_ST /* ST Micro <--> Micron */
#define SNOR_MFR_MACRONIX	CFI_MFR_MACRONIX
#define SNOR_MFR_SPANSION	CFI_MFR_AMD
#define SNOR_MFR_SST		CFI_MFR_SST
#define SNOR_MFR_WINBOND	0xef /* Also used by some Spansion */

/*
 * Note on opcode nomenclature: some opcodes have a format like
 * SPINOR_OP_FUNCTION{4,}_x_y_z. The numbers x, y, and z stand for the number
 * of I/O lines used for the opcode, address, and data (respectively). The
 * FUNCTION has an optional suffix of '4', to represent an opcode which
 * requires a 4-byte (32-bit) address.
 */

/* Flash opcodes. */
#define SPINOR_OP_WREN		0x06	/* Write enable */
#define SPINOR_OP_RDSR		0x05	/* Read status register */
#define SPINOR_OP_WRSR		0x01	/* Write status register 1 byte */
#define SPINOR_OP_RDSR2		0x3f	/* Read status register 2 */
#define SPINOR_OP_WRSR2		0x3e	/* Write status register 2 */
#define SPINOR_OP_READ		0x03	/* Read data bytes (low frequency) */
#define SPINOR_OP_READ_FAST	0x0b	/* Read data bytes (high frequency) */
#define SPINOR_OP_READ_1_1_2	0x3b	/* Read data bytes (Dual Output SPI) */
#define SPINOR_OP_READ_1_2_2	0xbb	/* Read data bytes (Dual I/O SPI) */
#define SPINOR_OP_READ_1_1_4	0x6b	/* Read data bytes (Quad Output SPI) */
#define SPINOR_OP_READ_1_4_4	0xeb	/* Read data bytes (Quad I/O SPI) */
#define SPINOR_OP_PP		0x02	/* Page program (up to 256 bytes) */
#define SPINOR_OP_PP_1_1_4	0x32	/* Quad page program */
#define SPINOR_OP_PP_1_4_4	0x38	/* Quad page program */
#define SPINOR_OP_BE_4K		0x20	/* Erase 4KiB block */
#define SPINOR_OP_BE_4K_PMC	0xd7	/* Erase 4KiB block on PMC chips */
#define SPINOR_OP_BE_32K	0x52	/* Erase 32KiB block */
#define SPINOR_OP_CHIP_ERASE	0xc7	/* Erase whole flash chip */
#define SPINOR_OP_SE		0xd8	/* Sector erase (usually 64KiB) */
#define SPINOR_OP_RDID		0x9f	/* Read JEDEC ID */
#define SPINOR_OP_RDSFDP	0x5a	/* Read SFDP */
#define SPINOR_OP_RDCR		0x35	/* Read configuration register */
#define SPINOR_OP_RDFSR		0x70	/* Read flag status register */

/* 4-byte address opcodes - used on Spansion and some Macronix flashes. */
#define SPINOR_OP_READ_4B	0x13	/* Read data bytes (low frequency) */
#define SPINOR_OP_READ_FAST_4B	0x0c	/* Read data bytes (high frequency) */
#define SPINOR_OP_READ_1_1_2_4B	0x3c	/* Read data bytes (Dual Output SPI) */
#define SPINOR_OP_READ_1_2_2_4B	0xbc	/* Read data bytes (Dual I/O SPI) */
#define SPINOR_OP_READ_1_1_4_4B	0x6c	/* Read data bytes (Quad Output SPI) */
#define SPINOR_OP_READ_1_4_4_4B	0xec	/* Read data bytes (Quad I/O SPI) */
#define SPINOR_OP_PP_4B		0x12	/* Page program (up to 256 bytes) */
#define SPINOR_OP_PP_1_1_4_4B	0x34	/* Quad page program */
#define SPINOR_OP_PP_1_4_4_4B	0x3e	/* Quad page program */
#define SPINOR_OP_BE_4K_4B	0x21	/* Erase 4KiB block */
#define SPINOR_OP_BE_32K_4B	0x5c	/* Erase 32KiB block */
#define SPINOR_OP_SE_4B		0xdc	/* Sector erase (usually 64KiB) */

/* Double Transfer Rate opcodes - defined in JEDEC JESD216B. */
#define SPINOR_OP_READ_1_1_1_DTR	0x0d
#define SPINOR_OP_READ_1_2_2_DTR	0xbd
#define SPINOR_OP_READ_1_4_4_DTR	0xed

#define SPINOR_OP_READ_1_1_1_DTR_4B	0x0e
#define SPINOR_OP_READ_1_2_2_DTR_4B	0xbe
#define SPINOR_OP_READ_1_4_4_DTR_4B	0xee

/* Used for SST flashes only. */
#define SPINOR_OP_BP		0x02	/* Byte program */
#define SPINOR_OP_WRDI		0x04	/* Write disable */
#define SPINOR_OP_AAI_WP	0xad	/* Auto address increment word program */

/* Used for S3AN flashes only */
#define SPINOR_OP_XSE		0x50	/* Sector erase */
#define SPINOR_OP_XPP		0x82	/* Page program */
#define SPINOR_OP_XRDSR		0xd7	/* Read status register */

#define XSR_PAGESIZE		BIT(0)	/* Page size in Po2 or Linear */
#define XSR_RDY			BIT(7)	/* Ready */


/* Used for Macronix and Winbond flashes. */
#define SPINOR_OP_EN4B		0xb7	/* Enter 4-byte mode */
#define SPINOR_OP_EX4B		0xe9	/* Exit 4-byte mode */

/* Used for Spansion flashes only. */
#define SPINOR_OP_BRWR		0x17	/* Bank register write */
#define SPINOR_OP_CLSR		0x30	/* Clear status register 1 */

/* Used for Micron flashes only. */
#define SPINOR_OP_RD_EVCR      0x65    /* Read EVCR register */
#define SPINOR_OP_WD_EVCR      0x61    /* Write EVCR register */

/* Status Register bits. */
#define SR_WIP			BIT(0)	/* Write in progress */
#define SR_WEL			BIT(1)	/* Write enable latch */
/* meaning of other SR_* bits may differ between vendors */
#define SR_BP0			BIT(2)	/* Block protect 0 */
#define SR_BP1			BIT(3)	/* Block protect 1 */
#define SR_BP2			BIT(4)	/* Block protect 2 */
#define SR_TB			BIT(5)	/* Top/Bottom protect */
#define SR_SRWD			BIT(7)	/* SR write protect */
/* Spansion/Cypress specific status bits */
#define SR_E_ERR		BIT(5)
#define SR_P_ERR		BIT(6)

#define SR_QUAD_EN_MX		BIT(6)	/* Macronix Quad I/O */

/* Enhanced Volatile Configuration Register bits */
#define EVCR_QUAD_EN_MICRON	BIT(7)	/* Micron Quad I/O */

/* Flag Status Register bits */
#define FSR_READY		BIT(7)

/* Configuration Register bits. */
#define CR_QUAD_EN_SPAN		BIT(1)	/* Spansion Quad I/O */

/* Status Register 2 bits. */
#define SR2_QUAD_EN_BIT7	BIT(7)

/* Supported SPI protocols */
#define SNOR_PROTO_INST_MASK	GENMASK(23, 16)
#define SNOR_PROTO_INST_SHIFT	16
#define SNOR_PROTO_INST(_nbits)	\
	((((unsigned long)(_nbits)) << SNOR_PROTO_INST_SHIFT) & \
	 SNOR_PROTO_INST_MASK)

#define SNOR_PROTO_ADDR_MASK	GENMASK(15, 8)
#define SNOR_PROTO_ADDR_SHIFT	8
#define SNOR_PROTO_ADDR(_nbits)	\
	((((unsigned long)(_nbits)) << SNOR_PROTO_ADDR_SHIFT) & \
	 SNOR_PROTO_ADDR_MASK)

#define SNOR_PROTO_DATA_MASK	GENMASK(7, 0)
#define SNOR_PROTO_DATA_SHIFT	0
#define SNOR_PROTO_DATA(_nbits)	\
	((((unsigned long)(_nbits)) << SNOR_PROTO_DATA_SHIFT) & \
	 SNOR_PROTO_DATA_MASK)

#define SNOR_PROTO_IS_DTR	BIT(24)	/* Double Transfer Rate */

#define SNOR_PROTO_STR(_inst_nbits, _addr_nbits, _data_nbits)	\
	(SNOR_PROTO_INST(_inst_nbits) |				\
	 SNOR_PROTO_ADDR(_addr_nbits) |				\
	 SNOR_PROTO_DATA(_data_nbits))
#define SNOR_PROTO_DTR(_inst_nbits, _addr_nbits, _data_nbits)	\
	(SNOR_PROTO_IS_DTR |					\
	 SNOR_PROTO_STR(_inst_nbits, _addr_nbits, _data_nbits))

enum spi_nor_protocol {
	SNOR_PROTO_1_1_1 = SNOR_PROTO_STR(1, 1, 1),
	SNOR_PROTO_1_1_2 = SNOR_PROTO_STR(1, 1, 2),
	SNOR_PROTO_1_1_4 = SNOR_PROTO_STR(1, 1, 4),
	SNOR_PROTO_1_1_8 = SNOR_PROTO_STR(1, 1, 8),
	SNOR_PROTO_1_2_2 = SNOR_PROTO_STR(1, 2, 2),
	SNOR_PROTO_1_4_4 = SNOR_PROTO_STR(1, 4, 4),
	SNOR_PROTO_1_8_8 = SNOR_PROTO_STR(1, 8, 8),
	SNOR_PROTO_2_2_2 = SNOR_PROTO_STR(2, 2, 2),
	SNOR_PROTO_4_4_4 = SNOR_PROTO_STR(4, 4, 4),
	SNOR_PROTO_8_8_8 = SNOR_PROTO_STR(8, 8, 8),

	SNOR_PROTO_1_1_1_DTR = SNOR_PROTO_DTR(1, 1, 1),
	SNOR_PROTO_1_2_2_DTR = SNOR_PROTO_DTR(1, 2, 2),
	SNOR_PROTO_1_4_4_DTR = SNOR_PROTO_DTR(1, 4, 4),
	SNOR_PROTO_1_8_8_DTR = SNOR_PROTO_DTR(1, 8, 8),
};

static inline bool spi_nor_protocol_is_dtr(enum spi_nor_protocol proto)
{
	return !!(proto & SNOR_PROTO_IS_DTR);
}

static inline u8 spi_nor_get_protocol_inst_nbits(enum spi_nor_protocol proto)
{
	return ((unsigned long)(proto & SNOR_PROTO_INST_MASK)) >>
		SNOR_PROTO_INST_SHIFT;
}

static inline u8 spi_nor_get_protocol_addr_nbits(enum spi_nor_protocol proto)
{
	return ((unsigned long)(proto & SNOR_PROTO_ADDR_MASK)) >>
		SNOR_PROTO_ADDR_SHIFT;
}

static inline u8 spi_nor_get_protocol_data_nbits(enum spi_nor_protocol proto)
{
	return ((unsigned long)(proto & SNOR_PROTO_DATA_MASK)) >>
		SNOR_PROTO_DATA_SHIFT;
}

static inline u8 spi_nor_get_protocol_width(enum spi_nor_protocol proto)
{
	return spi_nor_get_protocol_data_nbits(proto);
}

#define SPI_NOR_MAX_CMD_SIZE	8
enum spi_nor_ops {
	SPI_NOR_OPS_READ = 0,
	SPI_NOR_OPS_WRITE,
	SPI_NOR_OPS_ERASE,
	SPI_NOR_OPS_LOCK,
	SPI_NOR_OPS_UNLOCK,
};

enum spi_nor_option_flags {
	SNOR_F_USE_FSR		= BIT(0),
	SNOR_F_HAS_SR_TB	= BIT(1),
	SNOR_F_NO_OP_CHIP_ERASE	= BIT(2),
	SNOR_F_S3AN_ADDR_DEFAULT = BIT(3),
	SNOR_F_READY_XSR_RDY	= BIT(4),
	SNOR_F_USE_CLSR		= BIT(5),
};

/**
 * struct spi_nor - Structure for defining a the SPI NOR layer
 * @mtd:		point to a mtd_info structure
 * @lock:		the lock for the read/write/erase/lock/unlock operations
 * @dev:		point to a spi device, or a spi nor controller device.
 * @page_size:		the page size of the SPI NOR
 * @addr_width:		number of address bytes
 * @erase_opcode:	the opcode for erasing a sector
 * @read_opcode:	the read opcode
 * @read_dummy:		the dummy needed by the read operation
 * @program_opcode:	the program opcode
 * @sst_write_second:	used by the SST write operation
 * @flags:		flag options for the current SPI-NOR (SNOR_F_*)
 * @read_proto:		the SPI protocol for read operations
 * @write_proto:	the SPI protocol for write operations
 * @reg_proto		the SPI protocol for read_reg/write_reg/erase operations
 * @cmd_buf:		used by the write_reg
 * @prepare:		[OPTIONAL] do some preparations for the
 *			read/write/erase/lock/unlock operations
 * @unprepare:		[OPTIONAL] do some post work after the
 *			read/write/erase/lock/unlock operations
 * @read_reg:		[DRIVER-SPECIFIC] read out the register
 * @write_reg:		[DRIVER-SPECIFIC] write data to the register
 * @read:		[DRIVER-SPECIFIC] read data from the SPI NOR
 * @write:		[DRIVER-SPECIFIC] write data to the SPI NOR
 * @erase:		[DRIVER-SPECIFIC] erase a sector of the SPI NOR
 *			at the offset @offs; if not provided by the driver,
 *			spi-nor will send the erase opcode via write_reg()
 * @flash_lock:		[FLASH-SPECIFIC] lock a region of the SPI NOR
 * @flash_unlock:	[FLASH-SPECIFIC] unlock a region of the SPI NOR
 * @flash_is_locked:	[FLASH-SPECIFIC] check if a region of the SPI NOR is
 *			completely locked
 * @priv:		the private data
 */
struct spi_nor {
	struct mtd_info		mtd;
	struct mutex		lock;
	struct device		*dev;
	u32			page_size;
	u8			addr_width;
	u8			erase_opcode;
	u8			read_opcode;
	u8			read_dummy;
	u8			program_opcode;
	enum spi_nor_protocol	read_proto;
	enum spi_nor_protocol	write_proto;
	enum spi_nor_protocol	reg_proto;
	bool			sst_write_second;
	u32			flags;
	u8			cmd_buf[SPI_NOR_MAX_CMD_SIZE];

	int (*prepare)(struct spi_nor *nor, enum spi_nor_ops ops);
	void (*unprepare)(struct spi_nor *nor, enum spi_nor_ops ops);
	int (*read_reg)(struct spi_nor *nor, u8 opcode, u8 *buf, int len);
	int (*write_reg)(struct spi_nor *nor, u8 opcode, u8 *buf, int len);

	ssize_t (*read)(struct spi_nor *nor, loff_t from,
			size_t len, u_char *read_buf);
	ssize_t (*write)(struct spi_nor *nor, loff_t to,
			size_t len, const u_char *write_buf);
	int (*erase)(struct spi_nor *nor, loff_t offs);

	int (*flash_lock)(struct spi_nor *nor, loff_t ofs, uint64_t len);
	int (*flash_unlock)(struct spi_nor *nor, loff_t ofs, uint64_t len);
	int (*flash_is_locked)(struct spi_nor *nor, loff_t ofs, uint64_t len);

	void *priv;
};

static inline void spi_nor_set_flash_node(struct spi_nor *nor,
					  struct device_node *np)
{
	mtd_set_of_node(&nor->mtd, np);
}

static inline struct device_node *spi_nor_get_flash_node(struct spi_nor *nor)
{
	return mtd_get_of_node(&nor->mtd);
}

/**
 * struct spi_nor_hwcaps - Structure for describing the hardware capabilies
 * supported by the SPI controller (bus master).
 * @mask:		the bitmask listing all the supported hw capabilies
 */
struct spi_nor_hwcaps {
	u32	mask;
};

/*
 *(Fast) Read capabilities.
 * MUST be ordered by priority: the higher bit position, the higher priority.
 * As a matter of performances, it is relevant to use Octo SPI protocols first,
 * then Quad SPI protocols before Dual SPI protocols, Fast Read and lastly
 * (Slow) Read.
 */
#define SNOR_HWCAPS_READ_MASK		GENMASK(14, 0)
#define SNOR_HWCAPS_READ		BIT(0)
#define SNOR_HWCAPS_READ_FAST		BIT(1)
#define SNOR_HWCAPS_READ_1_1_1_DTR	BIT(2)

#define SNOR_HWCAPS_READ_DUAL		GENMASK(6, 3)
#define SNOR_HWCAPS_READ_1_1_2		BIT(3)
#define SNOR_HWCAPS_READ_1_2_2		BIT(4)
#define SNOR_HWCAPS_READ_2_2_2		BIT(5)
#define SNOR_HWCAPS_READ_1_2_2_DTR	BIT(6)

#define SNOR_HWCAPS_READ_QUAD		GENMASK(10, 7)
#define SNOR_HWCAPS_READ_1_1_4		BIT(7)
#define SNOR_HWCAPS_READ_1_4_4		BIT(8)
#define SNOR_HWCAPS_READ_4_4_4		BIT(9)
#define SNOR_HWCAPS_READ_1_4_4_DTR	BIT(10)

#define SNOR_HWCPAS_READ_OCTO		GENMASK(14, 11)
#define SNOR_HWCAPS_READ_1_1_8		BIT(11)
#define SNOR_HWCAPS_READ_1_8_8		BIT(12)
#define SNOR_HWCAPS_READ_8_8_8		BIT(13)
#define SNOR_HWCAPS_READ_1_8_8_DTR	BIT(14)

/*
 * Page Program capabilities.
 * MUST be ordered by priority: the higher bit position, the higher priority.
 * Like (Fast) Read capabilities, Octo/Quad SPI protocols are preferred to the
 * legacy SPI 1-1-1 protocol.
 * Note that Dual Page Programs are not supported because there is no existing
 * JEDEC/SFDP standard to define them. Also at this moment no SPI flash memory
 * implements such commands.
 */
#define SNOR_HWCAPS_PP_MASK	GENMASK(22, 16)
#define SNOR_HWCAPS_PP		BIT(16)

#define SNOR_HWCAPS_PP_QUAD	GENMASK(19, 17)
#define SNOR_HWCAPS_PP_1_1_4	BIT(17)
#define SNOR_HWCAPS_PP_1_4_4	BIT(18)
#define SNOR_HWCAPS_PP_4_4_4	BIT(19)

#define SNOR_HWCAPS_PP_OCTO	GENMASK(22, 20)
#define SNOR_HWCAPS_PP_1_1_8	BIT(20)
#define SNOR_HWCAPS_PP_1_8_8	BIT(21)
#define SNOR_HWCAPS_PP_8_8_8	BIT(22)

/**
 * spi_nor_scan() - scan the SPI NOR
 * @nor:	the spi_nor structure
 * @name:	the chip type name
 * @hwcaps:	the hardware capabilities supported by the controller driver
 *
 * The drivers can use this fuction to scan the SPI NOR.
 * In the scanning, it will try to get all the necessary information to
 * fill the mtd_info{} and the spi_nor{}.
 *
 * The chip type name can be provided through the @name parameter.
 *
 * Return: 0 for success, others for failure.
 */
int spi_nor_scan(struct spi_nor *nor, const char *name,
		 const struct spi_nor_hwcaps *hwcaps);

#endif
Commit	Line	Data
8eabdd1e HS	1	/*
	2	* Copyright (C) 2014 Freescale Semiconductor, Inc.
	3	*
	4	* This program is free software; you can redistribute it and/or modify
	5	* it under the terms of the GNU General Public License as published by
	6	* the Free Software Foundation; either version 2 of the License, or
	7	* (at your option) any later version.
	8	*/
	9
f39d2fa0 HS	10	#ifndef __LINUX_MTD_SPI_NOR_H
	11	#define __LINUX_MTD_SPI_NOR_H
	12
801cf21b	13	#include <linux/bitops.h>
db4745ed	14	#include <linux/mtd/cfi.h>
2c81de77	15	#include <linux/mtd/mtd.h>
db4745ed BN	16
	17	/*
	18	* Manufacturer IDs
	19	*
	20	* The first byte returned from the flash after sending opcode SPINOR_OP_RDID.
	21	* Sometimes these are the same as CFI IDs, but sometimes they aren't.
	22	*/
	23	#define SNOR_MFR_ATMEL CFI_MFR_ATMEL
e5366a26	24	#define SNOR_MFR_GIGADEVICE 0xc8
db4745ed BN	25	#define SNOR_MFR_INTEL CFI_MFR_INTEL
	26	#define SNOR_MFR_MICRON CFI_MFR_ST /* ST Micro <--> Micron */
	27	#define SNOR_MFR_MACRONIX CFI_MFR_MACRONIX
	28	#define SNOR_MFR_SPANSION CFI_MFR_AMD
	29	#define SNOR_MFR_SST CFI_MFR_SST
67b9bcd3	30	#define SNOR_MFR_WINBOND 0xef /* Also used by some Spansion */
801cf21b	31
58b89a1f BN	32	/*
	33	* Note on opcode nomenclature: some opcodes have a format like
	34	* SPINOR_OP_FUNCTION{4,}_x_y_z. The numbers x, y, and z stand for the number
	35	* of I/O lines used for the opcode, address, and data (respectively). The
	36	* FUNCTION has an optional suffix of '4', to represent an opcode which
	37	* requires a 4-byte (32-bit) address.
	38	*/
	39
f39d2fa0	40	/* Flash opcodes. */
b02e7f3e BN	41	#define SPINOR_OP_WREN 0x06 /* Write enable */
	42	#define SPINOR_OP_RDSR 0x05 /* Read status register */
	43	#define SPINOR_OP_WRSR 0x01 /* Write status register 1 byte */
f384b352 CP	44	#define SPINOR_OP_RDSR2 0x3f /* Read status register 2 */
f384b352 CP	45	#define SPINOR_OP_WRSR2 0x3e /* Write status register 2 */
58b89a1f BN	46	#define SPINOR_OP_READ 0x03 /* Read data bytes (low frequency) */
58b89a1f BN	47	#define SPINOR_OP_READ_FAST 0x0b /* Read data bytes (high frequency) */
902cc69a CP	48	#define SPINOR_OP_READ_1_1_2 0x3b /* Read data bytes (Dual Output SPI) */
	49	#define SPINOR_OP_READ_1_2_2 0xbb /* Read data bytes (Dual I/O SPI) */
	50	#define SPINOR_OP_READ_1_1_4 0x6b /* Read data bytes (Quad Output SPI) */
	51	#define SPINOR_OP_READ_1_4_4 0xeb /* Read data bytes (Quad I/O SPI) */
b02e7f3e	52	#define SPINOR_OP_PP 0x02 /* Page program (up to 256 bytes) */
902cc69a CP	53	#define SPINOR_OP_PP_1_1_4 0x32 /* Quad page program */
902cc69a CP	54	#define SPINOR_OP_PP_1_4_4 0x38 /* Quad page program */
b02e7f3e BN	55	#define SPINOR_OP_BE_4K 0x20 /* Erase 4KiB block */
	56	#define SPINOR_OP_BE_4K_PMC 0xd7 /* Erase 4KiB block on PMC chips */
	57	#define SPINOR_OP_BE_32K 0x52 /* Erase 32KiB block */
	58	#define SPINOR_OP_CHIP_ERASE 0xc7 /* Erase whole flash chip */
	59	#define SPINOR_OP_SE 0xd8 /* Sector erase (usually 64KiB) */
	60	#define SPINOR_OP_RDID 0x9f /* Read JEDEC ID */
f384b352	61	#define SPINOR_OP_RDSFDP 0x5a /* Read SFDP */
b02e7f3e	62	#define SPINOR_OP_RDCR 0x35 /* Read configuration register */
c14dedde	63	#define SPINOR_OP_RDFSR 0x70 /* Read flag status register */
f39d2fa0 HS	64
f39d2fa0 HS	65	/* 4-byte address opcodes - used on Spansion and some Macronix flashes. */
902cc69a CP	66	#define SPINOR_OP_READ_4B 0x13 /* Read data bytes (low frequency) */
	67	#define SPINOR_OP_READ_FAST_4B 0x0c /* Read data bytes (high frequency) */
	68	#define SPINOR_OP_READ_1_1_2_4B 0x3c /* Read data bytes (Dual Output SPI) */
	69	#define SPINOR_OP_READ_1_2_2_4B 0xbc /* Read data bytes (Dual I/O SPI) */
	70	#define SPINOR_OP_READ_1_1_4_4B 0x6c /* Read data bytes (Quad Output SPI) */
	71	#define SPINOR_OP_READ_1_4_4_4B 0xec /* Read data bytes (Quad I/O SPI) */
b02e7f3e	72	#define SPINOR_OP_PP_4B 0x12 /* Page program (up to 256 bytes) */
902cc69a CP	73	#define SPINOR_OP_PP_1_1_4_4B 0x34 /* Quad page program */
	74	#define SPINOR_OP_PP_1_4_4_4B 0x3e /* Quad page program */
	75	#define SPINOR_OP_BE_4K_4B 0x21 /* Erase 4KiB block */
	76	#define SPINOR_OP_BE_32K_4B 0x5c /* Erase 32KiB block */
b02e7f3e	77	#define SPINOR_OP_SE_4B 0xdc /* Sector erase (usually 64KiB) */
f39d2fa0	78
15f55331 CP	79	/* Double Transfer Rate opcodes - defined in JEDEC JESD216B. */
	80	#define SPINOR_OP_READ_1_1_1_DTR 0x0d
	81	#define SPINOR_OP_READ_1_2_2_DTR 0xbd
	82	#define SPINOR_OP_READ_1_4_4_DTR 0xed
	83
	84	#define SPINOR_OP_READ_1_1_1_DTR_4B 0x0e
	85	#define SPINOR_OP_READ_1_2_2_DTR_4B 0xbe
	86	#define SPINOR_OP_READ_1_4_4_DTR_4B 0xee
	87
f39d2fa0	88	/* Used for SST flashes only. */
b02e7f3e BN	89	#define SPINOR_OP_BP 0x02 /* Byte program */
	90	#define SPINOR_OP_WRDI 0x04 /* Write disable */
	91	#define SPINOR_OP_AAI_WP 0xad /* Auto address increment word program */
f39d2fa0	92
e99ca98f RRD	93	/* Used for S3AN flashes only */
	94	#define SPINOR_OP_XSE 0x50 /* Sector erase */
	95	#define SPINOR_OP_XPP 0x82 /* Page program */
	96	#define SPINOR_OP_XRDSR 0xd7 /* Read status register */
	97
	98	#define XSR_PAGESIZE BIT(0) /* Page size in Po2 or Linear */
	99	#define XSR_RDY BIT(7) /* Ready */
	100
	101
f39d2fa0	102	/* Used for Macronix and Winbond flashes. */
b02e7f3e BN	103	#define SPINOR_OP_EN4B 0xb7 /* Enter 4-byte mode */
b02e7f3e BN	104	#define SPINOR_OP_EX4B 0xe9 /* Exit 4-byte mode */
f39d2fa0 HS	105
f39d2fa0 HS	106	/* Used for Spansion flashes only. */
b02e7f3e	107	#define SPINOR_OP_BRWR 0x17 /* Bank register write */
c4b3eacc	108	#define SPINOR_OP_CLSR 0x30 /* Clear status register 1 */
f39d2fa0	109
548cd3ab BH	110	/* Used for Micron flashes only. */
	111	#define SPINOR_OP_RD_EVCR 0x65 /* Read EVCR register */
	112	#define SPINOR_OP_WD_EVCR 0x61 /* Write EVCR register */
	113
f39d2fa0	114	/* Status Register bits. */
a8a16454 BN	115	#define SR_WIP BIT(0) /* Write in progress */
a8a16454 BN	116	#define SR_WEL BIT(1) /* Write enable latch */
f39d2fa0	117	/* meaning of other SR_* bits may differ between vendors */
a8a16454 BN	118	#define SR_BP0 BIT(2) /* Block protect 0 */
	119	#define SR_BP1 BIT(3) /* Block protect 1 */
	120	#define SR_BP2 BIT(4) /* Block protect 2 */
3dd8012a	121	#define SR_TB BIT(5) /* Top/Bottom protect */
a8a16454	122	#define SR_SRWD BIT(7) /* SR write protect */
c4b3eacc AS	123	/* Spansion/Cypress specific status bits */
	124	#define SR_E_ERR BIT(5)
	125	#define SR_P_ERR BIT(6)
f39d2fa0	126
a8a16454	127	#define SR_QUAD_EN_MX BIT(6) /* Macronix Quad I/O */
f39d2fa0	128
548cd3ab	129	/* Enhanced Volatile Configuration Register bits */
a8a16454	130	#define EVCR_QUAD_EN_MICRON BIT(7) /* Micron Quad I/O */
548cd3ab	131
c14dedde	132	/* Flag Status Register bits */
a8a16454	133	#define FSR_READY BIT(7)
c14dedde	134
f39d2fa0	135	/* Configuration Register bits. */
a8a16454	136	#define CR_QUAD_EN_SPAN BIT(1) /* Spansion Quad I/O */
f39d2fa0	137
f384b352 CP	138	/* Status Register 2 bits. */
	139	#define SR2_QUAD_EN_BIT7 BIT(7)
	140
cfc5604c CP	141	/* Supported SPI protocols */
	142	#define SNOR_PROTO_INST_MASK GENMASK(23, 16)
	143	#define SNOR_PROTO_INST_SHIFT 16
	144	#define SNOR_PROTO_INST(_nbits) \
	145	((((unsigned long)(_nbits)) << SNOR_PROTO_INST_SHIFT) & \
	146	SNOR_PROTO_INST_MASK)
	147
	148	#define SNOR_PROTO_ADDR_MASK GENMASK(15, 8)
	149	#define SNOR_PROTO_ADDR_SHIFT 8
	150	#define SNOR_PROTO_ADDR(_nbits) \
	151	((((unsigned long)(_nbits)) << SNOR_PROTO_ADDR_SHIFT) & \
	152	SNOR_PROTO_ADDR_MASK)
	153
	154	#define SNOR_PROTO_DATA_MASK GENMASK(7, 0)
	155	#define SNOR_PROTO_DATA_SHIFT 0
	156	#define SNOR_PROTO_DATA(_nbits) \
	157	((((unsigned long)(_nbits)) << SNOR_PROTO_DATA_SHIFT) & \
	158	SNOR_PROTO_DATA_MASK)
	159
15f55331 CP	160	#define SNOR_PROTO_IS_DTR BIT(24) /* Double Transfer Rate */
15f55331 CP	161
cfc5604c CP	162	#define SNOR_PROTO_STR(_inst_nbits, _addr_nbits, _data_nbits) \
	163	(SNOR_PROTO_INST(_inst_nbits) \| \
	164	SNOR_PROTO_ADDR(_addr_nbits) \| \
	165	SNOR_PROTO_DATA(_data_nbits))
15f55331 CP	166	#define SNOR_PROTO_DTR(_inst_nbits, _addr_nbits, _data_nbits) \
	167	(SNOR_PROTO_IS_DTR \| \
	168	SNOR_PROTO_STR(_inst_nbits, _addr_nbits, _data_nbits))
cfc5604c CP	169
	170	enum spi_nor_protocol {
	171	SNOR_PROTO_1_1_1 = SNOR_PROTO_STR(1, 1, 1),
	172	SNOR_PROTO_1_1_2 = SNOR_PROTO_STR(1, 1, 2),
	173	SNOR_PROTO_1_1_4 = SNOR_PROTO_STR(1, 1, 4),
fe488a5e	174	SNOR_PROTO_1_1_8 = SNOR_PROTO_STR(1, 1, 8),
cfc5604c CP	175	SNOR_PROTO_1_2_2 = SNOR_PROTO_STR(1, 2, 2),
cfc5604c CP	176	SNOR_PROTO_1_4_4 = SNOR_PROTO_STR(1, 4, 4),
fe488a5e	177	SNOR_PROTO_1_8_8 = SNOR_PROTO_STR(1, 8, 8),
cfc5604c CP	178	SNOR_PROTO_2_2_2 = SNOR_PROTO_STR(2, 2, 2),
cfc5604c CP	179	SNOR_PROTO_4_4_4 = SNOR_PROTO_STR(4, 4, 4),
fe488a5e	180	SNOR_PROTO_8_8_8 = SNOR_PROTO_STR(8, 8, 8),
15f55331 CP	181
	182	SNOR_PROTO_1_1_1_DTR = SNOR_PROTO_DTR(1, 1, 1),
	183	SNOR_PROTO_1_2_2_DTR = SNOR_PROTO_DTR(1, 2, 2),
	184	SNOR_PROTO_1_4_4_DTR = SNOR_PROTO_DTR(1, 4, 4),
fe488a5e	185	SNOR_PROTO_1_8_8_DTR = SNOR_PROTO_DTR(1, 8, 8),
6e602ef7 HS	186	};
6e602ef7 HS	187
15f55331 CP	188	static inline bool spi_nor_protocol_is_dtr(enum spi_nor_protocol proto)
	189	{
	190	return !!(proto & SNOR_PROTO_IS_DTR);
	191	}
	192
cfc5604c CP	193	static inline u8 spi_nor_get_protocol_inst_nbits(enum spi_nor_protocol proto)
	194	{
	195	return ((unsigned long)(proto & SNOR_PROTO_INST_MASK)) >>
	196	SNOR_PROTO_INST_SHIFT;
	197	}
	198
	199	static inline u8 spi_nor_get_protocol_addr_nbits(enum spi_nor_protocol proto)
	200	{
	201	return ((unsigned long)(proto & SNOR_PROTO_ADDR_MASK)) >>
	202	SNOR_PROTO_ADDR_SHIFT;
	203	}
	204
	205	static inline u8 spi_nor_get_protocol_data_nbits(enum spi_nor_protocol proto)
	206	{
	207	return ((unsigned long)(proto & SNOR_PROTO_DATA_MASK)) >>
	208	SNOR_PROTO_DATA_SHIFT;
	209	}
	210
	211	static inline u8 spi_nor_get_protocol_width(enum spi_nor_protocol proto)
	212	{
	213	return spi_nor_get_protocol_data_nbits(proto);
	214	}
	215
becd0cb8	216	#define SPI_NOR_MAX_CMD_SIZE 8
6e602ef7 HS	217	enum spi_nor_ops {
	218	SPI_NOR_OPS_READ = 0,
	219	SPI_NOR_OPS_WRITE,
	220	SPI_NOR_OPS_ERASE,
	221	SPI_NOR_OPS_LOCK,
	222	SPI_NOR_OPS_UNLOCK,
	223	};
	224
6af91949 BN	225	enum spi_nor_option_flags {
6af91949 BN	226	SNOR_F_USE_FSR = BIT(0),
3dd8012a	227	SNOR_F_HAS_SR_TB = BIT(1),
e99ca98f RRD	228	SNOR_F_NO_OP_CHIP_ERASE = BIT(2),
	229	SNOR_F_S3AN_ADDR_DEFAULT = BIT(3),
	230	SNOR_F_READY_XSR_RDY = BIT(4),
c4b3eacc	231	SNOR_F_USE_CLSR = BIT(5),
6af91949 BN	232	};
6af91949 BN	233
6e602ef7 HS	234	/**
	235	* struct spi_nor - Structure for defining a the SPI NOR layer
	236	* @mtd: point to a mtd_info structure
	237	* @lock: the lock for the read/write/erase/lock/unlock operations
	238	* @dev: point to a spi device, or a spi nor controller device.
	239	* @page_size: the page size of the SPI NOR
	240	* @addr_width: number of address bytes
	241	* @erase_opcode: the opcode for erasing a sector
	242	* @read_opcode: the read opcode
	243	* @read_dummy: the dummy needed by the read operation
	244	* @program_opcode: the program opcode
6e602ef7	245	* @sst_write_second: used by the SST write operation
6af91949	246	* @flags: flag options for the current SPI-NOR (SNOR_F_*)
cfc5604c CP	247	* @read_proto: the SPI protocol for read operations
	248	* @write_proto: the SPI protocol for write operations
	249	* @reg_proto the SPI protocol for read_reg/write_reg/erase operations
6e602ef7 HS	250	* @cmd_buf: used by the write_reg
	251	* @prepare: [OPTIONAL] do some preparations for the
	252	* read/write/erase/lock/unlock operations
	253	* @unprepare: [OPTIONAL] do some post work after the
	254	* read/write/erase/lock/unlock operations
6e602ef7 HS	255	* @read_reg: [DRIVER-SPECIFIC] read out the register
6e602ef7 HS	256	* @write_reg: [DRIVER-SPECIFIC] write data to the register
6e602ef7 HS	257	* @read: [DRIVER-SPECIFIC] read data from the SPI NOR
	258	* @write: [DRIVER-SPECIFIC] write data to the SPI NOR
	259	* @erase: [DRIVER-SPECIFIC] erase a sector of the SPI NOR
c67cbb83 BN	260	* at the offset @offs; if not provided by the driver,
c67cbb83 BN	261	* spi-nor will send the erase opcode via write_reg()
f8900258 BN	262	* @flash_lock: [FLASH-SPECIFIC] lock a region of the SPI NOR
f8900258 BN	263	* @flash_unlock: [FLASH-SPECIFIC] unlock a region of the SPI NOR
5bf0e69b BN	264	* @flash_is_locked: [FLASH-SPECIFIC] check if a region of the SPI NOR is
5bf0e69b BN	265	* completely locked
6e602ef7 HS	266	* @priv: the private data
	267	*/
	268	struct spi_nor {
19763671	269	struct mtd_info mtd;
6e602ef7 HS	270	struct mutex lock;
	271	struct device *dev;
	272	u32 page_size;
	273	u8 addr_width;
	274	u8 erase_opcode;
	275	u8 read_opcode;
	276	u8 read_dummy;
	277	u8 program_opcode;
cfc5604c CP	278	enum spi_nor_protocol read_proto;
	279	enum spi_nor_protocol write_proto;
	280	enum spi_nor_protocol reg_proto;
6e602ef7	281	bool sst_write_second;
6af91949	282	u32 flags;
6e602ef7 HS	283	u8 cmd_buf[SPI_NOR_MAX_CMD_SIZE];
	284
	285	int (prepare)(struct spi_nor nor, enum spi_nor_ops ops);
	286	void (unprepare)(struct spi_nor nor, enum spi_nor_ops ops);
6e602ef7	287	int (read_reg)(struct spi_nor nor, u8 opcode, u8 *buf, int len);
f9f3ce83	288	int (write_reg)(struct spi_nor nor, u8 opcode, u8 *buf, int len);
6e602ef7	289
59451e12	290	ssize_t (read)(struct spi_nor nor, loff_t from,
2dd087b1	291	size_t len, u_char *read_buf);
59451e12	292	ssize_t (write)(struct spi_nor nor, loff_t to,
2dd087b1	293	size_t len, const u_char *write_buf);
6e602ef7 HS	294	int (erase)(struct spi_nor nor, loff_t offs);
6e602ef7 HS	295
8cc7f33a BN	296	int (flash_lock)(struct spi_nor nor, loff_t ofs, uint64_t len);
8cc7f33a BN	297	int (flash_unlock)(struct spi_nor nor, loff_t ofs, uint64_t len);
5bf0e69b	298	int (flash_is_locked)(struct spi_nor nor, loff_t ofs, uint64_t len);
8cc7f33a	299
6e602ef7 HS	300	void *priv;
6e602ef7 HS	301	};
b199489d	302
28b8b26b BN	303	static inline void spi_nor_set_flash_node(struct spi_nor *nor,
	304	struct device_node *np)
	305	{
30069af7	306	mtd_set_of_node(&nor->mtd, np);
28b8b26b BN	307	}
	308
	309	static inline struct device_node spi_nor_get_flash_node(struct spi_nor nor)
	310	{
30069af7	311	return mtd_get_of_node(&nor->mtd);
28b8b26b BN	312	}
28b8b26b BN	313
cfc5604c CP	314	/**
	315	* struct spi_nor_hwcaps - Structure for describing the hardware capabilies
	316	* supported by the SPI controller (bus master).
	317	* @mask: the bitmask listing all the supported hw capabilies
	318	*/
	319	struct spi_nor_hwcaps {
	320	u32 mask;
	321	};
	322
	323	/*
	324	*(Fast) Read capabilities.
	325	* MUST be ordered by priority: the higher bit position, the higher priority.
fe488a5e CP	326	* As a matter of performances, it is relevant to use Octo SPI protocols first,
	327	* then Quad SPI protocols before Dual SPI protocols, Fast Read and lastly
	328	* (Slow) Read.
cfc5604c	329	*/
fe488a5e	330	#define SNOR_HWCAPS_READ_MASK GENMASK(14, 0)
cfc5604c CP	331	#define SNOR_HWCAPS_READ BIT(0)
cfc5604c CP	332	#define SNOR_HWCAPS_READ_FAST BIT(1)
15f55331 CP	333	#define SNOR_HWCAPS_READ_1_1_1_DTR BIT(2)
	334
	335	#define SNOR_HWCAPS_READ_DUAL GENMASK(6, 3)
	336	#define SNOR_HWCAPS_READ_1_1_2 BIT(3)
	337	#define SNOR_HWCAPS_READ_1_2_2 BIT(4)
	338	#define SNOR_HWCAPS_READ_2_2_2 BIT(5)
	339	#define SNOR_HWCAPS_READ_1_2_2_DTR BIT(6)
	340
	341	#define SNOR_HWCAPS_READ_QUAD GENMASK(10, 7)
	342	#define SNOR_HWCAPS_READ_1_1_4 BIT(7)
	343	#define SNOR_HWCAPS_READ_1_4_4 BIT(8)
	344	#define SNOR_HWCAPS_READ_4_4_4 BIT(9)
	345	#define SNOR_HWCAPS_READ_1_4_4_DTR BIT(10)
cfc5604c	346
fe488a5e CP	347	#define SNOR_HWCPAS_READ_OCTO GENMASK(14, 11)
	348	#define SNOR_HWCAPS_READ_1_1_8 BIT(11)
	349	#define SNOR_HWCAPS_READ_1_8_8 BIT(12)
	350	#define SNOR_HWCAPS_READ_8_8_8 BIT(13)
	351	#define SNOR_HWCAPS_READ_1_8_8_DTR BIT(14)
	352
cfc5604c CP	353	/*
	354	* Page Program capabilities.
	355	* MUST be ordered by priority: the higher bit position, the higher priority.
fe488a5e	356	* Like (Fast) Read capabilities, Octo/Quad SPI protocols are preferred to the
cfc5604c CP	357	* legacy SPI 1-1-1 protocol.
	358	* Note that Dual Page Programs are not supported because there is no existing
	359	* JEDEC/SFDP standard to define them. Also at this moment no SPI flash memory
	360	* implements such commands.
	361	*/
fe488a5e	362	#define SNOR_HWCAPS_PP_MASK GENMASK(22, 16)
cfc5604c CP	363	#define SNOR_HWCAPS_PP BIT(16)
	364
	365	#define SNOR_HWCAPS_PP_QUAD GENMASK(19, 17)
	366	#define SNOR_HWCAPS_PP_1_1_4 BIT(17)
	367	#define SNOR_HWCAPS_PP_1_4_4 BIT(18)
	368	#define SNOR_HWCAPS_PP_4_4_4 BIT(19)
	369
fe488a5e CP	370	#define SNOR_HWCAPS_PP_OCTO GENMASK(22, 20)
	371	#define SNOR_HWCAPS_PP_1_1_8 BIT(20)
	372	#define SNOR_HWCAPS_PP_1_8_8 BIT(21)
	373	#define SNOR_HWCAPS_PP_8_8_8 BIT(22)
	374
b199489d HS	375	/**
	376	* spi_nor_scan() - scan the SPI NOR
	377	* @nor: the spi_nor structure
70f3ce05	378	* @name: the chip type name
cfc5604c	379	* @hwcaps: the hardware capabilities supported by the controller driver
b199489d HS	380	*
	381	* The drivers can use this fuction to scan the SPI NOR.
	382	* In the scanning, it will try to get all the necessary information to
	383	* fill the mtd_info{} and the spi_nor{}.
	384	*
70f3ce05	385	* The chip type name can be provided through the @name parameter.
b199489d HS	386	*
	387	* Return: 0 for success, others for failure.
	388	*/
cfc5604c CP	389	int spi_nor_scan(struct spi_nor nor, const char name,
cfc5604c CP	390	const struct spi_nor_hwcaps *hwcaps);
b199489d	391
f39d2fa0	392	#endif