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b60503ba MW |
1 | /* |
2 | * Definitions for the NVM Express interface | |
8757ad65 | 3 | * Copyright (c) 2011-2014, Intel Corporation. |
b60503ba MW |
4 | * |
5 | * This program is free software; you can redistribute it and/or modify it | |
6 | * under the terms and conditions of the GNU General Public License, | |
7 | * version 2, as published by the Free Software Foundation. | |
8 | * | |
9 | * This program is distributed in the hope it will be useful, but WITHOUT | |
10 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
11 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
12 | * more details. | |
b60503ba MW |
13 | */ |
14 | ||
15 | #ifndef _LINUX_NVME_H | |
16 | #define _LINUX_NVME_H | |
17 | ||
42c77683 MW |
18 | #include <uapi/linux/nvme.h> |
19 | #include <linux/pci.h> | |
20 | #include <linux/miscdevice.h> | |
21 | #include <linux/kref.h> | |
b60503ba MW |
22 | |
23 | struct nvme_bar { | |
24 | __u64 cap; /* Controller Capabilities */ | |
25 | __u32 vs; /* Version */ | |
897cfe1c MW |
26 | __u32 intms; /* Interrupt Mask Set */ |
27 | __u32 intmc; /* Interrupt Mask Clear */ | |
b60503ba | 28 | __u32 cc; /* Controller Configuration */ |
897cfe1c | 29 | __u32 rsvd1; /* Reserved */ |
b60503ba | 30 | __u32 csts; /* Controller Status */ |
897cfe1c | 31 | __u32 rsvd2; /* Reserved */ |
b60503ba MW |
32 | __u32 aqa; /* Admin Queue Attributes */ |
33 | __u64 asq; /* Admin SQ Base Address */ | |
34 | __u64 acq; /* Admin CQ Base Address */ | |
35 | }; | |
36 | ||
a0cadb85 | 37 | #define NVME_CAP_MQES(cap) ((cap) & 0xffff) |
22605f96 | 38 | #define NVME_CAP_TIMEOUT(cap) (((cap) >> 24) & 0xff) |
f1938f6e | 39 | #define NVME_CAP_STRIDE(cap) (((cap) >> 32) & 0xf) |
8fc23e03 | 40 | #define NVME_CAP_MPSMIN(cap) (((cap) >> 48) & 0xf) |
22605f96 | 41 | |
b60503ba MW |
42 | enum { |
43 | NVME_CC_ENABLE = 1 << 0, | |
44 | NVME_CC_CSS_NVM = 0 << 4, | |
45 | NVME_CC_MPS_SHIFT = 7, | |
46 | NVME_CC_ARB_RR = 0 << 11, | |
47 | NVME_CC_ARB_WRRU = 1 << 11, | |
7f53f9d2 MW |
48 | NVME_CC_ARB_VS = 7 << 11, |
49 | NVME_CC_SHN_NONE = 0 << 14, | |
50 | NVME_CC_SHN_NORMAL = 1 << 14, | |
51 | NVME_CC_SHN_ABRUPT = 2 << 14, | |
1894d8f1 | 52 | NVME_CC_SHN_MASK = 3 << 14, |
7f53f9d2 MW |
53 | NVME_CC_IOSQES = 6 << 16, |
54 | NVME_CC_IOCQES = 4 << 20, | |
b60503ba MW |
55 | NVME_CSTS_RDY = 1 << 0, |
56 | NVME_CSTS_CFS = 1 << 1, | |
57 | NVME_CSTS_SHST_NORMAL = 0 << 2, | |
58 | NVME_CSTS_SHST_OCCUR = 1 << 2, | |
59 | NVME_CSTS_SHST_CMPLT = 2 << 2, | |
1894d8f1 | 60 | NVME_CSTS_SHST_MASK = 3 << 2, |
b60503ba MW |
61 | }; |
62 | ||
63 | #define NVME_VS(major, minor) (major << 16 | minor) | |
64 | ||
bd67608a MW |
65 | extern unsigned char nvme_io_timeout; |
66 | #define NVME_IO_TIMEOUT (nvme_io_timeout * HZ) | |
13c3b0fc VV |
67 | |
68 | /* | |
69 | * Represents an NVM Express device. Each nvme_dev is a PCI function. | |
70 | */ | |
71 | struct nvme_dev { | |
72 | struct list_head node; | |
5a92e700 | 73 | struct nvme_queue __rcu **queues; |
42f61420 | 74 | unsigned short __percpu *io_queue; |
13c3b0fc VV |
75 | u32 __iomem *dbs; |
76 | struct pci_dev *pci_dev; | |
77 | struct dma_pool *prp_page_pool; | |
78 | struct dma_pool *prp_small_pool; | |
79 | int instance; | |
42f61420 KB |
80 | unsigned queue_count; |
81 | unsigned online_queues; | |
82 | unsigned max_qid; | |
83 | int q_depth; | |
b80d5ccc | 84 | u32 db_stride; |
13c3b0fc VV |
85 | u32 ctrl_config; |
86 | struct msix_entry *entry; | |
87 | struct nvme_bar __iomem *bar; | |
88 | struct list_head namespaces; | |
5e82e952 KB |
89 | struct kref kref; |
90 | struct miscdevice miscdev; | |
9ca97374 | 91 | work_func_t reset_workfn; |
9a6b9458 | 92 | struct work_struct reset_work; |
f3db22fe | 93 | struct work_struct cpu_work; |
5e82e952 | 94 | char name[12]; |
13c3b0fc VV |
95 | char serial[20]; |
96 | char model[40]; | |
97 | char firmware_rev[8]; | |
98 | u32 max_hw_sectors; | |
159b67d7 | 99 | u32 stripe_size; |
13c3b0fc | 100 | u16 oncs; |
c30341dc | 101 | u16 abort_limit; |
a7d2ce28 | 102 | u8 vwc; |
d4b4ff8e | 103 | u8 initialized; |
13c3b0fc VV |
104 | }; |
105 | ||
106 | /* | |
107 | * An NVM Express namespace is equivalent to a SCSI LUN | |
108 | */ | |
109 | struct nvme_ns { | |
110 | struct list_head list; | |
111 | ||
112 | struct nvme_dev *dev; | |
113 | struct request_queue *queue; | |
114 | struct gendisk *disk; | |
115 | ||
c3bfe717 | 116 | unsigned ns_id; |
13c3b0fc | 117 | int lba_shift; |
f410c680 | 118 | int ms; |
5d0f6131 VV |
119 | u64 mode_select_num_blocks; |
120 | u32 mode_select_block_len; | |
13c3b0fc VV |
121 | }; |
122 | ||
123 | /* | |
124 | * The nvme_iod describes the data in an I/O, including the list of PRP | |
125 | * entries. You can't see it in this data structure because C doesn't let | |
126 | * me express that. Use nvme_alloc_iod to ensure there's enough space | |
127 | * allocated to store the PRP list. | |
128 | */ | |
129 | struct nvme_iod { | |
130 | void *private; /* For the use of the submitter of the I/O */ | |
131 | int npages; /* In the PRP list. 0 means small pool in use */ | |
132 | int offset; /* Of PRP list */ | |
133 | int nents; /* Used in scatterlist */ | |
134 | int length; /* Of data, in bytes */ | |
6198221f | 135 | unsigned long start_time; |
13c3b0fc | 136 | dma_addr_t first_dma; |
edd10d33 | 137 | struct list_head node; |
13c3b0fc VV |
138 | struct scatterlist sg[0]; |
139 | }; | |
5d0f6131 | 140 | |
063cc6d5 MW |
141 | static inline u64 nvme_block_nr(struct nvme_ns *ns, sector_t sector) |
142 | { | |
143 | return (sector >> (ns->lba_shift - 9)); | |
144 | } | |
145 | ||
5d0f6131 VV |
146 | /** |
147 | * nvme_free_iod - frees an nvme_iod | |
148 | * @dev: The device that the I/O was submitted to | |
149 | * @iod: The memory to free | |
150 | */ | |
151 | void nvme_free_iod(struct nvme_dev *dev, struct nvme_iod *iod); | |
152 | ||
edd10d33 | 153 | int nvme_setup_prps(struct nvme_dev *, struct nvme_iod *, int , gfp_t); |
5d0f6131 VV |
154 | struct nvme_iod *nvme_map_user_pages(struct nvme_dev *dev, int write, |
155 | unsigned long addr, unsigned length); | |
156 | void nvme_unmap_user_pages(struct nvme_dev *dev, int write, | |
157 | struct nvme_iod *iod); | |
4f5099af | 158 | int nvme_submit_io_cmd(struct nvme_dev *, struct nvme_command *, u32 *); |
5d0f6131 VV |
159 | int nvme_submit_admin_cmd(struct nvme_dev *, struct nvme_command *, |
160 | u32 *result); | |
161 | int nvme_identify(struct nvme_dev *, unsigned nsid, unsigned cns, | |
162 | dma_addr_t dma_addr); | |
163 | int nvme_get_features(struct nvme_dev *dev, unsigned fid, unsigned nsid, | |
164 | dma_addr_t dma_addr, u32 *result); | |
165 | int nvme_set_features(struct nvme_dev *dev, unsigned fid, unsigned dword11, | |
166 | dma_addr_t dma_addr, u32 *result); | |
167 | ||
168 | struct sg_io_hdr; | |
169 | ||
170 | int nvme_sg_io(struct nvme_ns *ns, struct sg_io_hdr __user *u_hdr); | |
320a3827 | 171 | int nvme_sg_io32(struct nvme_ns *ns, unsigned long arg); |
5d0f6131 VV |
172 | int nvme_sg_get_version_num(int __user *ip); |
173 | ||
b60503ba | 174 | #endif /* _LINUX_NVME_H */ |