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nvmet: don't override treq upon modification.
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b60503ba
MW		 1/*
2 * Definitions for the NVM Express interface
8757ad65 3 * Copyright (c) 2011-2014, Intel Corporation.
b60503ba
MW		 4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms and conditions of the GNU General Public License,
7 * version 2, as published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
b60503ba
MW		 13 */
14
15#ifndef _LINUX_NVME_H
16#define _LINUX_NVME_H
17
2812dfe3 18#include <linux/types.h>
8e412263 19#include <linux/uuid.h>
eb793e2c
CH		 20
21/* NQN names in commands fields specified one size */
22#define NVMF_NQN_FIELD_LEN 256
23
24/* However the max length of a qualified name is another size */
25#define NVMF_NQN_SIZE 223
26
27#define NVMF_TRSVCID_SIZE 32
28#define NVMF_TRADDR_SIZE 256
29#define NVMF_TSAS_SIZE 256
30
31#define NVME_DISC_SUBSYS_NAME "nqn.2014-08.org.nvmexpress.discovery"
32
33#define NVME_RDMA_IP_PORT 4420
34
62346eae
AD		 35#define NVME_NSID_ALL 0xffffffff
36
eb793e2c
CH		 37enum nvme_subsys_type {
38 NVME_NQN_DISC = 1, /* Discovery type target subsystem */
39 NVME_NQN_NVME = 2, /* NVME type target subsystem */
40};
41
42/* Address Family codes for Discovery Log Page entry ADRFAM field */
43enum {
44 NVMF_ADDR_FAMILY_PCI = 0, /* PCIe */
45 NVMF_ADDR_FAMILY_IP4 = 1, /* IP4 */
46 NVMF_ADDR_FAMILY_IP6 = 2, /* IP6 */
47 NVMF_ADDR_FAMILY_IB = 3, /* InfiniBand */
48 NVMF_ADDR_FAMILY_FC = 4, /* Fibre Channel */
49};
50
51/* Transport Type codes for Discovery Log Page entry TRTYPE field */
52enum {
53 NVMF_TRTYPE_RDMA = 1, /* RDMA */
54 NVMF_TRTYPE_FC = 2, /* Fibre Channel */
55 NVMF_TRTYPE_LOOP = 254, /* Reserved for host usage */
56 NVMF_TRTYPE_MAX,
57};
58
59/* Transport Requirements codes for Discovery Log Page entry TREQ field */
60enum {
61 NVMF_TREQ_NOT_SPECIFIED = 0, /* Not specified */
62 NVMF_TREQ_REQUIRED = 1, /* Required */
63 NVMF_TREQ_NOT_REQUIRED = 2, /* Not Required */
0445e1b5
SG		 64#define NVME_TREQ_SECURE_CHANNEL_MASK \
65 (NVMF_TREQ_REQUIRED | NVMF_TREQ_NOT_REQUIRED)
eb793e2c
CH		 66};
67
68/* RDMA QP Service Type codes for Discovery Log Page entry TSAS
69 * RDMA_QPTYPE field
70 */
71enum {
bf17aa36
RD		 72 NVMF_RDMA_QPTYPE_CONNECTED = 1, /* Reliable Connected */
73 NVMF_RDMA_QPTYPE_DATAGRAM = 2, /* Reliable Datagram */
eb793e2c
CH		 74};
75
76/* RDMA QP Service Type codes for Discovery Log Page entry TSAS
77 * RDMA_QPTYPE field
78 */
79enum {
bf17aa36
RD		 80 NVMF_RDMA_PRTYPE_NOT_SPECIFIED = 1, /* No Provider Specified */
81 NVMF_RDMA_PRTYPE_IB = 2, /* InfiniBand */
82 NVMF_RDMA_PRTYPE_ROCE = 3, /* InfiniBand RoCE */
83 NVMF_RDMA_PRTYPE_ROCEV2 = 4, /* InfiniBand RoCEV2 */
84 NVMF_RDMA_PRTYPE_IWARP = 5, /* IWARP */
eb793e2c
CH		 85};
86
87/* RDMA Connection Management Service Type codes for Discovery Log Page
88 * entry TSAS RDMA_CMS field
89 */
90enum {
bf17aa36 91 NVMF_RDMA_CMS_RDMA_CM = 1, /* Sockets based endpoint addressing */
eb793e2c
CH		 92};
93
7aa1f427 94#define NVME_AQ_DEPTH 32
38dabe21
KB		 95#define NVME_NR_AEN_COMMANDS 1
96#define NVME_AQ_BLK_MQ_DEPTH (NVME_AQ_DEPTH - NVME_NR_AEN_COMMANDS)
97
98/*
99 * Subtract one to leave an empty queue entry for 'Full Queue' condition. See
100 * NVM-Express 1.2 specification, section 4.1.2.
101 */
102#define NVME_AQ_MQ_TAG_DEPTH (NVME_AQ_BLK_MQ_DEPTH - 1)
2812dfe3 103
7a67cbea
CH		 104enum {
105 NVME_REG_CAP = 0x0000, /* Controller Capabilities */
106 NVME_REG_VS = 0x0008, /* Version */
107 NVME_REG_INTMS = 0x000c, /* Interrupt Mask Set */
a5b714ad 108 NVME_REG_INTMC = 0x0010, /* Interrupt Mask Clear */
7a67cbea
CH		 109 NVME_REG_CC = 0x0014, /* Controller Configuration */
110 NVME_REG_CSTS = 0x001c, /* Controller Status */
111 NVME_REG_NSSR = 0x0020, /* NVM Subsystem Reset */
112 NVME_REG_AQA = 0x0024, /* Admin Queue Attributes */
113 NVME_REG_ASQ = 0x0028, /* Admin SQ Base Address */
a5b714ad 114 NVME_REG_ACQ = 0x0030, /* Admin CQ Base Address */
7a67cbea
CH		 115 NVME_REG_CMBLOC = 0x0038, /* Controller Memory Buffer Location */
116 NVME_REG_CMBSZ = 0x003c, /* Controller Memory Buffer Size */
97f6ef64 117 NVME_REG_DBS = 0x1000, /* SQ 0 Tail Doorbell */
b60503ba
MW		 118};
119
a0cadb85 120#define NVME_CAP_MQES(cap) ((cap) & 0xffff)
22605f96 121#define NVME_CAP_TIMEOUT(cap) (((cap) >> 24) & 0xff)
f1938f6e 122#define NVME_CAP_STRIDE(cap) (((cap) >> 32) & 0xf)
dfbac8c7 123#define NVME_CAP_NSSRC(cap) (((cap) >> 36) & 0x1)
8fc23e03 124#define NVME_CAP_MPSMIN(cap) (((cap) >> 48) & 0xf)
1d090624 125#define NVME_CAP_MPSMAX(cap) (((cap) >> 52) & 0xf)
22605f96 126
8ffaadf7
JD		 127#define NVME_CMB_BIR(cmbloc) ((cmbloc) & 0x7)
128#define NVME_CMB_OFST(cmbloc) (((cmbloc) >> 12) & 0xfffff)
88de4598
CH		 129
130enum {
131 NVME_CMBSZ_SQS = 1 << 0,
132 NVME_CMBSZ_CQS = 1 << 1,
133 NVME_CMBSZ_LISTS = 1 << 2,
134 NVME_CMBSZ_RDS = 1 << 3,
135 NVME_CMBSZ_WDS = 1 << 4,
136
137 NVME_CMBSZ_SZ_SHIFT = 12,
138 NVME_CMBSZ_SZ_MASK = 0xfffff,
139
140 NVME_CMBSZ_SZU_SHIFT = 8,
141 NVME_CMBSZ_SZU_MASK = 0xf,
142};
8ffaadf7 143
69cd27e2
CH		 144/*
145 * Submission and Completion Queue Entry Sizes for the NVM command set.
146 * (In bytes and specified as a power of two (2^n)).
147 */
148#define NVME_NVM_IOSQES 6
149#define NVME_NVM_IOCQES 4
150
b60503ba
MW		 151enum {
152 NVME_CC_ENABLE = 1 << 0,
153 NVME_CC_CSS_NVM = 0 << 4,
ad4e05b2
MG		 154 NVME_CC_EN_SHIFT = 0,
155 NVME_CC_CSS_SHIFT = 4,
b60503ba 156 NVME_CC_MPS_SHIFT = 7,
ad4e05b2
MG		 157 NVME_CC_AMS_SHIFT = 11,
158 NVME_CC_SHN_SHIFT = 14,
159 NVME_CC_IOSQES_SHIFT = 16,
160 NVME_CC_IOCQES_SHIFT = 20,
60b43f62
MG		 161 NVME_CC_AMS_RR = 0 << NVME_CC_AMS_SHIFT,
162 NVME_CC_AMS_WRRU = 1 << NVME_CC_AMS_SHIFT,
163 NVME_CC_AMS_VS = 7 << NVME_CC_AMS_SHIFT,
ad4e05b2
MG		 164 NVME_CC_SHN_NONE = 0 << NVME_CC_SHN_SHIFT,
165 NVME_CC_SHN_NORMAL = 1 << NVME_CC_SHN_SHIFT,
166 NVME_CC_SHN_ABRUPT = 2 << NVME_CC_SHN_SHIFT,
167 NVME_CC_SHN_MASK = 3 << NVME_CC_SHN_SHIFT,
168 NVME_CC_IOSQES = NVME_NVM_IOSQES << NVME_CC_IOSQES_SHIFT,
169 NVME_CC_IOCQES = NVME_NVM_IOCQES << NVME_CC_IOCQES_SHIFT,
b60503ba
MW		 170 NVME_CSTS_RDY = 1 << 0,
171 NVME_CSTS_CFS = 1 << 1,
dfbac8c7 172 NVME_CSTS_NSSRO = 1 << 4,
b6dccf7f 173 NVME_CSTS_PP = 1 << 5,
b60503ba
MW		 174 NVME_CSTS_SHST_NORMAL = 0 << 2,
175 NVME_CSTS_SHST_OCCUR = 1 << 2,
176 NVME_CSTS_SHST_CMPLT = 2 << 2,
1894d8f1 177 NVME_CSTS_SHST_MASK = 3 << 2,
b60503ba
MW		 178};
179
9d99a8dd
CH		 180struct nvme_id_power_state {
181 __le16 max_power; /* centiwatts */
182 __u8 rsvd2;
183 __u8 flags;
184 __le32 entry_lat; /* microseconds */
185 __le32 exit_lat; /* microseconds */
186 __u8 read_tput;
187 __u8 read_lat;
188 __u8 write_tput;
189 __u8 write_lat;
190 __le16 idle_power;
191 __u8 idle_scale;
192 __u8 rsvd19;
193 __le16 active_power;
194 __u8 active_work_scale;
195 __u8 rsvd23[9];
196};
197
198enum {
199 NVME_PS_FLAGS_MAX_POWER_SCALE = 1 << 0,
200 NVME_PS_FLAGS_NON_OP_STATE = 1 << 1,
201};
202
12b21171
SG		 203enum nvme_ctrl_attr {
204 NVME_CTRL_ATTR_HID_128_BIT = (1 << 0),
6e3ca03e 205 NVME_CTRL_ATTR_TBKAS = (1 << 6),
12b21171
SG		 206};
207
9d99a8dd
CH		 208struct nvme_id_ctrl {
209 __le16 vid;
210 __le16 ssvid;
211 char sn[20];
212 char mn[40];
213 char fr[8];
214 __u8 rab;
215 __u8 ieee[3];
a446c084 216 __u8 cmic;
9d99a8dd 217 __u8 mdts;
08c69640
CH		 218 __le16 cntlid;
219 __le32 ver;
14e974a8
CH		 220 __le32 rtd3r;
221 __le32 rtd3e;
222 __le32 oaes;
eb793e2c
CH		 223 __le32 ctratt;
224 __u8 rsvd100[156];
9d99a8dd
CH		 225 __le16 oacs;
226 __u8 acl;
227 __u8 aerl;
228 __u8 frmw;
229 __u8 lpa;
230 __u8 elpe;
231 __u8 npss;
232 __u8 avscc;
233 __u8 apsta;
234 __le16 wctemp;
235 __le16 cctemp;
a446c084
CH		 236 __le16 mtfa;
237 __le32 hmpre;
238 __le32 hmmin;
239 __u8 tnvmcap[16];
240 __u8 unvmcap[16];
241 __le32 rpmbs;
435e8090
GJ		 242 __le16 edstt;
243 __u8 dsto;
244 __u8 fwug;
7b89eae2 245 __le16 kas;
435e8090
GJ		 246 __le16 hctma;
247 __le16 mntmt;
248 __le16 mxtmt;
249 __le32 sanicap;
044a9df1
CH		 250 __le32 hmminds;
251 __le16 hmmaxd;
1a376216
CH		 252 __u8 rsvd338[4];
253 __u8 anatt;
254 __u8 anacap;
255 __le32 anagrpmax;
256 __le32 nanagrpid;
257 __u8 rsvd352[160];
9d99a8dd
CH		 258 __u8 sqes;
259 __u8 cqes;
eb793e2c 260 __le16 maxcmd;
9d99a8dd
CH		 261 __le32 nn;
262 __le16 oncs;
263 __le16 fuses;
264 __u8 fna;
265 __u8 vwc;
266 __le16 awun;
267 __le16 awupf;
268 __u8 nvscc;
93045d59 269 __u8 nwpc;
9d99a8dd
CH		 270 __le16 acwu;
271 __u8 rsvd534[2];
272 __le32 sgls;
1a376216
CH		 273 __le32 mnan;
274 __u8 rsvd544[224];
eb793e2c
CH		 275 char subnqn[256];
276 __u8 rsvd1024[768];
277 __le32 ioccsz;
278 __le32 iorcsz;
279 __le16 icdoff;
280 __u8 ctrattr;
281 __u8 msdbd;
282 __u8 rsvd1804[244];
9d99a8dd
CH		 283 struct nvme_id_power_state psd[32];
284 __u8 vs[1024];
285};
286
287enum {
288 NVME_CTRL_ONCS_COMPARE = 1 << 0,
289 NVME_CTRL_ONCS_WRITE_UNCORRECTABLE = 1 << 1,
290 NVME_CTRL_ONCS_DSM = 1 << 2,
3b7c33b2 291 NVME_CTRL_ONCS_WRITE_ZEROES = 1 << 3,
dbf86b39 292 NVME_CTRL_ONCS_TIMESTAMP = 1 << 6,
9d99a8dd 293 NVME_CTRL_VWC_PRESENT = 1 << 0,
8a9ae523 294 NVME_CTRL_OACS_SEC_SUPP = 1 << 0,
f5d11840 295 NVME_CTRL_OACS_DIRECTIVES = 1 << 5,
223694b9 296 NVME_CTRL_OACS_DBBUF_SUPP = 1 << 8,
84fef62d 297 NVME_CTRL_LPA_CMD_EFFECTS_LOG = 1 << 1,
9d99a8dd
CH		 298};
299
300struct nvme_lbaf {
301 __le16 ms;
302 __u8 ds;
303 __u8 rp;
304};
305
306struct nvme_id_ns {
307 __le64 nsze;
308 __le64 ncap;
309 __le64 nuse;
310 __u8 nsfeat;
311 __u8 nlbaf;
312 __u8 flbas;
313 __u8 mc;
314 __u8 dpc;
315 __u8 dps;
316 __u8 nmic;
317 __u8 rescap;
318 __u8 fpi;
319 __u8 rsvd33;
320 __le16 nawun;
321 __le16 nawupf;
322 __le16 nacwu;
323 __le16 nabsn;
324 __le16 nabo;
325 __le16 nabspf;
6b8190d6 326 __le16 noiob;
a446c084 327 __u8 nvmcap[16];
1a376216
CH		 328 __u8 rsvd64[28];
329 __le32 anagrpid;
93045d59
CK		 330 __u8 rsvd96[3];
331 __u8 nsattr;
332 __u8 rsvd100[4];
9d99a8dd
CH		 333 __u8 nguid[16];
334 __u8 eui64[8];
335 struct nvme_lbaf lbaf[16];
336 __u8 rsvd192[192];
337 __u8 vs[3712];
338};
339
329dd768
CH		 340enum {
341 NVME_ID_CNS_NS = 0x00,
342 NVME_ID_CNS_CTRL = 0x01,
343 NVME_ID_CNS_NS_ACTIVE_LIST = 0x02,
af8b86e9 344 NVME_ID_CNS_NS_DESC_LIST = 0x03,
329dd768
CH		 345 NVME_ID_CNS_NS_PRESENT_LIST = 0x10,
346 NVME_ID_CNS_NS_PRESENT = 0x11,
347 NVME_ID_CNS_CTRL_NS_LIST = 0x12,
348 NVME_ID_CNS_CTRL_LIST = 0x13,
349};
350
f5d11840
JA		 351enum {
352 NVME_DIR_IDENTIFY = 0x00,
353 NVME_DIR_STREAMS = 0x01,
354 NVME_DIR_SND_ID_OP_ENABLE = 0x01,
355 NVME_DIR_SND_ST_OP_REL_ID = 0x01,
356 NVME_DIR_SND_ST_OP_REL_RSC = 0x02,
357 NVME_DIR_RCV_ID_OP_PARAM = 0x01,
358 NVME_DIR_RCV_ST_OP_PARAM = 0x01,
359 NVME_DIR_RCV_ST_OP_STATUS = 0x02,
360 NVME_DIR_RCV_ST_OP_RESOURCE = 0x03,
361 NVME_DIR_ENDIR = 0x01,
362};
363
9d99a8dd
CH		 364enum {
365 NVME_NS_FEAT_THIN = 1 << 0,
366 NVME_NS_FLBAS_LBA_MASK = 0xf,
367 NVME_NS_FLBAS_META_EXT = 0x10,
368 NVME_LBAF_RP_BEST = 0,
369 NVME_LBAF_RP_BETTER = 1,
370 NVME_LBAF_RP_GOOD = 2,
371 NVME_LBAF_RP_DEGRADED = 3,
372 NVME_NS_DPC_PI_LAST = 1 << 4,
373 NVME_NS_DPC_PI_FIRST = 1 << 3,
374 NVME_NS_DPC_PI_TYPE3 = 1 << 2,
375 NVME_NS_DPC_PI_TYPE2 = 1 << 1,
376 NVME_NS_DPC_PI_TYPE1 = 1 << 0,
377 NVME_NS_DPS_PI_FIRST = 1 << 3,
378 NVME_NS_DPS_PI_MASK = 0x7,
379 NVME_NS_DPS_PI_TYPE1 = 1,
380 NVME_NS_DPS_PI_TYPE2 = 2,
381 NVME_NS_DPS_PI_TYPE3 = 3,
382};
383
af8b86e9
JT		 384struct nvme_ns_id_desc {
385 __u8 nidt;
386 __u8 nidl;
387 __le16 reserved;
388};
389
390#define NVME_NIDT_EUI64_LEN 8
391#define NVME_NIDT_NGUID_LEN 16
392#define NVME_NIDT_UUID_LEN 16
393
394enum {
395 NVME_NIDT_EUI64 = 0x01,
396 NVME_NIDT_NGUID = 0x02,
397 NVME_NIDT_UUID = 0x03,
398};
399
9d99a8dd
CH		 400struct nvme_smart_log {
401 __u8 critical_warning;
402 __u8 temperature[2];
403 __u8 avail_spare;
404 __u8 spare_thresh;
405 __u8 percent_used;
406 __u8 rsvd6[26];
407 __u8 data_units_read[16];
408 __u8 data_units_written[16];
409 __u8 host_reads[16];
410 __u8 host_writes[16];
411 __u8 ctrl_busy_time[16];
412 __u8 power_cycles[16];
413 __u8 power_on_hours[16];
414 __u8 unsafe_shutdowns[16];
415 __u8 media_errors[16];
416 __u8 num_err_log_entries[16];
417 __le32 warning_temp_time;
418 __le32 critical_comp_time;
419 __le16 temp_sensor[8];
420 __u8 rsvd216[296];
421};
422
b6dccf7f
AD		 423struct nvme_fw_slot_info_log {
424 __u8 afi;
425 __u8 rsvd1[7];
426 __le64 frs[7];
427 __u8 rsvd64[448];
428};
429
84fef62d
KB		 430enum {
431 NVME_CMD_EFFECTS_CSUPP = 1 << 0,
432 NVME_CMD_EFFECTS_LBCC = 1 << 1,
433 NVME_CMD_EFFECTS_NCC = 1 << 2,
434 NVME_CMD_EFFECTS_NIC = 1 << 3,
435 NVME_CMD_EFFECTS_CCC = 1 << 4,
436 NVME_CMD_EFFECTS_CSE_MASK = 3 << 16,
437};
438
439struct nvme_effects_log {
440 __le32 acs[256];
441 __le32 iocs[256];
442 __u8 resv[2048];
443};
444
1a376216
CH		 445enum nvme_ana_state {
446 NVME_ANA_OPTIMIZED = 0x01,
447 NVME_ANA_NONOPTIMIZED = 0x02,
448 NVME_ANA_INACCESSIBLE = 0x03,
449 NVME_ANA_PERSISTENT_LOSS = 0x04,
450 NVME_ANA_CHANGE = 0x0f,
451};
452
453struct nvme_ana_group_desc {
454 __le32 grpid;
455 __le32 nnsids;
456 __le64 chgcnt;
457 __u8 state;
8b92d0e3 458 __u8 rsvd17[15];
1a376216
CH		 459 __le32 nsids[];
460};
461
462/* flag for the log specific field of the ANA log */
463#define NVME_ANA_LOG_RGO (1 << 0)
464
465struct nvme_ana_rsp_hdr {
466 __le64 chgcnt;
467 __le16 ngrps;
468 __le16 rsvd10[3];
469};
470
9d99a8dd
CH		 471enum {
472 NVME_SMART_CRIT_SPARE = 1 << 0,
473 NVME_SMART_CRIT_TEMPERATURE = 1 << 1,
474 NVME_SMART_CRIT_RELIABILITY = 1 << 2,
475 NVME_SMART_CRIT_MEDIA = 1 << 3,
476 NVME_SMART_CRIT_VOLATILE_MEMORY = 1 << 4,
477};
478
479enum {
e3d7874d
KB		 480 NVME_AER_ERROR = 0,
481 NVME_AER_SMART = 1,
868c2392 482 NVME_AER_NOTICE = 2,
e3d7874d
KB		 483 NVME_AER_CSS = 6,
484 NVME_AER_VS = 7,
868c2392
CH		 485};
486
487enum {
488 NVME_AER_NOTICE_NS_CHANGED = 0x00,
489 NVME_AER_NOTICE_FW_ACT_STARTING = 0x01,
1a376216 490 NVME_AER_NOTICE_ANA = 0x03,
f301c2b1 491 NVME_AER_NOTICE_DISC_CHANGED = 0xf0,
9d99a8dd
CH		 492};
493
aafd3afe 494enum {
7114ddeb
JS		 495 NVME_AEN_BIT_NS_ATTR = 8,
496 NVME_AEN_BIT_FW_ACT = 9,
497 NVME_AEN_BIT_ANA_CHANGE = 11,
f301c2b1 498 NVME_AEN_BIT_DISC_CHANGE = 31,
7114ddeb
JS		 499};
500
501enum {
502 NVME_AEN_CFG_NS_ATTR = 1 << NVME_AEN_BIT_NS_ATTR,
503 NVME_AEN_CFG_FW_ACT = 1 << NVME_AEN_BIT_FW_ACT,
504 NVME_AEN_CFG_ANA_CHANGE = 1 << NVME_AEN_BIT_ANA_CHANGE,
f301c2b1 505 NVME_AEN_CFG_DISC_CHANGE = 1 << NVME_AEN_BIT_DISC_CHANGE,
aafd3afe
HR		 506};
507
9d99a8dd
CH		 508struct nvme_lba_range_type {
509 __u8 type;
510 __u8 attributes;
511 __u8 rsvd2[14];
512 __u64 slba;
513 __u64 nlb;
514 __u8 guid[16];
515 __u8 rsvd48[16];
516};
517
518enum {
519 NVME_LBART_TYPE_FS = 0x01,
520 NVME_LBART_TYPE_RAID = 0x02,
521 NVME_LBART_TYPE_CACHE = 0x03,
522 NVME_LBART_TYPE_SWAP = 0x04,
523
524 NVME_LBART_ATTRIB_TEMP = 1 << 0,
525 NVME_LBART_ATTRIB_HIDE = 1 << 1,
526};
527
528struct nvme_reservation_status {
529 __le32 gen;
530 __u8 rtype;
531 __u8 regctl[2];
532 __u8 resv5[2];
533 __u8 ptpls;
534 __u8 resv10[13];
535 struct {
536 __le16 cntlid;
537 __u8 rcsts;
538 __u8 resv3[5];
539 __le64 hostid;
540 __le64 rkey;
541 } regctl_ds[];
542};
543
79f370ea
CH		 544enum nvme_async_event_type {
545 NVME_AER_TYPE_ERROR = 0,
546 NVME_AER_TYPE_SMART = 1,
547 NVME_AER_TYPE_NOTICE = 2,
548};
549
9d99a8dd
CH		 550/* I/O commands */
551
552enum nvme_opcode {
553 nvme_cmd_flush = 0x00,
554 nvme_cmd_write = 0x01,
555 nvme_cmd_read = 0x02,
556 nvme_cmd_write_uncor = 0x04,
557 nvme_cmd_compare = 0x05,
558 nvme_cmd_write_zeroes = 0x08,
559 nvme_cmd_dsm = 0x09,
560 nvme_cmd_resv_register = 0x0d,
561 nvme_cmd_resv_report = 0x0e,
562 nvme_cmd_resv_acquire = 0x11,
563 nvme_cmd_resv_release = 0x15,
564};
565
eb793e2c
CH		 566/*
567 * Descriptor subtype - lower 4 bits of nvme_(keyed_)sgl_desc identifier
568 *
569 * @NVME_SGL_FMT_ADDRESS: absolute address of the data block
570 * @NVME_SGL_FMT_OFFSET: relative offset of the in-capsule data block
d85cf207 571 * @NVME_SGL_FMT_TRANSPORT_A: transport defined format, value 0xA
eb793e2c
CH		 572 * @NVME_SGL_FMT_INVALIDATE: RDMA transport specific remote invalidation
573 * request subtype
574 */
575enum {
576 NVME_SGL_FMT_ADDRESS = 0x00,
577 NVME_SGL_FMT_OFFSET = 0x01,
d85cf207 578 NVME_SGL_FMT_TRANSPORT_A = 0x0A,
eb793e2c
CH		 579 NVME_SGL_FMT_INVALIDATE = 0x0f,
580};
581
582/*
583 * Descriptor type - upper 4 bits of nvme_(keyed_)sgl_desc identifier
584 *
585 * For struct nvme_sgl_desc:
586 * @NVME_SGL_FMT_DATA_DESC: data block descriptor
587 * @NVME_SGL_FMT_SEG_DESC: sgl segment descriptor
588 * @NVME_SGL_FMT_LAST_SEG_DESC: last sgl segment descriptor
589 *
590 * For struct nvme_keyed_sgl_desc:
591 * @NVME_KEY_SGL_FMT_DATA_DESC: keyed data block descriptor
d85cf207
JS		 592 *
593 * Transport-specific SGL types:
594 * @NVME_TRANSPORT_SGL_DATA_DESC: Transport SGL data dlock descriptor
eb793e2c
CH		 595 */
596enum {
597 NVME_SGL_FMT_DATA_DESC = 0x00,
598 NVME_SGL_FMT_SEG_DESC = 0x02,
599 NVME_SGL_FMT_LAST_SEG_DESC = 0x03,
600 NVME_KEY_SGL_FMT_DATA_DESC = 0x04,
d85cf207 601 NVME_TRANSPORT_SGL_DATA_DESC = 0x05,
eb793e2c
CH		 602};
603
604struct nvme_sgl_desc {
605 __le64 addr;
606 __le32 length;
607 __u8 rsvd[3];
608 __u8 type;
609};
610
611struct nvme_keyed_sgl_desc {
612 __le64 addr;
613 __u8 length[3];
614 __u8 key[4];
615 __u8 type;
616};
617
618union nvme_data_ptr {
619 struct {
620 __le64 prp1;
621 __le64 prp2;
622 };
623 struct nvme_sgl_desc sgl;
624 struct nvme_keyed_sgl_desc ksgl;
625};
626
3972be23
JS		 627/*
628 * Lowest two bits of our flags field (FUSE field in the spec):
629 *
630 * @NVME_CMD_FUSE_FIRST: Fused Operation, first command
631 * @NVME_CMD_FUSE_SECOND: Fused Operation, second command
632 *
633 * Highest two bits in our flags field (PSDT field in the spec):
634 *
635 * @NVME_CMD_PSDT_SGL_METABUF: Use SGLS for this transfer,
636 * If used, MPTR contains addr of single physical buffer (byte aligned).
637 * @NVME_CMD_PSDT_SGL_METASEG: Use SGLS for this transfer,
638 * If used, MPTR contains an address of an SGL segment containing
639 * exactly 1 SGL descriptor (qword aligned).
640 */
641enum {
642 NVME_CMD_FUSE_FIRST = (1 << 0),
643 NVME_CMD_FUSE_SECOND = (1 << 1),
644
645 NVME_CMD_SGL_METABUF = (1 << 6),
646 NVME_CMD_SGL_METASEG = (1 << 7),
647 NVME_CMD_SGL_ALL = NVME_CMD_SGL_METABUF | NVME_CMD_SGL_METASEG,
648};
649
9d99a8dd
CH		 650struct nvme_common_command {
651 __u8 opcode;
652 __u8 flags;
653 __u16 command_id;
654 __le32 nsid;
655 __le32 cdw2[2];
656 __le64 metadata;
eb793e2c 657 union nvme_data_ptr dptr;
9d99a8dd
CH		 658 __le32 cdw10[6];
659};
660
661struct nvme_rw_command {
662 __u8 opcode;
663 __u8 flags;
664 __u16 command_id;
665 __le32 nsid;
666 __u64 rsvd2;
667 __le64 metadata;
eb793e2c 668 union nvme_data_ptr dptr;
9d99a8dd
CH		 669 __le64 slba;
670 __le16 length;
671 __le16 control;
672 __le32 dsmgmt;
673 __le32 reftag;
674 __le16 apptag;
675 __le16 appmask;
676};
677
678enum {
679 NVME_RW_LR = 1 << 15,
680 NVME_RW_FUA = 1 << 14,
681 NVME_RW_DSM_FREQ_UNSPEC = 0,
682 NVME_RW_DSM_FREQ_TYPICAL = 1,
683 NVME_RW_DSM_FREQ_RARE = 2,
684 NVME_RW_DSM_FREQ_READS = 3,
685 NVME_RW_DSM_FREQ_WRITES = 4,
686 NVME_RW_DSM_FREQ_RW = 5,
687 NVME_RW_DSM_FREQ_ONCE = 6,
688 NVME_RW_DSM_FREQ_PREFETCH = 7,
689 NVME_RW_DSM_FREQ_TEMP = 8,
690 NVME_RW_DSM_LATENCY_NONE = 0 << 4,
691 NVME_RW_DSM_LATENCY_IDLE = 1 << 4,
692 NVME_RW_DSM_LATENCY_NORM = 2 << 4,
693 NVME_RW_DSM_LATENCY_LOW = 3 << 4,
694 NVME_RW_DSM_SEQ_REQ = 1 << 6,
695 NVME_RW_DSM_COMPRESSED = 1 << 7,
696 NVME_RW_PRINFO_PRCHK_REF = 1 << 10,
697 NVME_RW_PRINFO_PRCHK_APP = 1 << 11,
698 NVME_RW_PRINFO_PRCHK_GUARD = 1 << 12,
699 NVME_RW_PRINFO_PRACT = 1 << 13,
f5d11840 700 NVME_RW_DTYPE_STREAMS = 1 << 4,
9d99a8dd
CH		 701};
702
703struct nvme_dsm_cmd {
704 __u8 opcode;
705 __u8 flags;
706 __u16 command_id;
707 __le32 nsid;
708 __u64 rsvd2[2];
eb793e2c 709 union nvme_data_ptr dptr;
9d99a8dd
CH		 710 __le32 nr;
711 __le32 attributes;
712 __u32 rsvd12[4];
713};
714
715enum {
716 NVME_DSMGMT_IDR = 1 << 0,
717 NVME_DSMGMT_IDW = 1 << 1,
718 NVME_DSMGMT_AD = 1 << 2,
719};
720
b35ba01e
CH		 721#define NVME_DSM_MAX_RANGES 256
722
9d99a8dd
CH		 723struct nvme_dsm_range {
724 __le32 cattr;
725 __le32 nlb;
726 __le64 slba;
727};
728
3b7c33b2
CK		 729struct nvme_write_zeroes_cmd {
730 __u8 opcode;
731 __u8 flags;
732 __u16 command_id;
733 __le32 nsid;
734 __u64 rsvd2;
735 __le64 metadata;
736 union nvme_data_ptr dptr;
737 __le64 slba;
738 __le16 length;
739 __le16 control;
740 __le32 dsmgmt;
741 __le32 reftag;
742 __le16 apptag;
743 __le16 appmask;
744};
745
c5552fde
AL		 746/* Features */
747
748struct nvme_feat_auto_pst {
749 __le64 entries[32];
750};
751
39673e19
CH		 752enum {
753 NVME_HOST_MEM_ENABLE = (1 << 0),
754 NVME_HOST_MEM_RETURN = (1 << 1),
755};
756
9d99a8dd
CH		 757/* Admin commands */
758
759enum nvme_admin_opcode {
760 nvme_admin_delete_sq = 0x00,
761 nvme_admin_create_sq = 0x01,
762 nvme_admin_get_log_page = 0x02,
763 nvme_admin_delete_cq = 0x04,
764 nvme_admin_create_cq = 0x05,
765 nvme_admin_identify = 0x06,
766 nvme_admin_abort_cmd = 0x08,
767 nvme_admin_set_features = 0x09,
768 nvme_admin_get_features = 0x0a,
769 nvme_admin_async_event = 0x0c,
a446c084 770 nvme_admin_ns_mgmt = 0x0d,
9d99a8dd
CH		 771 nvme_admin_activate_fw = 0x10,
772 nvme_admin_download_fw = 0x11,
a446c084 773 nvme_admin_ns_attach = 0x15,
7b89eae2 774 nvme_admin_keep_alive = 0x18,
f5d11840
JA		 775 nvme_admin_directive_send = 0x19,
776 nvme_admin_directive_recv = 0x1a,
f9f38e33 777 nvme_admin_dbbuf = 0x7C,
9d99a8dd
CH		 778 nvme_admin_format_nvm = 0x80,
779 nvme_admin_security_send = 0x81,
780 nvme_admin_security_recv = 0x82,
84fef62d 781 nvme_admin_sanitize_nvm = 0x84,
9d99a8dd
CH		 782};
783
784enum {
785 NVME_QUEUE_PHYS_CONTIG = (1 << 0),
786 NVME_CQ_IRQ_ENABLED = (1 << 1),
787 NVME_SQ_PRIO_URGENT = (0 << 1),
788 NVME_SQ_PRIO_HIGH = (1 << 1),
789 NVME_SQ_PRIO_MEDIUM = (2 << 1),
790 NVME_SQ_PRIO_LOW = (3 << 1),
791 NVME_FEAT_ARBITRATION = 0x01,
792 NVME_FEAT_POWER_MGMT = 0x02,
793 NVME_FEAT_LBA_RANGE = 0x03,
794 NVME_FEAT_TEMP_THRESH = 0x04,
795 NVME_FEAT_ERR_RECOVERY = 0x05,
796 NVME_FEAT_VOLATILE_WC = 0x06,
797 NVME_FEAT_NUM_QUEUES = 0x07,
798 NVME_FEAT_IRQ_COALESCE = 0x08,
799 NVME_FEAT_IRQ_CONFIG = 0x09,
800 NVME_FEAT_WRITE_ATOMIC = 0x0a,
801 NVME_FEAT_ASYNC_EVENT = 0x0b,
802 NVME_FEAT_AUTO_PST = 0x0c,
a446c084 803 NVME_FEAT_HOST_MEM_BUF = 0x0d,
dbf86b39 804 NVME_FEAT_TIMESTAMP = 0x0e,
7b89eae2 805 NVME_FEAT_KATO = 0x0f,
40c6f9c2
RR		 806 NVME_FEAT_HCTM = 0x10,
807 NVME_FEAT_NOPSC = 0x11,
808 NVME_FEAT_RRL = 0x12,
809 NVME_FEAT_PLM_CONFIG = 0x13,
810 NVME_FEAT_PLM_WINDOW = 0x14,
9d99a8dd
CH		 811 NVME_FEAT_SW_PROGRESS = 0x80,
812 NVME_FEAT_HOST_ID = 0x81,
813 NVME_FEAT_RESV_MASK = 0x82,
814 NVME_FEAT_RESV_PERSIST = 0x83,
93045d59 815 NVME_FEAT_WRITE_PROTECT = 0x84,
9d99a8dd
CH		 816 NVME_LOG_ERROR = 0x01,
817 NVME_LOG_SMART = 0x02,
818 NVME_LOG_FW_SLOT = 0x03,
b3984e06 819 NVME_LOG_CHANGED_NS = 0x04,
84fef62d 820 NVME_LOG_CMD_EFFECTS = 0x05,
1a376216 821 NVME_LOG_ANA = 0x0c,
eb793e2c 822 NVME_LOG_DISC = 0x70,
9d99a8dd
CH		 823 NVME_LOG_RESERVATION = 0x80,
824 NVME_FWACT_REPL = (0 << 3),
825 NVME_FWACT_REPL_ACTV = (1 << 3),
826 NVME_FWACT_ACTV = (2 << 3),
827};
828
93045d59
CK		 829/* NVMe Namespace Write Protect State */
830enum {
831 NVME_NS_NO_WRITE_PROTECT = 0,
832 NVME_NS_WRITE_PROTECT,
833 NVME_NS_WRITE_PROTECT_POWER_CYCLE,
834 NVME_NS_WRITE_PROTECT_PERMANENT,
835};
836
b3984e06
CH		 837#define NVME_MAX_CHANGED_NAMESPACES 1024
838
9d99a8dd
CH		 839struct nvme_identify {
840 __u8 opcode;
841 __u8 flags;
842 __u16 command_id;
843 __le32 nsid;
844 __u64 rsvd2[2];
eb793e2c 845 union nvme_data_ptr dptr;
986994a2
PP		 846 __u8 cns;
847 __u8 rsvd3;
848 __le16 ctrlid;
9d99a8dd
CH		 849 __u32 rsvd11[5];
850};
851
0add5e8e
JT		 852#define NVME_IDENTIFY_DATA_SIZE 4096
853
9d99a8dd
CH		 854struct nvme_features {
855 __u8 opcode;
856 __u8 flags;
857 __u16 command_id;
858 __le32 nsid;
859 __u64 rsvd2[2];
eb793e2c 860 union nvme_data_ptr dptr;
9d99a8dd
CH		 861 __le32 fid;
862 __le32 dword11;
b85cf734
AD		 863 __le32 dword12;
864 __le32 dword13;
865 __le32 dword14;
866 __le32 dword15;
9d99a8dd
CH		 867};
868
39673e19
CH		 869struct nvme_host_mem_buf_desc {
870 __le64 addr;
871 __le32 size;
872 __u32 rsvd;
873};
874
9d99a8dd
CH		 875struct nvme_create_cq {
876 __u8 opcode;
877 __u8 flags;
878 __u16 command_id;
879 __u32 rsvd1[5];
880 __le64 prp1;
881 __u64 rsvd8;
882 __le16 cqid;
883 __le16 qsize;
884 __le16 cq_flags;
885 __le16 irq_vector;
886 __u32 rsvd12[4];
887};
888
889struct nvme_create_sq {
890 __u8 opcode;
891 __u8 flags;
892 __u16 command_id;
893 __u32 rsvd1[5];
894 __le64 prp1;
895 __u64 rsvd8;
896 __le16 sqid;
897 __le16 qsize;
898 __le16 sq_flags;
899 __le16 cqid;
900 __u32 rsvd12[4];
901};
902
903struct nvme_delete_queue {
904 __u8 opcode;
905 __u8 flags;
906 __u16 command_id;
907 __u32 rsvd1[9];
908 __le16 qid;
909 __u16 rsvd10;
910 __u32 rsvd11[5];
911};
912
913struct nvme_abort_cmd {
914 __u8 opcode;
915 __u8 flags;
916 __u16 command_id;
917 __u32 rsvd1[9];
918 __le16 sqid;
919 __u16 cid;
920 __u32 rsvd11[5];
921};
922
923struct nvme_download_firmware {
924 __u8 opcode;
925 __u8 flags;
926 __u16 command_id;
927 __u32 rsvd1[5];
eb793e2c 928 union nvme_data_ptr dptr;
9d99a8dd
CH		 929 __le32 numd;
930 __le32 offset;
931 __u32 rsvd12[4];
932};
933
934struct nvme_format_cmd {
935 __u8 opcode;
936 __u8 flags;
937 __u16 command_id;
938 __le32 nsid;
939 __u64 rsvd2[4];
940 __le32 cdw10;
941 __u32 rsvd11[5];
942};
943
725b3588
AB		 944struct nvme_get_log_page_command {
945 __u8 opcode;
946 __u8 flags;
947 __u16 command_id;
948 __le32 nsid;
949 __u64 rsvd2[2];
eb793e2c 950 union nvme_data_ptr dptr;
725b3588 951 __u8 lid;
9b89bc38 952 __u8 lsp; /* upper 4 bits reserved */
725b3588
AB		 953 __le16 numdl;
954 __le16 numdu;
955 __u16 rsvd11;
956 __le32 lpol;
957 __le32 lpou;
958 __u32 rsvd14[2];
959};
960
f5d11840
JA		 961struct nvme_directive_cmd {
962 __u8 opcode;
963 __u8 flags;
964 __u16 command_id;
965 __le32 nsid;
966 __u64 rsvd2[2];
967 union nvme_data_ptr dptr;
968 __le32 numd;
969 __u8 doper;
970 __u8 dtype;
971 __le16 dspec;
972 __u8 endir;
973 __u8 tdtype;
974 __u16 rsvd15;
975
976 __u32 rsvd16[3];
977};
978
eb793e2c
CH		 979/*
980 * Fabrics subcommands.
981 */
982enum nvmf_fabrics_opcode {
983 nvme_fabrics_command = 0x7f,
984};
985
986enum nvmf_capsule_command {
987 nvme_fabrics_type_property_set = 0x00,
988 nvme_fabrics_type_connect = 0x01,
989 nvme_fabrics_type_property_get = 0x04,
990};
991
992struct nvmf_common_command {
993 __u8 opcode;
994 __u8 resv1;
995 __u16 command_id;
996 __u8 fctype;
997 __u8 resv2[35];
998 __u8 ts[24];
999};
1000
1001/*
1002 * The legal cntlid range a NVMe Target will provide.
1003 * Note that cntlid of value 0 is considered illegal in the fabrics world.
1004 * Devices based on earlier specs did not have the subsystem concept;
1005 * therefore, those devices had their cntlid value set to 0 as a result.
1006 */
1007#define NVME_CNTLID_MIN 1
1008#define NVME_CNTLID_MAX 0xffef
1009#define NVME_CNTLID_DYNAMIC 0xffff
1010
1011#define MAX_DISC_LOGS 255
1012
1013/* Discovery log page entry */
1014struct nvmf_disc_rsp_page_entry {
1015 __u8 trtype;
1016 __u8 adrfam;
a446c084 1017 __u8 subtype;
eb793e2c
CH		 1018 __u8 treq;
1019 __le16 portid;
1020 __le16 cntlid;
1021 __le16 asqsz;
1022 __u8 resv8[22];
1023 char trsvcid[NVMF_TRSVCID_SIZE];
1024 __u8 resv64[192];
1025 char subnqn[NVMF_NQN_FIELD_LEN];
1026 char traddr[NVMF_TRADDR_SIZE];
1027 union tsas {
1028 char common[NVMF_TSAS_SIZE];
1029 struct rdma {
1030 __u8 qptype;
1031 __u8 prtype;
1032 __u8 cms;
1033 __u8 resv3[5];
1034 __u16 pkey;
1035 __u8 resv10[246];
1036 } rdma;
1037 } tsas;
1038};
1039
1040/* Discovery log page header */
1041struct nvmf_disc_rsp_page_hdr {
1042 __le64 genctr;
1043 __le64 numrec;
1044 __le16 recfmt;
1045 __u8 resv14[1006];
1046 struct nvmf_disc_rsp_page_entry entries[0];
1047};
1048
e6a622fd
SG		 1049enum {
1050 NVME_CONNECT_DISABLE_SQFLOW = (1 << 2),
1051};
1052
eb793e2c
CH		 1053struct nvmf_connect_command {
1054 __u8 opcode;
1055 __u8 resv1;
1056 __u16 command_id;
1057 __u8 fctype;
1058 __u8 resv2[19];
1059 union nvme_data_ptr dptr;
1060 __le16 recfmt;
1061 __le16 qid;
1062 __le16 sqsize;
1063 __u8 cattr;
1064 __u8 resv3;
1065 __le32 kato;
1066 __u8 resv4[12];
1067};
1068
1069struct nvmf_connect_data {
8e412263 1070 uuid_t hostid;
eb793e2c
CH		 1071 __le16 cntlid;
1072 char resv4[238];
1073 char subsysnqn[NVMF_NQN_FIELD_LEN];
1074 char hostnqn[NVMF_NQN_FIELD_LEN];
1075 char resv5[256];
1076};
1077
1078struct nvmf_property_set_command {
1079 __u8 opcode;
1080 __u8 resv1;
1081 __u16 command_id;
1082 __u8 fctype;
1083 __u8 resv2[35];
1084 __u8 attrib;
1085 __u8 resv3[3];
1086 __le32 offset;
1087 __le64 value;
1088 __u8 resv4[8];
1089};
1090
1091struct nvmf_property_get_command {
1092 __u8 opcode;
1093 __u8 resv1;
1094 __u16 command_id;
1095 __u8 fctype;
1096 __u8 resv2[35];
1097 __u8 attrib;
1098 __u8 resv3[3];
1099 __le32 offset;
1100 __u8 resv4[16];
1101};
1102
f9f38e33
HK		 1103struct nvme_dbbuf {
1104 __u8 opcode;
1105 __u8 flags;
1106 __u16 command_id;
1107 __u32 rsvd1[5];
1108 __le64 prp1;
1109 __le64 prp2;
1110 __u32 rsvd12[6];
1111};
1112
f5d11840 1113struct streams_directive_params {
dc1a0afb
CH		 1114 __le16 msl;
1115 __le16 nssa;
1116 __le16 nsso;
f5d11840 1117 __u8 rsvd[10];
dc1a0afb
CH		 1118 __le32 sws;
1119 __le16 sgs;
1120 __le16 nsa;
1121 __le16 nso;
f5d11840
JA		 1122 __u8 rsvd2[6];
1123};
1124
9d99a8dd
CH		 1125struct nvme_command {
1126 union {
1127 struct nvme_common_command common;
1128 struct nvme_rw_command rw;
1129 struct nvme_identify identify;
1130 struct nvme_features features;
1131 struct nvme_create_cq create_cq;
1132 struct nvme_create_sq create_sq;
1133 struct nvme_delete_queue delete_queue;
1134 struct nvme_download_firmware dlfw;
1135 struct nvme_format_cmd format;
1136 struct nvme_dsm_cmd dsm;
3b7c33b2 1137 struct nvme_write_zeroes_cmd write_zeroes;
9d99a8dd 1138 struct nvme_abort_cmd abort;
725b3588 1139 struct nvme_get_log_page_command get_log_page;
eb793e2c
CH		 1140 struct nvmf_common_command fabrics;
1141 struct nvmf_connect_command connect;
1142 struct nvmf_property_set_command prop_set;
1143 struct nvmf_property_get_command prop_get;
f9f38e33 1144 struct nvme_dbbuf dbbuf;
f5d11840 1145 struct nvme_directive_cmd directive;
9d99a8dd
CH		 1146 };
1147};
1148
7a5abb4b
CH		 1149static inline bool nvme_is_write(struct nvme_command *cmd)
1150{
eb793e2c
CH		 1151 /*
1152 * What a mess...
1153 *
1154 * Why can't we simply have a Fabrics In and Fabrics out command?
1155 */
1156 if (unlikely(cmd->common.opcode == nvme_fabrics_command))
2fd4167f 1157 return cmd->fabrics.fctype & 1;
7a5abb4b
CH		 1158 return cmd->common.opcode & 1;
1159}
1160
9d99a8dd 1161enum {
eb793e2c
CH		 1162 /*
1163 * Generic Command Status:
1164 */
9d99a8dd
CH		 1165 NVME_SC_SUCCESS = 0x0,
1166 NVME_SC_INVALID_OPCODE = 0x1,
1167 NVME_SC_INVALID_FIELD = 0x2,
1168 NVME_SC_CMDID_CONFLICT = 0x3,
1169 NVME_SC_DATA_XFER_ERROR = 0x4,
1170 NVME_SC_POWER_LOSS = 0x5,
1171 NVME_SC_INTERNAL = 0x6,
1172 NVME_SC_ABORT_REQ = 0x7,
1173 NVME_SC_ABORT_QUEUE = 0x8,
1174 NVME_SC_FUSED_FAIL = 0x9,
1175 NVME_SC_FUSED_MISSING = 0xa,
1176 NVME_SC_INVALID_NS = 0xb,
1177 NVME_SC_CMD_SEQ_ERROR = 0xc,
1178 NVME_SC_SGL_INVALID_LAST = 0xd,
1179 NVME_SC_SGL_INVALID_COUNT = 0xe,
1180 NVME_SC_SGL_INVALID_DATA = 0xf,
1181 NVME_SC_SGL_INVALID_METADATA = 0x10,
1182 NVME_SC_SGL_INVALID_TYPE = 0x11,
eb793e2c
CH		 1183
1184 NVME_SC_SGL_INVALID_OFFSET = 0x16,
1185 NVME_SC_SGL_INVALID_SUBTYPE = 0x17,
1186
93045d59
CK		 1187 NVME_SC_NS_WRITE_PROTECTED = 0x20,
1188
9d99a8dd
CH		 1189 NVME_SC_LBA_RANGE = 0x80,
1190 NVME_SC_CAP_EXCEEDED = 0x81,
1191 NVME_SC_NS_NOT_READY = 0x82,
1192 NVME_SC_RESERVATION_CONFLICT = 0x83,
eb793e2c
CH		 1193
1194 /*
1195 * Command Specific Status:
1196 */
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CH		 1197 NVME_SC_CQ_INVALID = 0x100,
1198 NVME_SC_QID_INVALID = 0x101,
1199 NVME_SC_QUEUE_SIZE = 0x102,
1200 NVME_SC_ABORT_LIMIT = 0x103,
1201 NVME_SC_ABORT_MISSING = 0x104,
1202 NVME_SC_ASYNC_LIMIT = 0x105,
1203 NVME_SC_FIRMWARE_SLOT = 0x106,
1204 NVME_SC_FIRMWARE_IMAGE = 0x107,
1205 NVME_SC_INVALID_VECTOR = 0x108,
1206 NVME_SC_INVALID_LOG_PAGE = 0x109,
1207 NVME_SC_INVALID_FORMAT = 0x10a,
a446c084 1208 NVME_SC_FW_NEEDS_CONV_RESET = 0x10b,
9d99a8dd
CH		 1209 NVME_SC_INVALID_QUEUE = 0x10c,
1210 NVME_SC_FEATURE_NOT_SAVEABLE = 0x10d,
1211 NVME_SC_FEATURE_NOT_CHANGEABLE = 0x10e,
1212 NVME_SC_FEATURE_NOT_PER_NS = 0x10f,
a446c084
CH		 1213 NVME_SC_FW_NEEDS_SUBSYS_RESET = 0x110,
1214 NVME_SC_FW_NEEDS_RESET = 0x111,
1215 NVME_SC_FW_NEEDS_MAX_TIME = 0x112,
1216 NVME_SC_FW_ACIVATE_PROHIBITED = 0x113,
1217 NVME_SC_OVERLAPPING_RANGE = 0x114,
1218 NVME_SC_NS_INSUFFICENT_CAP = 0x115,
1219 NVME_SC_NS_ID_UNAVAILABLE = 0x116,
1220 NVME_SC_NS_ALREADY_ATTACHED = 0x118,
1221 NVME_SC_NS_IS_PRIVATE = 0x119,
1222 NVME_SC_NS_NOT_ATTACHED = 0x11a,
1223 NVME_SC_THIN_PROV_NOT_SUPP = 0x11b,
1224 NVME_SC_CTRL_LIST_INVALID = 0x11c,
eb793e2c
CH		 1225
1226 /*
1227 * I/O Command Set Specific - NVM commands:
1228 */
9d99a8dd
CH		 1229 NVME_SC_BAD_ATTRIBUTES = 0x180,
1230 NVME_SC_INVALID_PI = 0x181,
1231 NVME_SC_READ_ONLY = 0x182,
3b7c33b2 1232 NVME_SC_ONCS_NOT_SUPPORTED = 0x183,
eb793e2c
CH		 1233
1234 /*
1235 * I/O Command Set Specific - Fabrics commands:
1236 */
1237 NVME_SC_CONNECT_FORMAT = 0x180,
1238 NVME_SC_CONNECT_CTRL_BUSY = 0x181,
1239 NVME_SC_CONNECT_INVALID_PARAM = 0x182,
1240 NVME_SC_CONNECT_RESTART_DISC = 0x183,
1241 NVME_SC_CONNECT_INVALID_HOST = 0x184,
1242
1243 NVME_SC_DISCOVERY_RESTART = 0x190,
1244 NVME_SC_AUTH_REQUIRED = 0x191,
1245
1246 /*
1247 * Media and Data Integrity Errors:
1248 */
9d99a8dd
CH		 1249 NVME_SC_WRITE_FAULT = 0x280,
1250 NVME_SC_READ_ERROR = 0x281,
1251 NVME_SC_GUARD_CHECK = 0x282,
1252 NVME_SC_APPTAG_CHECK = 0x283,
1253 NVME_SC_REFTAG_CHECK = 0x284,
1254 NVME_SC_COMPARE_FAILED = 0x285,
1255 NVME_SC_ACCESS_DENIED = 0x286,
a446c084 1256 NVME_SC_UNWRITTEN_BLOCK = 0x287,
eb793e2c 1257
1a376216
CH		 1258 /*
1259 * Path-related Errors:
1260 */
1261 NVME_SC_ANA_PERSISTENT_LOSS = 0x301,
1262 NVME_SC_ANA_INACCESSIBLE = 0x302,
1263 NVME_SC_ANA_TRANSITION = 0x303,
783f4a44 1264 NVME_SC_HOST_PATH_ERROR = 0x370,
1a376216 1265
9d99a8dd
CH		 1266 NVME_SC_DNR = 0x4000,
1267};
1268
1269struct nvme_completion {
eb793e2c
CH		 1270 /*
1271 * Used by Admin and Fabrics commands to return data:
1272 */
d49187e9
CH		 1273 union nvme_result {
1274 __le16 u16;
1275 __le32 u32;
1276 __le64 u64;
1277 } result;
9d99a8dd
CH		 1278 __le16 sq_head; /* how much of this queue may be reclaimed */
1279 __le16 sq_id; /* submission queue that generated this entry */
1280 __u16 command_id; /* of the command which completed */
1281 __le16 status; /* did the command fail, and if so, why? */
1282};
1283
8ef2074d
GKB		 1284#define NVME_VS(major, minor, tertiary) \
1285 (((major) << 16) | ((minor) << 8) | (tertiary))
9d99a8dd 1286
c61d788b
JT		 1287#define NVME_MAJOR(ver) ((ver) >> 16)
1288#define NVME_MINOR(ver) (((ver) >> 8) & 0xff)
1289#define NVME_TERTIARY(ver) ((ver) & 0xff)
1290
b60503ba 1291#endif /* _LINUX_NVME_H */
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