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UBUNTU: SAUCE: nvme: improve performance for virtual NVMe devices
[mirror_ubuntu-zesty-kernel.git] / include / linux / nvme.h
CommitLineData
b60503ba
MW		 1/*
2 * Definitions for the NVM Express interface
8757ad65 3 * Copyright (c) 2011-2014, Intel Corporation.
b60503ba
MW		 4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms and conditions of the GNU General Public License,
7 * version 2, as published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
b60503ba
MW		 13 */
14
15#ifndef _LINUX_NVME_H
16#define _LINUX_NVME_H
17
2812dfe3 18#include <linux/types.h>
eb793e2c
CH		 19
20/* NQN names in commands fields specified one size */
21#define NVMF_NQN_FIELD_LEN 256
22
23/* However the max length of a qualified name is another size */
24#define NVMF_NQN_SIZE 223
25
26#define NVMF_TRSVCID_SIZE 32
27#define NVMF_TRADDR_SIZE 256
28#define NVMF_TSAS_SIZE 256
29
30#define NVME_DISC_SUBSYS_NAME "nqn.2014-08.org.nvmexpress.discovery"
31
32#define NVME_RDMA_IP_PORT 4420
33
34enum nvme_subsys_type {
35 NVME_NQN_DISC = 1, /* Discovery type target subsystem */
36 NVME_NQN_NVME = 2, /* NVME type target subsystem */
37};
38
39/* Address Family codes for Discovery Log Page entry ADRFAM field */
40enum {
41 NVMF_ADDR_FAMILY_PCI = 0, /* PCIe */
42 NVMF_ADDR_FAMILY_IP4 = 1, /* IP4 */
43 NVMF_ADDR_FAMILY_IP6 = 2, /* IP6 */
44 NVMF_ADDR_FAMILY_IB = 3, /* InfiniBand */
45 NVMF_ADDR_FAMILY_FC = 4, /* Fibre Channel */
46};
47
48/* Transport Type codes for Discovery Log Page entry TRTYPE field */
49enum {
50 NVMF_TRTYPE_RDMA = 1, /* RDMA */
51 NVMF_TRTYPE_FC = 2, /* Fibre Channel */
52 NVMF_TRTYPE_LOOP = 254, /* Reserved for host usage */
53 NVMF_TRTYPE_MAX,
54};
55
56/* Transport Requirements codes for Discovery Log Page entry TREQ field */
57enum {
58 NVMF_TREQ_NOT_SPECIFIED = 0, /* Not specified */
59 NVMF_TREQ_REQUIRED = 1, /* Required */
60 NVMF_TREQ_NOT_REQUIRED = 2, /* Not Required */
61};
62
63/* RDMA QP Service Type codes for Discovery Log Page entry TSAS
64 * RDMA_QPTYPE field
65 */
66enum {
67 NVMF_RDMA_QPTYPE_CONNECTED = 0, /* Reliable Connected */
68 NVMF_RDMA_QPTYPE_DATAGRAM = 1, /* Reliable Datagram */
69};
70
71/* RDMA QP Service Type codes for Discovery Log Page entry TSAS
72 * RDMA_QPTYPE field
73 */
74enum {
75 NVMF_RDMA_PRTYPE_NOT_SPECIFIED = 0, /* No Provider Specified */
76 NVMF_RDMA_PRTYPE_IB = 1, /* InfiniBand */
77 NVMF_RDMA_PRTYPE_ROCE = 2, /* InfiniBand RoCE */
78 NVMF_RDMA_PRTYPE_ROCEV2 = 3, /* InfiniBand RoCEV2 */
79 NVMF_RDMA_PRTYPE_IWARP = 4, /* IWARP */
80};
81
82/* RDMA Connection Management Service Type codes for Discovery Log Page
83 * entry TSAS RDMA_CMS field
84 */
85enum {
86 NVMF_RDMA_CMS_RDMA_CM = 0, /* Sockets based enpoint addressing */
87};
88
89#define NVMF_AQ_DEPTH 32
2812dfe3 90
7a67cbea
CH		 91enum {
92 NVME_REG_CAP = 0x0000, /* Controller Capabilities */
93 NVME_REG_VS = 0x0008, /* Version */
94 NVME_REG_INTMS = 0x000c, /* Interrupt Mask Set */
a5b714ad 95 NVME_REG_INTMC = 0x0010, /* Interrupt Mask Clear */
7a67cbea
CH		 96 NVME_REG_CC = 0x0014, /* Controller Configuration */
97 NVME_REG_CSTS = 0x001c, /* Controller Status */
98 NVME_REG_NSSR = 0x0020, /* NVM Subsystem Reset */
99 NVME_REG_AQA = 0x0024, /* Admin Queue Attributes */
100 NVME_REG_ASQ = 0x0028, /* Admin SQ Base Address */
a5b714ad 101 NVME_REG_ACQ = 0x0030, /* Admin CQ Base Address */
7a67cbea
CH		 102 NVME_REG_CMBLOC = 0x0038, /* Controller Memory Buffer Location */
103 NVME_REG_CMBSZ = 0x003c, /* Controller Memory Buffer Size */
b60503ba
MW		 104};
105
a0cadb85 106#define NVME_CAP_MQES(cap) ((cap) & 0xffff)
22605f96 107#define NVME_CAP_TIMEOUT(cap) (((cap) >> 24) & 0xff)
f1938f6e 108#define NVME_CAP_STRIDE(cap) (((cap) >> 32) & 0xf)
dfbac8c7 109#define NVME_CAP_NSSRC(cap) (((cap) >> 36) & 0x1)
8fc23e03 110#define NVME_CAP_MPSMIN(cap) (((cap) >> 48) & 0xf)
1d090624 111#define NVME_CAP_MPSMAX(cap) (((cap) >> 52) & 0xf)
22605f96 112
8ffaadf7
JD		 113#define NVME_CMB_BIR(cmbloc) ((cmbloc) & 0x7)
114#define NVME_CMB_OFST(cmbloc) (((cmbloc) >> 12) & 0xfffff)
115#define NVME_CMB_SZ(cmbsz) (((cmbsz) >> 12) & 0xfffff)
116#define NVME_CMB_SZU(cmbsz) (((cmbsz) >> 8) & 0xf)
117
118#define NVME_CMB_WDS(cmbsz) ((cmbsz) & 0x10)
119#define NVME_CMB_RDS(cmbsz) ((cmbsz) & 0x8)
120#define NVME_CMB_LISTS(cmbsz) ((cmbsz) & 0x4)
121#define NVME_CMB_CQS(cmbsz) ((cmbsz) & 0x2)
122#define NVME_CMB_SQS(cmbsz) ((cmbsz) & 0x1)
123
69cd27e2
CH		 124/*
125 * Submission and Completion Queue Entry Sizes for the NVM command set.
126 * (In bytes and specified as a power of two (2^n)).
127 */
128#define NVME_NVM_IOSQES 6
129#define NVME_NVM_IOCQES 4
130
b60503ba
MW		 131enum {
132 NVME_CC_ENABLE = 1 << 0,
133 NVME_CC_CSS_NVM = 0 << 4,
134 NVME_CC_MPS_SHIFT = 7,
135 NVME_CC_ARB_RR = 0 << 11,
136 NVME_CC_ARB_WRRU = 1 << 11,
7f53f9d2
MW		 137 NVME_CC_ARB_VS = 7 << 11,
138 NVME_CC_SHN_NONE = 0 << 14,
139 NVME_CC_SHN_NORMAL = 1 << 14,
140 NVME_CC_SHN_ABRUPT = 2 << 14,
1894d8f1 141 NVME_CC_SHN_MASK = 3 << 14,
69cd27e2
CH		 142 NVME_CC_IOSQES = NVME_NVM_IOSQES << 16,
143 NVME_CC_IOCQES = NVME_NVM_IOCQES << 20,
b60503ba
MW		 144 NVME_CSTS_RDY = 1 << 0,
145 NVME_CSTS_CFS = 1 << 1,
dfbac8c7 146 NVME_CSTS_NSSRO = 1 << 4,
b60503ba
MW		 147 NVME_CSTS_SHST_NORMAL = 0 << 2,
148 NVME_CSTS_SHST_OCCUR = 1 << 2,
149 NVME_CSTS_SHST_CMPLT = 2 << 2,
1894d8f1 150 NVME_CSTS_SHST_MASK = 3 << 2,
b60503ba
MW		 151};
152
9d99a8dd
CH		 153struct nvme_id_power_state {
154 __le16 max_power; /* centiwatts */
155 __u8 rsvd2;
156 __u8 flags;
157 __le32 entry_lat; /* microseconds */
158 __le32 exit_lat; /* microseconds */
159 __u8 read_tput;
160 __u8 read_lat;
161 __u8 write_tput;
162 __u8 write_lat;
163 __le16 idle_power;
164 __u8 idle_scale;
165 __u8 rsvd19;
166 __le16 active_power;
167 __u8 active_work_scale;
168 __u8 rsvd23[9];
169};
170
171enum {
172 NVME_PS_FLAGS_MAX_POWER_SCALE = 1 << 0,
173 NVME_PS_FLAGS_NON_OP_STATE = 1 << 1,
174};
175
176struct nvme_id_ctrl {
177 __le16 vid;
178 __le16 ssvid;
179 char sn[20];
180 char mn[40];
181 char fr[8];
182 __u8 rab;
183 __u8 ieee[3];
a446c084 184 __u8 cmic;
9d99a8dd 185 __u8 mdts;
08c69640
CH		 186 __le16 cntlid;
187 __le32 ver;
14e974a8
CH		 188 __le32 rtd3r;
189 __le32 rtd3e;
190 __le32 oaes;
eb793e2c
CH		 191 __le32 ctratt;
192 __u8 rsvd100[156];
9d99a8dd
CH		 193 __le16 oacs;
194 __u8 acl;
195 __u8 aerl;
196 __u8 frmw;
197 __u8 lpa;
198 __u8 elpe;
199 __u8 npss;
200 __u8 avscc;
201 __u8 apsta;
202 __le16 wctemp;
203 __le16 cctemp;
a446c084
CH		 204 __le16 mtfa;
205 __le32 hmpre;
206 __le32 hmmin;
207 __u8 tnvmcap[16];
208 __u8 unvmcap[16];
209 __le32 rpmbs;
210 __u8 rsvd316[4];
7b89eae2
SG		 211 __le16 kas;
212 __u8 rsvd322[190];
9d99a8dd
CH		 213 __u8 sqes;
214 __u8 cqes;
eb793e2c 215 __le16 maxcmd;
9d99a8dd
CH		 216 __le32 nn;
217 __le16 oncs;
218 __le16 fuses;
219 __u8 fna;
220 __u8 vwc;
221 __le16 awun;
222 __le16 awupf;
223 __u8 nvscc;
224 __u8 rsvd531;
225 __le16 acwu;
226 __u8 rsvd534[2];
227 __le32 sgls;
eb793e2c
CH		 228 __u8 rsvd540[228];
229 char subnqn[256];
230 __u8 rsvd1024[768];
231 __le32 ioccsz;
232 __le32 iorcsz;
233 __le16 icdoff;
234 __u8 ctrattr;
235 __u8 msdbd;
236 __u8 rsvd1804[244];
9d99a8dd
CH		 237 struct nvme_id_power_state psd[32];
238 __u8 vs[1024];
239};
240
241enum {
242 NVME_CTRL_ONCS_COMPARE = 1 << 0,
243 NVME_CTRL_ONCS_WRITE_UNCORRECTABLE = 1 << 1,
244 NVME_CTRL_ONCS_DSM = 1 << 2,
3b7c33b2 245 NVME_CTRL_ONCS_WRITE_ZEROES = 1 << 3,
9d99a8dd
CH		 246 NVME_CTRL_VWC_PRESENT = 1 << 0,
247};
248
249struct nvme_lbaf {
250 __le16 ms;
251 __u8 ds;
252 __u8 rp;
253};
254
255struct nvme_id_ns {
256 __le64 nsze;
257 __le64 ncap;
258 __le64 nuse;
259 __u8 nsfeat;
260 __u8 nlbaf;
261 __u8 flbas;
262 __u8 mc;
263 __u8 dpc;
264 __u8 dps;
265 __u8 nmic;
266 __u8 rescap;
267 __u8 fpi;
268 __u8 rsvd33;
269 __le16 nawun;
270 __le16 nawupf;
271 __le16 nacwu;
272 __le16 nabsn;
273 __le16 nabo;
274 __le16 nabspf;
275 __u16 rsvd46;
a446c084 276 __u8 nvmcap[16];
9d99a8dd
CH		 277 __u8 rsvd64[40];
278 __u8 nguid[16];
279 __u8 eui64[8];
280 struct nvme_lbaf lbaf[16];
281 __u8 rsvd192[192];
282 __u8 vs[3712];
283};
284
329dd768
CH		 285enum {
286 NVME_ID_CNS_NS = 0x00,
287 NVME_ID_CNS_CTRL = 0x01,
288 NVME_ID_CNS_NS_ACTIVE_LIST = 0x02,
289 NVME_ID_CNS_NS_PRESENT_LIST = 0x10,
290 NVME_ID_CNS_NS_PRESENT = 0x11,
291 NVME_ID_CNS_CTRL_NS_LIST = 0x12,
292 NVME_ID_CNS_CTRL_LIST = 0x13,
293};
294
9d99a8dd
CH		 295enum {
296 NVME_NS_FEAT_THIN = 1 << 0,
297 NVME_NS_FLBAS_LBA_MASK = 0xf,
298 NVME_NS_FLBAS_META_EXT = 0x10,
299 NVME_LBAF_RP_BEST = 0,
300 NVME_LBAF_RP_BETTER = 1,
301 NVME_LBAF_RP_GOOD = 2,
302 NVME_LBAF_RP_DEGRADED = 3,
303 NVME_NS_DPC_PI_LAST = 1 << 4,
304 NVME_NS_DPC_PI_FIRST = 1 << 3,
305 NVME_NS_DPC_PI_TYPE3 = 1 << 2,
306 NVME_NS_DPC_PI_TYPE2 = 1 << 1,
307 NVME_NS_DPC_PI_TYPE1 = 1 << 0,
308 NVME_NS_DPS_PI_FIRST = 1 << 3,
309 NVME_NS_DPS_PI_MASK = 0x7,
310 NVME_NS_DPS_PI_TYPE1 = 1,
311 NVME_NS_DPS_PI_TYPE2 = 2,
312 NVME_NS_DPS_PI_TYPE3 = 3,
313};
314
315struct nvme_smart_log {
316 __u8 critical_warning;
317 __u8 temperature[2];
318 __u8 avail_spare;
319 __u8 spare_thresh;
320 __u8 percent_used;
321 __u8 rsvd6[26];
322 __u8 data_units_read[16];
323 __u8 data_units_written[16];
324 __u8 host_reads[16];
325 __u8 host_writes[16];
326 __u8 ctrl_busy_time[16];
327 __u8 power_cycles[16];
328 __u8 power_on_hours[16];
329 __u8 unsafe_shutdowns[16];
330 __u8 media_errors[16];
331 __u8 num_err_log_entries[16];
332 __le32 warning_temp_time;
333 __le32 critical_comp_time;
334 __le16 temp_sensor[8];
335 __u8 rsvd216[296];
336};
337
338enum {
339 NVME_SMART_CRIT_SPARE = 1 << 0,
340 NVME_SMART_CRIT_TEMPERATURE = 1 << 1,
341 NVME_SMART_CRIT_RELIABILITY = 1 << 2,
342 NVME_SMART_CRIT_MEDIA = 1 << 3,
343 NVME_SMART_CRIT_VOLATILE_MEMORY = 1 << 4,
344};
345
346enum {
347 NVME_AER_NOTICE_NS_CHANGED = 0x0002,
348};
349
350struct nvme_lba_range_type {
351 __u8 type;
352 __u8 attributes;
353 __u8 rsvd2[14];
354 __u64 slba;
355 __u64 nlb;
356 __u8 guid[16];
357 __u8 rsvd48[16];
358};
359
360enum {
361 NVME_LBART_TYPE_FS = 0x01,
362 NVME_LBART_TYPE_RAID = 0x02,
363 NVME_LBART_TYPE_CACHE = 0x03,
364 NVME_LBART_TYPE_SWAP = 0x04,
365
366 NVME_LBART_ATTRIB_TEMP = 1 << 0,
367 NVME_LBART_ATTRIB_HIDE = 1 << 1,
368};
369
370struct nvme_reservation_status {
371 __le32 gen;
372 __u8 rtype;
373 __u8 regctl[2];
374 __u8 resv5[2];
375 __u8 ptpls;
376 __u8 resv10[13];
377 struct {
378 __le16 cntlid;
379 __u8 rcsts;
380 __u8 resv3[5];
381 __le64 hostid;
382 __le64 rkey;
383 } regctl_ds[];
384};
385
79f370ea
CH		 386enum nvme_async_event_type {
387 NVME_AER_TYPE_ERROR = 0,
388 NVME_AER_TYPE_SMART = 1,
389 NVME_AER_TYPE_NOTICE = 2,
390};
391
9d99a8dd
CH		 392/* I/O commands */
393
394enum nvme_opcode {
395 nvme_cmd_flush = 0x00,
396 nvme_cmd_write = 0x01,
397 nvme_cmd_read = 0x02,
398 nvme_cmd_write_uncor = 0x04,
399 nvme_cmd_compare = 0x05,
400 nvme_cmd_write_zeroes = 0x08,
401 nvme_cmd_dsm = 0x09,
402 nvme_cmd_resv_register = 0x0d,
403 nvme_cmd_resv_report = 0x0e,
404 nvme_cmd_resv_acquire = 0x11,
405 nvme_cmd_resv_release = 0x15,
406};
407
eb793e2c
CH		 408/*
409 * Descriptor subtype - lower 4 bits of nvme_(keyed_)sgl_desc identifier
410 *
411 * @NVME_SGL_FMT_ADDRESS: absolute address of the data block
412 * @NVME_SGL_FMT_OFFSET: relative offset of the in-capsule data block
413 * @NVME_SGL_FMT_INVALIDATE: RDMA transport specific remote invalidation
414 * request subtype
415 */
416enum {
417 NVME_SGL_FMT_ADDRESS = 0x00,
418 NVME_SGL_FMT_OFFSET = 0x01,
419 NVME_SGL_FMT_INVALIDATE = 0x0f,
420};
421
422/*
423 * Descriptor type - upper 4 bits of nvme_(keyed_)sgl_desc identifier
424 *
425 * For struct nvme_sgl_desc:
426 * @NVME_SGL_FMT_DATA_DESC: data block descriptor
427 * @NVME_SGL_FMT_SEG_DESC: sgl segment descriptor
428 * @NVME_SGL_FMT_LAST_SEG_DESC: last sgl segment descriptor
429 *
430 * For struct nvme_keyed_sgl_desc:
431 * @NVME_KEY_SGL_FMT_DATA_DESC: keyed data block descriptor
432 */
433enum {
434 NVME_SGL_FMT_DATA_DESC = 0x00,
435 NVME_SGL_FMT_SEG_DESC = 0x02,
436 NVME_SGL_FMT_LAST_SEG_DESC = 0x03,
437 NVME_KEY_SGL_FMT_DATA_DESC = 0x04,
438};
439
440struct nvme_sgl_desc {
441 __le64 addr;
442 __le32 length;
443 __u8 rsvd[3];
444 __u8 type;
445};
446
447struct nvme_keyed_sgl_desc {
448 __le64 addr;
449 __u8 length[3];
450 __u8 key[4];
451 __u8 type;
452};
453
454union nvme_data_ptr {
455 struct {
456 __le64 prp1;
457 __le64 prp2;
458 };
459 struct nvme_sgl_desc sgl;
460 struct nvme_keyed_sgl_desc ksgl;
461};
462
3972be23
JS		 463/*
464 * Lowest two bits of our flags field (FUSE field in the spec):
465 *
466 * @NVME_CMD_FUSE_FIRST: Fused Operation, first command
467 * @NVME_CMD_FUSE_SECOND: Fused Operation, second command
468 *
469 * Highest two bits in our flags field (PSDT field in the spec):
470 *
471 * @NVME_CMD_PSDT_SGL_METABUF: Use SGLS for this transfer,
472 * If used, MPTR contains addr of single physical buffer (byte aligned).
473 * @NVME_CMD_PSDT_SGL_METASEG: Use SGLS for this transfer,
474 * If used, MPTR contains an address of an SGL segment containing
475 * exactly 1 SGL descriptor (qword aligned).
476 */
477enum {
478 NVME_CMD_FUSE_FIRST = (1 << 0),
479 NVME_CMD_FUSE_SECOND = (1 << 1),
480
481 NVME_CMD_SGL_METABUF = (1 << 6),
482 NVME_CMD_SGL_METASEG = (1 << 7),
483 NVME_CMD_SGL_ALL = NVME_CMD_SGL_METABUF | NVME_CMD_SGL_METASEG,
484};
485
9d99a8dd
CH		 486struct nvme_common_command {
487 __u8 opcode;
488 __u8 flags;
489 __u16 command_id;
490 __le32 nsid;
491 __le32 cdw2[2];
492 __le64 metadata;
eb793e2c 493 union nvme_data_ptr dptr;
9d99a8dd
CH		 494 __le32 cdw10[6];
495};
496
497struct nvme_rw_command {
498 __u8 opcode;
499 __u8 flags;
500 __u16 command_id;
501 __le32 nsid;
502 __u64 rsvd2;
503 __le64 metadata;
eb793e2c 504 union nvme_data_ptr dptr;
9d99a8dd
CH		 505 __le64 slba;
506 __le16 length;
507 __le16 control;
508 __le32 dsmgmt;
509 __le32 reftag;
510 __le16 apptag;
511 __le16 appmask;
512};
513
514enum {
515 NVME_RW_LR = 1 << 15,
516 NVME_RW_FUA = 1 << 14,
517 NVME_RW_DSM_FREQ_UNSPEC = 0,
518 NVME_RW_DSM_FREQ_TYPICAL = 1,
519 NVME_RW_DSM_FREQ_RARE = 2,
520 NVME_RW_DSM_FREQ_READS = 3,
521 NVME_RW_DSM_FREQ_WRITES = 4,
522 NVME_RW_DSM_FREQ_RW = 5,
523 NVME_RW_DSM_FREQ_ONCE = 6,
524 NVME_RW_DSM_FREQ_PREFETCH = 7,
525 NVME_RW_DSM_FREQ_TEMP = 8,
526 NVME_RW_DSM_LATENCY_NONE = 0 << 4,
527 NVME_RW_DSM_LATENCY_IDLE = 1 << 4,
528 NVME_RW_DSM_LATENCY_NORM = 2 << 4,
529 NVME_RW_DSM_LATENCY_LOW = 3 << 4,
530 NVME_RW_DSM_SEQ_REQ = 1 << 6,
531 NVME_RW_DSM_COMPRESSED = 1 << 7,
532 NVME_RW_PRINFO_PRCHK_REF = 1 << 10,
533 NVME_RW_PRINFO_PRCHK_APP = 1 << 11,
534 NVME_RW_PRINFO_PRCHK_GUARD = 1 << 12,
535 NVME_RW_PRINFO_PRACT = 1 << 13,
536};
537
538struct nvme_dsm_cmd {
539 __u8 opcode;
540 __u8 flags;
541 __u16 command_id;
542 __le32 nsid;
543 __u64 rsvd2[2];
eb793e2c 544 union nvme_data_ptr dptr;
9d99a8dd
CH		 545 __le32 nr;
546 __le32 attributes;
547 __u32 rsvd12[4];
548};
549
550enum {
551 NVME_DSMGMT_IDR = 1 << 0,
552 NVME_DSMGMT_IDW = 1 << 1,
553 NVME_DSMGMT_AD = 1 << 2,
554};
555
556struct nvme_dsm_range {
557 __le32 cattr;
558 __le32 nlb;
559 __le64 slba;
560};
561
3b7c33b2
CK		 562struct nvme_write_zeroes_cmd {
563 __u8 opcode;
564 __u8 flags;
565 __u16 command_id;
566 __le32 nsid;
567 __u64 rsvd2;
568 __le64 metadata;
569 union nvme_data_ptr dptr;
570 __le64 slba;
571 __le16 length;
572 __le16 control;
573 __le32 dsmgmt;
574 __le32 reftag;
575 __le16 apptag;
576 __le16 appmask;
577};
578
9d99a8dd
CH		 579/* Admin commands */
580
581enum nvme_admin_opcode {
582 nvme_admin_delete_sq = 0x00,
583 nvme_admin_create_sq = 0x01,
584 nvme_admin_get_log_page = 0x02,
585 nvme_admin_delete_cq = 0x04,
586 nvme_admin_create_cq = 0x05,
587 nvme_admin_identify = 0x06,
588 nvme_admin_abort_cmd = 0x08,
589 nvme_admin_set_features = 0x09,
590 nvme_admin_get_features = 0x0a,
591 nvme_admin_async_event = 0x0c,
a446c084 592 nvme_admin_ns_mgmt = 0x0d,
9d99a8dd
CH		 593 nvme_admin_activate_fw = 0x10,
594 nvme_admin_download_fw = 0x11,
a446c084 595 nvme_admin_ns_attach = 0x15,
7b89eae2 596 nvme_admin_keep_alive = 0x18,
9d99a8dd
CH		 597 nvme_admin_format_nvm = 0x80,
598 nvme_admin_security_send = 0x81,
599 nvme_admin_security_recv = 0x82,
12e6f749
RN		 600#ifdef CONFIG_NVME_VENDOR_EXT_GOOGLE
601 nvme_admin_doorbell_memory = 0xC0,
602#endif
9d99a8dd
CH		 603};
604
605enum {
606 NVME_QUEUE_PHYS_CONTIG = (1 << 0),
607 NVME_CQ_IRQ_ENABLED = (1 << 1),
608 NVME_SQ_PRIO_URGENT = (0 << 1),
609 NVME_SQ_PRIO_HIGH = (1 << 1),
610 NVME_SQ_PRIO_MEDIUM = (2 << 1),
611 NVME_SQ_PRIO_LOW = (3 << 1),
612 NVME_FEAT_ARBITRATION = 0x01,
613 NVME_FEAT_POWER_MGMT = 0x02,
614 NVME_FEAT_LBA_RANGE = 0x03,
615 NVME_FEAT_TEMP_THRESH = 0x04,
616 NVME_FEAT_ERR_RECOVERY = 0x05,
617 NVME_FEAT_VOLATILE_WC = 0x06,
618 NVME_FEAT_NUM_QUEUES = 0x07,
619 NVME_FEAT_IRQ_COALESCE = 0x08,
620 NVME_FEAT_IRQ_CONFIG = 0x09,
621 NVME_FEAT_WRITE_ATOMIC = 0x0a,
622 NVME_FEAT_ASYNC_EVENT = 0x0b,
623 NVME_FEAT_AUTO_PST = 0x0c,
a446c084 624 NVME_FEAT_HOST_MEM_BUF = 0x0d,
7b89eae2 625 NVME_FEAT_KATO = 0x0f,
9d99a8dd
CH		 626 NVME_FEAT_SW_PROGRESS = 0x80,
627 NVME_FEAT_HOST_ID = 0x81,
628 NVME_FEAT_RESV_MASK = 0x82,
629 NVME_FEAT_RESV_PERSIST = 0x83,
630 NVME_LOG_ERROR = 0x01,
631 NVME_LOG_SMART = 0x02,
632 NVME_LOG_FW_SLOT = 0x03,
eb793e2c 633 NVME_LOG_DISC = 0x70,
9d99a8dd
CH		 634 NVME_LOG_RESERVATION = 0x80,
635 NVME_FWACT_REPL = (0 << 3),
636 NVME_FWACT_REPL_ACTV = (1 << 3),
637 NVME_FWACT_ACTV = (2 << 3),
638};
639
640struct nvme_identify {
641 __u8 opcode;
642 __u8 flags;
643 __u16 command_id;
644 __le32 nsid;
645 __u64 rsvd2[2];
eb793e2c 646 union nvme_data_ptr dptr;
9d99a8dd
CH		 647 __le32 cns;
648 __u32 rsvd11[5];
649};
650
651struct nvme_features {
652 __u8 opcode;
653 __u8 flags;
654 __u16 command_id;
655 __le32 nsid;
656 __u64 rsvd2[2];
eb793e2c 657 union nvme_data_ptr dptr;
9d99a8dd
CH		 658 __le32 fid;
659 __le32 dword11;
660 __u32 rsvd12[4];
661};
662
663struct nvme_create_cq {
664 __u8 opcode;
665 __u8 flags;
666 __u16 command_id;
667 __u32 rsvd1[5];
668 __le64 prp1;
669 __u64 rsvd8;
670 __le16 cqid;
671 __le16 qsize;
672 __le16 cq_flags;
673 __le16 irq_vector;
674 __u32 rsvd12[4];
675};
676
677struct nvme_create_sq {
678 __u8 opcode;
679 __u8 flags;
680 __u16 command_id;
681 __u32 rsvd1[5];
682 __le64 prp1;
683 __u64 rsvd8;
684 __le16 sqid;
685 __le16 qsize;
686 __le16 sq_flags;
687 __le16 cqid;
688 __u32 rsvd12[4];
689};
690
691struct nvme_delete_queue {
692 __u8 opcode;
693 __u8 flags;
694 __u16 command_id;
695 __u32 rsvd1[9];
696 __le16 qid;
697 __u16 rsvd10;
698 __u32 rsvd11[5];
699};
700
701struct nvme_abort_cmd {
702 __u8 opcode;
703 __u8 flags;
704 __u16 command_id;
705 __u32 rsvd1[9];
706 __le16 sqid;
707 __u16 cid;
708 __u32 rsvd11[5];
709};
710
711struct nvme_download_firmware {
712 __u8 opcode;
713 __u8 flags;
714 __u16 command_id;
715 __u32 rsvd1[5];
eb793e2c 716 union nvme_data_ptr dptr;
9d99a8dd
CH		 717 __le32 numd;
718 __le32 offset;
719 __u32 rsvd12[4];
720};
721
722struct nvme_format_cmd {
723 __u8 opcode;
724 __u8 flags;
725 __u16 command_id;
726 __le32 nsid;
727 __u64 rsvd2[4];
728 __le32 cdw10;
729 __u32 rsvd11[5];
730};
731
725b3588
AB		 732struct nvme_get_log_page_command {
733 __u8 opcode;
734 __u8 flags;
735 __u16 command_id;
736 __le32 nsid;
737 __u64 rsvd2[2];
eb793e2c 738 union nvme_data_ptr dptr;
725b3588
AB		 739 __u8 lid;
740 __u8 rsvd10;
741 __le16 numdl;
742 __le16 numdu;
743 __u16 rsvd11;
744 __le32 lpol;
745 __le32 lpou;
746 __u32 rsvd14[2];
747};
748
eb793e2c
CH		 749/*
750 * Fabrics subcommands.
751 */
752enum nvmf_fabrics_opcode {
753 nvme_fabrics_command = 0x7f,
754};
755
756enum nvmf_capsule_command {
757 nvme_fabrics_type_property_set = 0x00,
758 nvme_fabrics_type_connect = 0x01,
759 nvme_fabrics_type_property_get = 0x04,
760};
761
762struct nvmf_common_command {
763 __u8 opcode;
764 __u8 resv1;
765 __u16 command_id;
766 __u8 fctype;
767 __u8 resv2[35];
768 __u8 ts[24];
769};
770
771/*
772 * The legal cntlid range a NVMe Target will provide.
773 * Note that cntlid of value 0 is considered illegal in the fabrics world.
774 * Devices based on earlier specs did not have the subsystem concept;
775 * therefore, those devices had their cntlid value set to 0 as a result.
776 */
777#define NVME_CNTLID_MIN 1
778#define NVME_CNTLID_MAX 0xffef
779#define NVME_CNTLID_DYNAMIC 0xffff
780
781#define MAX_DISC_LOGS 255
782
783/* Discovery log page entry */
784struct nvmf_disc_rsp_page_entry {
785 __u8 trtype;
786 __u8 adrfam;
a446c084 787 __u8 subtype;
eb793e2c
CH		 788 __u8 treq;
789 __le16 portid;
790 __le16 cntlid;
791 __le16 asqsz;
792 __u8 resv8[22];
793 char trsvcid[NVMF_TRSVCID_SIZE];
794 __u8 resv64[192];
795 char subnqn[NVMF_NQN_FIELD_LEN];
796 char traddr[NVMF_TRADDR_SIZE];
797 union tsas {
798 char common[NVMF_TSAS_SIZE];
799 struct rdma {
800 __u8 qptype;
801 __u8 prtype;
802 __u8 cms;
803 __u8 resv3[5];
804 __u16 pkey;
805 __u8 resv10[246];
806 } rdma;
807 } tsas;
808};
809
810/* Discovery log page header */
811struct nvmf_disc_rsp_page_hdr {
812 __le64 genctr;
813 __le64 numrec;
814 __le16 recfmt;
815 __u8 resv14[1006];
816 struct nvmf_disc_rsp_page_entry entries[0];
817};
818
819struct nvmf_connect_command {
820 __u8 opcode;
821 __u8 resv1;
822 __u16 command_id;
823 __u8 fctype;
824 __u8 resv2[19];
825 union nvme_data_ptr dptr;
826 __le16 recfmt;
827 __le16 qid;
828 __le16 sqsize;
829 __u8 cattr;
830 __u8 resv3;
831 __le32 kato;
832 __u8 resv4[12];
833};
834
835struct nvmf_connect_data {
8d63687a 836 __u8 hostid[16];
eb793e2c
CH		 837 __le16 cntlid;
838 char resv4[238];
839 char subsysnqn[NVMF_NQN_FIELD_LEN];
840 char hostnqn[NVMF_NQN_FIELD_LEN];
841 char resv5[256];
842};
843
844struct nvmf_property_set_command {
845 __u8 opcode;
846 __u8 resv1;
847 __u16 command_id;
848 __u8 fctype;
849 __u8 resv2[35];
850 __u8 attrib;
851 __u8 resv3[3];
852 __le32 offset;
853 __le64 value;
854 __u8 resv4[8];
855};
856
857struct nvmf_property_get_command {
858 __u8 opcode;
859 __u8 resv1;
860 __u16 command_id;
861 __u8 fctype;
862 __u8 resv2[35];
863 __u8 attrib;
864 __u8 resv3[3];
865 __le32 offset;
866 __u8 resv4[16];
867};
868
12e6f749
RN		 869#ifdef CONFIG_NVME_VENDOR_EXT_GOOGLE
870struct nvme_doorbell_memory {
871 __u8 opcode;
872 __u8 flags;
873 __u16 command_id;
874 __u32 rsvd1[5];
875 __le64 prp1;
876 __le64 prp2;
877 __u32 rsvd12[6];
878};
879#endif
880
9d99a8dd
CH		 881struct nvme_command {
882 union {
883 struct nvme_common_command common;
884 struct nvme_rw_command rw;
885 struct nvme_identify identify;
886 struct nvme_features features;
887 struct nvme_create_cq create_cq;
888 struct nvme_create_sq create_sq;
889 struct nvme_delete_queue delete_queue;
890 struct nvme_download_firmware dlfw;
891 struct nvme_format_cmd format;
892 struct nvme_dsm_cmd dsm;
3b7c33b2 893 struct nvme_write_zeroes_cmd write_zeroes;
9d99a8dd 894 struct nvme_abort_cmd abort;
12e6f749
RN		 895#ifdef CONFIG_NVME_VENDOR_EXT_GOOGLE
896 struct nvme_doorbell_memory doorbell_memory;
897#endif
725b3588 898 struct nvme_get_log_page_command get_log_page;
eb793e2c
CH		 899 struct nvmf_common_command fabrics;
900 struct nvmf_connect_command connect;
901 struct nvmf_property_set_command prop_set;
902 struct nvmf_property_get_command prop_get;
9d99a8dd
CH		 903 };
904};
905
7a5abb4b
CH		 906static inline bool nvme_is_write(struct nvme_command *cmd)
907{
eb793e2c
CH		 908 /*
909 * What a mess...
910 *
911 * Why can't we simply have a Fabrics In and Fabrics out command?
912 */
913 if (unlikely(cmd->common.opcode == nvme_fabrics_command))
914 return cmd->fabrics.opcode & 1;
7a5abb4b
CH		 915 return cmd->common.opcode & 1;
916}
917
9d99a8dd 918enum {
eb793e2c
CH		 919 /*
920 * Generic Command Status:
921 */
9d99a8dd
CH		 922 NVME_SC_SUCCESS = 0x0,
923 NVME_SC_INVALID_OPCODE = 0x1,
924 NVME_SC_INVALID_FIELD = 0x2,
925 NVME_SC_CMDID_CONFLICT = 0x3,
926 NVME_SC_DATA_XFER_ERROR = 0x4,
927 NVME_SC_POWER_LOSS = 0x5,
928 NVME_SC_INTERNAL = 0x6,
929 NVME_SC_ABORT_REQ = 0x7,
930 NVME_SC_ABORT_QUEUE = 0x8,
931 NVME_SC_FUSED_FAIL = 0x9,
932 NVME_SC_FUSED_MISSING = 0xa,
933 NVME_SC_INVALID_NS = 0xb,
934 NVME_SC_CMD_SEQ_ERROR = 0xc,
935 NVME_SC_SGL_INVALID_LAST = 0xd,
936 NVME_SC_SGL_INVALID_COUNT = 0xe,
937 NVME_SC_SGL_INVALID_DATA = 0xf,
938 NVME_SC_SGL_INVALID_METADATA = 0x10,
939 NVME_SC_SGL_INVALID_TYPE = 0x11,
eb793e2c
CH		 940
941 NVME_SC_SGL_INVALID_OFFSET = 0x16,
942 NVME_SC_SGL_INVALID_SUBTYPE = 0x17,
943
9d99a8dd
CH		 944 NVME_SC_LBA_RANGE = 0x80,
945 NVME_SC_CAP_EXCEEDED = 0x81,
946 NVME_SC_NS_NOT_READY = 0x82,
947 NVME_SC_RESERVATION_CONFLICT = 0x83,
eb793e2c
CH		 948
949 /*
950 * Command Specific Status:
951 */
9d99a8dd
CH		 952 NVME_SC_CQ_INVALID = 0x100,
953 NVME_SC_QID_INVALID = 0x101,
954 NVME_SC_QUEUE_SIZE = 0x102,
955 NVME_SC_ABORT_LIMIT = 0x103,
956 NVME_SC_ABORT_MISSING = 0x104,
957 NVME_SC_ASYNC_LIMIT = 0x105,
958 NVME_SC_FIRMWARE_SLOT = 0x106,
959 NVME_SC_FIRMWARE_IMAGE = 0x107,
960 NVME_SC_INVALID_VECTOR = 0x108,
961 NVME_SC_INVALID_LOG_PAGE = 0x109,
962 NVME_SC_INVALID_FORMAT = 0x10a,
a446c084 963 NVME_SC_FW_NEEDS_CONV_RESET = 0x10b,
9d99a8dd
CH		 964 NVME_SC_INVALID_QUEUE = 0x10c,
965 NVME_SC_FEATURE_NOT_SAVEABLE = 0x10d,
966 NVME_SC_FEATURE_NOT_CHANGEABLE = 0x10e,
967 NVME_SC_FEATURE_NOT_PER_NS = 0x10f,
a446c084
CH		 968 NVME_SC_FW_NEEDS_SUBSYS_RESET = 0x110,
969 NVME_SC_FW_NEEDS_RESET = 0x111,
970 NVME_SC_FW_NEEDS_MAX_TIME = 0x112,
971 NVME_SC_FW_ACIVATE_PROHIBITED = 0x113,
972 NVME_SC_OVERLAPPING_RANGE = 0x114,
973 NVME_SC_NS_INSUFFICENT_CAP = 0x115,
974 NVME_SC_NS_ID_UNAVAILABLE = 0x116,
975 NVME_SC_NS_ALREADY_ATTACHED = 0x118,
976 NVME_SC_NS_IS_PRIVATE = 0x119,
977 NVME_SC_NS_NOT_ATTACHED = 0x11a,
978 NVME_SC_THIN_PROV_NOT_SUPP = 0x11b,
979 NVME_SC_CTRL_LIST_INVALID = 0x11c,
eb793e2c
CH		 980
981 /*
982 * I/O Command Set Specific - NVM commands:
983 */
9d99a8dd
CH		 984 NVME_SC_BAD_ATTRIBUTES = 0x180,
985 NVME_SC_INVALID_PI = 0x181,
986 NVME_SC_READ_ONLY = 0x182,
3b7c33b2 987 NVME_SC_ONCS_NOT_SUPPORTED = 0x183,
12e6f749
RN		 988#ifdef CONFIG_NVME_VENDOR_EXT_GOOGLE
989 NVME_SC_DOORBELL_MEMORY_INVALID = 0x1C0,
990#endif
eb793e2c
CH		 991
992 /*
993 * I/O Command Set Specific - Fabrics commands:
994 */
995 NVME_SC_CONNECT_FORMAT = 0x180,
996 NVME_SC_CONNECT_CTRL_BUSY = 0x181,
997 NVME_SC_CONNECT_INVALID_PARAM = 0x182,
998 NVME_SC_CONNECT_RESTART_DISC = 0x183,
999 NVME_SC_CONNECT_INVALID_HOST = 0x184,
1000
1001 NVME_SC_DISCOVERY_RESTART = 0x190,
1002 NVME_SC_AUTH_REQUIRED = 0x191,
1003
1004 /*
1005 * Media and Data Integrity Errors:
1006 */
9d99a8dd
CH		 1007 NVME_SC_WRITE_FAULT = 0x280,
1008 NVME_SC_READ_ERROR = 0x281,
1009 NVME_SC_GUARD_CHECK = 0x282,
1010 NVME_SC_APPTAG_CHECK = 0x283,
1011 NVME_SC_REFTAG_CHECK = 0x284,
1012 NVME_SC_COMPARE_FAILED = 0x285,
1013 NVME_SC_ACCESS_DENIED = 0x286,
a446c084 1014 NVME_SC_UNWRITTEN_BLOCK = 0x287,
eb793e2c 1015
9d99a8dd 1016 NVME_SC_DNR = 0x4000,
cba3bdfd
JS		 1017
1018
1019 /*
1020 * FC Transport-specific error status values for NVME commands
1021 *
1022 * Transport-specific status code values must be in the range 0xB0..0xBF
1023 */
1024
1025 /* Generic FC failure - catchall */
1026 NVME_SC_FC_TRANSPORT_ERROR = 0x00B0,
1027
1028 /* I/O failure due to FC ABTS'd */
1029 NVME_SC_FC_TRANSPORT_ABORTED = 0x00B1,
9d99a8dd
CH		 1030};
1031
1032struct nvme_completion {
eb793e2c
CH		 1033 /*
1034 * Used by Admin and Fabrics commands to return data:
1035 */
d49187e9
CH		 1036 union nvme_result {
1037 __le16 u16;
1038 __le32 u32;
1039 __le64 u64;
1040 } result;
9d99a8dd
CH		 1041 __le16 sq_head; /* how much of this queue may be reclaimed */
1042 __le16 sq_id; /* submission queue that generated this entry */
1043 __u16 command_id; /* of the command which completed */
1044 __le16 status; /* did the command fail, and if so, why? */
1045};
1046
8ef2074d
GKB		 1047#define NVME_VS(major, minor, tertiary) \
1048 (((major) << 16) | ((minor) << 8) | (tertiary))
9d99a8dd 1049
b60503ba 1050#endif /* _LINUX_NVME_H */
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