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b60503ba MW |
1 | /* |
2 | * Definitions for the NVM Express interface | |
8757ad65 | 3 | * Copyright (c) 2011-2014, Intel Corporation. |
b60503ba MW |
4 | * |
5 | * This program is free software; you can redistribute it and/or modify it | |
6 | * under the terms and conditions of the GNU General Public License, | |
7 | * version 2, as published by the Free Software Foundation. | |
8 | * | |
9 | * This program is distributed in the hope it will be useful, but WITHOUT | |
10 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
11 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
12 | * more details. | |
b60503ba MW |
13 | */ |
14 | ||
15 | #ifndef _LINUX_NVME_H | |
16 | #define _LINUX_NVME_H | |
17 | ||
2812dfe3 | 18 | #include <linux/types.h> |
8e412263 | 19 | #include <linux/uuid.h> |
eb793e2c CH |
20 | |
21 | /* NQN names in commands fields specified one size */ | |
22 | #define NVMF_NQN_FIELD_LEN 256 | |
23 | ||
24 | /* However the max length of a qualified name is another size */ | |
25 | #define NVMF_NQN_SIZE 223 | |
26 | ||
27 | #define NVMF_TRSVCID_SIZE 32 | |
28 | #define NVMF_TRADDR_SIZE 256 | |
29 | #define NVMF_TSAS_SIZE 256 | |
30 | ||
31 | #define NVME_DISC_SUBSYS_NAME "nqn.2014-08.org.nvmexpress.discovery" | |
32 | ||
33 | #define NVME_RDMA_IP_PORT 4420 | |
34 | ||
35 | enum nvme_subsys_type { | |
36 | NVME_NQN_DISC = 1, /* Discovery type target subsystem */ | |
37 | NVME_NQN_NVME = 2, /* NVME type target subsystem */ | |
38 | }; | |
39 | ||
40 | /* Address Family codes for Discovery Log Page entry ADRFAM field */ | |
41 | enum { | |
42 | NVMF_ADDR_FAMILY_PCI = 0, /* PCIe */ | |
43 | NVMF_ADDR_FAMILY_IP4 = 1, /* IP4 */ | |
44 | NVMF_ADDR_FAMILY_IP6 = 2, /* IP6 */ | |
45 | NVMF_ADDR_FAMILY_IB = 3, /* InfiniBand */ | |
46 | NVMF_ADDR_FAMILY_FC = 4, /* Fibre Channel */ | |
47 | }; | |
48 | ||
49 | /* Transport Type codes for Discovery Log Page entry TRTYPE field */ | |
50 | enum { | |
51 | NVMF_TRTYPE_RDMA = 1, /* RDMA */ | |
52 | NVMF_TRTYPE_FC = 2, /* Fibre Channel */ | |
53 | NVMF_TRTYPE_LOOP = 254, /* Reserved for host usage */ | |
54 | NVMF_TRTYPE_MAX, | |
55 | }; | |
56 | ||
57 | /* Transport Requirements codes for Discovery Log Page entry TREQ field */ | |
58 | enum { | |
59 | NVMF_TREQ_NOT_SPECIFIED = 0, /* Not specified */ | |
60 | NVMF_TREQ_REQUIRED = 1, /* Required */ | |
61 | NVMF_TREQ_NOT_REQUIRED = 2, /* Not Required */ | |
62 | }; | |
63 | ||
64 | /* RDMA QP Service Type codes for Discovery Log Page entry TSAS | |
65 | * RDMA_QPTYPE field | |
66 | */ | |
67 | enum { | |
bf17aa36 RD |
68 | NVMF_RDMA_QPTYPE_CONNECTED = 1, /* Reliable Connected */ |
69 | NVMF_RDMA_QPTYPE_DATAGRAM = 2, /* Reliable Datagram */ | |
eb793e2c CH |
70 | }; |
71 | ||
72 | /* RDMA QP Service Type codes for Discovery Log Page entry TSAS | |
73 | * RDMA_QPTYPE field | |
74 | */ | |
75 | enum { | |
bf17aa36 RD |
76 | NVMF_RDMA_PRTYPE_NOT_SPECIFIED = 1, /* No Provider Specified */ |
77 | NVMF_RDMA_PRTYPE_IB = 2, /* InfiniBand */ | |
78 | NVMF_RDMA_PRTYPE_ROCE = 3, /* InfiniBand RoCE */ | |
79 | NVMF_RDMA_PRTYPE_ROCEV2 = 4, /* InfiniBand RoCEV2 */ | |
80 | NVMF_RDMA_PRTYPE_IWARP = 5, /* IWARP */ | |
eb793e2c CH |
81 | }; |
82 | ||
83 | /* RDMA Connection Management Service Type codes for Discovery Log Page | |
84 | * entry TSAS RDMA_CMS field | |
85 | */ | |
86 | enum { | |
bf17aa36 | 87 | NVMF_RDMA_CMS_RDMA_CM = 1, /* Sockets based endpoint addressing */ |
eb793e2c CH |
88 | }; |
89 | ||
90 | #define NVMF_AQ_DEPTH 32 | |
2812dfe3 | 91 | |
7a67cbea CH |
92 | enum { |
93 | NVME_REG_CAP = 0x0000, /* Controller Capabilities */ | |
94 | NVME_REG_VS = 0x0008, /* Version */ | |
95 | NVME_REG_INTMS = 0x000c, /* Interrupt Mask Set */ | |
a5b714ad | 96 | NVME_REG_INTMC = 0x0010, /* Interrupt Mask Clear */ |
7a67cbea CH |
97 | NVME_REG_CC = 0x0014, /* Controller Configuration */ |
98 | NVME_REG_CSTS = 0x001c, /* Controller Status */ | |
99 | NVME_REG_NSSR = 0x0020, /* NVM Subsystem Reset */ | |
100 | NVME_REG_AQA = 0x0024, /* Admin Queue Attributes */ | |
101 | NVME_REG_ASQ = 0x0028, /* Admin SQ Base Address */ | |
a5b714ad | 102 | NVME_REG_ACQ = 0x0030, /* Admin CQ Base Address */ |
7a67cbea CH |
103 | NVME_REG_CMBLOC = 0x0038, /* Controller Memory Buffer Location */ |
104 | NVME_REG_CMBSZ = 0x003c, /* Controller Memory Buffer Size */ | |
97f6ef64 | 105 | NVME_REG_DBS = 0x1000, /* SQ 0 Tail Doorbell */ |
b60503ba MW |
106 | }; |
107 | ||
a0cadb85 | 108 | #define NVME_CAP_MQES(cap) ((cap) & 0xffff) |
22605f96 | 109 | #define NVME_CAP_TIMEOUT(cap) (((cap) >> 24) & 0xff) |
f1938f6e | 110 | #define NVME_CAP_STRIDE(cap) (((cap) >> 32) & 0xf) |
dfbac8c7 | 111 | #define NVME_CAP_NSSRC(cap) (((cap) >> 36) & 0x1) |
8fc23e03 | 112 | #define NVME_CAP_MPSMIN(cap) (((cap) >> 48) & 0xf) |
1d090624 | 113 | #define NVME_CAP_MPSMAX(cap) (((cap) >> 52) & 0xf) |
22605f96 | 114 | |
8ffaadf7 JD |
115 | #define NVME_CMB_BIR(cmbloc) ((cmbloc) & 0x7) |
116 | #define NVME_CMB_OFST(cmbloc) (((cmbloc) >> 12) & 0xfffff) | |
117 | #define NVME_CMB_SZ(cmbsz) (((cmbsz) >> 12) & 0xfffff) | |
118 | #define NVME_CMB_SZU(cmbsz) (((cmbsz) >> 8) & 0xf) | |
119 | ||
120 | #define NVME_CMB_WDS(cmbsz) ((cmbsz) & 0x10) | |
121 | #define NVME_CMB_RDS(cmbsz) ((cmbsz) & 0x8) | |
122 | #define NVME_CMB_LISTS(cmbsz) ((cmbsz) & 0x4) | |
123 | #define NVME_CMB_CQS(cmbsz) ((cmbsz) & 0x2) | |
124 | #define NVME_CMB_SQS(cmbsz) ((cmbsz) & 0x1) | |
125 | ||
69cd27e2 CH |
126 | /* |
127 | * Submission and Completion Queue Entry Sizes for the NVM command set. | |
128 | * (In bytes and specified as a power of two (2^n)). | |
129 | */ | |
130 | #define NVME_NVM_IOSQES 6 | |
131 | #define NVME_NVM_IOCQES 4 | |
132 | ||
b60503ba MW |
133 | enum { |
134 | NVME_CC_ENABLE = 1 << 0, | |
135 | NVME_CC_CSS_NVM = 0 << 4, | |
136 | NVME_CC_MPS_SHIFT = 7, | |
137 | NVME_CC_ARB_RR = 0 << 11, | |
138 | NVME_CC_ARB_WRRU = 1 << 11, | |
7f53f9d2 MW |
139 | NVME_CC_ARB_VS = 7 << 11, |
140 | NVME_CC_SHN_NONE = 0 << 14, | |
141 | NVME_CC_SHN_NORMAL = 1 << 14, | |
142 | NVME_CC_SHN_ABRUPT = 2 << 14, | |
1894d8f1 | 143 | NVME_CC_SHN_MASK = 3 << 14, |
69cd27e2 CH |
144 | NVME_CC_IOSQES = NVME_NVM_IOSQES << 16, |
145 | NVME_CC_IOCQES = NVME_NVM_IOCQES << 20, | |
b60503ba MW |
146 | NVME_CSTS_RDY = 1 << 0, |
147 | NVME_CSTS_CFS = 1 << 1, | |
dfbac8c7 | 148 | NVME_CSTS_NSSRO = 1 << 4, |
b60503ba MW |
149 | NVME_CSTS_SHST_NORMAL = 0 << 2, |
150 | NVME_CSTS_SHST_OCCUR = 1 << 2, | |
151 | NVME_CSTS_SHST_CMPLT = 2 << 2, | |
1894d8f1 | 152 | NVME_CSTS_SHST_MASK = 3 << 2, |
b60503ba MW |
153 | }; |
154 | ||
9d99a8dd CH |
155 | struct nvme_id_power_state { |
156 | __le16 max_power; /* centiwatts */ | |
157 | __u8 rsvd2; | |
158 | __u8 flags; | |
159 | __le32 entry_lat; /* microseconds */ | |
160 | __le32 exit_lat; /* microseconds */ | |
161 | __u8 read_tput; | |
162 | __u8 read_lat; | |
163 | __u8 write_tput; | |
164 | __u8 write_lat; | |
165 | __le16 idle_power; | |
166 | __u8 idle_scale; | |
167 | __u8 rsvd19; | |
168 | __le16 active_power; | |
169 | __u8 active_work_scale; | |
170 | __u8 rsvd23[9]; | |
171 | }; | |
172 | ||
173 | enum { | |
174 | NVME_PS_FLAGS_MAX_POWER_SCALE = 1 << 0, | |
175 | NVME_PS_FLAGS_NON_OP_STATE = 1 << 1, | |
176 | }; | |
177 | ||
178 | struct nvme_id_ctrl { | |
179 | __le16 vid; | |
180 | __le16 ssvid; | |
181 | char sn[20]; | |
182 | char mn[40]; | |
183 | char fr[8]; | |
184 | __u8 rab; | |
185 | __u8 ieee[3]; | |
a446c084 | 186 | __u8 cmic; |
9d99a8dd | 187 | __u8 mdts; |
08c69640 CH |
188 | __le16 cntlid; |
189 | __le32 ver; | |
14e974a8 CH |
190 | __le32 rtd3r; |
191 | __le32 rtd3e; | |
192 | __le32 oaes; | |
eb793e2c CH |
193 | __le32 ctratt; |
194 | __u8 rsvd100[156]; | |
9d99a8dd CH |
195 | __le16 oacs; |
196 | __u8 acl; | |
197 | __u8 aerl; | |
198 | __u8 frmw; | |
199 | __u8 lpa; | |
200 | __u8 elpe; | |
201 | __u8 npss; | |
202 | __u8 avscc; | |
203 | __u8 apsta; | |
204 | __le16 wctemp; | |
205 | __le16 cctemp; | |
a446c084 CH |
206 | __le16 mtfa; |
207 | __le32 hmpre; | |
208 | __le32 hmmin; | |
209 | __u8 tnvmcap[16]; | |
210 | __u8 unvmcap[16]; | |
211 | __le32 rpmbs; | |
212 | __u8 rsvd316[4]; | |
7b89eae2 SG |
213 | __le16 kas; |
214 | __u8 rsvd322[190]; | |
9d99a8dd CH |
215 | __u8 sqes; |
216 | __u8 cqes; | |
eb793e2c | 217 | __le16 maxcmd; |
9d99a8dd CH |
218 | __le32 nn; |
219 | __le16 oncs; | |
220 | __le16 fuses; | |
221 | __u8 fna; | |
222 | __u8 vwc; | |
223 | __le16 awun; | |
224 | __le16 awupf; | |
225 | __u8 nvscc; | |
226 | __u8 rsvd531; | |
227 | __le16 acwu; | |
228 | __u8 rsvd534[2]; | |
229 | __le32 sgls; | |
eb793e2c CH |
230 | __u8 rsvd540[228]; |
231 | char subnqn[256]; | |
232 | __u8 rsvd1024[768]; | |
233 | __le32 ioccsz; | |
234 | __le32 iorcsz; | |
235 | __le16 icdoff; | |
236 | __u8 ctrattr; | |
237 | __u8 msdbd; | |
238 | __u8 rsvd1804[244]; | |
9d99a8dd CH |
239 | struct nvme_id_power_state psd[32]; |
240 | __u8 vs[1024]; | |
241 | }; | |
242 | ||
243 | enum { | |
244 | NVME_CTRL_ONCS_COMPARE = 1 << 0, | |
245 | NVME_CTRL_ONCS_WRITE_UNCORRECTABLE = 1 << 1, | |
246 | NVME_CTRL_ONCS_DSM = 1 << 2, | |
3b7c33b2 | 247 | NVME_CTRL_ONCS_WRITE_ZEROES = 1 << 3, |
9d99a8dd | 248 | NVME_CTRL_VWC_PRESENT = 1 << 0, |
8a9ae523 | 249 | NVME_CTRL_OACS_SEC_SUPP = 1 << 0, |
f9f38e33 | 250 | NVME_CTRL_OACS_DBBUF_SUPP = 1 << 7, |
9d99a8dd CH |
251 | }; |
252 | ||
253 | struct nvme_lbaf { | |
254 | __le16 ms; | |
255 | __u8 ds; | |
256 | __u8 rp; | |
257 | }; | |
258 | ||
259 | struct nvme_id_ns { | |
260 | __le64 nsze; | |
261 | __le64 ncap; | |
262 | __le64 nuse; | |
263 | __u8 nsfeat; | |
264 | __u8 nlbaf; | |
265 | __u8 flbas; | |
266 | __u8 mc; | |
267 | __u8 dpc; | |
268 | __u8 dps; | |
269 | __u8 nmic; | |
270 | __u8 rescap; | |
271 | __u8 fpi; | |
272 | __u8 rsvd33; | |
273 | __le16 nawun; | |
274 | __le16 nawupf; | |
275 | __le16 nacwu; | |
276 | __le16 nabsn; | |
277 | __le16 nabo; | |
278 | __le16 nabspf; | |
279 | __u16 rsvd46; | |
a446c084 | 280 | __u8 nvmcap[16]; |
9d99a8dd CH |
281 | __u8 rsvd64[40]; |
282 | __u8 nguid[16]; | |
283 | __u8 eui64[8]; | |
284 | struct nvme_lbaf lbaf[16]; | |
285 | __u8 rsvd192[192]; | |
286 | __u8 vs[3712]; | |
287 | }; | |
288 | ||
329dd768 CH |
289 | enum { |
290 | NVME_ID_CNS_NS = 0x00, | |
291 | NVME_ID_CNS_CTRL = 0x01, | |
292 | NVME_ID_CNS_NS_ACTIVE_LIST = 0x02, | |
af8b86e9 | 293 | NVME_ID_CNS_NS_DESC_LIST = 0x03, |
329dd768 CH |
294 | NVME_ID_CNS_NS_PRESENT_LIST = 0x10, |
295 | NVME_ID_CNS_NS_PRESENT = 0x11, | |
296 | NVME_ID_CNS_CTRL_NS_LIST = 0x12, | |
297 | NVME_ID_CNS_CTRL_LIST = 0x13, | |
298 | }; | |
299 | ||
9d99a8dd CH |
300 | enum { |
301 | NVME_NS_FEAT_THIN = 1 << 0, | |
302 | NVME_NS_FLBAS_LBA_MASK = 0xf, | |
303 | NVME_NS_FLBAS_META_EXT = 0x10, | |
304 | NVME_LBAF_RP_BEST = 0, | |
305 | NVME_LBAF_RP_BETTER = 1, | |
306 | NVME_LBAF_RP_GOOD = 2, | |
307 | NVME_LBAF_RP_DEGRADED = 3, | |
308 | NVME_NS_DPC_PI_LAST = 1 << 4, | |
309 | NVME_NS_DPC_PI_FIRST = 1 << 3, | |
310 | NVME_NS_DPC_PI_TYPE3 = 1 << 2, | |
311 | NVME_NS_DPC_PI_TYPE2 = 1 << 1, | |
312 | NVME_NS_DPC_PI_TYPE1 = 1 << 0, | |
313 | NVME_NS_DPS_PI_FIRST = 1 << 3, | |
314 | NVME_NS_DPS_PI_MASK = 0x7, | |
315 | NVME_NS_DPS_PI_TYPE1 = 1, | |
316 | NVME_NS_DPS_PI_TYPE2 = 2, | |
317 | NVME_NS_DPS_PI_TYPE3 = 3, | |
318 | }; | |
319 | ||
af8b86e9 JT |
320 | struct nvme_ns_id_desc { |
321 | __u8 nidt; | |
322 | __u8 nidl; | |
323 | __le16 reserved; | |
324 | }; | |
325 | ||
326 | #define NVME_NIDT_EUI64_LEN 8 | |
327 | #define NVME_NIDT_NGUID_LEN 16 | |
328 | #define NVME_NIDT_UUID_LEN 16 | |
329 | ||
330 | enum { | |
331 | NVME_NIDT_EUI64 = 0x01, | |
332 | NVME_NIDT_NGUID = 0x02, | |
333 | NVME_NIDT_UUID = 0x03, | |
334 | }; | |
335 | ||
9d99a8dd CH |
336 | struct nvme_smart_log { |
337 | __u8 critical_warning; | |
338 | __u8 temperature[2]; | |
339 | __u8 avail_spare; | |
340 | __u8 spare_thresh; | |
341 | __u8 percent_used; | |
342 | __u8 rsvd6[26]; | |
343 | __u8 data_units_read[16]; | |
344 | __u8 data_units_written[16]; | |
345 | __u8 host_reads[16]; | |
346 | __u8 host_writes[16]; | |
347 | __u8 ctrl_busy_time[16]; | |
348 | __u8 power_cycles[16]; | |
349 | __u8 power_on_hours[16]; | |
350 | __u8 unsafe_shutdowns[16]; | |
351 | __u8 media_errors[16]; | |
352 | __u8 num_err_log_entries[16]; | |
353 | __le32 warning_temp_time; | |
354 | __le32 critical_comp_time; | |
355 | __le16 temp_sensor[8]; | |
356 | __u8 rsvd216[296]; | |
357 | }; | |
358 | ||
359 | enum { | |
360 | NVME_SMART_CRIT_SPARE = 1 << 0, | |
361 | NVME_SMART_CRIT_TEMPERATURE = 1 << 1, | |
362 | NVME_SMART_CRIT_RELIABILITY = 1 << 2, | |
363 | NVME_SMART_CRIT_MEDIA = 1 << 3, | |
364 | NVME_SMART_CRIT_VOLATILE_MEMORY = 1 << 4, | |
365 | }; | |
366 | ||
367 | enum { | |
368 | NVME_AER_NOTICE_NS_CHANGED = 0x0002, | |
369 | }; | |
370 | ||
371 | struct nvme_lba_range_type { | |
372 | __u8 type; | |
373 | __u8 attributes; | |
374 | __u8 rsvd2[14]; | |
375 | __u64 slba; | |
376 | __u64 nlb; | |
377 | __u8 guid[16]; | |
378 | __u8 rsvd48[16]; | |
379 | }; | |
380 | ||
381 | enum { | |
382 | NVME_LBART_TYPE_FS = 0x01, | |
383 | NVME_LBART_TYPE_RAID = 0x02, | |
384 | NVME_LBART_TYPE_CACHE = 0x03, | |
385 | NVME_LBART_TYPE_SWAP = 0x04, | |
386 | ||
387 | NVME_LBART_ATTRIB_TEMP = 1 << 0, | |
388 | NVME_LBART_ATTRIB_HIDE = 1 << 1, | |
389 | }; | |
390 | ||
391 | struct nvme_reservation_status { | |
392 | __le32 gen; | |
393 | __u8 rtype; | |
394 | __u8 regctl[2]; | |
395 | __u8 resv5[2]; | |
396 | __u8 ptpls; | |
397 | __u8 resv10[13]; | |
398 | struct { | |
399 | __le16 cntlid; | |
400 | __u8 rcsts; | |
401 | __u8 resv3[5]; | |
402 | __le64 hostid; | |
403 | __le64 rkey; | |
404 | } regctl_ds[]; | |
405 | }; | |
406 | ||
79f370ea CH |
407 | enum nvme_async_event_type { |
408 | NVME_AER_TYPE_ERROR = 0, | |
409 | NVME_AER_TYPE_SMART = 1, | |
410 | NVME_AER_TYPE_NOTICE = 2, | |
411 | }; | |
412 | ||
9d99a8dd CH |
413 | /* I/O commands */ |
414 | ||
415 | enum nvme_opcode { | |
416 | nvme_cmd_flush = 0x00, | |
417 | nvme_cmd_write = 0x01, | |
418 | nvme_cmd_read = 0x02, | |
419 | nvme_cmd_write_uncor = 0x04, | |
420 | nvme_cmd_compare = 0x05, | |
421 | nvme_cmd_write_zeroes = 0x08, | |
422 | nvme_cmd_dsm = 0x09, | |
423 | nvme_cmd_resv_register = 0x0d, | |
424 | nvme_cmd_resv_report = 0x0e, | |
425 | nvme_cmd_resv_acquire = 0x11, | |
426 | nvme_cmd_resv_release = 0x15, | |
427 | }; | |
428 | ||
eb793e2c CH |
429 | /* |
430 | * Descriptor subtype - lower 4 bits of nvme_(keyed_)sgl_desc identifier | |
431 | * | |
432 | * @NVME_SGL_FMT_ADDRESS: absolute address of the data block | |
433 | * @NVME_SGL_FMT_OFFSET: relative offset of the in-capsule data block | |
434 | * @NVME_SGL_FMT_INVALIDATE: RDMA transport specific remote invalidation | |
435 | * request subtype | |
436 | */ | |
437 | enum { | |
438 | NVME_SGL_FMT_ADDRESS = 0x00, | |
439 | NVME_SGL_FMT_OFFSET = 0x01, | |
440 | NVME_SGL_FMT_INVALIDATE = 0x0f, | |
441 | }; | |
442 | ||
443 | /* | |
444 | * Descriptor type - upper 4 bits of nvme_(keyed_)sgl_desc identifier | |
445 | * | |
446 | * For struct nvme_sgl_desc: | |
447 | * @NVME_SGL_FMT_DATA_DESC: data block descriptor | |
448 | * @NVME_SGL_FMT_SEG_DESC: sgl segment descriptor | |
449 | * @NVME_SGL_FMT_LAST_SEG_DESC: last sgl segment descriptor | |
450 | * | |
451 | * For struct nvme_keyed_sgl_desc: | |
452 | * @NVME_KEY_SGL_FMT_DATA_DESC: keyed data block descriptor | |
453 | */ | |
454 | enum { | |
455 | NVME_SGL_FMT_DATA_DESC = 0x00, | |
456 | NVME_SGL_FMT_SEG_DESC = 0x02, | |
457 | NVME_SGL_FMT_LAST_SEG_DESC = 0x03, | |
458 | NVME_KEY_SGL_FMT_DATA_DESC = 0x04, | |
459 | }; | |
460 | ||
461 | struct nvme_sgl_desc { | |
462 | __le64 addr; | |
463 | __le32 length; | |
464 | __u8 rsvd[3]; | |
465 | __u8 type; | |
466 | }; | |
467 | ||
468 | struct nvme_keyed_sgl_desc { | |
469 | __le64 addr; | |
470 | __u8 length[3]; | |
471 | __u8 key[4]; | |
472 | __u8 type; | |
473 | }; | |
474 | ||
475 | union nvme_data_ptr { | |
476 | struct { | |
477 | __le64 prp1; | |
478 | __le64 prp2; | |
479 | }; | |
480 | struct nvme_sgl_desc sgl; | |
481 | struct nvme_keyed_sgl_desc ksgl; | |
482 | }; | |
483 | ||
3972be23 JS |
484 | /* |
485 | * Lowest two bits of our flags field (FUSE field in the spec): | |
486 | * | |
487 | * @NVME_CMD_FUSE_FIRST: Fused Operation, first command | |
488 | * @NVME_CMD_FUSE_SECOND: Fused Operation, second command | |
489 | * | |
490 | * Highest two bits in our flags field (PSDT field in the spec): | |
491 | * | |
492 | * @NVME_CMD_PSDT_SGL_METABUF: Use SGLS for this transfer, | |
493 | * If used, MPTR contains addr of single physical buffer (byte aligned). | |
494 | * @NVME_CMD_PSDT_SGL_METASEG: Use SGLS for this transfer, | |
495 | * If used, MPTR contains an address of an SGL segment containing | |
496 | * exactly 1 SGL descriptor (qword aligned). | |
497 | */ | |
498 | enum { | |
499 | NVME_CMD_FUSE_FIRST = (1 << 0), | |
500 | NVME_CMD_FUSE_SECOND = (1 << 1), | |
501 | ||
502 | NVME_CMD_SGL_METABUF = (1 << 6), | |
503 | NVME_CMD_SGL_METASEG = (1 << 7), | |
504 | NVME_CMD_SGL_ALL = NVME_CMD_SGL_METABUF | NVME_CMD_SGL_METASEG, | |
505 | }; | |
506 | ||
9d99a8dd CH |
507 | struct nvme_common_command { |
508 | __u8 opcode; | |
509 | __u8 flags; | |
510 | __u16 command_id; | |
511 | __le32 nsid; | |
512 | __le32 cdw2[2]; | |
513 | __le64 metadata; | |
eb793e2c | 514 | union nvme_data_ptr dptr; |
9d99a8dd CH |
515 | __le32 cdw10[6]; |
516 | }; | |
517 | ||
518 | struct nvme_rw_command { | |
519 | __u8 opcode; | |
520 | __u8 flags; | |
521 | __u16 command_id; | |
522 | __le32 nsid; | |
523 | __u64 rsvd2; | |
524 | __le64 metadata; | |
eb793e2c | 525 | union nvme_data_ptr dptr; |
9d99a8dd CH |
526 | __le64 slba; |
527 | __le16 length; | |
528 | __le16 control; | |
529 | __le32 dsmgmt; | |
530 | __le32 reftag; | |
531 | __le16 apptag; | |
532 | __le16 appmask; | |
533 | }; | |
534 | ||
535 | enum { | |
536 | NVME_RW_LR = 1 << 15, | |
537 | NVME_RW_FUA = 1 << 14, | |
538 | NVME_RW_DSM_FREQ_UNSPEC = 0, | |
539 | NVME_RW_DSM_FREQ_TYPICAL = 1, | |
540 | NVME_RW_DSM_FREQ_RARE = 2, | |
541 | NVME_RW_DSM_FREQ_READS = 3, | |
542 | NVME_RW_DSM_FREQ_WRITES = 4, | |
543 | NVME_RW_DSM_FREQ_RW = 5, | |
544 | NVME_RW_DSM_FREQ_ONCE = 6, | |
545 | NVME_RW_DSM_FREQ_PREFETCH = 7, | |
546 | NVME_RW_DSM_FREQ_TEMP = 8, | |
547 | NVME_RW_DSM_LATENCY_NONE = 0 << 4, | |
548 | NVME_RW_DSM_LATENCY_IDLE = 1 << 4, | |
549 | NVME_RW_DSM_LATENCY_NORM = 2 << 4, | |
550 | NVME_RW_DSM_LATENCY_LOW = 3 << 4, | |
551 | NVME_RW_DSM_SEQ_REQ = 1 << 6, | |
552 | NVME_RW_DSM_COMPRESSED = 1 << 7, | |
553 | NVME_RW_PRINFO_PRCHK_REF = 1 << 10, | |
554 | NVME_RW_PRINFO_PRCHK_APP = 1 << 11, | |
555 | NVME_RW_PRINFO_PRCHK_GUARD = 1 << 12, | |
556 | NVME_RW_PRINFO_PRACT = 1 << 13, | |
557 | }; | |
558 | ||
559 | struct nvme_dsm_cmd { | |
560 | __u8 opcode; | |
561 | __u8 flags; | |
562 | __u16 command_id; | |
563 | __le32 nsid; | |
564 | __u64 rsvd2[2]; | |
eb793e2c | 565 | union nvme_data_ptr dptr; |
9d99a8dd CH |
566 | __le32 nr; |
567 | __le32 attributes; | |
568 | __u32 rsvd12[4]; | |
569 | }; | |
570 | ||
571 | enum { | |
572 | NVME_DSMGMT_IDR = 1 << 0, | |
573 | NVME_DSMGMT_IDW = 1 << 1, | |
574 | NVME_DSMGMT_AD = 1 << 2, | |
575 | }; | |
576 | ||
b35ba01e CH |
577 | #define NVME_DSM_MAX_RANGES 256 |
578 | ||
9d99a8dd CH |
579 | struct nvme_dsm_range { |
580 | __le32 cattr; | |
581 | __le32 nlb; | |
582 | __le64 slba; | |
583 | }; | |
584 | ||
3b7c33b2 CK |
585 | struct nvme_write_zeroes_cmd { |
586 | __u8 opcode; | |
587 | __u8 flags; | |
588 | __u16 command_id; | |
589 | __le32 nsid; | |
590 | __u64 rsvd2; | |
591 | __le64 metadata; | |
592 | union nvme_data_ptr dptr; | |
593 | __le64 slba; | |
594 | __le16 length; | |
595 | __le16 control; | |
596 | __le32 dsmgmt; | |
597 | __le32 reftag; | |
598 | __le16 apptag; | |
599 | __le16 appmask; | |
600 | }; | |
601 | ||
c5552fde AL |
602 | /* Features */ |
603 | ||
604 | struct nvme_feat_auto_pst { | |
605 | __le64 entries[32]; | |
606 | }; | |
607 | ||
39673e19 CH |
608 | enum { |
609 | NVME_HOST_MEM_ENABLE = (1 << 0), | |
610 | NVME_HOST_MEM_RETURN = (1 << 1), | |
611 | }; | |
612 | ||
9d99a8dd CH |
613 | /* Admin commands */ |
614 | ||
615 | enum nvme_admin_opcode { | |
616 | nvme_admin_delete_sq = 0x00, | |
617 | nvme_admin_create_sq = 0x01, | |
618 | nvme_admin_get_log_page = 0x02, | |
619 | nvme_admin_delete_cq = 0x04, | |
620 | nvme_admin_create_cq = 0x05, | |
621 | nvme_admin_identify = 0x06, | |
622 | nvme_admin_abort_cmd = 0x08, | |
623 | nvme_admin_set_features = 0x09, | |
624 | nvme_admin_get_features = 0x0a, | |
625 | nvme_admin_async_event = 0x0c, | |
a446c084 | 626 | nvme_admin_ns_mgmt = 0x0d, |
9d99a8dd CH |
627 | nvme_admin_activate_fw = 0x10, |
628 | nvme_admin_download_fw = 0x11, | |
a446c084 | 629 | nvme_admin_ns_attach = 0x15, |
7b89eae2 | 630 | nvme_admin_keep_alive = 0x18, |
f9f38e33 | 631 | nvme_admin_dbbuf = 0x7C, |
9d99a8dd CH |
632 | nvme_admin_format_nvm = 0x80, |
633 | nvme_admin_security_send = 0x81, | |
634 | nvme_admin_security_recv = 0x82, | |
635 | }; | |
636 | ||
637 | enum { | |
638 | NVME_QUEUE_PHYS_CONTIG = (1 << 0), | |
639 | NVME_CQ_IRQ_ENABLED = (1 << 1), | |
640 | NVME_SQ_PRIO_URGENT = (0 << 1), | |
641 | NVME_SQ_PRIO_HIGH = (1 << 1), | |
642 | NVME_SQ_PRIO_MEDIUM = (2 << 1), | |
643 | NVME_SQ_PRIO_LOW = (3 << 1), | |
644 | NVME_FEAT_ARBITRATION = 0x01, | |
645 | NVME_FEAT_POWER_MGMT = 0x02, | |
646 | NVME_FEAT_LBA_RANGE = 0x03, | |
647 | NVME_FEAT_TEMP_THRESH = 0x04, | |
648 | NVME_FEAT_ERR_RECOVERY = 0x05, | |
649 | NVME_FEAT_VOLATILE_WC = 0x06, | |
650 | NVME_FEAT_NUM_QUEUES = 0x07, | |
651 | NVME_FEAT_IRQ_COALESCE = 0x08, | |
652 | NVME_FEAT_IRQ_CONFIG = 0x09, | |
653 | NVME_FEAT_WRITE_ATOMIC = 0x0a, | |
654 | NVME_FEAT_ASYNC_EVENT = 0x0b, | |
655 | NVME_FEAT_AUTO_PST = 0x0c, | |
a446c084 | 656 | NVME_FEAT_HOST_MEM_BUF = 0x0d, |
7b89eae2 | 657 | NVME_FEAT_KATO = 0x0f, |
9d99a8dd CH |
658 | NVME_FEAT_SW_PROGRESS = 0x80, |
659 | NVME_FEAT_HOST_ID = 0x81, | |
660 | NVME_FEAT_RESV_MASK = 0x82, | |
661 | NVME_FEAT_RESV_PERSIST = 0x83, | |
662 | NVME_LOG_ERROR = 0x01, | |
663 | NVME_LOG_SMART = 0x02, | |
664 | NVME_LOG_FW_SLOT = 0x03, | |
eb793e2c | 665 | NVME_LOG_DISC = 0x70, |
9d99a8dd CH |
666 | NVME_LOG_RESERVATION = 0x80, |
667 | NVME_FWACT_REPL = (0 << 3), | |
668 | NVME_FWACT_REPL_ACTV = (1 << 3), | |
669 | NVME_FWACT_ACTV = (2 << 3), | |
670 | }; | |
671 | ||
672 | struct nvme_identify { | |
673 | __u8 opcode; | |
674 | __u8 flags; | |
675 | __u16 command_id; | |
676 | __le32 nsid; | |
677 | __u64 rsvd2[2]; | |
eb793e2c | 678 | union nvme_data_ptr dptr; |
986994a2 PP |
679 | __u8 cns; |
680 | __u8 rsvd3; | |
681 | __le16 ctrlid; | |
9d99a8dd CH |
682 | __u32 rsvd11[5]; |
683 | }; | |
684 | ||
0add5e8e JT |
685 | #define NVME_IDENTIFY_DATA_SIZE 4096 |
686 | ||
9d99a8dd CH |
687 | struct nvme_features { |
688 | __u8 opcode; | |
689 | __u8 flags; | |
690 | __u16 command_id; | |
691 | __le32 nsid; | |
692 | __u64 rsvd2[2]; | |
eb793e2c | 693 | union nvme_data_ptr dptr; |
9d99a8dd CH |
694 | __le32 fid; |
695 | __le32 dword11; | |
b85cf734 AD |
696 | __le32 dword12; |
697 | __le32 dword13; | |
698 | __le32 dword14; | |
699 | __le32 dword15; | |
9d99a8dd CH |
700 | }; |
701 | ||
39673e19 CH |
702 | struct nvme_host_mem_buf_desc { |
703 | __le64 addr; | |
704 | __le32 size; | |
705 | __u32 rsvd; | |
706 | }; | |
707 | ||
9d99a8dd CH |
708 | struct nvme_create_cq { |
709 | __u8 opcode; | |
710 | __u8 flags; | |
711 | __u16 command_id; | |
712 | __u32 rsvd1[5]; | |
713 | __le64 prp1; | |
714 | __u64 rsvd8; | |
715 | __le16 cqid; | |
716 | __le16 qsize; | |
717 | __le16 cq_flags; | |
718 | __le16 irq_vector; | |
719 | __u32 rsvd12[4]; | |
720 | }; | |
721 | ||
722 | struct nvme_create_sq { | |
723 | __u8 opcode; | |
724 | __u8 flags; | |
725 | __u16 command_id; | |
726 | __u32 rsvd1[5]; | |
727 | __le64 prp1; | |
728 | __u64 rsvd8; | |
729 | __le16 sqid; | |
730 | __le16 qsize; | |
731 | __le16 sq_flags; | |
732 | __le16 cqid; | |
733 | __u32 rsvd12[4]; | |
734 | }; | |
735 | ||
736 | struct nvme_delete_queue { | |
737 | __u8 opcode; | |
738 | __u8 flags; | |
739 | __u16 command_id; | |
740 | __u32 rsvd1[9]; | |
741 | __le16 qid; | |
742 | __u16 rsvd10; | |
743 | __u32 rsvd11[5]; | |
744 | }; | |
745 | ||
746 | struct nvme_abort_cmd { | |
747 | __u8 opcode; | |
748 | __u8 flags; | |
749 | __u16 command_id; | |
750 | __u32 rsvd1[9]; | |
751 | __le16 sqid; | |
752 | __u16 cid; | |
753 | __u32 rsvd11[5]; | |
754 | }; | |
755 | ||
756 | struct nvme_download_firmware { | |
757 | __u8 opcode; | |
758 | __u8 flags; | |
759 | __u16 command_id; | |
760 | __u32 rsvd1[5]; | |
eb793e2c | 761 | union nvme_data_ptr dptr; |
9d99a8dd CH |
762 | __le32 numd; |
763 | __le32 offset; | |
764 | __u32 rsvd12[4]; | |
765 | }; | |
766 | ||
767 | struct nvme_format_cmd { | |
768 | __u8 opcode; | |
769 | __u8 flags; | |
770 | __u16 command_id; | |
771 | __le32 nsid; | |
772 | __u64 rsvd2[4]; | |
773 | __le32 cdw10; | |
774 | __u32 rsvd11[5]; | |
775 | }; | |
776 | ||
725b3588 AB |
777 | struct nvme_get_log_page_command { |
778 | __u8 opcode; | |
779 | __u8 flags; | |
780 | __u16 command_id; | |
781 | __le32 nsid; | |
782 | __u64 rsvd2[2]; | |
eb793e2c | 783 | union nvme_data_ptr dptr; |
725b3588 AB |
784 | __u8 lid; |
785 | __u8 rsvd10; | |
786 | __le16 numdl; | |
787 | __le16 numdu; | |
788 | __u16 rsvd11; | |
789 | __le32 lpol; | |
790 | __le32 lpou; | |
791 | __u32 rsvd14[2]; | |
792 | }; | |
793 | ||
eb793e2c CH |
794 | /* |
795 | * Fabrics subcommands. | |
796 | */ | |
797 | enum nvmf_fabrics_opcode { | |
798 | nvme_fabrics_command = 0x7f, | |
799 | }; | |
800 | ||
801 | enum nvmf_capsule_command { | |
802 | nvme_fabrics_type_property_set = 0x00, | |
803 | nvme_fabrics_type_connect = 0x01, | |
804 | nvme_fabrics_type_property_get = 0x04, | |
805 | }; | |
806 | ||
807 | struct nvmf_common_command { | |
808 | __u8 opcode; | |
809 | __u8 resv1; | |
810 | __u16 command_id; | |
811 | __u8 fctype; | |
812 | __u8 resv2[35]; | |
813 | __u8 ts[24]; | |
814 | }; | |
815 | ||
816 | /* | |
817 | * The legal cntlid range a NVMe Target will provide. | |
818 | * Note that cntlid of value 0 is considered illegal in the fabrics world. | |
819 | * Devices based on earlier specs did not have the subsystem concept; | |
820 | * therefore, those devices had their cntlid value set to 0 as a result. | |
821 | */ | |
822 | #define NVME_CNTLID_MIN 1 | |
823 | #define NVME_CNTLID_MAX 0xffef | |
824 | #define NVME_CNTLID_DYNAMIC 0xffff | |
825 | ||
826 | #define MAX_DISC_LOGS 255 | |
827 | ||
828 | /* Discovery log page entry */ | |
829 | struct nvmf_disc_rsp_page_entry { | |
830 | __u8 trtype; | |
831 | __u8 adrfam; | |
a446c084 | 832 | __u8 subtype; |
eb793e2c CH |
833 | __u8 treq; |
834 | __le16 portid; | |
835 | __le16 cntlid; | |
836 | __le16 asqsz; | |
837 | __u8 resv8[22]; | |
838 | char trsvcid[NVMF_TRSVCID_SIZE]; | |
839 | __u8 resv64[192]; | |
840 | char subnqn[NVMF_NQN_FIELD_LEN]; | |
841 | char traddr[NVMF_TRADDR_SIZE]; | |
842 | union tsas { | |
843 | char common[NVMF_TSAS_SIZE]; | |
844 | struct rdma { | |
845 | __u8 qptype; | |
846 | __u8 prtype; | |
847 | __u8 cms; | |
848 | __u8 resv3[5]; | |
849 | __u16 pkey; | |
850 | __u8 resv10[246]; | |
851 | } rdma; | |
852 | } tsas; | |
853 | }; | |
854 | ||
855 | /* Discovery log page header */ | |
856 | struct nvmf_disc_rsp_page_hdr { | |
857 | __le64 genctr; | |
858 | __le64 numrec; | |
859 | __le16 recfmt; | |
860 | __u8 resv14[1006]; | |
861 | struct nvmf_disc_rsp_page_entry entries[0]; | |
862 | }; | |
863 | ||
864 | struct nvmf_connect_command { | |
865 | __u8 opcode; | |
866 | __u8 resv1; | |
867 | __u16 command_id; | |
868 | __u8 fctype; | |
869 | __u8 resv2[19]; | |
870 | union nvme_data_ptr dptr; | |
871 | __le16 recfmt; | |
872 | __le16 qid; | |
873 | __le16 sqsize; | |
874 | __u8 cattr; | |
875 | __u8 resv3; | |
876 | __le32 kato; | |
877 | __u8 resv4[12]; | |
878 | }; | |
879 | ||
880 | struct nvmf_connect_data { | |
8e412263 | 881 | uuid_t hostid; |
eb793e2c CH |
882 | __le16 cntlid; |
883 | char resv4[238]; | |
884 | char subsysnqn[NVMF_NQN_FIELD_LEN]; | |
885 | char hostnqn[NVMF_NQN_FIELD_LEN]; | |
886 | char resv5[256]; | |
887 | }; | |
888 | ||
889 | struct nvmf_property_set_command { | |
890 | __u8 opcode; | |
891 | __u8 resv1; | |
892 | __u16 command_id; | |
893 | __u8 fctype; | |
894 | __u8 resv2[35]; | |
895 | __u8 attrib; | |
896 | __u8 resv3[3]; | |
897 | __le32 offset; | |
898 | __le64 value; | |
899 | __u8 resv4[8]; | |
900 | }; | |
901 | ||
902 | struct nvmf_property_get_command { | |
903 | __u8 opcode; | |
904 | __u8 resv1; | |
905 | __u16 command_id; | |
906 | __u8 fctype; | |
907 | __u8 resv2[35]; | |
908 | __u8 attrib; | |
909 | __u8 resv3[3]; | |
910 | __le32 offset; | |
911 | __u8 resv4[16]; | |
912 | }; | |
913 | ||
f9f38e33 HK |
914 | struct nvme_dbbuf { |
915 | __u8 opcode; | |
916 | __u8 flags; | |
917 | __u16 command_id; | |
918 | __u32 rsvd1[5]; | |
919 | __le64 prp1; | |
920 | __le64 prp2; | |
921 | __u32 rsvd12[6]; | |
922 | }; | |
923 | ||
9d99a8dd CH |
924 | struct nvme_command { |
925 | union { | |
926 | struct nvme_common_command common; | |
927 | struct nvme_rw_command rw; | |
928 | struct nvme_identify identify; | |
929 | struct nvme_features features; | |
930 | struct nvme_create_cq create_cq; | |
931 | struct nvme_create_sq create_sq; | |
932 | struct nvme_delete_queue delete_queue; | |
933 | struct nvme_download_firmware dlfw; | |
934 | struct nvme_format_cmd format; | |
935 | struct nvme_dsm_cmd dsm; | |
3b7c33b2 | 936 | struct nvme_write_zeroes_cmd write_zeroes; |
9d99a8dd | 937 | struct nvme_abort_cmd abort; |
725b3588 | 938 | struct nvme_get_log_page_command get_log_page; |
eb793e2c CH |
939 | struct nvmf_common_command fabrics; |
940 | struct nvmf_connect_command connect; | |
941 | struct nvmf_property_set_command prop_set; | |
942 | struct nvmf_property_get_command prop_get; | |
f9f38e33 | 943 | struct nvme_dbbuf dbbuf; |
9d99a8dd CH |
944 | }; |
945 | }; | |
946 | ||
7a5abb4b CH |
947 | static inline bool nvme_is_write(struct nvme_command *cmd) |
948 | { | |
eb793e2c CH |
949 | /* |
950 | * What a mess... | |
951 | * | |
952 | * Why can't we simply have a Fabrics In and Fabrics out command? | |
953 | */ | |
954 | if (unlikely(cmd->common.opcode == nvme_fabrics_command)) | |
955 | return cmd->fabrics.opcode & 1; | |
7a5abb4b CH |
956 | return cmd->common.opcode & 1; |
957 | } | |
958 | ||
9d99a8dd | 959 | enum { |
eb793e2c CH |
960 | /* |
961 | * Generic Command Status: | |
962 | */ | |
9d99a8dd CH |
963 | NVME_SC_SUCCESS = 0x0, |
964 | NVME_SC_INVALID_OPCODE = 0x1, | |
965 | NVME_SC_INVALID_FIELD = 0x2, | |
966 | NVME_SC_CMDID_CONFLICT = 0x3, | |
967 | NVME_SC_DATA_XFER_ERROR = 0x4, | |
968 | NVME_SC_POWER_LOSS = 0x5, | |
969 | NVME_SC_INTERNAL = 0x6, | |
970 | NVME_SC_ABORT_REQ = 0x7, | |
971 | NVME_SC_ABORT_QUEUE = 0x8, | |
972 | NVME_SC_FUSED_FAIL = 0x9, | |
973 | NVME_SC_FUSED_MISSING = 0xa, | |
974 | NVME_SC_INVALID_NS = 0xb, | |
975 | NVME_SC_CMD_SEQ_ERROR = 0xc, | |
976 | NVME_SC_SGL_INVALID_LAST = 0xd, | |
977 | NVME_SC_SGL_INVALID_COUNT = 0xe, | |
978 | NVME_SC_SGL_INVALID_DATA = 0xf, | |
979 | NVME_SC_SGL_INVALID_METADATA = 0x10, | |
980 | NVME_SC_SGL_INVALID_TYPE = 0x11, | |
eb793e2c CH |
981 | |
982 | NVME_SC_SGL_INVALID_OFFSET = 0x16, | |
983 | NVME_SC_SGL_INVALID_SUBTYPE = 0x17, | |
984 | ||
9d99a8dd CH |
985 | NVME_SC_LBA_RANGE = 0x80, |
986 | NVME_SC_CAP_EXCEEDED = 0x81, | |
987 | NVME_SC_NS_NOT_READY = 0x82, | |
988 | NVME_SC_RESERVATION_CONFLICT = 0x83, | |
eb793e2c CH |
989 | |
990 | /* | |
991 | * Command Specific Status: | |
992 | */ | |
9d99a8dd CH |
993 | NVME_SC_CQ_INVALID = 0x100, |
994 | NVME_SC_QID_INVALID = 0x101, | |
995 | NVME_SC_QUEUE_SIZE = 0x102, | |
996 | NVME_SC_ABORT_LIMIT = 0x103, | |
997 | NVME_SC_ABORT_MISSING = 0x104, | |
998 | NVME_SC_ASYNC_LIMIT = 0x105, | |
999 | NVME_SC_FIRMWARE_SLOT = 0x106, | |
1000 | NVME_SC_FIRMWARE_IMAGE = 0x107, | |
1001 | NVME_SC_INVALID_VECTOR = 0x108, | |
1002 | NVME_SC_INVALID_LOG_PAGE = 0x109, | |
1003 | NVME_SC_INVALID_FORMAT = 0x10a, | |
a446c084 | 1004 | NVME_SC_FW_NEEDS_CONV_RESET = 0x10b, |
9d99a8dd CH |
1005 | NVME_SC_INVALID_QUEUE = 0x10c, |
1006 | NVME_SC_FEATURE_NOT_SAVEABLE = 0x10d, | |
1007 | NVME_SC_FEATURE_NOT_CHANGEABLE = 0x10e, | |
1008 | NVME_SC_FEATURE_NOT_PER_NS = 0x10f, | |
a446c084 CH |
1009 | NVME_SC_FW_NEEDS_SUBSYS_RESET = 0x110, |
1010 | NVME_SC_FW_NEEDS_RESET = 0x111, | |
1011 | NVME_SC_FW_NEEDS_MAX_TIME = 0x112, | |
1012 | NVME_SC_FW_ACIVATE_PROHIBITED = 0x113, | |
1013 | NVME_SC_OVERLAPPING_RANGE = 0x114, | |
1014 | NVME_SC_NS_INSUFFICENT_CAP = 0x115, | |
1015 | NVME_SC_NS_ID_UNAVAILABLE = 0x116, | |
1016 | NVME_SC_NS_ALREADY_ATTACHED = 0x118, | |
1017 | NVME_SC_NS_IS_PRIVATE = 0x119, | |
1018 | NVME_SC_NS_NOT_ATTACHED = 0x11a, | |
1019 | NVME_SC_THIN_PROV_NOT_SUPP = 0x11b, | |
1020 | NVME_SC_CTRL_LIST_INVALID = 0x11c, | |
eb793e2c CH |
1021 | |
1022 | /* | |
1023 | * I/O Command Set Specific - NVM commands: | |
1024 | */ | |
9d99a8dd CH |
1025 | NVME_SC_BAD_ATTRIBUTES = 0x180, |
1026 | NVME_SC_INVALID_PI = 0x181, | |
1027 | NVME_SC_READ_ONLY = 0x182, | |
3b7c33b2 | 1028 | NVME_SC_ONCS_NOT_SUPPORTED = 0x183, |
eb793e2c CH |
1029 | |
1030 | /* | |
1031 | * I/O Command Set Specific - Fabrics commands: | |
1032 | */ | |
1033 | NVME_SC_CONNECT_FORMAT = 0x180, | |
1034 | NVME_SC_CONNECT_CTRL_BUSY = 0x181, | |
1035 | NVME_SC_CONNECT_INVALID_PARAM = 0x182, | |
1036 | NVME_SC_CONNECT_RESTART_DISC = 0x183, | |
1037 | NVME_SC_CONNECT_INVALID_HOST = 0x184, | |
1038 | ||
1039 | NVME_SC_DISCOVERY_RESTART = 0x190, | |
1040 | NVME_SC_AUTH_REQUIRED = 0x191, | |
1041 | ||
1042 | /* | |
1043 | * Media and Data Integrity Errors: | |
1044 | */ | |
9d99a8dd CH |
1045 | NVME_SC_WRITE_FAULT = 0x280, |
1046 | NVME_SC_READ_ERROR = 0x281, | |
1047 | NVME_SC_GUARD_CHECK = 0x282, | |
1048 | NVME_SC_APPTAG_CHECK = 0x283, | |
1049 | NVME_SC_REFTAG_CHECK = 0x284, | |
1050 | NVME_SC_COMPARE_FAILED = 0x285, | |
1051 | NVME_SC_ACCESS_DENIED = 0x286, | |
a446c084 | 1052 | NVME_SC_UNWRITTEN_BLOCK = 0x287, |
eb793e2c | 1053 | |
9d99a8dd | 1054 | NVME_SC_DNR = 0x4000, |
cba3bdfd JS |
1055 | |
1056 | ||
1057 | /* | |
1058 | * FC Transport-specific error status values for NVME commands | |
1059 | * | |
1060 | * Transport-specific status code values must be in the range 0xB0..0xBF | |
1061 | */ | |
1062 | ||
1063 | /* Generic FC failure - catchall */ | |
1064 | NVME_SC_FC_TRANSPORT_ERROR = 0x00B0, | |
1065 | ||
1066 | /* I/O failure due to FC ABTS'd */ | |
1067 | NVME_SC_FC_TRANSPORT_ABORTED = 0x00B1, | |
9d99a8dd CH |
1068 | }; |
1069 | ||
1070 | struct nvme_completion { | |
eb793e2c CH |
1071 | /* |
1072 | * Used by Admin and Fabrics commands to return data: | |
1073 | */ | |
d49187e9 CH |
1074 | union nvme_result { |
1075 | __le16 u16; | |
1076 | __le32 u32; | |
1077 | __le64 u64; | |
1078 | } result; | |
9d99a8dd CH |
1079 | __le16 sq_head; /* how much of this queue may be reclaimed */ |
1080 | __le16 sq_id; /* submission queue that generated this entry */ | |
1081 | __u16 command_id; /* of the command which completed */ | |
1082 | __le16 status; /* did the command fail, and if so, why? */ | |
1083 | }; | |
1084 | ||
8ef2074d GKB |
1085 | #define NVME_VS(major, minor, tertiary) \ |
1086 | (((major) << 16) | ((minor) << 8) | (tertiary)) | |
9d99a8dd | 1087 | |
c61d788b JT |
1088 | #define NVME_MAJOR(ver) ((ver) >> 16) |
1089 | #define NVME_MINOR(ver) (((ver) >> 8) & 0xff) | |
1090 | #define NVME_TERTIARY(ver) ((ver) & 0xff) | |
1091 | ||
b60503ba | 1092 | #endif /* _LINUX_NVME_H */ |