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nvme: define NVME_NSID_ALL
[mirror_ubuntu-jammy-kernel.git] / include / linux / nvme.h
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b60503ba
MW		 1/*
2 * Definitions for the NVM Express interface
8757ad65 3 * Copyright (c) 2011-2014, Intel Corporation.
b60503ba
MW		 4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms and conditions of the GNU General Public License,
7 * version 2, as published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
b60503ba
MW		 13 */
14
15#ifndef _LINUX_NVME_H
16#define _LINUX_NVME_H
17
2812dfe3 18#include <linux/types.h>
8e412263 19#include <linux/uuid.h>
eb793e2c
CH		 20
21/* NQN names in commands fields specified one size */
22#define NVMF_NQN_FIELD_LEN 256
23
24/* However the max length of a qualified name is another size */
25#define NVMF_NQN_SIZE 223
26
27#define NVMF_TRSVCID_SIZE 32
28#define NVMF_TRADDR_SIZE 256
29#define NVMF_TSAS_SIZE 256
30
31#define NVME_DISC_SUBSYS_NAME "nqn.2014-08.org.nvmexpress.discovery"
32
33#define NVME_RDMA_IP_PORT 4420
34
62346eae
AD		 35#define NVME_NSID_ALL 0xffffffff
36
eb793e2c
CH		 37enum nvme_subsys_type {
38 NVME_NQN_DISC = 1, /* Discovery type target subsystem */
39 NVME_NQN_NVME = 2, /* NVME type target subsystem */
40};
41
42/* Address Family codes for Discovery Log Page entry ADRFAM field */
43enum {
44 NVMF_ADDR_FAMILY_PCI = 0, /* PCIe */
45 NVMF_ADDR_FAMILY_IP4 = 1, /* IP4 */
46 NVMF_ADDR_FAMILY_IP6 = 2, /* IP6 */
47 NVMF_ADDR_FAMILY_IB = 3, /* InfiniBand */
48 NVMF_ADDR_FAMILY_FC = 4, /* Fibre Channel */
49};
50
51/* Transport Type codes for Discovery Log Page entry TRTYPE field */
52enum {
53 NVMF_TRTYPE_RDMA = 1, /* RDMA */
54 NVMF_TRTYPE_FC = 2, /* Fibre Channel */
55 NVMF_TRTYPE_LOOP = 254, /* Reserved for host usage */
56 NVMF_TRTYPE_MAX,
57};
58
59/* Transport Requirements codes for Discovery Log Page entry TREQ field */
60enum {
61 NVMF_TREQ_NOT_SPECIFIED = 0, /* Not specified */
62 NVMF_TREQ_REQUIRED = 1, /* Required */
63 NVMF_TREQ_NOT_REQUIRED = 2, /* Not Required */
64};
65
66/* RDMA QP Service Type codes for Discovery Log Page entry TSAS
67 * RDMA_QPTYPE field
68 */
69enum {
bf17aa36
RD		 70 NVMF_RDMA_QPTYPE_CONNECTED = 1, /* Reliable Connected */
71 NVMF_RDMA_QPTYPE_DATAGRAM = 2, /* Reliable Datagram */
eb793e2c
CH		 72};
73
74/* RDMA QP Service Type codes for Discovery Log Page entry TSAS
75 * RDMA_QPTYPE field
76 */
77enum {
bf17aa36
RD		 78 NVMF_RDMA_PRTYPE_NOT_SPECIFIED = 1, /* No Provider Specified */
79 NVMF_RDMA_PRTYPE_IB = 2, /* InfiniBand */
80 NVMF_RDMA_PRTYPE_ROCE = 3, /* InfiniBand RoCE */
81 NVMF_RDMA_PRTYPE_ROCEV2 = 4, /* InfiniBand RoCEV2 */
82 NVMF_RDMA_PRTYPE_IWARP = 5, /* IWARP */
eb793e2c
CH		 83};
84
85/* RDMA Connection Management Service Type codes for Discovery Log Page
86 * entry TSAS RDMA_CMS field
87 */
88enum {
bf17aa36 89 NVMF_RDMA_CMS_RDMA_CM = 1, /* Sockets based endpoint addressing */
eb793e2c
CH		 90};
91
7aa1f427 92#define NVME_AQ_DEPTH 32
2812dfe3 93
7a67cbea
CH		 94enum {
95 NVME_REG_CAP = 0x0000, /* Controller Capabilities */
96 NVME_REG_VS = 0x0008, /* Version */
97 NVME_REG_INTMS = 0x000c, /* Interrupt Mask Set */
a5b714ad 98 NVME_REG_INTMC = 0x0010, /* Interrupt Mask Clear */
7a67cbea
CH		 99 NVME_REG_CC = 0x0014, /* Controller Configuration */
100 NVME_REG_CSTS = 0x001c, /* Controller Status */
101 NVME_REG_NSSR = 0x0020, /* NVM Subsystem Reset */
102 NVME_REG_AQA = 0x0024, /* Admin Queue Attributes */
103 NVME_REG_ASQ = 0x0028, /* Admin SQ Base Address */
a5b714ad 104 NVME_REG_ACQ = 0x0030, /* Admin CQ Base Address */
7a67cbea
CH		 105 NVME_REG_CMBLOC = 0x0038, /* Controller Memory Buffer Location */
106 NVME_REG_CMBSZ = 0x003c, /* Controller Memory Buffer Size */
97f6ef64 107 NVME_REG_DBS = 0x1000, /* SQ 0 Tail Doorbell */
b60503ba
MW		 108};
109
a0cadb85 110#define NVME_CAP_MQES(cap) ((cap) & 0xffff)
22605f96 111#define NVME_CAP_TIMEOUT(cap) (((cap) >> 24) & 0xff)
f1938f6e 112#define NVME_CAP_STRIDE(cap) (((cap) >> 32) & 0xf)
dfbac8c7 113#define NVME_CAP_NSSRC(cap) (((cap) >> 36) & 0x1)
8fc23e03 114#define NVME_CAP_MPSMIN(cap) (((cap) >> 48) & 0xf)
1d090624 115#define NVME_CAP_MPSMAX(cap) (((cap) >> 52) & 0xf)
22605f96 116
8ffaadf7
JD		 117#define NVME_CMB_BIR(cmbloc) ((cmbloc) & 0x7)
118#define NVME_CMB_OFST(cmbloc) (((cmbloc) >> 12) & 0xfffff)
119#define NVME_CMB_SZ(cmbsz) (((cmbsz) >> 12) & 0xfffff)
120#define NVME_CMB_SZU(cmbsz) (((cmbsz) >> 8) & 0xf)
121
122#define NVME_CMB_WDS(cmbsz) ((cmbsz) & 0x10)
123#define NVME_CMB_RDS(cmbsz) ((cmbsz) & 0x8)
124#define NVME_CMB_LISTS(cmbsz) ((cmbsz) & 0x4)
125#define NVME_CMB_CQS(cmbsz) ((cmbsz) & 0x2)
126#define NVME_CMB_SQS(cmbsz) ((cmbsz) & 0x1)
127
69cd27e2
CH		 128/*
129 * Submission and Completion Queue Entry Sizes for the NVM command set.
130 * (In bytes and specified as a power of two (2^n)).
131 */
132#define NVME_NVM_IOSQES 6
133#define NVME_NVM_IOCQES 4
134
b60503ba
MW		 135enum {
136 NVME_CC_ENABLE = 1 << 0,
137 NVME_CC_CSS_NVM = 0 << 4,
138 NVME_CC_MPS_SHIFT = 7,
139 NVME_CC_ARB_RR = 0 << 11,
140 NVME_CC_ARB_WRRU = 1 << 11,
7f53f9d2
MW		 141 NVME_CC_ARB_VS = 7 << 11,
142 NVME_CC_SHN_NONE = 0 << 14,
143 NVME_CC_SHN_NORMAL = 1 << 14,
144 NVME_CC_SHN_ABRUPT = 2 << 14,
1894d8f1 145 NVME_CC_SHN_MASK = 3 << 14,
69cd27e2
CH		 146 NVME_CC_IOSQES = NVME_NVM_IOSQES << 16,
147 NVME_CC_IOCQES = NVME_NVM_IOCQES << 20,
b60503ba
MW		 148 NVME_CSTS_RDY = 1 << 0,
149 NVME_CSTS_CFS = 1 << 1,
dfbac8c7 150 NVME_CSTS_NSSRO = 1 << 4,
b6dccf7f 151 NVME_CSTS_PP = 1 << 5,
b60503ba
MW		 152 NVME_CSTS_SHST_NORMAL = 0 << 2,
153 NVME_CSTS_SHST_OCCUR = 1 << 2,
154 NVME_CSTS_SHST_CMPLT = 2 << 2,
1894d8f1 155 NVME_CSTS_SHST_MASK = 3 << 2,
b60503ba
MW		 156};
157
9d99a8dd
CH		 158struct nvme_id_power_state {
159 __le16 max_power; /* centiwatts */
160 __u8 rsvd2;
161 __u8 flags;
162 __le32 entry_lat; /* microseconds */
163 __le32 exit_lat; /* microseconds */
164 __u8 read_tput;
165 __u8 read_lat;
166 __u8 write_tput;
167 __u8 write_lat;
168 __le16 idle_power;
169 __u8 idle_scale;
170 __u8 rsvd19;
171 __le16 active_power;
172 __u8 active_work_scale;
173 __u8 rsvd23[9];
174};
175
176enum {
177 NVME_PS_FLAGS_MAX_POWER_SCALE = 1 << 0,
178 NVME_PS_FLAGS_NON_OP_STATE = 1 << 1,
179};
180
181struct nvme_id_ctrl {
182 __le16 vid;
183 __le16 ssvid;
184 char sn[20];
185 char mn[40];
186 char fr[8];
187 __u8 rab;
188 __u8 ieee[3];
a446c084 189 __u8 cmic;
9d99a8dd 190 __u8 mdts;
08c69640
CH		 191 __le16 cntlid;
192 __le32 ver;
14e974a8
CH		 193 __le32 rtd3r;
194 __le32 rtd3e;
195 __le32 oaes;
eb793e2c
CH		 196 __le32 ctratt;
197 __u8 rsvd100[156];
9d99a8dd
CH		 198 __le16 oacs;
199 __u8 acl;
200 __u8 aerl;
201 __u8 frmw;
202 __u8 lpa;
203 __u8 elpe;
204 __u8 npss;
205 __u8 avscc;
206 __u8 apsta;
207 __le16 wctemp;
208 __le16 cctemp;
a446c084
CH		 209 __le16 mtfa;
210 __le32 hmpre;
211 __le32 hmmin;
212 __u8 tnvmcap[16];
213 __u8 unvmcap[16];
214 __le32 rpmbs;
435e8090
GJ		 215 __le16 edstt;
216 __u8 dsto;
217 __u8 fwug;
7b89eae2 218 __le16 kas;
435e8090
GJ		 219 __le16 hctma;
220 __le16 mntmt;
221 __le16 mxtmt;
222 __le32 sanicap;
223 __u8 rsvd332[180];
9d99a8dd
CH		 224 __u8 sqes;
225 __u8 cqes;
eb793e2c 226 __le16 maxcmd;
9d99a8dd
CH		 227 __le32 nn;
228 __le16 oncs;
229 __le16 fuses;
230 __u8 fna;
231 __u8 vwc;
232 __le16 awun;
233 __le16 awupf;
234 __u8 nvscc;
235 __u8 rsvd531;
236 __le16 acwu;
237 __u8 rsvd534[2];
238 __le32 sgls;
eb793e2c
CH		 239 __u8 rsvd540[228];
240 char subnqn[256];
241 __u8 rsvd1024[768];
242 __le32 ioccsz;
243 __le32 iorcsz;
244 __le16 icdoff;
245 __u8 ctrattr;
246 __u8 msdbd;
247 __u8 rsvd1804[244];
9d99a8dd
CH		 248 struct nvme_id_power_state psd[32];
249 __u8 vs[1024];
250};
251
252enum {
253 NVME_CTRL_ONCS_COMPARE = 1 << 0,
254 NVME_CTRL_ONCS_WRITE_UNCORRECTABLE = 1 << 1,
255 NVME_CTRL_ONCS_DSM = 1 << 2,
3b7c33b2 256 NVME_CTRL_ONCS_WRITE_ZEROES = 1 << 3,
9d99a8dd 257 NVME_CTRL_VWC_PRESENT = 1 << 0,
8a9ae523 258 NVME_CTRL_OACS_SEC_SUPP = 1 << 0,
f5d11840 259 NVME_CTRL_OACS_DIRECTIVES = 1 << 5,
f9f38e33 260 NVME_CTRL_OACS_DBBUF_SUPP = 1 << 7,
9d99a8dd
CH		 261};
262
263struct nvme_lbaf {
264 __le16 ms;
265 __u8 ds;
266 __u8 rp;
267};
268
269struct nvme_id_ns {
270 __le64 nsze;
271 __le64 ncap;
272 __le64 nuse;
273 __u8 nsfeat;
274 __u8 nlbaf;
275 __u8 flbas;
276 __u8 mc;
277 __u8 dpc;
278 __u8 dps;
279 __u8 nmic;
280 __u8 rescap;
281 __u8 fpi;
282 __u8 rsvd33;
283 __le16 nawun;
284 __le16 nawupf;
285 __le16 nacwu;
286 __le16 nabsn;
287 __le16 nabo;
288 __le16 nabspf;
6b8190d6 289 __le16 noiob;
a446c084 290 __u8 nvmcap[16];
9d99a8dd
CH		 291 __u8 rsvd64[40];
292 __u8 nguid[16];
293 __u8 eui64[8];
294 struct nvme_lbaf lbaf[16];
295 __u8 rsvd192[192];
296 __u8 vs[3712];
297};
298
329dd768
CH		 299enum {
300 NVME_ID_CNS_NS = 0x00,
301 NVME_ID_CNS_CTRL = 0x01,
302 NVME_ID_CNS_NS_ACTIVE_LIST = 0x02,
af8b86e9 303 NVME_ID_CNS_NS_DESC_LIST = 0x03,
329dd768
CH		 304 NVME_ID_CNS_NS_PRESENT_LIST = 0x10,
305 NVME_ID_CNS_NS_PRESENT = 0x11,
306 NVME_ID_CNS_CTRL_NS_LIST = 0x12,
307 NVME_ID_CNS_CTRL_LIST = 0x13,
308};
309
f5d11840
JA		 310enum {
311 NVME_DIR_IDENTIFY = 0x00,
312 NVME_DIR_STREAMS = 0x01,
313 NVME_DIR_SND_ID_OP_ENABLE = 0x01,
314 NVME_DIR_SND_ST_OP_REL_ID = 0x01,
315 NVME_DIR_SND_ST_OP_REL_RSC = 0x02,
316 NVME_DIR_RCV_ID_OP_PARAM = 0x01,
317 NVME_DIR_RCV_ST_OP_PARAM = 0x01,
318 NVME_DIR_RCV_ST_OP_STATUS = 0x02,
319 NVME_DIR_RCV_ST_OP_RESOURCE = 0x03,
320 NVME_DIR_ENDIR = 0x01,
321};
322
9d99a8dd
CH		 323enum {
324 NVME_NS_FEAT_THIN = 1 << 0,
325 NVME_NS_FLBAS_LBA_MASK = 0xf,
326 NVME_NS_FLBAS_META_EXT = 0x10,
327 NVME_LBAF_RP_BEST = 0,
328 NVME_LBAF_RP_BETTER = 1,
329 NVME_LBAF_RP_GOOD = 2,
330 NVME_LBAF_RP_DEGRADED = 3,
331 NVME_NS_DPC_PI_LAST = 1 << 4,
332 NVME_NS_DPC_PI_FIRST = 1 << 3,
333 NVME_NS_DPC_PI_TYPE3 = 1 << 2,
334 NVME_NS_DPC_PI_TYPE2 = 1 << 1,
335 NVME_NS_DPC_PI_TYPE1 = 1 << 0,
336 NVME_NS_DPS_PI_FIRST = 1 << 3,
337 NVME_NS_DPS_PI_MASK = 0x7,
338 NVME_NS_DPS_PI_TYPE1 = 1,
339 NVME_NS_DPS_PI_TYPE2 = 2,
340 NVME_NS_DPS_PI_TYPE3 = 3,
341};
342
af8b86e9
JT		 343struct nvme_ns_id_desc {
344 __u8 nidt;
345 __u8 nidl;
346 __le16 reserved;
347};
348
349#define NVME_NIDT_EUI64_LEN 8
350#define NVME_NIDT_NGUID_LEN 16
351#define NVME_NIDT_UUID_LEN 16
352
353enum {
354 NVME_NIDT_EUI64 = 0x01,
355 NVME_NIDT_NGUID = 0x02,
356 NVME_NIDT_UUID = 0x03,
357};
358
9d99a8dd
CH		 359struct nvme_smart_log {
360 __u8 critical_warning;
361 __u8 temperature[2];
362 __u8 avail_spare;
363 __u8 spare_thresh;
364 __u8 percent_used;
365 __u8 rsvd6[26];
366 __u8 data_units_read[16];
367 __u8 data_units_written[16];
368 __u8 host_reads[16];
369 __u8 host_writes[16];
370 __u8 ctrl_busy_time[16];
371 __u8 power_cycles[16];
372 __u8 power_on_hours[16];
373 __u8 unsafe_shutdowns[16];
374 __u8 media_errors[16];
375 __u8 num_err_log_entries[16];
376 __le32 warning_temp_time;
377 __le32 critical_comp_time;
378 __le16 temp_sensor[8];
379 __u8 rsvd216[296];
380};
381
b6dccf7f
AD		 382struct nvme_fw_slot_info_log {
383 __u8 afi;
384 __u8 rsvd1[7];
385 __le64 frs[7];
386 __u8 rsvd64[448];
387};
388
9d99a8dd
CH		 389enum {
390 NVME_SMART_CRIT_SPARE = 1 << 0,
391 NVME_SMART_CRIT_TEMPERATURE = 1 << 1,
392 NVME_SMART_CRIT_RELIABILITY = 1 << 2,
393 NVME_SMART_CRIT_MEDIA = 1 << 3,
394 NVME_SMART_CRIT_VOLATILE_MEMORY = 1 << 4,
395};
396
397enum {
398 NVME_AER_NOTICE_NS_CHANGED = 0x0002,
b6dccf7f 399 NVME_AER_NOTICE_FW_ACT_STARTING = 0x0102,
9d99a8dd
CH		 400};
401
402struct nvme_lba_range_type {
403 __u8 type;
404 __u8 attributes;
405 __u8 rsvd2[14];
406 __u64 slba;
407 __u64 nlb;
408 __u8 guid[16];
409 __u8 rsvd48[16];
410};
411
412enum {
413 NVME_LBART_TYPE_FS = 0x01,
414 NVME_LBART_TYPE_RAID = 0x02,
415 NVME_LBART_TYPE_CACHE = 0x03,
416 NVME_LBART_TYPE_SWAP = 0x04,
417
418 NVME_LBART_ATTRIB_TEMP = 1 << 0,
419 NVME_LBART_ATTRIB_HIDE = 1 << 1,
420};
421
422struct nvme_reservation_status {
423 __le32 gen;
424 __u8 rtype;
425 __u8 regctl[2];
426 __u8 resv5[2];
427 __u8 ptpls;
428 __u8 resv10[13];
429 struct {
430 __le16 cntlid;
431 __u8 rcsts;
432 __u8 resv3[5];
433 __le64 hostid;
434 __le64 rkey;
435 } regctl_ds[];
436};
437
79f370ea
CH		 438enum nvme_async_event_type {
439 NVME_AER_TYPE_ERROR = 0,
440 NVME_AER_TYPE_SMART = 1,
441 NVME_AER_TYPE_NOTICE = 2,
442};
443
9d99a8dd
CH		 444/* I/O commands */
445
446enum nvme_opcode {
447 nvme_cmd_flush = 0x00,
448 nvme_cmd_write = 0x01,
449 nvme_cmd_read = 0x02,
450 nvme_cmd_write_uncor = 0x04,
451 nvme_cmd_compare = 0x05,
452 nvme_cmd_write_zeroes = 0x08,
453 nvme_cmd_dsm = 0x09,
454 nvme_cmd_resv_register = 0x0d,
455 nvme_cmd_resv_report = 0x0e,
456 nvme_cmd_resv_acquire = 0x11,
457 nvme_cmd_resv_release = 0x15,
458};
459
eb793e2c
CH		 460/*
461 * Descriptor subtype - lower 4 bits of nvme_(keyed_)sgl_desc identifier
462 *
463 * @NVME_SGL_FMT_ADDRESS: absolute address of the data block
464 * @NVME_SGL_FMT_OFFSET: relative offset of the in-capsule data block
465 * @NVME_SGL_FMT_INVALIDATE: RDMA transport specific remote invalidation
466 * request subtype
467 */
468enum {
469 NVME_SGL_FMT_ADDRESS = 0x00,
470 NVME_SGL_FMT_OFFSET = 0x01,
471 NVME_SGL_FMT_INVALIDATE = 0x0f,
472};
473
474/*
475 * Descriptor type - upper 4 bits of nvme_(keyed_)sgl_desc identifier
476 *
477 * For struct nvme_sgl_desc:
478 * @NVME_SGL_FMT_DATA_DESC: data block descriptor
479 * @NVME_SGL_FMT_SEG_DESC: sgl segment descriptor
480 * @NVME_SGL_FMT_LAST_SEG_DESC: last sgl segment descriptor
481 *
482 * For struct nvme_keyed_sgl_desc:
483 * @NVME_KEY_SGL_FMT_DATA_DESC: keyed data block descriptor
484 */
485enum {
486 NVME_SGL_FMT_DATA_DESC = 0x00,
487 NVME_SGL_FMT_SEG_DESC = 0x02,
488 NVME_SGL_FMT_LAST_SEG_DESC = 0x03,
489 NVME_KEY_SGL_FMT_DATA_DESC = 0x04,
490};
491
492struct nvme_sgl_desc {
493 __le64 addr;
494 __le32 length;
495 __u8 rsvd[3];
496 __u8 type;
497};
498
499struct nvme_keyed_sgl_desc {
500 __le64 addr;
501 __u8 length[3];
502 __u8 key[4];
503 __u8 type;
504};
505
506union nvme_data_ptr {
507 struct {
508 __le64 prp1;
509 __le64 prp2;
510 };
511 struct nvme_sgl_desc sgl;
512 struct nvme_keyed_sgl_desc ksgl;
513};
514
3972be23
JS		 515/*
516 * Lowest two bits of our flags field (FUSE field in the spec):
517 *
518 * @NVME_CMD_FUSE_FIRST: Fused Operation, first command
519 * @NVME_CMD_FUSE_SECOND: Fused Operation, second command
520 *
521 * Highest two bits in our flags field (PSDT field in the spec):
522 *
523 * @NVME_CMD_PSDT_SGL_METABUF: Use SGLS for this transfer,
524 * If used, MPTR contains addr of single physical buffer (byte aligned).
525 * @NVME_CMD_PSDT_SGL_METASEG: Use SGLS for this transfer,
526 * If used, MPTR contains an address of an SGL segment containing
527 * exactly 1 SGL descriptor (qword aligned).
528 */
529enum {
530 NVME_CMD_FUSE_FIRST = (1 << 0),
531 NVME_CMD_FUSE_SECOND = (1 << 1),
532
533 NVME_CMD_SGL_METABUF = (1 << 6),
534 NVME_CMD_SGL_METASEG = (1 << 7),
535 NVME_CMD_SGL_ALL = NVME_CMD_SGL_METABUF | NVME_CMD_SGL_METASEG,
536};
537
9d99a8dd
CH		 538struct nvme_common_command {
539 __u8 opcode;
540 __u8 flags;
541 __u16 command_id;
542 __le32 nsid;
543 __le32 cdw2[2];
544 __le64 metadata;
eb793e2c 545 union nvme_data_ptr dptr;
9d99a8dd
CH		 546 __le32 cdw10[6];
547};
548
549struct nvme_rw_command {
550 __u8 opcode;
551 __u8 flags;
552 __u16 command_id;
553 __le32 nsid;
554 __u64 rsvd2;
555 __le64 metadata;
eb793e2c 556 union nvme_data_ptr dptr;
9d99a8dd
CH		 557 __le64 slba;
558 __le16 length;
559 __le16 control;
560 __le32 dsmgmt;
561 __le32 reftag;
562 __le16 apptag;
563 __le16 appmask;
564};
565
566enum {
567 NVME_RW_LR = 1 << 15,
568 NVME_RW_FUA = 1 << 14,
569 NVME_RW_DSM_FREQ_UNSPEC = 0,
570 NVME_RW_DSM_FREQ_TYPICAL = 1,
571 NVME_RW_DSM_FREQ_RARE = 2,
572 NVME_RW_DSM_FREQ_READS = 3,
573 NVME_RW_DSM_FREQ_WRITES = 4,
574 NVME_RW_DSM_FREQ_RW = 5,
575 NVME_RW_DSM_FREQ_ONCE = 6,
576 NVME_RW_DSM_FREQ_PREFETCH = 7,
577 NVME_RW_DSM_FREQ_TEMP = 8,
578 NVME_RW_DSM_LATENCY_NONE = 0 << 4,
579 NVME_RW_DSM_LATENCY_IDLE = 1 << 4,
580 NVME_RW_DSM_LATENCY_NORM = 2 << 4,
581 NVME_RW_DSM_LATENCY_LOW = 3 << 4,
582 NVME_RW_DSM_SEQ_REQ = 1 << 6,
583 NVME_RW_DSM_COMPRESSED = 1 << 7,
584 NVME_RW_PRINFO_PRCHK_REF = 1 << 10,
585 NVME_RW_PRINFO_PRCHK_APP = 1 << 11,
586 NVME_RW_PRINFO_PRCHK_GUARD = 1 << 12,
587 NVME_RW_PRINFO_PRACT = 1 << 13,
f5d11840 588 NVME_RW_DTYPE_STREAMS = 1 << 4,
9d99a8dd
CH		 589};
590
591struct nvme_dsm_cmd {
592 __u8 opcode;
593 __u8 flags;
594 __u16 command_id;
595 __le32 nsid;
596 __u64 rsvd2[2];
eb793e2c 597 union nvme_data_ptr dptr;
9d99a8dd
CH		 598 __le32 nr;
599 __le32 attributes;
600 __u32 rsvd12[4];
601};
602
603enum {
604 NVME_DSMGMT_IDR = 1 << 0,
605 NVME_DSMGMT_IDW = 1 << 1,
606 NVME_DSMGMT_AD = 1 << 2,
607};
608
b35ba01e
CH		 609#define NVME_DSM_MAX_RANGES 256
610
9d99a8dd
CH		 611struct nvme_dsm_range {
612 __le32 cattr;
613 __le32 nlb;
614 __le64 slba;
615};
616
3b7c33b2
CK		 617struct nvme_write_zeroes_cmd {
618 __u8 opcode;
619 __u8 flags;
620 __u16 command_id;
621 __le32 nsid;
622 __u64 rsvd2;
623 __le64 metadata;
624 union nvme_data_ptr dptr;
625 __le64 slba;
626 __le16 length;
627 __le16 control;
628 __le32 dsmgmt;
629 __le32 reftag;
630 __le16 apptag;
631 __le16 appmask;
632};
633
c5552fde
AL		 634/* Features */
635
636struct nvme_feat_auto_pst {
637 __le64 entries[32];
638};
639
39673e19
CH		 640enum {
641 NVME_HOST_MEM_ENABLE = (1 << 0),
642 NVME_HOST_MEM_RETURN = (1 << 1),
643};
644
9d99a8dd
CH		 645/* Admin commands */
646
647enum nvme_admin_opcode {
648 nvme_admin_delete_sq = 0x00,
649 nvme_admin_create_sq = 0x01,
650 nvme_admin_get_log_page = 0x02,
651 nvme_admin_delete_cq = 0x04,
652 nvme_admin_create_cq = 0x05,
653 nvme_admin_identify = 0x06,
654 nvme_admin_abort_cmd = 0x08,
655 nvme_admin_set_features = 0x09,
656 nvme_admin_get_features = 0x0a,
657 nvme_admin_async_event = 0x0c,
a446c084 658 nvme_admin_ns_mgmt = 0x0d,
9d99a8dd
CH		 659 nvme_admin_activate_fw = 0x10,
660 nvme_admin_download_fw = 0x11,
a446c084 661 nvme_admin_ns_attach = 0x15,
7b89eae2 662 nvme_admin_keep_alive = 0x18,
f5d11840
JA		 663 nvme_admin_directive_send = 0x19,
664 nvme_admin_directive_recv = 0x1a,
f9f38e33 665 nvme_admin_dbbuf = 0x7C,
9d99a8dd
CH		 666 nvme_admin_format_nvm = 0x80,
667 nvme_admin_security_send = 0x81,
668 nvme_admin_security_recv = 0x82,
669};
670
671enum {
672 NVME_QUEUE_PHYS_CONTIG = (1 << 0),
673 NVME_CQ_IRQ_ENABLED = (1 << 1),
674 NVME_SQ_PRIO_URGENT = (0 << 1),
675 NVME_SQ_PRIO_HIGH = (1 << 1),
676 NVME_SQ_PRIO_MEDIUM = (2 << 1),
677 NVME_SQ_PRIO_LOW = (3 << 1),
678 NVME_FEAT_ARBITRATION = 0x01,
679 NVME_FEAT_POWER_MGMT = 0x02,
680 NVME_FEAT_LBA_RANGE = 0x03,
681 NVME_FEAT_TEMP_THRESH = 0x04,
682 NVME_FEAT_ERR_RECOVERY = 0x05,
683 NVME_FEAT_VOLATILE_WC = 0x06,
684 NVME_FEAT_NUM_QUEUES = 0x07,
685 NVME_FEAT_IRQ_COALESCE = 0x08,
686 NVME_FEAT_IRQ_CONFIG = 0x09,
687 NVME_FEAT_WRITE_ATOMIC = 0x0a,
688 NVME_FEAT_ASYNC_EVENT = 0x0b,
689 NVME_FEAT_AUTO_PST = 0x0c,
a446c084 690 NVME_FEAT_HOST_MEM_BUF = 0x0d,
7b89eae2 691 NVME_FEAT_KATO = 0x0f,
9d99a8dd
CH		 692 NVME_FEAT_SW_PROGRESS = 0x80,
693 NVME_FEAT_HOST_ID = 0x81,
694 NVME_FEAT_RESV_MASK = 0x82,
695 NVME_FEAT_RESV_PERSIST = 0x83,
696 NVME_LOG_ERROR = 0x01,
697 NVME_LOG_SMART = 0x02,
698 NVME_LOG_FW_SLOT = 0x03,
eb793e2c 699 NVME_LOG_DISC = 0x70,
9d99a8dd
CH		 700 NVME_LOG_RESERVATION = 0x80,
701 NVME_FWACT_REPL = (0 << 3),
702 NVME_FWACT_REPL_ACTV = (1 << 3),
703 NVME_FWACT_ACTV = (2 << 3),
704};
705
706struct nvme_identify {
707 __u8 opcode;
708 __u8 flags;
709 __u16 command_id;
710 __le32 nsid;
711 __u64 rsvd2[2];
eb793e2c 712 union nvme_data_ptr dptr;
986994a2
PP		 713 __u8 cns;
714 __u8 rsvd3;
715 __le16 ctrlid;
9d99a8dd
CH		 716 __u32 rsvd11[5];
717};
718
0add5e8e
JT		 719#define NVME_IDENTIFY_DATA_SIZE 4096
720
9d99a8dd
CH		 721struct nvme_features {
722 __u8 opcode;
723 __u8 flags;
724 __u16 command_id;
725 __le32 nsid;
726 __u64 rsvd2[2];
eb793e2c 727 union nvme_data_ptr dptr;
9d99a8dd
CH		 728 __le32 fid;
729 __le32 dword11;
b85cf734
AD		 730 __le32 dword12;
731 __le32 dword13;
732 __le32 dword14;
733 __le32 dword15;
9d99a8dd
CH		 734};
735
39673e19
CH		 736struct nvme_host_mem_buf_desc {
737 __le64 addr;
738 __le32 size;
739 __u32 rsvd;
740};
741
9d99a8dd
CH		 742struct nvme_create_cq {
743 __u8 opcode;
744 __u8 flags;
745 __u16 command_id;
746 __u32 rsvd1[5];
747 __le64 prp1;
748 __u64 rsvd8;
749 __le16 cqid;
750 __le16 qsize;
751 __le16 cq_flags;
752 __le16 irq_vector;
753 __u32 rsvd12[4];
754};
755
756struct nvme_create_sq {
757 __u8 opcode;
758 __u8 flags;
759 __u16 command_id;
760 __u32 rsvd1[5];
761 __le64 prp1;
762 __u64 rsvd8;
763 __le16 sqid;
764 __le16 qsize;
765 __le16 sq_flags;
766 __le16 cqid;
767 __u32 rsvd12[4];
768};
769
770struct nvme_delete_queue {
771 __u8 opcode;
772 __u8 flags;
773 __u16 command_id;
774 __u32 rsvd1[9];
775 __le16 qid;
776 __u16 rsvd10;
777 __u32 rsvd11[5];
778};
779
780struct nvme_abort_cmd {
781 __u8 opcode;
782 __u8 flags;
783 __u16 command_id;
784 __u32 rsvd1[9];
785 __le16 sqid;
786 __u16 cid;
787 __u32 rsvd11[5];
788};
789
790struct nvme_download_firmware {
791 __u8 opcode;
792 __u8 flags;
793 __u16 command_id;
794 __u32 rsvd1[5];
eb793e2c 795 union nvme_data_ptr dptr;
9d99a8dd
CH		 796 __le32 numd;
797 __le32 offset;
798 __u32 rsvd12[4];
799};
800
801struct nvme_format_cmd {
802 __u8 opcode;
803 __u8 flags;
804 __u16 command_id;
805 __le32 nsid;
806 __u64 rsvd2[4];
807 __le32 cdw10;
808 __u32 rsvd11[5];
809};
810
725b3588
AB		 811struct nvme_get_log_page_command {
812 __u8 opcode;
813 __u8 flags;
814 __u16 command_id;
815 __le32 nsid;
816 __u64 rsvd2[2];
eb793e2c 817 union nvme_data_ptr dptr;
725b3588
AB		 818 __u8 lid;
819 __u8 rsvd10;
820 __le16 numdl;
821 __le16 numdu;
822 __u16 rsvd11;
823 __le32 lpol;
824 __le32 lpou;
825 __u32 rsvd14[2];
826};
827
f5d11840
JA		 828struct nvme_directive_cmd {
829 __u8 opcode;
830 __u8 flags;
831 __u16 command_id;
832 __le32 nsid;
833 __u64 rsvd2[2];
834 union nvme_data_ptr dptr;
835 __le32 numd;
836 __u8 doper;
837 __u8 dtype;
838 __le16 dspec;
839 __u8 endir;
840 __u8 tdtype;
841 __u16 rsvd15;
842
843 __u32 rsvd16[3];
844};
845
eb793e2c
CH		 846/*
847 * Fabrics subcommands.
848 */
849enum nvmf_fabrics_opcode {
850 nvme_fabrics_command = 0x7f,
851};
852
853enum nvmf_capsule_command {
854 nvme_fabrics_type_property_set = 0x00,
855 nvme_fabrics_type_connect = 0x01,
856 nvme_fabrics_type_property_get = 0x04,
857};
858
859struct nvmf_common_command {
860 __u8 opcode;
861 __u8 resv1;
862 __u16 command_id;
863 __u8 fctype;
864 __u8 resv2[35];
865 __u8 ts[24];
866};
867
868/*
869 * The legal cntlid range a NVMe Target will provide.
870 * Note that cntlid of value 0 is considered illegal in the fabrics world.
871 * Devices based on earlier specs did not have the subsystem concept;
872 * therefore, those devices had their cntlid value set to 0 as a result.
873 */
874#define NVME_CNTLID_MIN 1
875#define NVME_CNTLID_MAX 0xffef
876#define NVME_CNTLID_DYNAMIC 0xffff
877
878#define MAX_DISC_LOGS 255
879
880/* Discovery log page entry */
881struct nvmf_disc_rsp_page_entry {
882 __u8 trtype;
883 __u8 adrfam;
a446c084 884 __u8 subtype;
eb793e2c
CH		 885 __u8 treq;
886 __le16 portid;
887 __le16 cntlid;
888 __le16 asqsz;
889 __u8 resv8[22];
890 char trsvcid[NVMF_TRSVCID_SIZE];
891 __u8 resv64[192];
892 char subnqn[NVMF_NQN_FIELD_LEN];
893 char traddr[NVMF_TRADDR_SIZE];
894 union tsas {
895 char common[NVMF_TSAS_SIZE];
896 struct rdma {
897 __u8 qptype;
898 __u8 prtype;
899 __u8 cms;
900 __u8 resv3[5];
901 __u16 pkey;
902 __u8 resv10[246];
903 } rdma;
904 } tsas;
905};
906
907/* Discovery log page header */
908struct nvmf_disc_rsp_page_hdr {
909 __le64 genctr;
910 __le64 numrec;
911 __le16 recfmt;
912 __u8 resv14[1006];
913 struct nvmf_disc_rsp_page_entry entries[0];
914};
915
916struct nvmf_connect_command {
917 __u8 opcode;
918 __u8 resv1;
919 __u16 command_id;
920 __u8 fctype;
921 __u8 resv2[19];
922 union nvme_data_ptr dptr;
923 __le16 recfmt;
924 __le16 qid;
925 __le16 sqsize;
926 __u8 cattr;
927 __u8 resv3;
928 __le32 kato;
929 __u8 resv4[12];
930};
931
932struct nvmf_connect_data {
8e412263 933 uuid_t hostid;
eb793e2c
CH		 934 __le16 cntlid;
935 char resv4[238];
936 char subsysnqn[NVMF_NQN_FIELD_LEN];
937 char hostnqn[NVMF_NQN_FIELD_LEN];
938 char resv5[256];
939};
940
941struct nvmf_property_set_command {
942 __u8 opcode;
943 __u8 resv1;
944 __u16 command_id;
945 __u8 fctype;
946 __u8 resv2[35];
947 __u8 attrib;
948 __u8 resv3[3];
949 __le32 offset;
950 __le64 value;
951 __u8 resv4[8];
952};
953
954struct nvmf_property_get_command {
955 __u8 opcode;
956 __u8 resv1;
957 __u16 command_id;
958 __u8 fctype;
959 __u8 resv2[35];
960 __u8 attrib;
961 __u8 resv3[3];
962 __le32 offset;
963 __u8 resv4[16];
964};
965
f9f38e33
HK		 966struct nvme_dbbuf {
967 __u8 opcode;
968 __u8 flags;
969 __u16 command_id;
970 __u32 rsvd1[5];
971 __le64 prp1;
972 __le64 prp2;
973 __u32 rsvd12[6];
974};
975
f5d11840 976struct streams_directive_params {
dc1a0afb
CH		 977 __le16 msl;
978 __le16 nssa;
979 __le16 nsso;
f5d11840 980 __u8 rsvd[10];
dc1a0afb
CH		 981 __le32 sws;
982 __le16 sgs;
983 __le16 nsa;
984 __le16 nso;
f5d11840
JA		 985 __u8 rsvd2[6];
986};
987
9d99a8dd
CH		 988struct nvme_command {
989 union {
990 struct nvme_common_command common;
991 struct nvme_rw_command rw;
992 struct nvme_identify identify;
993 struct nvme_features features;
994 struct nvme_create_cq create_cq;
995 struct nvme_create_sq create_sq;
996 struct nvme_delete_queue delete_queue;
997 struct nvme_download_firmware dlfw;
998 struct nvme_format_cmd format;
999 struct nvme_dsm_cmd dsm;
3b7c33b2 1000 struct nvme_write_zeroes_cmd write_zeroes;
9d99a8dd 1001 struct nvme_abort_cmd abort;
725b3588 1002 struct nvme_get_log_page_command get_log_page;
eb793e2c
CH		 1003 struct nvmf_common_command fabrics;
1004 struct nvmf_connect_command connect;
1005 struct nvmf_property_set_command prop_set;
1006 struct nvmf_property_get_command prop_get;
f9f38e33 1007 struct nvme_dbbuf dbbuf;
f5d11840 1008 struct nvme_directive_cmd directive;
9d99a8dd
CH		 1009 };
1010};
1011
7a5abb4b
CH		 1012static inline bool nvme_is_write(struct nvme_command *cmd)
1013{
eb793e2c
CH		 1014 /*
1015 * What a mess...
1016 *
1017 * Why can't we simply have a Fabrics In and Fabrics out command?
1018 */
1019 if (unlikely(cmd->common.opcode == nvme_fabrics_command))
2fd4167f 1020 return cmd->fabrics.fctype & 1;
7a5abb4b
CH		 1021 return cmd->common.opcode & 1;
1022}
1023
9d99a8dd 1024enum {
eb793e2c
CH		 1025 /*
1026 * Generic Command Status:
1027 */
9d99a8dd
CH		 1028 NVME_SC_SUCCESS = 0x0,
1029 NVME_SC_INVALID_OPCODE = 0x1,
1030 NVME_SC_INVALID_FIELD = 0x2,
1031 NVME_SC_CMDID_CONFLICT = 0x3,
1032 NVME_SC_DATA_XFER_ERROR = 0x4,
1033 NVME_SC_POWER_LOSS = 0x5,
1034 NVME_SC_INTERNAL = 0x6,
1035 NVME_SC_ABORT_REQ = 0x7,
1036 NVME_SC_ABORT_QUEUE = 0x8,
1037 NVME_SC_FUSED_FAIL = 0x9,
1038 NVME_SC_FUSED_MISSING = 0xa,
1039 NVME_SC_INVALID_NS = 0xb,
1040 NVME_SC_CMD_SEQ_ERROR = 0xc,
1041 NVME_SC_SGL_INVALID_LAST = 0xd,
1042 NVME_SC_SGL_INVALID_COUNT = 0xe,
1043 NVME_SC_SGL_INVALID_DATA = 0xf,
1044 NVME_SC_SGL_INVALID_METADATA = 0x10,
1045 NVME_SC_SGL_INVALID_TYPE = 0x11,
eb793e2c
CH		 1046
1047 NVME_SC_SGL_INVALID_OFFSET = 0x16,
1048 NVME_SC_SGL_INVALID_SUBTYPE = 0x17,
1049
9d99a8dd
CH		 1050 NVME_SC_LBA_RANGE = 0x80,
1051 NVME_SC_CAP_EXCEEDED = 0x81,
1052 NVME_SC_NS_NOT_READY = 0x82,
1053 NVME_SC_RESERVATION_CONFLICT = 0x83,
eb793e2c
CH		 1054
1055 /*
1056 * Command Specific Status:
1057 */
9d99a8dd
CH		 1058 NVME_SC_CQ_INVALID = 0x100,
1059 NVME_SC_QID_INVALID = 0x101,
1060 NVME_SC_QUEUE_SIZE = 0x102,
1061 NVME_SC_ABORT_LIMIT = 0x103,
1062 NVME_SC_ABORT_MISSING = 0x104,
1063 NVME_SC_ASYNC_LIMIT = 0x105,
1064 NVME_SC_FIRMWARE_SLOT = 0x106,
1065 NVME_SC_FIRMWARE_IMAGE = 0x107,
1066 NVME_SC_INVALID_VECTOR = 0x108,
1067 NVME_SC_INVALID_LOG_PAGE = 0x109,
1068 NVME_SC_INVALID_FORMAT = 0x10a,
a446c084 1069 NVME_SC_FW_NEEDS_CONV_RESET = 0x10b,
9d99a8dd
CH		 1070 NVME_SC_INVALID_QUEUE = 0x10c,
1071 NVME_SC_FEATURE_NOT_SAVEABLE = 0x10d,
1072 NVME_SC_FEATURE_NOT_CHANGEABLE = 0x10e,
1073 NVME_SC_FEATURE_NOT_PER_NS = 0x10f,
a446c084
CH		 1074 NVME_SC_FW_NEEDS_SUBSYS_RESET = 0x110,
1075 NVME_SC_FW_NEEDS_RESET = 0x111,
1076 NVME_SC_FW_NEEDS_MAX_TIME = 0x112,
1077 NVME_SC_FW_ACIVATE_PROHIBITED = 0x113,
1078 NVME_SC_OVERLAPPING_RANGE = 0x114,
1079 NVME_SC_NS_INSUFFICENT_CAP = 0x115,
1080 NVME_SC_NS_ID_UNAVAILABLE = 0x116,
1081 NVME_SC_NS_ALREADY_ATTACHED = 0x118,
1082 NVME_SC_NS_IS_PRIVATE = 0x119,
1083 NVME_SC_NS_NOT_ATTACHED = 0x11a,
1084 NVME_SC_THIN_PROV_NOT_SUPP = 0x11b,
1085 NVME_SC_CTRL_LIST_INVALID = 0x11c,
eb793e2c
CH		 1086
1087 /*
1088 * I/O Command Set Specific - NVM commands:
1089 */
9d99a8dd
CH		 1090 NVME_SC_BAD_ATTRIBUTES = 0x180,
1091 NVME_SC_INVALID_PI = 0x181,
1092 NVME_SC_READ_ONLY = 0x182,
3b7c33b2 1093 NVME_SC_ONCS_NOT_SUPPORTED = 0x183,
eb793e2c
CH		 1094
1095 /*
1096 * I/O Command Set Specific - Fabrics commands:
1097 */
1098 NVME_SC_CONNECT_FORMAT = 0x180,
1099 NVME_SC_CONNECT_CTRL_BUSY = 0x181,
1100 NVME_SC_CONNECT_INVALID_PARAM = 0x182,
1101 NVME_SC_CONNECT_RESTART_DISC = 0x183,
1102 NVME_SC_CONNECT_INVALID_HOST = 0x184,
1103
1104 NVME_SC_DISCOVERY_RESTART = 0x190,
1105 NVME_SC_AUTH_REQUIRED = 0x191,
1106
1107 /*
1108 * Media and Data Integrity Errors:
1109 */
9d99a8dd
CH		 1110 NVME_SC_WRITE_FAULT = 0x280,
1111 NVME_SC_READ_ERROR = 0x281,
1112 NVME_SC_GUARD_CHECK = 0x282,
1113 NVME_SC_APPTAG_CHECK = 0x283,
1114 NVME_SC_REFTAG_CHECK = 0x284,
1115 NVME_SC_COMPARE_FAILED = 0x285,
1116 NVME_SC_ACCESS_DENIED = 0x286,
a446c084 1117 NVME_SC_UNWRITTEN_BLOCK = 0x287,
eb793e2c 1118
9d99a8dd 1119 NVME_SC_DNR = 0x4000,
cba3bdfd
JS		 1120
1121
1122 /*
1123 * FC Transport-specific error status values for NVME commands
1124 *
1125 * Transport-specific status code values must be in the range 0xB0..0xBF
1126 */
1127
1128 /* Generic FC failure - catchall */
1129 NVME_SC_FC_TRANSPORT_ERROR = 0x00B0,
1130
1131 /* I/O failure due to FC ABTS'd */
1132 NVME_SC_FC_TRANSPORT_ABORTED = 0x00B1,
9d99a8dd
CH		 1133};
1134
1135struct nvme_completion {
eb793e2c
CH		 1136 /*
1137 * Used by Admin and Fabrics commands to return data:
1138 */
d49187e9
CH		 1139 union nvme_result {
1140 __le16 u16;
1141 __le32 u32;
1142 __le64 u64;
1143 } result;
9d99a8dd
CH		 1144 __le16 sq_head; /* how much of this queue may be reclaimed */
1145 __le16 sq_id; /* submission queue that generated this entry */
1146 __u16 command_id; /* of the command which completed */
1147 __le16 status; /* did the command fail, and if so, why? */
1148};
1149
8ef2074d
GKB		 1150#define NVME_VS(major, minor, tertiary) \
1151 (((major) << 16) | ((minor) << 8) | (tertiary))
9d99a8dd 1152
c61d788b
JT		 1153#define NVME_MAJOR(ver) ((ver) >> 16)
1154#define NVME_MINOR(ver) (((ver) >> 8) & 0xff)
1155#define NVME_TERTIARY(ver) ((ver) & 0xff)
1156
b60503ba 1157#endif /* _LINUX_NVME_H */
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