]>
Commit | Line | Data |
---|---|---|
b60503ba MW |
1 | /* |
2 | * Definitions for the NVM Express interface | |
8757ad65 | 3 | * Copyright (c) 2011-2014, Intel Corporation. |
b60503ba MW |
4 | * |
5 | * This program is free software; you can redistribute it and/or modify it | |
6 | * under the terms and conditions of the GNU General Public License, | |
7 | * version 2, as published by the Free Software Foundation. | |
8 | * | |
9 | * This program is distributed in the hope it will be useful, but WITHOUT | |
10 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
11 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
12 | * more details. | |
b60503ba MW |
13 | */ |
14 | ||
15 | #ifndef _LINUX_NVME_H | |
16 | #define _LINUX_NVME_H | |
17 | ||
2812dfe3 | 18 | #include <linux/types.h> |
8e412263 | 19 | #include <linux/uuid.h> |
eb793e2c CH |
20 | |
21 | /* NQN names in commands fields specified one size */ | |
22 | #define NVMF_NQN_FIELD_LEN 256 | |
23 | ||
24 | /* However the max length of a qualified name is another size */ | |
25 | #define NVMF_NQN_SIZE 223 | |
26 | ||
27 | #define NVMF_TRSVCID_SIZE 32 | |
28 | #define NVMF_TRADDR_SIZE 256 | |
29 | #define NVMF_TSAS_SIZE 256 | |
30 | ||
31 | #define NVME_DISC_SUBSYS_NAME "nqn.2014-08.org.nvmexpress.discovery" | |
32 | ||
33 | #define NVME_RDMA_IP_PORT 4420 | |
34 | ||
62346eae AD |
35 | #define NVME_NSID_ALL 0xffffffff |
36 | ||
eb793e2c CH |
37 | enum nvme_subsys_type { |
38 | NVME_NQN_DISC = 1, /* Discovery type target subsystem */ | |
39 | NVME_NQN_NVME = 2, /* NVME type target subsystem */ | |
40 | }; | |
41 | ||
42 | /* Address Family codes for Discovery Log Page entry ADRFAM field */ | |
43 | enum { | |
44 | NVMF_ADDR_FAMILY_PCI = 0, /* PCIe */ | |
45 | NVMF_ADDR_FAMILY_IP4 = 1, /* IP4 */ | |
46 | NVMF_ADDR_FAMILY_IP6 = 2, /* IP6 */ | |
47 | NVMF_ADDR_FAMILY_IB = 3, /* InfiniBand */ | |
48 | NVMF_ADDR_FAMILY_FC = 4, /* Fibre Channel */ | |
49 | }; | |
50 | ||
51 | /* Transport Type codes for Discovery Log Page entry TRTYPE field */ | |
52 | enum { | |
53 | NVMF_TRTYPE_RDMA = 1, /* RDMA */ | |
54 | NVMF_TRTYPE_FC = 2, /* Fibre Channel */ | |
55 | NVMF_TRTYPE_LOOP = 254, /* Reserved for host usage */ | |
56 | NVMF_TRTYPE_MAX, | |
57 | }; | |
58 | ||
59 | /* Transport Requirements codes for Discovery Log Page entry TREQ field */ | |
60 | enum { | |
61 | NVMF_TREQ_NOT_SPECIFIED = 0, /* Not specified */ | |
62 | NVMF_TREQ_REQUIRED = 1, /* Required */ | |
63 | NVMF_TREQ_NOT_REQUIRED = 2, /* Not Required */ | |
64 | }; | |
65 | ||
66 | /* RDMA QP Service Type codes for Discovery Log Page entry TSAS | |
67 | * RDMA_QPTYPE field | |
68 | */ | |
69 | enum { | |
bf17aa36 RD |
70 | NVMF_RDMA_QPTYPE_CONNECTED = 1, /* Reliable Connected */ |
71 | NVMF_RDMA_QPTYPE_DATAGRAM = 2, /* Reliable Datagram */ | |
eb793e2c CH |
72 | }; |
73 | ||
74 | /* RDMA QP Service Type codes for Discovery Log Page entry TSAS | |
75 | * RDMA_QPTYPE field | |
76 | */ | |
77 | enum { | |
bf17aa36 RD |
78 | NVMF_RDMA_PRTYPE_NOT_SPECIFIED = 1, /* No Provider Specified */ |
79 | NVMF_RDMA_PRTYPE_IB = 2, /* InfiniBand */ | |
80 | NVMF_RDMA_PRTYPE_ROCE = 3, /* InfiniBand RoCE */ | |
81 | NVMF_RDMA_PRTYPE_ROCEV2 = 4, /* InfiniBand RoCEV2 */ | |
82 | NVMF_RDMA_PRTYPE_IWARP = 5, /* IWARP */ | |
eb793e2c CH |
83 | }; |
84 | ||
85 | /* RDMA Connection Management Service Type codes for Discovery Log Page | |
86 | * entry TSAS RDMA_CMS field | |
87 | */ | |
88 | enum { | |
bf17aa36 | 89 | NVMF_RDMA_CMS_RDMA_CM = 1, /* Sockets based endpoint addressing */ |
eb793e2c CH |
90 | }; |
91 | ||
7aa1f427 | 92 | #define NVME_AQ_DEPTH 32 |
38dabe21 KB |
93 | #define NVME_NR_AEN_COMMANDS 1 |
94 | #define NVME_AQ_BLK_MQ_DEPTH (NVME_AQ_DEPTH - NVME_NR_AEN_COMMANDS) | |
95 | ||
96 | /* | |
97 | * Subtract one to leave an empty queue entry for 'Full Queue' condition. See | |
98 | * NVM-Express 1.2 specification, section 4.1.2. | |
99 | */ | |
100 | #define NVME_AQ_MQ_TAG_DEPTH (NVME_AQ_BLK_MQ_DEPTH - 1) | |
2812dfe3 | 101 | |
7a67cbea CH |
102 | enum { |
103 | NVME_REG_CAP = 0x0000, /* Controller Capabilities */ | |
104 | NVME_REG_VS = 0x0008, /* Version */ | |
105 | NVME_REG_INTMS = 0x000c, /* Interrupt Mask Set */ | |
a5b714ad | 106 | NVME_REG_INTMC = 0x0010, /* Interrupt Mask Clear */ |
7a67cbea CH |
107 | NVME_REG_CC = 0x0014, /* Controller Configuration */ |
108 | NVME_REG_CSTS = 0x001c, /* Controller Status */ | |
109 | NVME_REG_NSSR = 0x0020, /* NVM Subsystem Reset */ | |
110 | NVME_REG_AQA = 0x0024, /* Admin Queue Attributes */ | |
111 | NVME_REG_ASQ = 0x0028, /* Admin SQ Base Address */ | |
a5b714ad | 112 | NVME_REG_ACQ = 0x0030, /* Admin CQ Base Address */ |
7a67cbea CH |
113 | NVME_REG_CMBLOC = 0x0038, /* Controller Memory Buffer Location */ |
114 | NVME_REG_CMBSZ = 0x003c, /* Controller Memory Buffer Size */ | |
97f6ef64 | 115 | NVME_REG_DBS = 0x1000, /* SQ 0 Tail Doorbell */ |
b60503ba MW |
116 | }; |
117 | ||
a0cadb85 | 118 | #define NVME_CAP_MQES(cap) ((cap) & 0xffff) |
22605f96 | 119 | #define NVME_CAP_TIMEOUT(cap) (((cap) >> 24) & 0xff) |
f1938f6e | 120 | #define NVME_CAP_STRIDE(cap) (((cap) >> 32) & 0xf) |
dfbac8c7 | 121 | #define NVME_CAP_NSSRC(cap) (((cap) >> 36) & 0x1) |
8fc23e03 | 122 | #define NVME_CAP_MPSMIN(cap) (((cap) >> 48) & 0xf) |
1d090624 | 123 | #define NVME_CAP_MPSMAX(cap) (((cap) >> 52) & 0xf) |
22605f96 | 124 | |
8ffaadf7 JD |
125 | #define NVME_CMB_BIR(cmbloc) ((cmbloc) & 0x7) |
126 | #define NVME_CMB_OFST(cmbloc) (((cmbloc) >> 12) & 0xfffff) | |
88de4598 CH |
127 | |
128 | enum { | |
129 | NVME_CMBSZ_SQS = 1 << 0, | |
130 | NVME_CMBSZ_CQS = 1 << 1, | |
131 | NVME_CMBSZ_LISTS = 1 << 2, | |
132 | NVME_CMBSZ_RDS = 1 << 3, | |
133 | NVME_CMBSZ_WDS = 1 << 4, | |
134 | ||
135 | NVME_CMBSZ_SZ_SHIFT = 12, | |
136 | NVME_CMBSZ_SZ_MASK = 0xfffff, | |
137 | ||
138 | NVME_CMBSZ_SZU_SHIFT = 8, | |
139 | NVME_CMBSZ_SZU_MASK = 0xf, | |
140 | }; | |
8ffaadf7 | 141 | |
69cd27e2 CH |
142 | /* |
143 | * Submission and Completion Queue Entry Sizes for the NVM command set. | |
144 | * (In bytes and specified as a power of two (2^n)). | |
145 | */ | |
146 | #define NVME_NVM_IOSQES 6 | |
147 | #define NVME_NVM_IOCQES 4 | |
148 | ||
b60503ba MW |
149 | enum { |
150 | NVME_CC_ENABLE = 1 << 0, | |
151 | NVME_CC_CSS_NVM = 0 << 4, | |
ad4e05b2 MG |
152 | NVME_CC_EN_SHIFT = 0, |
153 | NVME_CC_CSS_SHIFT = 4, | |
b60503ba | 154 | NVME_CC_MPS_SHIFT = 7, |
ad4e05b2 MG |
155 | NVME_CC_AMS_SHIFT = 11, |
156 | NVME_CC_SHN_SHIFT = 14, | |
157 | NVME_CC_IOSQES_SHIFT = 16, | |
158 | NVME_CC_IOCQES_SHIFT = 20, | |
60b43f62 MG |
159 | NVME_CC_AMS_RR = 0 << NVME_CC_AMS_SHIFT, |
160 | NVME_CC_AMS_WRRU = 1 << NVME_CC_AMS_SHIFT, | |
161 | NVME_CC_AMS_VS = 7 << NVME_CC_AMS_SHIFT, | |
ad4e05b2 MG |
162 | NVME_CC_SHN_NONE = 0 << NVME_CC_SHN_SHIFT, |
163 | NVME_CC_SHN_NORMAL = 1 << NVME_CC_SHN_SHIFT, | |
164 | NVME_CC_SHN_ABRUPT = 2 << NVME_CC_SHN_SHIFT, | |
165 | NVME_CC_SHN_MASK = 3 << NVME_CC_SHN_SHIFT, | |
166 | NVME_CC_IOSQES = NVME_NVM_IOSQES << NVME_CC_IOSQES_SHIFT, | |
167 | NVME_CC_IOCQES = NVME_NVM_IOCQES << NVME_CC_IOCQES_SHIFT, | |
b60503ba MW |
168 | NVME_CSTS_RDY = 1 << 0, |
169 | NVME_CSTS_CFS = 1 << 1, | |
dfbac8c7 | 170 | NVME_CSTS_NSSRO = 1 << 4, |
b6dccf7f | 171 | NVME_CSTS_PP = 1 << 5, |
b60503ba MW |
172 | NVME_CSTS_SHST_NORMAL = 0 << 2, |
173 | NVME_CSTS_SHST_OCCUR = 1 << 2, | |
174 | NVME_CSTS_SHST_CMPLT = 2 << 2, | |
1894d8f1 | 175 | NVME_CSTS_SHST_MASK = 3 << 2, |
b60503ba MW |
176 | }; |
177 | ||
9d99a8dd CH |
178 | struct nvme_id_power_state { |
179 | __le16 max_power; /* centiwatts */ | |
180 | __u8 rsvd2; | |
181 | __u8 flags; | |
182 | __le32 entry_lat; /* microseconds */ | |
183 | __le32 exit_lat; /* microseconds */ | |
184 | __u8 read_tput; | |
185 | __u8 read_lat; | |
186 | __u8 write_tput; | |
187 | __u8 write_lat; | |
188 | __le16 idle_power; | |
189 | __u8 idle_scale; | |
190 | __u8 rsvd19; | |
191 | __le16 active_power; | |
192 | __u8 active_work_scale; | |
193 | __u8 rsvd23[9]; | |
194 | }; | |
195 | ||
196 | enum { | |
197 | NVME_PS_FLAGS_MAX_POWER_SCALE = 1 << 0, | |
198 | NVME_PS_FLAGS_NON_OP_STATE = 1 << 1, | |
199 | }; | |
200 | ||
201 | struct nvme_id_ctrl { | |
202 | __le16 vid; | |
203 | __le16 ssvid; | |
204 | char sn[20]; | |
205 | char mn[40]; | |
206 | char fr[8]; | |
207 | __u8 rab; | |
208 | __u8 ieee[3]; | |
a446c084 | 209 | __u8 cmic; |
9d99a8dd | 210 | __u8 mdts; |
08c69640 CH |
211 | __le16 cntlid; |
212 | __le32 ver; | |
14e974a8 CH |
213 | __le32 rtd3r; |
214 | __le32 rtd3e; | |
215 | __le32 oaes; | |
eb793e2c CH |
216 | __le32 ctratt; |
217 | __u8 rsvd100[156]; | |
9d99a8dd CH |
218 | __le16 oacs; |
219 | __u8 acl; | |
220 | __u8 aerl; | |
221 | __u8 frmw; | |
222 | __u8 lpa; | |
223 | __u8 elpe; | |
224 | __u8 npss; | |
225 | __u8 avscc; | |
226 | __u8 apsta; | |
227 | __le16 wctemp; | |
228 | __le16 cctemp; | |
a446c084 CH |
229 | __le16 mtfa; |
230 | __le32 hmpre; | |
231 | __le32 hmmin; | |
232 | __u8 tnvmcap[16]; | |
233 | __u8 unvmcap[16]; | |
234 | __le32 rpmbs; | |
435e8090 GJ |
235 | __le16 edstt; |
236 | __u8 dsto; | |
237 | __u8 fwug; | |
7b89eae2 | 238 | __le16 kas; |
435e8090 GJ |
239 | __le16 hctma; |
240 | __le16 mntmt; | |
241 | __le16 mxtmt; | |
242 | __le32 sanicap; | |
044a9df1 CH |
243 | __le32 hmminds; |
244 | __le16 hmmaxd; | |
1a376216 CH |
245 | __u8 rsvd338[4]; |
246 | __u8 anatt; | |
247 | __u8 anacap; | |
248 | __le32 anagrpmax; | |
249 | __le32 nanagrpid; | |
250 | __u8 rsvd352[160]; | |
9d99a8dd CH |
251 | __u8 sqes; |
252 | __u8 cqes; | |
eb793e2c | 253 | __le16 maxcmd; |
9d99a8dd CH |
254 | __le32 nn; |
255 | __le16 oncs; | |
256 | __le16 fuses; | |
257 | __u8 fna; | |
258 | __u8 vwc; | |
259 | __le16 awun; | |
260 | __le16 awupf; | |
261 | __u8 nvscc; | |
262 | __u8 rsvd531; | |
263 | __le16 acwu; | |
264 | __u8 rsvd534[2]; | |
265 | __le32 sgls; | |
1a376216 CH |
266 | __le32 mnan; |
267 | __u8 rsvd544[224]; | |
eb793e2c CH |
268 | char subnqn[256]; |
269 | __u8 rsvd1024[768]; | |
270 | __le32 ioccsz; | |
271 | __le32 iorcsz; | |
272 | __le16 icdoff; | |
273 | __u8 ctrattr; | |
274 | __u8 msdbd; | |
275 | __u8 rsvd1804[244]; | |
9d99a8dd CH |
276 | struct nvme_id_power_state psd[32]; |
277 | __u8 vs[1024]; | |
278 | }; | |
279 | ||
280 | enum { | |
281 | NVME_CTRL_ONCS_COMPARE = 1 << 0, | |
282 | NVME_CTRL_ONCS_WRITE_UNCORRECTABLE = 1 << 1, | |
283 | NVME_CTRL_ONCS_DSM = 1 << 2, | |
3b7c33b2 | 284 | NVME_CTRL_ONCS_WRITE_ZEROES = 1 << 3, |
dbf86b39 | 285 | NVME_CTRL_ONCS_TIMESTAMP = 1 << 6, |
9d99a8dd | 286 | NVME_CTRL_VWC_PRESENT = 1 << 0, |
8a9ae523 | 287 | NVME_CTRL_OACS_SEC_SUPP = 1 << 0, |
f5d11840 | 288 | NVME_CTRL_OACS_DIRECTIVES = 1 << 5, |
223694b9 | 289 | NVME_CTRL_OACS_DBBUF_SUPP = 1 << 8, |
84fef62d | 290 | NVME_CTRL_LPA_CMD_EFFECTS_LOG = 1 << 1, |
9d99a8dd CH |
291 | }; |
292 | ||
293 | struct nvme_lbaf { | |
294 | __le16 ms; | |
295 | __u8 ds; | |
296 | __u8 rp; | |
297 | }; | |
298 | ||
299 | struct nvme_id_ns { | |
300 | __le64 nsze; | |
301 | __le64 ncap; | |
302 | __le64 nuse; | |
303 | __u8 nsfeat; | |
304 | __u8 nlbaf; | |
305 | __u8 flbas; | |
306 | __u8 mc; | |
307 | __u8 dpc; | |
308 | __u8 dps; | |
309 | __u8 nmic; | |
310 | __u8 rescap; | |
311 | __u8 fpi; | |
312 | __u8 rsvd33; | |
313 | __le16 nawun; | |
314 | __le16 nawupf; | |
315 | __le16 nacwu; | |
316 | __le16 nabsn; | |
317 | __le16 nabo; | |
318 | __le16 nabspf; | |
6b8190d6 | 319 | __le16 noiob; |
a446c084 | 320 | __u8 nvmcap[16]; |
1a376216 CH |
321 | __u8 rsvd64[28]; |
322 | __le32 anagrpid; | |
323 | __u8 rsvd96[8]; | |
9d99a8dd CH |
324 | __u8 nguid[16]; |
325 | __u8 eui64[8]; | |
326 | struct nvme_lbaf lbaf[16]; | |
327 | __u8 rsvd192[192]; | |
328 | __u8 vs[3712]; | |
329 | }; | |
330 | ||
329dd768 CH |
331 | enum { |
332 | NVME_ID_CNS_NS = 0x00, | |
333 | NVME_ID_CNS_CTRL = 0x01, | |
334 | NVME_ID_CNS_NS_ACTIVE_LIST = 0x02, | |
af8b86e9 | 335 | NVME_ID_CNS_NS_DESC_LIST = 0x03, |
329dd768 CH |
336 | NVME_ID_CNS_NS_PRESENT_LIST = 0x10, |
337 | NVME_ID_CNS_NS_PRESENT = 0x11, | |
338 | NVME_ID_CNS_CTRL_NS_LIST = 0x12, | |
339 | NVME_ID_CNS_CTRL_LIST = 0x13, | |
340 | }; | |
341 | ||
f5d11840 JA |
342 | enum { |
343 | NVME_DIR_IDENTIFY = 0x00, | |
344 | NVME_DIR_STREAMS = 0x01, | |
345 | NVME_DIR_SND_ID_OP_ENABLE = 0x01, | |
346 | NVME_DIR_SND_ST_OP_REL_ID = 0x01, | |
347 | NVME_DIR_SND_ST_OP_REL_RSC = 0x02, | |
348 | NVME_DIR_RCV_ID_OP_PARAM = 0x01, | |
349 | NVME_DIR_RCV_ST_OP_PARAM = 0x01, | |
350 | NVME_DIR_RCV_ST_OP_STATUS = 0x02, | |
351 | NVME_DIR_RCV_ST_OP_RESOURCE = 0x03, | |
352 | NVME_DIR_ENDIR = 0x01, | |
353 | }; | |
354 | ||
9d99a8dd CH |
355 | enum { |
356 | NVME_NS_FEAT_THIN = 1 << 0, | |
357 | NVME_NS_FLBAS_LBA_MASK = 0xf, | |
358 | NVME_NS_FLBAS_META_EXT = 0x10, | |
359 | NVME_LBAF_RP_BEST = 0, | |
360 | NVME_LBAF_RP_BETTER = 1, | |
361 | NVME_LBAF_RP_GOOD = 2, | |
362 | NVME_LBAF_RP_DEGRADED = 3, | |
363 | NVME_NS_DPC_PI_LAST = 1 << 4, | |
364 | NVME_NS_DPC_PI_FIRST = 1 << 3, | |
365 | NVME_NS_DPC_PI_TYPE3 = 1 << 2, | |
366 | NVME_NS_DPC_PI_TYPE2 = 1 << 1, | |
367 | NVME_NS_DPC_PI_TYPE1 = 1 << 0, | |
368 | NVME_NS_DPS_PI_FIRST = 1 << 3, | |
369 | NVME_NS_DPS_PI_MASK = 0x7, | |
370 | NVME_NS_DPS_PI_TYPE1 = 1, | |
371 | NVME_NS_DPS_PI_TYPE2 = 2, | |
372 | NVME_NS_DPS_PI_TYPE3 = 3, | |
373 | }; | |
374 | ||
af8b86e9 JT |
375 | struct nvme_ns_id_desc { |
376 | __u8 nidt; | |
377 | __u8 nidl; | |
378 | __le16 reserved; | |
379 | }; | |
380 | ||
381 | #define NVME_NIDT_EUI64_LEN 8 | |
382 | #define NVME_NIDT_NGUID_LEN 16 | |
383 | #define NVME_NIDT_UUID_LEN 16 | |
384 | ||
385 | enum { | |
386 | NVME_NIDT_EUI64 = 0x01, | |
387 | NVME_NIDT_NGUID = 0x02, | |
388 | NVME_NIDT_UUID = 0x03, | |
389 | }; | |
390 | ||
9d99a8dd CH |
391 | struct nvme_smart_log { |
392 | __u8 critical_warning; | |
393 | __u8 temperature[2]; | |
394 | __u8 avail_spare; | |
395 | __u8 spare_thresh; | |
396 | __u8 percent_used; | |
397 | __u8 rsvd6[26]; | |
398 | __u8 data_units_read[16]; | |
399 | __u8 data_units_written[16]; | |
400 | __u8 host_reads[16]; | |
401 | __u8 host_writes[16]; | |
402 | __u8 ctrl_busy_time[16]; | |
403 | __u8 power_cycles[16]; | |
404 | __u8 power_on_hours[16]; | |
405 | __u8 unsafe_shutdowns[16]; | |
406 | __u8 media_errors[16]; | |
407 | __u8 num_err_log_entries[16]; | |
408 | __le32 warning_temp_time; | |
409 | __le32 critical_comp_time; | |
410 | __le16 temp_sensor[8]; | |
411 | __u8 rsvd216[296]; | |
412 | }; | |
413 | ||
b6dccf7f AD |
414 | struct nvme_fw_slot_info_log { |
415 | __u8 afi; | |
416 | __u8 rsvd1[7]; | |
417 | __le64 frs[7]; | |
418 | __u8 rsvd64[448]; | |
419 | }; | |
420 | ||
84fef62d KB |
421 | enum { |
422 | NVME_CMD_EFFECTS_CSUPP = 1 << 0, | |
423 | NVME_CMD_EFFECTS_LBCC = 1 << 1, | |
424 | NVME_CMD_EFFECTS_NCC = 1 << 2, | |
425 | NVME_CMD_EFFECTS_NIC = 1 << 3, | |
426 | NVME_CMD_EFFECTS_CCC = 1 << 4, | |
427 | NVME_CMD_EFFECTS_CSE_MASK = 3 << 16, | |
428 | }; | |
429 | ||
430 | struct nvme_effects_log { | |
431 | __le32 acs[256]; | |
432 | __le32 iocs[256]; | |
433 | __u8 resv[2048]; | |
434 | }; | |
435 | ||
1a376216 CH |
436 | enum nvme_ana_state { |
437 | NVME_ANA_OPTIMIZED = 0x01, | |
438 | NVME_ANA_NONOPTIMIZED = 0x02, | |
439 | NVME_ANA_INACCESSIBLE = 0x03, | |
440 | NVME_ANA_PERSISTENT_LOSS = 0x04, | |
441 | NVME_ANA_CHANGE = 0x0f, | |
442 | }; | |
443 | ||
444 | struct nvme_ana_group_desc { | |
445 | __le32 grpid; | |
446 | __le32 nnsids; | |
447 | __le64 chgcnt; | |
448 | __u8 state; | |
449 | __u8 rsvd17[7]; | |
450 | __le32 nsids[]; | |
451 | }; | |
452 | ||
453 | /* flag for the log specific field of the ANA log */ | |
454 | #define NVME_ANA_LOG_RGO (1 << 0) | |
455 | ||
456 | struct nvme_ana_rsp_hdr { | |
457 | __le64 chgcnt; | |
458 | __le16 ngrps; | |
459 | __le16 rsvd10[3]; | |
460 | }; | |
461 | ||
9d99a8dd CH |
462 | enum { |
463 | NVME_SMART_CRIT_SPARE = 1 << 0, | |
464 | NVME_SMART_CRIT_TEMPERATURE = 1 << 1, | |
465 | NVME_SMART_CRIT_RELIABILITY = 1 << 2, | |
466 | NVME_SMART_CRIT_MEDIA = 1 << 3, | |
467 | NVME_SMART_CRIT_VOLATILE_MEMORY = 1 << 4, | |
468 | }; | |
469 | ||
470 | enum { | |
e3d7874d KB |
471 | NVME_AER_ERROR = 0, |
472 | NVME_AER_SMART = 1, | |
868c2392 | 473 | NVME_AER_NOTICE = 2, |
e3d7874d KB |
474 | NVME_AER_CSS = 6, |
475 | NVME_AER_VS = 7, | |
868c2392 CH |
476 | }; |
477 | ||
478 | enum { | |
479 | NVME_AER_NOTICE_NS_CHANGED = 0x00, | |
480 | NVME_AER_NOTICE_FW_ACT_STARTING = 0x01, | |
1a376216 | 481 | NVME_AER_NOTICE_ANA = 0x03, |
9d99a8dd CH |
482 | }; |
483 | ||
aafd3afe HR |
484 | enum { |
485 | NVME_AEN_CFG_NS_ATTR = 1 << 8, | |
486 | NVME_AEN_CFG_FW_ACT = 1 << 9, | |
1a376216 | 487 | NVME_AEN_CFG_ANA_CHANGE = 1 << 11, |
aafd3afe HR |
488 | }; |
489 | ||
9d99a8dd CH |
490 | struct nvme_lba_range_type { |
491 | __u8 type; | |
492 | __u8 attributes; | |
493 | __u8 rsvd2[14]; | |
494 | __u64 slba; | |
495 | __u64 nlb; | |
496 | __u8 guid[16]; | |
497 | __u8 rsvd48[16]; | |
498 | }; | |
499 | ||
500 | enum { | |
501 | NVME_LBART_TYPE_FS = 0x01, | |
502 | NVME_LBART_TYPE_RAID = 0x02, | |
503 | NVME_LBART_TYPE_CACHE = 0x03, | |
504 | NVME_LBART_TYPE_SWAP = 0x04, | |
505 | ||
506 | NVME_LBART_ATTRIB_TEMP = 1 << 0, | |
507 | NVME_LBART_ATTRIB_HIDE = 1 << 1, | |
508 | }; | |
509 | ||
510 | struct nvme_reservation_status { | |
511 | __le32 gen; | |
512 | __u8 rtype; | |
513 | __u8 regctl[2]; | |
514 | __u8 resv5[2]; | |
515 | __u8 ptpls; | |
516 | __u8 resv10[13]; | |
517 | struct { | |
518 | __le16 cntlid; | |
519 | __u8 rcsts; | |
520 | __u8 resv3[5]; | |
521 | __le64 hostid; | |
522 | __le64 rkey; | |
523 | } regctl_ds[]; | |
524 | }; | |
525 | ||
79f370ea CH |
526 | enum nvme_async_event_type { |
527 | NVME_AER_TYPE_ERROR = 0, | |
528 | NVME_AER_TYPE_SMART = 1, | |
529 | NVME_AER_TYPE_NOTICE = 2, | |
530 | }; | |
531 | ||
9d99a8dd CH |
532 | /* I/O commands */ |
533 | ||
534 | enum nvme_opcode { | |
535 | nvme_cmd_flush = 0x00, | |
536 | nvme_cmd_write = 0x01, | |
537 | nvme_cmd_read = 0x02, | |
538 | nvme_cmd_write_uncor = 0x04, | |
539 | nvme_cmd_compare = 0x05, | |
540 | nvme_cmd_write_zeroes = 0x08, | |
541 | nvme_cmd_dsm = 0x09, | |
542 | nvme_cmd_resv_register = 0x0d, | |
543 | nvme_cmd_resv_report = 0x0e, | |
544 | nvme_cmd_resv_acquire = 0x11, | |
545 | nvme_cmd_resv_release = 0x15, | |
546 | }; | |
547 | ||
eb793e2c CH |
548 | /* |
549 | * Descriptor subtype - lower 4 bits of nvme_(keyed_)sgl_desc identifier | |
550 | * | |
551 | * @NVME_SGL_FMT_ADDRESS: absolute address of the data block | |
552 | * @NVME_SGL_FMT_OFFSET: relative offset of the in-capsule data block | |
d85cf207 | 553 | * @NVME_SGL_FMT_TRANSPORT_A: transport defined format, value 0xA |
eb793e2c CH |
554 | * @NVME_SGL_FMT_INVALIDATE: RDMA transport specific remote invalidation |
555 | * request subtype | |
556 | */ | |
557 | enum { | |
558 | NVME_SGL_FMT_ADDRESS = 0x00, | |
559 | NVME_SGL_FMT_OFFSET = 0x01, | |
d85cf207 | 560 | NVME_SGL_FMT_TRANSPORT_A = 0x0A, |
eb793e2c CH |
561 | NVME_SGL_FMT_INVALIDATE = 0x0f, |
562 | }; | |
563 | ||
564 | /* | |
565 | * Descriptor type - upper 4 bits of nvme_(keyed_)sgl_desc identifier | |
566 | * | |
567 | * For struct nvme_sgl_desc: | |
568 | * @NVME_SGL_FMT_DATA_DESC: data block descriptor | |
569 | * @NVME_SGL_FMT_SEG_DESC: sgl segment descriptor | |
570 | * @NVME_SGL_FMT_LAST_SEG_DESC: last sgl segment descriptor | |
571 | * | |
572 | * For struct nvme_keyed_sgl_desc: | |
573 | * @NVME_KEY_SGL_FMT_DATA_DESC: keyed data block descriptor | |
d85cf207 JS |
574 | * |
575 | * Transport-specific SGL types: | |
576 | * @NVME_TRANSPORT_SGL_DATA_DESC: Transport SGL data dlock descriptor | |
eb793e2c CH |
577 | */ |
578 | enum { | |
579 | NVME_SGL_FMT_DATA_DESC = 0x00, | |
580 | NVME_SGL_FMT_SEG_DESC = 0x02, | |
581 | NVME_SGL_FMT_LAST_SEG_DESC = 0x03, | |
582 | NVME_KEY_SGL_FMT_DATA_DESC = 0x04, | |
d85cf207 | 583 | NVME_TRANSPORT_SGL_DATA_DESC = 0x05, |
eb793e2c CH |
584 | }; |
585 | ||
586 | struct nvme_sgl_desc { | |
587 | __le64 addr; | |
588 | __le32 length; | |
589 | __u8 rsvd[3]; | |
590 | __u8 type; | |
591 | }; | |
592 | ||
593 | struct nvme_keyed_sgl_desc { | |
594 | __le64 addr; | |
595 | __u8 length[3]; | |
596 | __u8 key[4]; | |
597 | __u8 type; | |
598 | }; | |
599 | ||
600 | union nvme_data_ptr { | |
601 | struct { | |
602 | __le64 prp1; | |
603 | __le64 prp2; | |
604 | }; | |
605 | struct nvme_sgl_desc sgl; | |
606 | struct nvme_keyed_sgl_desc ksgl; | |
607 | }; | |
608 | ||
3972be23 JS |
609 | /* |
610 | * Lowest two bits of our flags field (FUSE field in the spec): | |
611 | * | |
612 | * @NVME_CMD_FUSE_FIRST: Fused Operation, first command | |
613 | * @NVME_CMD_FUSE_SECOND: Fused Operation, second command | |
614 | * | |
615 | * Highest two bits in our flags field (PSDT field in the spec): | |
616 | * | |
617 | * @NVME_CMD_PSDT_SGL_METABUF: Use SGLS for this transfer, | |
618 | * If used, MPTR contains addr of single physical buffer (byte aligned). | |
619 | * @NVME_CMD_PSDT_SGL_METASEG: Use SGLS for this transfer, | |
620 | * If used, MPTR contains an address of an SGL segment containing | |
621 | * exactly 1 SGL descriptor (qword aligned). | |
622 | */ | |
623 | enum { | |
624 | NVME_CMD_FUSE_FIRST = (1 << 0), | |
625 | NVME_CMD_FUSE_SECOND = (1 << 1), | |
626 | ||
627 | NVME_CMD_SGL_METABUF = (1 << 6), | |
628 | NVME_CMD_SGL_METASEG = (1 << 7), | |
629 | NVME_CMD_SGL_ALL = NVME_CMD_SGL_METABUF | NVME_CMD_SGL_METASEG, | |
630 | }; | |
631 | ||
9d99a8dd CH |
632 | struct nvme_common_command { |
633 | __u8 opcode; | |
634 | __u8 flags; | |
635 | __u16 command_id; | |
636 | __le32 nsid; | |
637 | __le32 cdw2[2]; | |
638 | __le64 metadata; | |
eb793e2c | 639 | union nvme_data_ptr dptr; |
9d99a8dd CH |
640 | __le32 cdw10[6]; |
641 | }; | |
642 | ||
643 | struct nvme_rw_command { | |
644 | __u8 opcode; | |
645 | __u8 flags; | |
646 | __u16 command_id; | |
647 | __le32 nsid; | |
648 | __u64 rsvd2; | |
649 | __le64 metadata; | |
eb793e2c | 650 | union nvme_data_ptr dptr; |
9d99a8dd CH |
651 | __le64 slba; |
652 | __le16 length; | |
653 | __le16 control; | |
654 | __le32 dsmgmt; | |
655 | __le32 reftag; | |
656 | __le16 apptag; | |
657 | __le16 appmask; | |
658 | }; | |
659 | ||
660 | enum { | |
661 | NVME_RW_LR = 1 << 15, | |
662 | NVME_RW_FUA = 1 << 14, | |
663 | NVME_RW_DSM_FREQ_UNSPEC = 0, | |
664 | NVME_RW_DSM_FREQ_TYPICAL = 1, | |
665 | NVME_RW_DSM_FREQ_RARE = 2, | |
666 | NVME_RW_DSM_FREQ_READS = 3, | |
667 | NVME_RW_DSM_FREQ_WRITES = 4, | |
668 | NVME_RW_DSM_FREQ_RW = 5, | |
669 | NVME_RW_DSM_FREQ_ONCE = 6, | |
670 | NVME_RW_DSM_FREQ_PREFETCH = 7, | |
671 | NVME_RW_DSM_FREQ_TEMP = 8, | |
672 | NVME_RW_DSM_LATENCY_NONE = 0 << 4, | |
673 | NVME_RW_DSM_LATENCY_IDLE = 1 << 4, | |
674 | NVME_RW_DSM_LATENCY_NORM = 2 << 4, | |
675 | NVME_RW_DSM_LATENCY_LOW = 3 << 4, | |
676 | NVME_RW_DSM_SEQ_REQ = 1 << 6, | |
677 | NVME_RW_DSM_COMPRESSED = 1 << 7, | |
678 | NVME_RW_PRINFO_PRCHK_REF = 1 << 10, | |
679 | NVME_RW_PRINFO_PRCHK_APP = 1 << 11, | |
680 | NVME_RW_PRINFO_PRCHK_GUARD = 1 << 12, | |
681 | NVME_RW_PRINFO_PRACT = 1 << 13, | |
f5d11840 | 682 | NVME_RW_DTYPE_STREAMS = 1 << 4, |
9d99a8dd CH |
683 | }; |
684 | ||
685 | struct nvme_dsm_cmd { | |
686 | __u8 opcode; | |
687 | __u8 flags; | |
688 | __u16 command_id; | |
689 | __le32 nsid; | |
690 | __u64 rsvd2[2]; | |
eb793e2c | 691 | union nvme_data_ptr dptr; |
9d99a8dd CH |
692 | __le32 nr; |
693 | __le32 attributes; | |
694 | __u32 rsvd12[4]; | |
695 | }; | |
696 | ||
697 | enum { | |
698 | NVME_DSMGMT_IDR = 1 << 0, | |
699 | NVME_DSMGMT_IDW = 1 << 1, | |
700 | NVME_DSMGMT_AD = 1 << 2, | |
701 | }; | |
702 | ||
b35ba01e CH |
703 | #define NVME_DSM_MAX_RANGES 256 |
704 | ||
9d99a8dd CH |
705 | struct nvme_dsm_range { |
706 | __le32 cattr; | |
707 | __le32 nlb; | |
708 | __le64 slba; | |
709 | }; | |
710 | ||
3b7c33b2 CK |
711 | struct nvme_write_zeroes_cmd { |
712 | __u8 opcode; | |
713 | __u8 flags; | |
714 | __u16 command_id; | |
715 | __le32 nsid; | |
716 | __u64 rsvd2; | |
717 | __le64 metadata; | |
718 | union nvme_data_ptr dptr; | |
719 | __le64 slba; | |
720 | __le16 length; | |
721 | __le16 control; | |
722 | __le32 dsmgmt; | |
723 | __le32 reftag; | |
724 | __le16 apptag; | |
725 | __le16 appmask; | |
726 | }; | |
727 | ||
c5552fde AL |
728 | /* Features */ |
729 | ||
730 | struct nvme_feat_auto_pst { | |
731 | __le64 entries[32]; | |
732 | }; | |
733 | ||
39673e19 CH |
734 | enum { |
735 | NVME_HOST_MEM_ENABLE = (1 << 0), | |
736 | NVME_HOST_MEM_RETURN = (1 << 1), | |
737 | }; | |
738 | ||
9d99a8dd CH |
739 | /* Admin commands */ |
740 | ||
741 | enum nvme_admin_opcode { | |
742 | nvme_admin_delete_sq = 0x00, | |
743 | nvme_admin_create_sq = 0x01, | |
744 | nvme_admin_get_log_page = 0x02, | |
745 | nvme_admin_delete_cq = 0x04, | |
746 | nvme_admin_create_cq = 0x05, | |
747 | nvme_admin_identify = 0x06, | |
748 | nvme_admin_abort_cmd = 0x08, | |
749 | nvme_admin_set_features = 0x09, | |
750 | nvme_admin_get_features = 0x0a, | |
751 | nvme_admin_async_event = 0x0c, | |
a446c084 | 752 | nvme_admin_ns_mgmt = 0x0d, |
9d99a8dd CH |
753 | nvme_admin_activate_fw = 0x10, |
754 | nvme_admin_download_fw = 0x11, | |
a446c084 | 755 | nvme_admin_ns_attach = 0x15, |
7b89eae2 | 756 | nvme_admin_keep_alive = 0x18, |
f5d11840 JA |
757 | nvme_admin_directive_send = 0x19, |
758 | nvme_admin_directive_recv = 0x1a, | |
f9f38e33 | 759 | nvme_admin_dbbuf = 0x7C, |
9d99a8dd CH |
760 | nvme_admin_format_nvm = 0x80, |
761 | nvme_admin_security_send = 0x81, | |
762 | nvme_admin_security_recv = 0x82, | |
84fef62d | 763 | nvme_admin_sanitize_nvm = 0x84, |
9d99a8dd CH |
764 | }; |
765 | ||
766 | enum { | |
767 | NVME_QUEUE_PHYS_CONTIG = (1 << 0), | |
768 | NVME_CQ_IRQ_ENABLED = (1 << 1), | |
769 | NVME_SQ_PRIO_URGENT = (0 << 1), | |
770 | NVME_SQ_PRIO_HIGH = (1 << 1), | |
771 | NVME_SQ_PRIO_MEDIUM = (2 << 1), | |
772 | NVME_SQ_PRIO_LOW = (3 << 1), | |
773 | NVME_FEAT_ARBITRATION = 0x01, | |
774 | NVME_FEAT_POWER_MGMT = 0x02, | |
775 | NVME_FEAT_LBA_RANGE = 0x03, | |
776 | NVME_FEAT_TEMP_THRESH = 0x04, | |
777 | NVME_FEAT_ERR_RECOVERY = 0x05, | |
778 | NVME_FEAT_VOLATILE_WC = 0x06, | |
779 | NVME_FEAT_NUM_QUEUES = 0x07, | |
780 | NVME_FEAT_IRQ_COALESCE = 0x08, | |
781 | NVME_FEAT_IRQ_CONFIG = 0x09, | |
782 | NVME_FEAT_WRITE_ATOMIC = 0x0a, | |
783 | NVME_FEAT_ASYNC_EVENT = 0x0b, | |
784 | NVME_FEAT_AUTO_PST = 0x0c, | |
a446c084 | 785 | NVME_FEAT_HOST_MEM_BUF = 0x0d, |
dbf86b39 | 786 | NVME_FEAT_TIMESTAMP = 0x0e, |
7b89eae2 | 787 | NVME_FEAT_KATO = 0x0f, |
40c6f9c2 RR |
788 | NVME_FEAT_HCTM = 0x10, |
789 | NVME_FEAT_NOPSC = 0x11, | |
790 | NVME_FEAT_RRL = 0x12, | |
791 | NVME_FEAT_PLM_CONFIG = 0x13, | |
792 | NVME_FEAT_PLM_WINDOW = 0x14, | |
9d99a8dd CH |
793 | NVME_FEAT_SW_PROGRESS = 0x80, |
794 | NVME_FEAT_HOST_ID = 0x81, | |
795 | NVME_FEAT_RESV_MASK = 0x82, | |
796 | NVME_FEAT_RESV_PERSIST = 0x83, | |
797 | NVME_LOG_ERROR = 0x01, | |
798 | NVME_LOG_SMART = 0x02, | |
799 | NVME_LOG_FW_SLOT = 0x03, | |
b3984e06 | 800 | NVME_LOG_CHANGED_NS = 0x04, |
84fef62d | 801 | NVME_LOG_CMD_EFFECTS = 0x05, |
1a376216 | 802 | NVME_LOG_ANA = 0x0c, |
eb793e2c | 803 | NVME_LOG_DISC = 0x70, |
9d99a8dd CH |
804 | NVME_LOG_RESERVATION = 0x80, |
805 | NVME_FWACT_REPL = (0 << 3), | |
806 | NVME_FWACT_REPL_ACTV = (1 << 3), | |
807 | NVME_FWACT_ACTV = (2 << 3), | |
808 | }; | |
809 | ||
b3984e06 CH |
810 | #define NVME_MAX_CHANGED_NAMESPACES 1024 |
811 | ||
9d99a8dd CH |
812 | struct nvme_identify { |
813 | __u8 opcode; | |
814 | __u8 flags; | |
815 | __u16 command_id; | |
816 | __le32 nsid; | |
817 | __u64 rsvd2[2]; | |
eb793e2c | 818 | union nvme_data_ptr dptr; |
986994a2 PP |
819 | __u8 cns; |
820 | __u8 rsvd3; | |
821 | __le16 ctrlid; | |
9d99a8dd CH |
822 | __u32 rsvd11[5]; |
823 | }; | |
824 | ||
0add5e8e JT |
825 | #define NVME_IDENTIFY_DATA_SIZE 4096 |
826 | ||
9d99a8dd CH |
827 | struct nvme_features { |
828 | __u8 opcode; | |
829 | __u8 flags; | |
830 | __u16 command_id; | |
831 | __le32 nsid; | |
832 | __u64 rsvd2[2]; | |
eb793e2c | 833 | union nvme_data_ptr dptr; |
9d99a8dd CH |
834 | __le32 fid; |
835 | __le32 dword11; | |
b85cf734 AD |
836 | __le32 dword12; |
837 | __le32 dword13; | |
838 | __le32 dword14; | |
839 | __le32 dword15; | |
9d99a8dd CH |
840 | }; |
841 | ||
39673e19 CH |
842 | struct nvme_host_mem_buf_desc { |
843 | __le64 addr; | |
844 | __le32 size; | |
845 | __u32 rsvd; | |
846 | }; | |
847 | ||
9d99a8dd CH |
848 | struct nvme_create_cq { |
849 | __u8 opcode; | |
850 | __u8 flags; | |
851 | __u16 command_id; | |
852 | __u32 rsvd1[5]; | |
853 | __le64 prp1; | |
854 | __u64 rsvd8; | |
855 | __le16 cqid; | |
856 | __le16 qsize; | |
857 | __le16 cq_flags; | |
858 | __le16 irq_vector; | |
859 | __u32 rsvd12[4]; | |
860 | }; | |
861 | ||
862 | struct nvme_create_sq { | |
863 | __u8 opcode; | |
864 | __u8 flags; | |
865 | __u16 command_id; | |
866 | __u32 rsvd1[5]; | |
867 | __le64 prp1; | |
868 | __u64 rsvd8; | |
869 | __le16 sqid; | |
870 | __le16 qsize; | |
871 | __le16 sq_flags; | |
872 | __le16 cqid; | |
873 | __u32 rsvd12[4]; | |
874 | }; | |
875 | ||
876 | struct nvme_delete_queue { | |
877 | __u8 opcode; | |
878 | __u8 flags; | |
879 | __u16 command_id; | |
880 | __u32 rsvd1[9]; | |
881 | __le16 qid; | |
882 | __u16 rsvd10; | |
883 | __u32 rsvd11[5]; | |
884 | }; | |
885 | ||
886 | struct nvme_abort_cmd { | |
887 | __u8 opcode; | |
888 | __u8 flags; | |
889 | __u16 command_id; | |
890 | __u32 rsvd1[9]; | |
891 | __le16 sqid; | |
892 | __u16 cid; | |
893 | __u32 rsvd11[5]; | |
894 | }; | |
895 | ||
896 | struct nvme_download_firmware { | |
897 | __u8 opcode; | |
898 | __u8 flags; | |
899 | __u16 command_id; | |
900 | __u32 rsvd1[5]; | |
eb793e2c | 901 | union nvme_data_ptr dptr; |
9d99a8dd CH |
902 | __le32 numd; |
903 | __le32 offset; | |
904 | __u32 rsvd12[4]; | |
905 | }; | |
906 | ||
907 | struct nvme_format_cmd { | |
908 | __u8 opcode; | |
909 | __u8 flags; | |
910 | __u16 command_id; | |
911 | __le32 nsid; | |
912 | __u64 rsvd2[4]; | |
913 | __le32 cdw10; | |
914 | __u32 rsvd11[5]; | |
915 | }; | |
916 | ||
725b3588 AB |
917 | struct nvme_get_log_page_command { |
918 | __u8 opcode; | |
919 | __u8 flags; | |
920 | __u16 command_id; | |
921 | __le32 nsid; | |
922 | __u64 rsvd2[2]; | |
eb793e2c | 923 | union nvme_data_ptr dptr; |
725b3588 | 924 | __u8 lid; |
9b89bc38 | 925 | __u8 lsp; /* upper 4 bits reserved */ |
725b3588 AB |
926 | __le16 numdl; |
927 | __le16 numdu; | |
928 | __u16 rsvd11; | |
929 | __le32 lpol; | |
930 | __le32 lpou; | |
931 | __u32 rsvd14[2]; | |
932 | }; | |
933 | ||
f5d11840 JA |
934 | struct nvme_directive_cmd { |
935 | __u8 opcode; | |
936 | __u8 flags; | |
937 | __u16 command_id; | |
938 | __le32 nsid; | |
939 | __u64 rsvd2[2]; | |
940 | union nvme_data_ptr dptr; | |
941 | __le32 numd; | |
942 | __u8 doper; | |
943 | __u8 dtype; | |
944 | __le16 dspec; | |
945 | __u8 endir; | |
946 | __u8 tdtype; | |
947 | __u16 rsvd15; | |
948 | ||
949 | __u32 rsvd16[3]; | |
950 | }; | |
951 | ||
eb793e2c CH |
952 | /* |
953 | * Fabrics subcommands. | |
954 | */ | |
955 | enum nvmf_fabrics_opcode { | |
956 | nvme_fabrics_command = 0x7f, | |
957 | }; | |
958 | ||
959 | enum nvmf_capsule_command { | |
960 | nvme_fabrics_type_property_set = 0x00, | |
961 | nvme_fabrics_type_connect = 0x01, | |
962 | nvme_fabrics_type_property_get = 0x04, | |
963 | }; | |
964 | ||
965 | struct nvmf_common_command { | |
966 | __u8 opcode; | |
967 | __u8 resv1; | |
968 | __u16 command_id; | |
969 | __u8 fctype; | |
970 | __u8 resv2[35]; | |
971 | __u8 ts[24]; | |
972 | }; | |
973 | ||
974 | /* | |
975 | * The legal cntlid range a NVMe Target will provide. | |
976 | * Note that cntlid of value 0 is considered illegal in the fabrics world. | |
977 | * Devices based on earlier specs did not have the subsystem concept; | |
978 | * therefore, those devices had their cntlid value set to 0 as a result. | |
979 | */ | |
980 | #define NVME_CNTLID_MIN 1 | |
981 | #define NVME_CNTLID_MAX 0xffef | |
982 | #define NVME_CNTLID_DYNAMIC 0xffff | |
983 | ||
984 | #define MAX_DISC_LOGS 255 | |
985 | ||
986 | /* Discovery log page entry */ | |
987 | struct nvmf_disc_rsp_page_entry { | |
988 | __u8 trtype; | |
989 | __u8 adrfam; | |
a446c084 | 990 | __u8 subtype; |
eb793e2c CH |
991 | __u8 treq; |
992 | __le16 portid; | |
993 | __le16 cntlid; | |
994 | __le16 asqsz; | |
995 | __u8 resv8[22]; | |
996 | char trsvcid[NVMF_TRSVCID_SIZE]; | |
997 | __u8 resv64[192]; | |
998 | char subnqn[NVMF_NQN_FIELD_LEN]; | |
999 | char traddr[NVMF_TRADDR_SIZE]; | |
1000 | union tsas { | |
1001 | char common[NVMF_TSAS_SIZE]; | |
1002 | struct rdma { | |
1003 | __u8 qptype; | |
1004 | __u8 prtype; | |
1005 | __u8 cms; | |
1006 | __u8 resv3[5]; | |
1007 | __u16 pkey; | |
1008 | __u8 resv10[246]; | |
1009 | } rdma; | |
1010 | } tsas; | |
1011 | }; | |
1012 | ||
1013 | /* Discovery log page header */ | |
1014 | struct nvmf_disc_rsp_page_hdr { | |
1015 | __le64 genctr; | |
1016 | __le64 numrec; | |
1017 | __le16 recfmt; | |
1018 | __u8 resv14[1006]; | |
1019 | struct nvmf_disc_rsp_page_entry entries[0]; | |
1020 | }; | |
1021 | ||
1022 | struct nvmf_connect_command { | |
1023 | __u8 opcode; | |
1024 | __u8 resv1; | |
1025 | __u16 command_id; | |
1026 | __u8 fctype; | |
1027 | __u8 resv2[19]; | |
1028 | union nvme_data_ptr dptr; | |
1029 | __le16 recfmt; | |
1030 | __le16 qid; | |
1031 | __le16 sqsize; | |
1032 | __u8 cattr; | |
1033 | __u8 resv3; | |
1034 | __le32 kato; | |
1035 | __u8 resv4[12]; | |
1036 | }; | |
1037 | ||
1038 | struct nvmf_connect_data { | |
8e412263 | 1039 | uuid_t hostid; |
eb793e2c CH |
1040 | __le16 cntlid; |
1041 | char resv4[238]; | |
1042 | char subsysnqn[NVMF_NQN_FIELD_LEN]; | |
1043 | char hostnqn[NVMF_NQN_FIELD_LEN]; | |
1044 | char resv5[256]; | |
1045 | }; | |
1046 | ||
1047 | struct nvmf_property_set_command { | |
1048 | __u8 opcode; | |
1049 | __u8 resv1; | |
1050 | __u16 command_id; | |
1051 | __u8 fctype; | |
1052 | __u8 resv2[35]; | |
1053 | __u8 attrib; | |
1054 | __u8 resv3[3]; | |
1055 | __le32 offset; | |
1056 | __le64 value; | |
1057 | __u8 resv4[8]; | |
1058 | }; | |
1059 | ||
1060 | struct nvmf_property_get_command { | |
1061 | __u8 opcode; | |
1062 | __u8 resv1; | |
1063 | __u16 command_id; | |
1064 | __u8 fctype; | |
1065 | __u8 resv2[35]; | |
1066 | __u8 attrib; | |
1067 | __u8 resv3[3]; | |
1068 | __le32 offset; | |
1069 | __u8 resv4[16]; | |
1070 | }; | |
1071 | ||
f9f38e33 HK |
1072 | struct nvme_dbbuf { |
1073 | __u8 opcode; | |
1074 | __u8 flags; | |
1075 | __u16 command_id; | |
1076 | __u32 rsvd1[5]; | |
1077 | __le64 prp1; | |
1078 | __le64 prp2; | |
1079 | __u32 rsvd12[6]; | |
1080 | }; | |
1081 | ||
f5d11840 | 1082 | struct streams_directive_params { |
dc1a0afb CH |
1083 | __le16 msl; |
1084 | __le16 nssa; | |
1085 | __le16 nsso; | |
f5d11840 | 1086 | __u8 rsvd[10]; |
dc1a0afb CH |
1087 | __le32 sws; |
1088 | __le16 sgs; | |
1089 | __le16 nsa; | |
1090 | __le16 nso; | |
f5d11840 JA |
1091 | __u8 rsvd2[6]; |
1092 | }; | |
1093 | ||
9d99a8dd CH |
1094 | struct nvme_command { |
1095 | union { | |
1096 | struct nvme_common_command common; | |
1097 | struct nvme_rw_command rw; | |
1098 | struct nvme_identify identify; | |
1099 | struct nvme_features features; | |
1100 | struct nvme_create_cq create_cq; | |
1101 | struct nvme_create_sq create_sq; | |
1102 | struct nvme_delete_queue delete_queue; | |
1103 | struct nvme_download_firmware dlfw; | |
1104 | struct nvme_format_cmd format; | |
1105 | struct nvme_dsm_cmd dsm; | |
3b7c33b2 | 1106 | struct nvme_write_zeroes_cmd write_zeroes; |
9d99a8dd | 1107 | struct nvme_abort_cmd abort; |
725b3588 | 1108 | struct nvme_get_log_page_command get_log_page; |
eb793e2c CH |
1109 | struct nvmf_common_command fabrics; |
1110 | struct nvmf_connect_command connect; | |
1111 | struct nvmf_property_set_command prop_set; | |
1112 | struct nvmf_property_get_command prop_get; | |
f9f38e33 | 1113 | struct nvme_dbbuf dbbuf; |
f5d11840 | 1114 | struct nvme_directive_cmd directive; |
9d99a8dd CH |
1115 | }; |
1116 | }; | |
1117 | ||
7a5abb4b CH |
1118 | static inline bool nvme_is_write(struct nvme_command *cmd) |
1119 | { | |
eb793e2c CH |
1120 | /* |
1121 | * What a mess... | |
1122 | * | |
1123 | * Why can't we simply have a Fabrics In and Fabrics out command? | |
1124 | */ | |
1125 | if (unlikely(cmd->common.opcode == nvme_fabrics_command)) | |
2fd4167f | 1126 | return cmd->fabrics.fctype & 1; |
7a5abb4b CH |
1127 | return cmd->common.opcode & 1; |
1128 | } | |
1129 | ||
9d99a8dd | 1130 | enum { |
eb793e2c CH |
1131 | /* |
1132 | * Generic Command Status: | |
1133 | */ | |
9d99a8dd CH |
1134 | NVME_SC_SUCCESS = 0x0, |
1135 | NVME_SC_INVALID_OPCODE = 0x1, | |
1136 | NVME_SC_INVALID_FIELD = 0x2, | |
1137 | NVME_SC_CMDID_CONFLICT = 0x3, | |
1138 | NVME_SC_DATA_XFER_ERROR = 0x4, | |
1139 | NVME_SC_POWER_LOSS = 0x5, | |
1140 | NVME_SC_INTERNAL = 0x6, | |
1141 | NVME_SC_ABORT_REQ = 0x7, | |
1142 | NVME_SC_ABORT_QUEUE = 0x8, | |
1143 | NVME_SC_FUSED_FAIL = 0x9, | |
1144 | NVME_SC_FUSED_MISSING = 0xa, | |
1145 | NVME_SC_INVALID_NS = 0xb, | |
1146 | NVME_SC_CMD_SEQ_ERROR = 0xc, | |
1147 | NVME_SC_SGL_INVALID_LAST = 0xd, | |
1148 | NVME_SC_SGL_INVALID_COUNT = 0xe, | |
1149 | NVME_SC_SGL_INVALID_DATA = 0xf, | |
1150 | NVME_SC_SGL_INVALID_METADATA = 0x10, | |
1151 | NVME_SC_SGL_INVALID_TYPE = 0x11, | |
eb793e2c CH |
1152 | |
1153 | NVME_SC_SGL_INVALID_OFFSET = 0x16, | |
1154 | NVME_SC_SGL_INVALID_SUBTYPE = 0x17, | |
1155 | ||
9d99a8dd CH |
1156 | NVME_SC_LBA_RANGE = 0x80, |
1157 | NVME_SC_CAP_EXCEEDED = 0x81, | |
1158 | NVME_SC_NS_NOT_READY = 0x82, | |
1159 | NVME_SC_RESERVATION_CONFLICT = 0x83, | |
eb793e2c CH |
1160 | |
1161 | /* | |
1162 | * Command Specific Status: | |
1163 | */ | |
9d99a8dd CH |
1164 | NVME_SC_CQ_INVALID = 0x100, |
1165 | NVME_SC_QID_INVALID = 0x101, | |
1166 | NVME_SC_QUEUE_SIZE = 0x102, | |
1167 | NVME_SC_ABORT_LIMIT = 0x103, | |
1168 | NVME_SC_ABORT_MISSING = 0x104, | |
1169 | NVME_SC_ASYNC_LIMIT = 0x105, | |
1170 | NVME_SC_FIRMWARE_SLOT = 0x106, | |
1171 | NVME_SC_FIRMWARE_IMAGE = 0x107, | |
1172 | NVME_SC_INVALID_VECTOR = 0x108, | |
1173 | NVME_SC_INVALID_LOG_PAGE = 0x109, | |
1174 | NVME_SC_INVALID_FORMAT = 0x10a, | |
a446c084 | 1175 | NVME_SC_FW_NEEDS_CONV_RESET = 0x10b, |
9d99a8dd CH |
1176 | NVME_SC_INVALID_QUEUE = 0x10c, |
1177 | NVME_SC_FEATURE_NOT_SAVEABLE = 0x10d, | |
1178 | NVME_SC_FEATURE_NOT_CHANGEABLE = 0x10e, | |
1179 | NVME_SC_FEATURE_NOT_PER_NS = 0x10f, | |
a446c084 CH |
1180 | NVME_SC_FW_NEEDS_SUBSYS_RESET = 0x110, |
1181 | NVME_SC_FW_NEEDS_RESET = 0x111, | |
1182 | NVME_SC_FW_NEEDS_MAX_TIME = 0x112, | |
1183 | NVME_SC_FW_ACIVATE_PROHIBITED = 0x113, | |
1184 | NVME_SC_OVERLAPPING_RANGE = 0x114, | |
1185 | NVME_SC_NS_INSUFFICENT_CAP = 0x115, | |
1186 | NVME_SC_NS_ID_UNAVAILABLE = 0x116, | |
1187 | NVME_SC_NS_ALREADY_ATTACHED = 0x118, | |
1188 | NVME_SC_NS_IS_PRIVATE = 0x119, | |
1189 | NVME_SC_NS_NOT_ATTACHED = 0x11a, | |
1190 | NVME_SC_THIN_PROV_NOT_SUPP = 0x11b, | |
1191 | NVME_SC_CTRL_LIST_INVALID = 0x11c, | |
eb793e2c CH |
1192 | |
1193 | /* | |
1194 | * I/O Command Set Specific - NVM commands: | |
1195 | */ | |
9d99a8dd CH |
1196 | NVME_SC_BAD_ATTRIBUTES = 0x180, |
1197 | NVME_SC_INVALID_PI = 0x181, | |
1198 | NVME_SC_READ_ONLY = 0x182, | |
3b7c33b2 | 1199 | NVME_SC_ONCS_NOT_SUPPORTED = 0x183, |
eb793e2c CH |
1200 | |
1201 | /* | |
1202 | * I/O Command Set Specific - Fabrics commands: | |
1203 | */ | |
1204 | NVME_SC_CONNECT_FORMAT = 0x180, | |
1205 | NVME_SC_CONNECT_CTRL_BUSY = 0x181, | |
1206 | NVME_SC_CONNECT_INVALID_PARAM = 0x182, | |
1207 | NVME_SC_CONNECT_RESTART_DISC = 0x183, | |
1208 | NVME_SC_CONNECT_INVALID_HOST = 0x184, | |
1209 | ||
1210 | NVME_SC_DISCOVERY_RESTART = 0x190, | |
1211 | NVME_SC_AUTH_REQUIRED = 0x191, | |
1212 | ||
1213 | /* | |
1214 | * Media and Data Integrity Errors: | |
1215 | */ | |
9d99a8dd CH |
1216 | NVME_SC_WRITE_FAULT = 0x280, |
1217 | NVME_SC_READ_ERROR = 0x281, | |
1218 | NVME_SC_GUARD_CHECK = 0x282, | |
1219 | NVME_SC_APPTAG_CHECK = 0x283, | |
1220 | NVME_SC_REFTAG_CHECK = 0x284, | |
1221 | NVME_SC_COMPARE_FAILED = 0x285, | |
1222 | NVME_SC_ACCESS_DENIED = 0x286, | |
a446c084 | 1223 | NVME_SC_UNWRITTEN_BLOCK = 0x287, |
eb793e2c | 1224 | |
1a376216 CH |
1225 | /* |
1226 | * Path-related Errors: | |
1227 | */ | |
1228 | NVME_SC_ANA_PERSISTENT_LOSS = 0x301, | |
1229 | NVME_SC_ANA_INACCESSIBLE = 0x302, | |
1230 | NVME_SC_ANA_TRANSITION = 0x303, | |
1231 | ||
9d99a8dd CH |
1232 | NVME_SC_DNR = 0x4000, |
1233 | }; | |
1234 | ||
1235 | struct nvme_completion { | |
eb793e2c CH |
1236 | /* |
1237 | * Used by Admin and Fabrics commands to return data: | |
1238 | */ | |
d49187e9 CH |
1239 | union nvme_result { |
1240 | __le16 u16; | |
1241 | __le32 u32; | |
1242 | __le64 u64; | |
1243 | } result; | |
9d99a8dd CH |
1244 | __le16 sq_head; /* how much of this queue may be reclaimed */ |
1245 | __le16 sq_id; /* submission queue that generated this entry */ | |
1246 | __u16 command_id; /* of the command which completed */ | |
1247 | __le16 status; /* did the command fail, and if so, why? */ | |
1248 | }; | |
1249 | ||
8ef2074d GKB |
1250 | #define NVME_VS(major, minor, tertiary) \ |
1251 | (((major) << 16) | ((minor) << 8) | (tertiary)) | |
9d99a8dd | 1252 | |
c61d788b JT |
1253 | #define NVME_MAJOR(ver) ((ver) >> 16) |
1254 | #define NVME_MINOR(ver) (((ver) >> 8) & 0xff) | |
1255 | #define NVME_TERTIARY(ver) ((ver) & 0xff) | |
1256 | ||
b60503ba | 1257 | #endif /* _LINUX_NVME_H */ |