]>
Commit | Line | Data |
---|---|---|
b60503ba MW |
1 | /* |
2 | * Definitions for the NVM Express interface | |
3 | * Copyright (c) 2011, Intel Corporation. | |
4 | * | |
5 | * This program is free software; you can redistribute it and/or modify it | |
6 | * under the terms and conditions of the GNU General Public License, | |
7 | * version 2, as published by the Free Software Foundation. | |
8 | * | |
9 | * This program is distributed in the hope it will be useful, but WITHOUT | |
10 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
11 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
12 | * more details. | |
13 | * | |
14 | * You should have received a copy of the GNU General Public License along with | |
15 | * this program; if not, write to the Free Software Foundation, Inc., | |
16 | * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. | |
17 | */ | |
18 | ||
19 | #ifndef _LINUX_NVME_H | |
20 | #define _LINUX_NVME_H | |
21 | ||
22 | #include <linux/types.h> | |
23 | ||
24 | struct nvme_bar { | |
25 | __u64 cap; /* Controller Capabilities */ | |
26 | __u32 vs; /* Version */ | |
27 | __u32 ims; /* Interrupt Mask Set */ | |
28 | __u32 imc; /* Interrupt Mask Clear */ | |
29 | __u32 cc; /* Controller Configuration */ | |
30 | __u32 csts; /* Controller Status */ | |
31 | __u32 aqa; /* Admin Queue Attributes */ | |
32 | __u64 asq; /* Admin SQ Base Address */ | |
33 | __u64 acq; /* Admin CQ Base Address */ | |
34 | }; | |
35 | ||
36 | enum { | |
37 | NVME_CC_ENABLE = 1 << 0, | |
38 | NVME_CC_CSS_NVM = 0 << 4, | |
39 | NVME_CC_MPS_SHIFT = 7, | |
40 | NVME_CC_ARB_RR = 0 << 11, | |
41 | NVME_CC_ARB_WRRU = 1 << 11, | |
42 | NVME_CC_ARB_VS = 3 << 11, | |
43 | NVME_CC_SHN_NONE = 0 << 13, | |
44 | NVME_CC_SHN_NORMAL = 1 << 13, | |
45 | NVME_CC_SHN_ABRUPT = 2 << 13, | |
46 | NVME_CSTS_RDY = 1 << 0, | |
47 | NVME_CSTS_CFS = 1 << 1, | |
48 | NVME_CSTS_SHST_NORMAL = 0 << 2, | |
49 | NVME_CSTS_SHST_OCCUR = 1 << 2, | |
50 | NVME_CSTS_SHST_CMPLT = 2 << 2, | |
51 | }; | |
52 | ||
53 | #define NVME_VS(major, minor) (major << 16 | minor) | |
54 | ||
55 | struct nvme_id_ctrl { | |
56 | __le16 vid; | |
57 | __le16 ssvid; | |
58 | char sn[20]; | |
59 | char mn[40]; | |
60 | char fr[8]; | |
61 | __le32 nn; | |
62 | __u8 rab; | |
63 | __u8 rsvd77[178]; | |
64 | __le16 oacs; | |
65 | __u8 acl; | |
66 | __u8 aerl; | |
67 | __u8 frmw; | |
68 | __u8 lpa; | |
69 | __u8 elpe; | |
70 | __u8 npss; | |
71 | __u8 rsvd264[248]; | |
72 | __le64 psd[32]; | |
73 | __le16 oncs; | |
74 | __le16 fuses; | |
75 | __u8 fna; | |
76 | __u8 vwc; | |
77 | __le16 awun; | |
78 | __le16 awupf; | |
79 | __u8 rsvd778[246]; | |
80 | __u8 cmdset[2048]; | |
81 | __u8 vs[1024]; | |
82 | }; | |
83 | ||
84 | struct nvme_lbaf { | |
85 | __le16 ms; | |
86 | __u8 ds; | |
87 | __u8 rp; | |
88 | }; | |
89 | ||
90 | struct nvme_id_ns { | |
91 | __le64 nsze; | |
92 | __le64 ncap; | |
93 | __le64 nuse; | |
94 | __u8 nsfeat; | |
95 | __u8 nlbaf; | |
96 | __u8 flbas; | |
97 | __u8 mc; | |
98 | __u8 dpc; | |
99 | __u8 dps; | |
100 | __u8 rsvd30[98]; | |
101 | struct nvme_lbaf lbaf[16]; | |
102 | __u8 rsvd192[192]; | |
103 | __u8 vs[3712]; | |
104 | }; | |
105 | ||
106 | enum { | |
107 | NVME_NS_FEAT_THIN = 1 << 0, | |
108 | NVME_LBAF_RP_BEST = 0, | |
109 | NVME_LBAF_RP_BETTER = 1, | |
110 | NVME_LBAF_RP_GOOD = 2, | |
111 | NVME_LBAF_RP_DEGRADED = 3, | |
112 | }; | |
113 | ||
114 | struct nvme_lba_range_type { | |
115 | __u8 type; | |
116 | __u8 attributes; | |
117 | __u8 rsvd2[14]; | |
118 | __u64 slba; | |
119 | __u64 nlb; | |
120 | __u8 guid[16]; | |
121 | __u8 rsvd48[16]; | |
122 | }; | |
123 | ||
124 | enum { | |
125 | NVME_LBART_TYPE_FS = 0x01, | |
126 | NVME_LBART_TYPE_RAID = 0x02, | |
127 | NVME_LBART_TYPE_CACHE = 0x03, | |
128 | NVME_LBART_TYPE_SWAP = 0x04, | |
129 | ||
130 | NVME_LBART_ATTRIB_TEMP = 1 << 0, | |
131 | NVME_LBART_ATTRIB_HIDE = 1 << 1, | |
132 | }; | |
133 | ||
134 | /* I/O commands */ | |
135 | ||
136 | enum nvme_opcode { | |
137 | nvme_cmd_flush = 0x00, | |
138 | nvme_cmd_write = 0x01, | |
139 | nvme_cmd_read = 0x02, | |
140 | nvme_cmd_write_uncor = 0x04, | |
141 | nvme_cmd_compare = 0x05, | |
142 | nvme_cmd_dsm = 0x09, | |
143 | }; | |
144 | ||
145 | struct nvme_rw_command { | |
146 | __u8 opcode; | |
147 | __u8 flags; | |
148 | __u16 command_id; | |
149 | __le32 nsid; | |
150 | __u64 rsvd2; | |
151 | __le64 metadata; | |
152 | __le64 prp1; | |
153 | __le64 prp2; | |
154 | __le64 slba; | |
155 | __le16 length; | |
156 | __le16 control; | |
157 | __le32 dsmgmt; | |
158 | __le32 reftag; | |
159 | __le16 apptag; | |
160 | __le16 appmask; | |
161 | }; | |
162 | ||
163 | enum { | |
164 | NVME_RW_LR = 1 << 15, | |
165 | NVME_RW_FUA = 1 << 14, | |
166 | NVME_RW_DSM_FREQ_UNSPEC = 0, | |
167 | NVME_RW_DSM_FREQ_TYPICAL = 1, | |
168 | NVME_RW_DSM_FREQ_RARE = 2, | |
169 | NVME_RW_DSM_FREQ_READS = 3, | |
170 | NVME_RW_DSM_FREQ_WRITES = 4, | |
171 | NVME_RW_DSM_FREQ_RW = 5, | |
172 | NVME_RW_DSM_FREQ_ONCE = 6, | |
173 | NVME_RW_DSM_FREQ_PREFETCH = 7, | |
174 | NVME_RW_DSM_FREQ_TEMP = 8, | |
175 | NVME_RW_DSM_LATENCY_NONE = 0 << 4, | |
176 | NVME_RW_DSM_LATENCY_IDLE = 1 << 4, | |
177 | NVME_RW_DSM_LATENCY_NORM = 2 << 4, | |
178 | NVME_RW_DSM_LATENCY_LOW = 3 << 4, | |
179 | NVME_RW_DSM_SEQ_REQ = 1 << 6, | |
180 | NVME_RW_DSM_COMPRESSED = 1 << 7, | |
181 | }; | |
182 | ||
183 | /* Admin commands */ | |
184 | ||
185 | enum nvme_admin_opcode { | |
186 | nvme_admin_delete_sq = 0x00, | |
187 | nvme_admin_create_sq = 0x01, | |
188 | nvme_admin_get_features = 0x02, | |
189 | nvme_admin_delete_cq = 0x04, | |
190 | nvme_admin_create_cq = 0x05, | |
191 | nvme_admin_identify = 0x06, | |
192 | nvme_admin_abort_cmd = 0x08, | |
193 | nvme_admin_set_features = 0x09, | |
194 | nvme_admin_get_log_page = 0x0a, | |
195 | nvme_admin_async_event = 0x0c, | |
196 | nvme_admin_download_fw = 0x0d, | |
197 | nvme_admin_security_recv = 0x0e, | |
198 | nvme_admin_format_nvm = 0x10, | |
199 | nvme_admin_security_send = 0x11, | |
200 | nvme_admin_activate_fw = 0x14, | |
201 | }; | |
202 | ||
203 | enum { | |
204 | NVME_QUEUE_PHYS_CONTIG = (1 << 0), | |
205 | NVME_CQ_IRQ_ENABLED = (1 << 1), | |
206 | NVME_SQ_PRIO_URGENT = (0 << 1), | |
207 | NVME_SQ_PRIO_HIGH = (1 << 1), | |
208 | NVME_SQ_PRIO_MEDIUM = (2 << 1), | |
209 | NVME_SQ_PRIO_LOW = (3 << 1), | |
210 | NVME_FEAT_ARBITRATION = 0x01, | |
211 | NVME_FEAT_POWER_MGMT = 0x02, | |
212 | NVME_FEAT_LBA_RANGE = 0x03, | |
213 | NVME_FEAT_TEMP_THRESH = 0x04, | |
214 | NVME_FEAT_ERR_RECOVERY = 0x05, | |
215 | NVME_FEAT_VOLATILE_WC = 0x06, | |
216 | NVME_FEAT_NUM_QUEUES = 0x07, | |
217 | NVME_FEAT_IRQ_COALESCE = 0x08, | |
218 | NVME_FEAT_IRQ_CONFIG = 0x09, | |
219 | NVME_FEAT_WRITE_ATOMIC = 0x0a, | |
220 | NVME_FEAT_ASYNC_EVENT = 0x0b, | |
221 | NVME_FEAT_SW_PROGRESS = 0x0c, | |
222 | }; | |
223 | ||
224 | struct nvme_identify { | |
225 | __u8 opcode; | |
226 | __u8 flags; | |
227 | __u16 command_id; | |
228 | __le32 nsid; | |
229 | __u64 rsvd2[2]; | |
230 | __le64 prp1; | |
231 | __le64 prp2; | |
232 | __le32 cns; | |
233 | __u32 rsvd11[5]; | |
234 | }; | |
235 | ||
236 | struct nvme_features { | |
237 | __u8 opcode; | |
238 | __u8 flags; | |
239 | __u16 command_id; | |
240 | __le32 nsid; | |
241 | __u64 rsvd2[2]; | |
242 | __le64 prp1; | |
243 | __le64 prp2; | |
244 | __le32 fid; | |
245 | __le32 dword11; | |
246 | __u32 rsvd12[4]; | |
247 | }; | |
248 | ||
249 | struct nvme_create_cq { | |
250 | __u8 opcode; | |
251 | __u8 flags; | |
252 | __u16 command_id; | |
253 | __le32 rsvd1[5]; | |
254 | __le64 prp1; | |
255 | __u64 rsvd8; | |
256 | __le16 cqid; | |
257 | __le16 qsize; | |
258 | __le16 cq_flags; | |
259 | __le16 irq_vector; | |
260 | __u32 rsvd12[4]; | |
261 | }; | |
262 | ||
263 | struct nvme_create_sq { | |
264 | __u8 opcode; | |
265 | __u8 flags; | |
266 | __u16 command_id; | |
267 | __le32 rsvd1[5]; | |
268 | __le64 prp1; | |
269 | __u64 rsvd8; | |
270 | __le16 sqid; | |
271 | __le16 qsize; | |
272 | __le16 sq_flags; | |
273 | __le16 cqid; | |
274 | __le32 rsvd12[4]; | |
275 | }; | |
276 | ||
277 | struct nvme_delete_queue { | |
278 | __u8 opcode; | |
279 | __u8 flags; | |
280 | __u16 command_id; | |
281 | __u32 rsvd1[9]; | |
282 | __le16 qid; | |
283 | __le16 rsvd10; | |
284 | __le32 rsvd11[5]; | |
285 | }; | |
286 | ||
287 | struct nvme_common_command { | |
288 | __u8 opcode; | |
289 | __u8 flags; | |
290 | __u16 command_id; | |
291 | __le32 nsid; | |
292 | __u32 rsvd2[14]; | |
293 | }; | |
294 | ||
295 | struct nvme_command { | |
296 | union { | |
297 | struct nvme_common_command common; | |
298 | struct nvme_rw_command rw; | |
299 | struct nvme_identify identify; | |
300 | struct nvme_features features; | |
301 | struct nvme_create_cq create_cq; | |
302 | struct nvme_create_sq create_sq; | |
303 | struct nvme_delete_queue delete_queue; | |
304 | }; | |
305 | }; | |
306 | ||
307 | /* XXX: Sync with spec */ | |
308 | enum { | |
309 | NVME_SC_SUCCESS = 0x0, | |
310 | NVME_SC_INVALID_OPCODE = 0x1, | |
311 | NVME_SC_INVALID_FIELD = 0x2, | |
312 | NVME_SC_CMDID_CONFLICT = 0x3, | |
313 | NVME_SC_DATA_XFER_ERROR = 0x4, | |
314 | NVME_SC_POWER_LOSS = 0x5, | |
315 | NVME_SC_INTERNAL = 0x6, | |
316 | NVME_SC_ABORT_REQ = 0x7, | |
317 | NVME_SC_ABORT_QUEUE = 0x8, | |
318 | NVME_SC_FUSED_FAIL = 0x9, | |
319 | NVME_SC_FUSED_MISSING = 0xa, | |
320 | NVME_SC_LBA_RANGE = 0x80, | |
321 | NVME_SC_CAP_EXCEEDED = 0x81, | |
322 | NVME_SC_NS_NOT_READY = 0x82, | |
323 | NVME_SC_CQ_INVALID = 0x100, | |
324 | NVME_SC_QID_INVALID = 0x101, | |
325 | NVME_SC_QUEUE_SIZE = 0x102, | |
326 | NVME_SC_WRITE_FAULT = 0x280, | |
327 | NVME_SC_READ_ERROR = 0x281, | |
328 | }; | |
329 | ||
330 | struct nvme_completion { | |
331 | __le32 result; /* Used by admin commands to return data */ | |
332 | __le32 rsvd; | |
333 | __le16 sq_head; /* how much of this queue may be reclaimed */ | |
334 | __le16 sq_id; /* submission queue that generated this entry */ | |
335 | __u16 command_id; /* of the command which completed */ | |
336 | __le16 status; /* did the command fail, and if so, why? */ | |
337 | }; | |
338 | ||
339 | #define NVME_IOCTL_IDENTIFY_NS _IOW('N', 0x40, struct nvme_id_ns) | |
340 | #define NVME_IOCTL_IDENTIFY_CTRL _IOW('N', 0x41, struct nvme_id_ctrl) | |
341 | #define NVME_IOCTL_GET_RANGE_TYPE _IOW('N', 0x42, struct nvme_lba_range_type) | |
342 | ||
343 | #endif /* _LINUX_NVME_H */ |