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nvme: add support for FW activation without reset
[mirror_ubuntu-bionic-kernel.git] / include / linux / nvme.h
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b60503ba
MW		 1/*
2 * Definitions for the NVM Express interface
8757ad65 3 * Copyright (c) 2011-2014, Intel Corporation.
b60503ba
MW		 4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms and conditions of the GNU General Public License,
7 * version 2, as published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
b60503ba
MW		 13 */
14
15#ifndef _LINUX_NVME_H
16#define _LINUX_NVME_H
17
2812dfe3 18#include <linux/types.h>
8e412263 19#include <linux/uuid.h>
eb793e2c
CH		 20
21/* NQN names in commands fields specified one size */
22#define NVMF_NQN_FIELD_LEN 256
23
24/* However the max length of a qualified name is another size */
25#define NVMF_NQN_SIZE 223
26
27#define NVMF_TRSVCID_SIZE 32
28#define NVMF_TRADDR_SIZE 256
29#define NVMF_TSAS_SIZE 256
30
31#define NVME_DISC_SUBSYS_NAME "nqn.2014-08.org.nvmexpress.discovery"
32
33#define NVME_RDMA_IP_PORT 4420
34
35enum nvme_subsys_type {
36 NVME_NQN_DISC = 1, /* Discovery type target subsystem */
37 NVME_NQN_NVME = 2, /* NVME type target subsystem */
38};
39
40/* Address Family codes for Discovery Log Page entry ADRFAM field */
41enum {
42 NVMF_ADDR_FAMILY_PCI = 0, /* PCIe */
43 NVMF_ADDR_FAMILY_IP4 = 1, /* IP4 */
44 NVMF_ADDR_FAMILY_IP6 = 2, /* IP6 */
45 NVMF_ADDR_FAMILY_IB = 3, /* InfiniBand */
46 NVMF_ADDR_FAMILY_FC = 4, /* Fibre Channel */
47};
48
49/* Transport Type codes for Discovery Log Page entry TRTYPE field */
50enum {
51 NVMF_TRTYPE_RDMA = 1, /* RDMA */
52 NVMF_TRTYPE_FC = 2, /* Fibre Channel */
53 NVMF_TRTYPE_LOOP = 254, /* Reserved for host usage */
54 NVMF_TRTYPE_MAX,
55};
56
57/* Transport Requirements codes for Discovery Log Page entry TREQ field */
58enum {
59 NVMF_TREQ_NOT_SPECIFIED = 0, /* Not specified */
60 NVMF_TREQ_REQUIRED = 1, /* Required */
61 NVMF_TREQ_NOT_REQUIRED = 2, /* Not Required */
62};
63
64/* RDMA QP Service Type codes for Discovery Log Page entry TSAS
65 * RDMA_QPTYPE field
66 */
67enum {
bf17aa36
RD		 68 NVMF_RDMA_QPTYPE_CONNECTED = 1, /* Reliable Connected */
69 NVMF_RDMA_QPTYPE_DATAGRAM = 2, /* Reliable Datagram */
eb793e2c
CH		 70};
71
72/* RDMA QP Service Type codes for Discovery Log Page entry TSAS
73 * RDMA_QPTYPE field
74 */
75enum {
bf17aa36
RD		 76 NVMF_RDMA_PRTYPE_NOT_SPECIFIED = 1, /* No Provider Specified */
77 NVMF_RDMA_PRTYPE_IB = 2, /* InfiniBand */
78 NVMF_RDMA_PRTYPE_ROCE = 3, /* InfiniBand RoCE */
79 NVMF_RDMA_PRTYPE_ROCEV2 = 4, /* InfiniBand RoCEV2 */
80 NVMF_RDMA_PRTYPE_IWARP = 5, /* IWARP */
eb793e2c
CH		 81};
82
83/* RDMA Connection Management Service Type codes for Discovery Log Page
84 * entry TSAS RDMA_CMS field
85 */
86enum {
bf17aa36 87 NVMF_RDMA_CMS_RDMA_CM = 1, /* Sockets based endpoint addressing */
eb793e2c
CH		 88};
89
7aa1f427 90#define NVME_AQ_DEPTH 32
2812dfe3 91
7a67cbea
CH		 92enum {
93 NVME_REG_CAP = 0x0000, /* Controller Capabilities */
94 NVME_REG_VS = 0x0008, /* Version */
95 NVME_REG_INTMS = 0x000c, /* Interrupt Mask Set */
a5b714ad 96 NVME_REG_INTMC = 0x0010, /* Interrupt Mask Clear */
7a67cbea
CH		 97 NVME_REG_CC = 0x0014, /* Controller Configuration */
98 NVME_REG_CSTS = 0x001c, /* Controller Status */
99 NVME_REG_NSSR = 0x0020, /* NVM Subsystem Reset */
100 NVME_REG_AQA = 0x0024, /* Admin Queue Attributes */
101 NVME_REG_ASQ = 0x0028, /* Admin SQ Base Address */
a5b714ad 102 NVME_REG_ACQ = 0x0030, /* Admin CQ Base Address */
7a67cbea
CH		 103 NVME_REG_CMBLOC = 0x0038, /* Controller Memory Buffer Location */
104 NVME_REG_CMBSZ = 0x003c, /* Controller Memory Buffer Size */
97f6ef64 105 NVME_REG_DBS = 0x1000, /* SQ 0 Tail Doorbell */
b60503ba
MW		 106};
107
a0cadb85 108#define NVME_CAP_MQES(cap) ((cap) & 0xffff)
22605f96 109#define NVME_CAP_TIMEOUT(cap) (((cap) >> 24) & 0xff)
f1938f6e 110#define NVME_CAP_STRIDE(cap) (((cap) >> 32) & 0xf)
dfbac8c7 111#define NVME_CAP_NSSRC(cap) (((cap) >> 36) & 0x1)
8fc23e03 112#define NVME_CAP_MPSMIN(cap) (((cap) >> 48) & 0xf)
1d090624 113#define NVME_CAP_MPSMAX(cap) (((cap) >> 52) & 0xf)
22605f96 114
8ffaadf7
JD		 115#define NVME_CMB_BIR(cmbloc) ((cmbloc) & 0x7)
116#define NVME_CMB_OFST(cmbloc) (((cmbloc) >> 12) & 0xfffff)
117#define NVME_CMB_SZ(cmbsz) (((cmbsz) >> 12) & 0xfffff)
118#define NVME_CMB_SZU(cmbsz) (((cmbsz) >> 8) & 0xf)
119
120#define NVME_CMB_WDS(cmbsz) ((cmbsz) & 0x10)
121#define NVME_CMB_RDS(cmbsz) ((cmbsz) & 0x8)
122#define NVME_CMB_LISTS(cmbsz) ((cmbsz) & 0x4)
123#define NVME_CMB_CQS(cmbsz) ((cmbsz) & 0x2)
124#define NVME_CMB_SQS(cmbsz) ((cmbsz) & 0x1)
125
69cd27e2
CH		 126/*
127 * Submission and Completion Queue Entry Sizes for the NVM command set.
128 * (In bytes and specified as a power of two (2^n)).
129 */
130#define NVME_NVM_IOSQES 6
131#define NVME_NVM_IOCQES 4
132
b60503ba
MW		 133enum {
134 NVME_CC_ENABLE = 1 << 0,
135 NVME_CC_CSS_NVM = 0 << 4,
136 NVME_CC_MPS_SHIFT = 7,
137 NVME_CC_ARB_RR = 0 << 11,
138 NVME_CC_ARB_WRRU = 1 << 11,
7f53f9d2
MW		 139 NVME_CC_ARB_VS = 7 << 11,
140 NVME_CC_SHN_NONE = 0 << 14,
141 NVME_CC_SHN_NORMAL = 1 << 14,
142 NVME_CC_SHN_ABRUPT = 2 << 14,
1894d8f1 143 NVME_CC_SHN_MASK = 3 << 14,
69cd27e2
CH		 144 NVME_CC_IOSQES = NVME_NVM_IOSQES << 16,
145 NVME_CC_IOCQES = NVME_NVM_IOCQES << 20,
b60503ba
MW		 146 NVME_CSTS_RDY = 1 << 0,
147 NVME_CSTS_CFS = 1 << 1,
dfbac8c7 148 NVME_CSTS_NSSRO = 1 << 4,
b6dccf7f 149 NVME_CSTS_PP = 1 << 5,
b60503ba
MW		 150 NVME_CSTS_SHST_NORMAL = 0 << 2,
151 NVME_CSTS_SHST_OCCUR = 1 << 2,
152 NVME_CSTS_SHST_CMPLT = 2 << 2,
1894d8f1 153 NVME_CSTS_SHST_MASK = 3 << 2,
b60503ba
MW		 154};
155
9d99a8dd
CH		 156struct nvme_id_power_state {
157 __le16 max_power; /* centiwatts */
158 __u8 rsvd2;
159 __u8 flags;
160 __le32 entry_lat; /* microseconds */
161 __le32 exit_lat; /* microseconds */
162 __u8 read_tput;
163 __u8 read_lat;
164 __u8 write_tput;
165 __u8 write_lat;
166 __le16 idle_power;
167 __u8 idle_scale;
168 __u8 rsvd19;
169 __le16 active_power;
170 __u8 active_work_scale;
171 __u8 rsvd23[9];
172};
173
174enum {
175 NVME_PS_FLAGS_MAX_POWER_SCALE = 1 << 0,
176 NVME_PS_FLAGS_NON_OP_STATE = 1 << 1,
177};
178
179struct nvme_id_ctrl {
180 __le16 vid;
181 __le16 ssvid;
182 char sn[20];
183 char mn[40];
184 char fr[8];
185 __u8 rab;
186 __u8 ieee[3];
a446c084 187 __u8 cmic;
9d99a8dd 188 __u8 mdts;
08c69640
CH		 189 __le16 cntlid;
190 __le32 ver;
14e974a8
CH		 191 __le32 rtd3r;
192 __le32 rtd3e;
193 __le32 oaes;
eb793e2c
CH		 194 __le32 ctratt;
195 __u8 rsvd100[156];
9d99a8dd
CH		 196 __le16 oacs;
197 __u8 acl;
198 __u8 aerl;
199 __u8 frmw;
200 __u8 lpa;
201 __u8 elpe;
202 __u8 npss;
203 __u8 avscc;
204 __u8 apsta;
205 __le16 wctemp;
206 __le16 cctemp;
a446c084
CH		 207 __le16 mtfa;
208 __le32 hmpre;
209 __le32 hmmin;
210 __u8 tnvmcap[16];
211 __u8 unvmcap[16];
212 __le32 rpmbs;
435e8090
GJ		 213 __le16 edstt;
214 __u8 dsto;
215 __u8 fwug;
7b89eae2 216 __le16 kas;
435e8090
GJ		 217 __le16 hctma;
218 __le16 mntmt;
219 __le16 mxtmt;
220 __le32 sanicap;
221 __u8 rsvd332[180];
9d99a8dd
CH		 222 __u8 sqes;
223 __u8 cqes;
eb793e2c 224 __le16 maxcmd;
9d99a8dd
CH		 225 __le32 nn;
226 __le16 oncs;
227 __le16 fuses;
228 __u8 fna;
229 __u8 vwc;
230 __le16 awun;
231 __le16 awupf;
232 __u8 nvscc;
233 __u8 rsvd531;
234 __le16 acwu;
235 __u8 rsvd534[2];
236 __le32 sgls;
eb793e2c
CH		 237 __u8 rsvd540[228];
238 char subnqn[256];
239 __u8 rsvd1024[768];
240 __le32 ioccsz;
241 __le32 iorcsz;
242 __le16 icdoff;
243 __u8 ctrattr;
244 __u8 msdbd;
245 __u8 rsvd1804[244];
9d99a8dd
CH		 246 struct nvme_id_power_state psd[32];
247 __u8 vs[1024];
248};
249
250enum {
251 NVME_CTRL_ONCS_COMPARE = 1 << 0,
252 NVME_CTRL_ONCS_WRITE_UNCORRECTABLE = 1 << 1,
253 NVME_CTRL_ONCS_DSM = 1 << 2,
3b7c33b2 254 NVME_CTRL_ONCS_WRITE_ZEROES = 1 << 3,
9d99a8dd 255 NVME_CTRL_VWC_PRESENT = 1 << 0,
8a9ae523 256 NVME_CTRL_OACS_SEC_SUPP = 1 << 0,
f5d11840 257 NVME_CTRL_OACS_DIRECTIVES = 1 << 5,
f9f38e33 258 NVME_CTRL_OACS_DBBUF_SUPP = 1 << 7,
9d99a8dd
CH		 259};
260
261struct nvme_lbaf {
262 __le16 ms;
263 __u8 ds;
264 __u8 rp;
265};
266
267struct nvme_id_ns {
268 __le64 nsze;
269 __le64 ncap;
270 __le64 nuse;
271 __u8 nsfeat;
272 __u8 nlbaf;
273 __u8 flbas;
274 __u8 mc;
275 __u8 dpc;
276 __u8 dps;
277 __u8 nmic;
278 __u8 rescap;
279 __u8 fpi;
280 __u8 rsvd33;
281 __le16 nawun;
282 __le16 nawupf;
283 __le16 nacwu;
284 __le16 nabsn;
285 __le16 nabo;
286 __le16 nabspf;
6b8190d6 287 __le16 noiob;
a446c084 288 __u8 nvmcap[16];
9d99a8dd
CH		 289 __u8 rsvd64[40];
290 __u8 nguid[16];
291 __u8 eui64[8];
292 struct nvme_lbaf lbaf[16];
293 __u8 rsvd192[192];
294 __u8 vs[3712];
295};
296
329dd768
CH		 297enum {
298 NVME_ID_CNS_NS = 0x00,
299 NVME_ID_CNS_CTRL = 0x01,
300 NVME_ID_CNS_NS_ACTIVE_LIST = 0x02,
af8b86e9 301 NVME_ID_CNS_NS_DESC_LIST = 0x03,
329dd768
CH		 302 NVME_ID_CNS_NS_PRESENT_LIST = 0x10,
303 NVME_ID_CNS_NS_PRESENT = 0x11,
304 NVME_ID_CNS_CTRL_NS_LIST = 0x12,
305 NVME_ID_CNS_CTRL_LIST = 0x13,
306};
307
f5d11840
JA		 308enum {
309 NVME_DIR_IDENTIFY = 0x00,
310 NVME_DIR_STREAMS = 0x01,
311 NVME_DIR_SND_ID_OP_ENABLE = 0x01,
312 NVME_DIR_SND_ST_OP_REL_ID = 0x01,
313 NVME_DIR_SND_ST_OP_REL_RSC = 0x02,
314 NVME_DIR_RCV_ID_OP_PARAM = 0x01,
315 NVME_DIR_RCV_ST_OP_PARAM = 0x01,
316 NVME_DIR_RCV_ST_OP_STATUS = 0x02,
317 NVME_DIR_RCV_ST_OP_RESOURCE = 0x03,
318 NVME_DIR_ENDIR = 0x01,
319};
320
9d99a8dd
CH		 321enum {
322 NVME_NS_FEAT_THIN = 1 << 0,
323 NVME_NS_FLBAS_LBA_MASK = 0xf,
324 NVME_NS_FLBAS_META_EXT = 0x10,
325 NVME_LBAF_RP_BEST = 0,
326 NVME_LBAF_RP_BETTER = 1,
327 NVME_LBAF_RP_GOOD = 2,
328 NVME_LBAF_RP_DEGRADED = 3,
329 NVME_NS_DPC_PI_LAST = 1 << 4,
330 NVME_NS_DPC_PI_FIRST = 1 << 3,
331 NVME_NS_DPC_PI_TYPE3 = 1 << 2,
332 NVME_NS_DPC_PI_TYPE2 = 1 << 1,
333 NVME_NS_DPC_PI_TYPE1 = 1 << 0,
334 NVME_NS_DPS_PI_FIRST = 1 << 3,
335 NVME_NS_DPS_PI_MASK = 0x7,
336 NVME_NS_DPS_PI_TYPE1 = 1,
337 NVME_NS_DPS_PI_TYPE2 = 2,
338 NVME_NS_DPS_PI_TYPE3 = 3,
339};
340
af8b86e9
JT		 341struct nvme_ns_id_desc {
342 __u8 nidt;
343 __u8 nidl;
344 __le16 reserved;
345};
346
347#define NVME_NIDT_EUI64_LEN 8
348#define NVME_NIDT_NGUID_LEN 16
349#define NVME_NIDT_UUID_LEN 16
350
351enum {
352 NVME_NIDT_EUI64 = 0x01,
353 NVME_NIDT_NGUID = 0x02,
354 NVME_NIDT_UUID = 0x03,
355};
356
9d99a8dd
CH		 357struct nvme_smart_log {
358 __u8 critical_warning;
359 __u8 temperature[2];
360 __u8 avail_spare;
361 __u8 spare_thresh;
362 __u8 percent_used;
363 __u8 rsvd6[26];
364 __u8 data_units_read[16];
365 __u8 data_units_written[16];
366 __u8 host_reads[16];
367 __u8 host_writes[16];
368 __u8 ctrl_busy_time[16];
369 __u8 power_cycles[16];
370 __u8 power_on_hours[16];
371 __u8 unsafe_shutdowns[16];
372 __u8 media_errors[16];
373 __u8 num_err_log_entries[16];
374 __le32 warning_temp_time;
375 __le32 critical_comp_time;
376 __le16 temp_sensor[8];
377 __u8 rsvd216[296];
378};
379
b6dccf7f
AD		 380struct nvme_fw_slot_info_log {
381 __u8 afi;
382 __u8 rsvd1[7];
383 __le64 frs[7];
384 __u8 rsvd64[448];
385};
386
9d99a8dd
CH		 387enum {
388 NVME_SMART_CRIT_SPARE = 1 << 0,
389 NVME_SMART_CRIT_TEMPERATURE = 1 << 1,
390 NVME_SMART_CRIT_RELIABILITY = 1 << 2,
391 NVME_SMART_CRIT_MEDIA = 1 << 3,
392 NVME_SMART_CRIT_VOLATILE_MEMORY = 1 << 4,
393};
394
395enum {
396 NVME_AER_NOTICE_NS_CHANGED = 0x0002,
b6dccf7f 397 NVME_AER_NOTICE_FW_ACT_STARTING = 0x0102,
9d99a8dd
CH		 398};
399
400struct nvme_lba_range_type {
401 __u8 type;
402 __u8 attributes;
403 __u8 rsvd2[14];
404 __u64 slba;
405 __u64 nlb;
406 __u8 guid[16];
407 __u8 rsvd48[16];
408};
409
410enum {
411 NVME_LBART_TYPE_FS = 0x01,
412 NVME_LBART_TYPE_RAID = 0x02,
413 NVME_LBART_TYPE_CACHE = 0x03,
414 NVME_LBART_TYPE_SWAP = 0x04,
415
416 NVME_LBART_ATTRIB_TEMP = 1 << 0,
417 NVME_LBART_ATTRIB_HIDE = 1 << 1,
418};
419
420struct nvme_reservation_status {
421 __le32 gen;
422 __u8 rtype;
423 __u8 regctl[2];
424 __u8 resv5[2];
425 __u8 ptpls;
426 __u8 resv10[13];
427 struct {
428 __le16 cntlid;
429 __u8 rcsts;
430 __u8 resv3[5];
431 __le64 hostid;
432 __le64 rkey;
433 } regctl_ds[];
434};
435
79f370ea
CH		 436enum nvme_async_event_type {
437 NVME_AER_TYPE_ERROR = 0,
438 NVME_AER_TYPE_SMART = 1,
439 NVME_AER_TYPE_NOTICE = 2,
440};
441
9d99a8dd
CH		 442/* I/O commands */
443
444enum nvme_opcode {
445 nvme_cmd_flush = 0x00,
446 nvme_cmd_write = 0x01,
447 nvme_cmd_read = 0x02,
448 nvme_cmd_write_uncor = 0x04,
449 nvme_cmd_compare = 0x05,
450 nvme_cmd_write_zeroes = 0x08,
451 nvme_cmd_dsm = 0x09,
452 nvme_cmd_resv_register = 0x0d,
453 nvme_cmd_resv_report = 0x0e,
454 nvme_cmd_resv_acquire = 0x11,
455 nvme_cmd_resv_release = 0x15,
456};
457
eb793e2c
CH		 458/*
459 * Descriptor subtype - lower 4 bits of nvme_(keyed_)sgl_desc identifier
460 *
461 * @NVME_SGL_FMT_ADDRESS: absolute address of the data block
462 * @NVME_SGL_FMT_OFFSET: relative offset of the in-capsule data block
463 * @NVME_SGL_FMT_INVALIDATE: RDMA transport specific remote invalidation
464 * request subtype
465 */
466enum {
467 NVME_SGL_FMT_ADDRESS = 0x00,
468 NVME_SGL_FMT_OFFSET = 0x01,
469 NVME_SGL_FMT_INVALIDATE = 0x0f,
470};
471
472/*
473 * Descriptor type - upper 4 bits of nvme_(keyed_)sgl_desc identifier
474 *
475 * For struct nvme_sgl_desc:
476 * @NVME_SGL_FMT_DATA_DESC: data block descriptor
477 * @NVME_SGL_FMT_SEG_DESC: sgl segment descriptor
478 * @NVME_SGL_FMT_LAST_SEG_DESC: last sgl segment descriptor
479 *
480 * For struct nvme_keyed_sgl_desc:
481 * @NVME_KEY_SGL_FMT_DATA_DESC: keyed data block descriptor
482 */
483enum {
484 NVME_SGL_FMT_DATA_DESC = 0x00,
485 NVME_SGL_FMT_SEG_DESC = 0x02,
486 NVME_SGL_FMT_LAST_SEG_DESC = 0x03,
487 NVME_KEY_SGL_FMT_DATA_DESC = 0x04,
488};
489
490struct nvme_sgl_desc {
491 __le64 addr;
492 __le32 length;
493 __u8 rsvd[3];
494 __u8 type;
495};
496
497struct nvme_keyed_sgl_desc {
498 __le64 addr;
499 __u8 length[3];
500 __u8 key[4];
501 __u8 type;
502};
503
504union nvme_data_ptr {
505 struct {
506 __le64 prp1;
507 __le64 prp2;
508 };
509 struct nvme_sgl_desc sgl;
510 struct nvme_keyed_sgl_desc ksgl;
511};
512
3972be23
JS		 513/*
514 * Lowest two bits of our flags field (FUSE field in the spec):
515 *
516 * @NVME_CMD_FUSE_FIRST: Fused Operation, first command
517 * @NVME_CMD_FUSE_SECOND: Fused Operation, second command
518 *
519 * Highest two bits in our flags field (PSDT field in the spec):
520 *
521 * @NVME_CMD_PSDT_SGL_METABUF: Use SGLS for this transfer,
522 * If used, MPTR contains addr of single physical buffer (byte aligned).
523 * @NVME_CMD_PSDT_SGL_METASEG: Use SGLS for this transfer,
524 * If used, MPTR contains an address of an SGL segment containing
525 * exactly 1 SGL descriptor (qword aligned).
526 */
527enum {
528 NVME_CMD_FUSE_FIRST = (1 << 0),
529 NVME_CMD_FUSE_SECOND = (1 << 1),
530
531 NVME_CMD_SGL_METABUF = (1 << 6),
532 NVME_CMD_SGL_METASEG = (1 << 7),
533 NVME_CMD_SGL_ALL = NVME_CMD_SGL_METABUF | NVME_CMD_SGL_METASEG,
534};
535
9d99a8dd
CH		 536struct nvme_common_command {
537 __u8 opcode;
538 __u8 flags;
539 __u16 command_id;
540 __le32 nsid;
541 __le32 cdw2[2];
542 __le64 metadata;
eb793e2c 543 union nvme_data_ptr dptr;
9d99a8dd
CH		 544 __le32 cdw10[6];
545};
546
547struct nvme_rw_command {
548 __u8 opcode;
549 __u8 flags;
550 __u16 command_id;
551 __le32 nsid;
552 __u64 rsvd2;
553 __le64 metadata;
eb793e2c 554 union nvme_data_ptr dptr;
9d99a8dd
CH		 555 __le64 slba;
556 __le16 length;
557 __le16 control;
558 __le32 dsmgmt;
559 __le32 reftag;
560 __le16 apptag;
561 __le16 appmask;
562};
563
564enum {
565 NVME_RW_LR = 1 << 15,
566 NVME_RW_FUA = 1 << 14,
567 NVME_RW_DSM_FREQ_UNSPEC = 0,
568 NVME_RW_DSM_FREQ_TYPICAL = 1,
569 NVME_RW_DSM_FREQ_RARE = 2,
570 NVME_RW_DSM_FREQ_READS = 3,
571 NVME_RW_DSM_FREQ_WRITES = 4,
572 NVME_RW_DSM_FREQ_RW = 5,
573 NVME_RW_DSM_FREQ_ONCE = 6,
574 NVME_RW_DSM_FREQ_PREFETCH = 7,
575 NVME_RW_DSM_FREQ_TEMP = 8,
576 NVME_RW_DSM_LATENCY_NONE = 0 << 4,
577 NVME_RW_DSM_LATENCY_IDLE = 1 << 4,
578 NVME_RW_DSM_LATENCY_NORM = 2 << 4,
579 NVME_RW_DSM_LATENCY_LOW = 3 << 4,
580 NVME_RW_DSM_SEQ_REQ = 1 << 6,
581 NVME_RW_DSM_COMPRESSED = 1 << 7,
582 NVME_RW_PRINFO_PRCHK_REF = 1 << 10,
583 NVME_RW_PRINFO_PRCHK_APP = 1 << 11,
584 NVME_RW_PRINFO_PRCHK_GUARD = 1 << 12,
585 NVME_RW_PRINFO_PRACT = 1 << 13,
f5d11840 586 NVME_RW_DTYPE_STREAMS = 1 << 4,
9d99a8dd
CH		 587};
588
589struct nvme_dsm_cmd {
590 __u8 opcode;
591 __u8 flags;
592 __u16 command_id;
593 __le32 nsid;
594 __u64 rsvd2[2];
eb793e2c 595 union nvme_data_ptr dptr;
9d99a8dd
CH		 596 __le32 nr;
597 __le32 attributes;
598 __u32 rsvd12[4];
599};
600
601enum {
602 NVME_DSMGMT_IDR = 1 << 0,
603 NVME_DSMGMT_IDW = 1 << 1,
604 NVME_DSMGMT_AD = 1 << 2,
605};
606
b35ba01e
CH		 607#define NVME_DSM_MAX_RANGES 256
608
9d99a8dd
CH		 609struct nvme_dsm_range {
610 __le32 cattr;
611 __le32 nlb;
612 __le64 slba;
613};
614
3b7c33b2
CK		 615struct nvme_write_zeroes_cmd {
616 __u8 opcode;
617 __u8 flags;
618 __u16 command_id;
619 __le32 nsid;
620 __u64 rsvd2;
621 __le64 metadata;
622 union nvme_data_ptr dptr;
623 __le64 slba;
624 __le16 length;
625 __le16 control;
626 __le32 dsmgmt;
627 __le32 reftag;
628 __le16 apptag;
629 __le16 appmask;
630};
631
c5552fde
AL		 632/* Features */
633
634struct nvme_feat_auto_pst {
635 __le64 entries[32];
636};
637
39673e19
CH		 638enum {
639 NVME_HOST_MEM_ENABLE = (1 << 0),
640 NVME_HOST_MEM_RETURN = (1 << 1),
641};
642
9d99a8dd
CH		 643/* Admin commands */
644
645enum nvme_admin_opcode {
646 nvme_admin_delete_sq = 0x00,
647 nvme_admin_create_sq = 0x01,
648 nvme_admin_get_log_page = 0x02,
649 nvme_admin_delete_cq = 0x04,
650 nvme_admin_create_cq = 0x05,
651 nvme_admin_identify = 0x06,
652 nvme_admin_abort_cmd = 0x08,
653 nvme_admin_set_features = 0x09,
654 nvme_admin_get_features = 0x0a,
655 nvme_admin_async_event = 0x0c,
a446c084 656 nvme_admin_ns_mgmt = 0x0d,
9d99a8dd
CH		 657 nvme_admin_activate_fw = 0x10,
658 nvme_admin_download_fw = 0x11,
a446c084 659 nvme_admin_ns_attach = 0x15,
7b89eae2 660 nvme_admin_keep_alive = 0x18,
f5d11840
JA		 661 nvme_admin_directive_send = 0x19,
662 nvme_admin_directive_recv = 0x1a,
f9f38e33 663 nvme_admin_dbbuf = 0x7C,
9d99a8dd
CH		 664 nvme_admin_format_nvm = 0x80,
665 nvme_admin_security_send = 0x81,
666 nvme_admin_security_recv = 0x82,
667};
668
669enum {
670 NVME_QUEUE_PHYS_CONTIG = (1 << 0),
671 NVME_CQ_IRQ_ENABLED = (1 << 1),
672 NVME_SQ_PRIO_URGENT = (0 << 1),
673 NVME_SQ_PRIO_HIGH = (1 << 1),
674 NVME_SQ_PRIO_MEDIUM = (2 << 1),
675 NVME_SQ_PRIO_LOW = (3 << 1),
676 NVME_FEAT_ARBITRATION = 0x01,
677 NVME_FEAT_POWER_MGMT = 0x02,
678 NVME_FEAT_LBA_RANGE = 0x03,
679 NVME_FEAT_TEMP_THRESH = 0x04,
680 NVME_FEAT_ERR_RECOVERY = 0x05,
681 NVME_FEAT_VOLATILE_WC = 0x06,
682 NVME_FEAT_NUM_QUEUES = 0x07,
683 NVME_FEAT_IRQ_COALESCE = 0x08,
684 NVME_FEAT_IRQ_CONFIG = 0x09,
685 NVME_FEAT_WRITE_ATOMIC = 0x0a,
686 NVME_FEAT_ASYNC_EVENT = 0x0b,
687 NVME_FEAT_AUTO_PST = 0x0c,
a446c084 688 NVME_FEAT_HOST_MEM_BUF = 0x0d,
7b89eae2 689 NVME_FEAT_KATO = 0x0f,
9d99a8dd
CH		 690 NVME_FEAT_SW_PROGRESS = 0x80,
691 NVME_FEAT_HOST_ID = 0x81,
692 NVME_FEAT_RESV_MASK = 0x82,
693 NVME_FEAT_RESV_PERSIST = 0x83,
694 NVME_LOG_ERROR = 0x01,
695 NVME_LOG_SMART = 0x02,
696 NVME_LOG_FW_SLOT = 0x03,
eb793e2c 697 NVME_LOG_DISC = 0x70,
9d99a8dd
CH		 698 NVME_LOG_RESERVATION = 0x80,
699 NVME_FWACT_REPL = (0 << 3),
700 NVME_FWACT_REPL_ACTV = (1 << 3),
701 NVME_FWACT_ACTV = (2 << 3),
702};
703
704struct nvme_identify {
705 __u8 opcode;
706 __u8 flags;
707 __u16 command_id;
708 __le32 nsid;
709 __u64 rsvd2[2];
eb793e2c 710 union nvme_data_ptr dptr;
986994a2
PP		 711 __u8 cns;
712 __u8 rsvd3;
713 __le16 ctrlid;
9d99a8dd
CH		 714 __u32 rsvd11[5];
715};
716
0add5e8e
JT		 717#define NVME_IDENTIFY_DATA_SIZE 4096
718
9d99a8dd
CH		 719struct nvme_features {
720 __u8 opcode;
721 __u8 flags;
722 __u16 command_id;
723 __le32 nsid;
724 __u64 rsvd2[2];
eb793e2c 725 union nvme_data_ptr dptr;
9d99a8dd
CH		 726 __le32 fid;
727 __le32 dword11;
b85cf734
AD		 728 __le32 dword12;
729 __le32 dword13;
730 __le32 dword14;
731 __le32 dword15;
9d99a8dd
CH		 732};
733
39673e19
CH		 734struct nvme_host_mem_buf_desc {
735 __le64 addr;
736 __le32 size;
737 __u32 rsvd;
738};
739
9d99a8dd
CH		 740struct nvme_create_cq {
741 __u8 opcode;
742 __u8 flags;
743 __u16 command_id;
744 __u32 rsvd1[5];
745 __le64 prp1;
746 __u64 rsvd8;
747 __le16 cqid;
748 __le16 qsize;
749 __le16 cq_flags;
750 __le16 irq_vector;
751 __u32 rsvd12[4];
752};
753
754struct nvme_create_sq {
755 __u8 opcode;
756 __u8 flags;
757 __u16 command_id;
758 __u32 rsvd1[5];
759 __le64 prp1;
760 __u64 rsvd8;
761 __le16 sqid;
762 __le16 qsize;
763 __le16 sq_flags;
764 __le16 cqid;
765 __u32 rsvd12[4];
766};
767
768struct nvme_delete_queue {
769 __u8 opcode;
770 __u8 flags;
771 __u16 command_id;
772 __u32 rsvd1[9];
773 __le16 qid;
774 __u16 rsvd10;
775 __u32 rsvd11[5];
776};
777
778struct nvme_abort_cmd {
779 __u8 opcode;
780 __u8 flags;
781 __u16 command_id;
782 __u32 rsvd1[9];
783 __le16 sqid;
784 __u16 cid;
785 __u32 rsvd11[5];
786};
787
788struct nvme_download_firmware {
789 __u8 opcode;
790 __u8 flags;
791 __u16 command_id;
792 __u32 rsvd1[5];
eb793e2c 793 union nvme_data_ptr dptr;
9d99a8dd
CH		 794 __le32 numd;
795 __le32 offset;
796 __u32 rsvd12[4];
797};
798
799struct nvme_format_cmd {
800 __u8 opcode;
801 __u8 flags;
802 __u16 command_id;
803 __le32 nsid;
804 __u64 rsvd2[4];
805 __le32 cdw10;
806 __u32 rsvd11[5];
807};
808
725b3588
AB		 809struct nvme_get_log_page_command {
810 __u8 opcode;
811 __u8 flags;
812 __u16 command_id;
813 __le32 nsid;
814 __u64 rsvd2[2];
eb793e2c 815 union nvme_data_ptr dptr;
725b3588
AB		 816 __u8 lid;
817 __u8 rsvd10;
818 __le16 numdl;
819 __le16 numdu;
820 __u16 rsvd11;
821 __le32 lpol;
822 __le32 lpou;
823 __u32 rsvd14[2];
824};
825
f5d11840
JA		 826struct nvme_directive_cmd {
827 __u8 opcode;
828 __u8 flags;
829 __u16 command_id;
830 __le32 nsid;
831 __u64 rsvd2[2];
832 union nvme_data_ptr dptr;
833 __le32 numd;
834 __u8 doper;
835 __u8 dtype;
836 __le16 dspec;
837 __u8 endir;
838 __u8 tdtype;
839 __u16 rsvd15;
840
841 __u32 rsvd16[3];
842};
843
eb793e2c
CH		 844/*
845 * Fabrics subcommands.
846 */
847enum nvmf_fabrics_opcode {
848 nvme_fabrics_command = 0x7f,
849};
850
851enum nvmf_capsule_command {
852 nvme_fabrics_type_property_set = 0x00,
853 nvme_fabrics_type_connect = 0x01,
854 nvme_fabrics_type_property_get = 0x04,
855};
856
857struct nvmf_common_command {
858 __u8 opcode;
859 __u8 resv1;
860 __u16 command_id;
861 __u8 fctype;
862 __u8 resv2[35];
863 __u8 ts[24];
864};
865
866/*
867 * The legal cntlid range a NVMe Target will provide.
868 * Note that cntlid of value 0 is considered illegal in the fabrics world.
869 * Devices based on earlier specs did not have the subsystem concept;
870 * therefore, those devices had their cntlid value set to 0 as a result.
871 */
872#define NVME_CNTLID_MIN 1
873#define NVME_CNTLID_MAX 0xffef
874#define NVME_CNTLID_DYNAMIC 0xffff
875
876#define MAX_DISC_LOGS 255
877
878/* Discovery log page entry */
879struct nvmf_disc_rsp_page_entry {
880 __u8 trtype;
881 __u8 adrfam;
a446c084 882 __u8 subtype;
eb793e2c
CH		 883 __u8 treq;
884 __le16 portid;
885 __le16 cntlid;
886 __le16 asqsz;
887 __u8 resv8[22];
888 char trsvcid[NVMF_TRSVCID_SIZE];
889 __u8 resv64[192];
890 char subnqn[NVMF_NQN_FIELD_LEN];
891 char traddr[NVMF_TRADDR_SIZE];
892 union tsas {
893 char common[NVMF_TSAS_SIZE];
894 struct rdma {
895 __u8 qptype;
896 __u8 prtype;
897 __u8 cms;
898 __u8 resv3[5];
899 __u16 pkey;
900 __u8 resv10[246];
901 } rdma;
902 } tsas;
903};
904
905/* Discovery log page header */
906struct nvmf_disc_rsp_page_hdr {
907 __le64 genctr;
908 __le64 numrec;
909 __le16 recfmt;
910 __u8 resv14[1006];
911 struct nvmf_disc_rsp_page_entry entries[0];
912};
913
914struct nvmf_connect_command {
915 __u8 opcode;
916 __u8 resv1;
917 __u16 command_id;
918 __u8 fctype;
919 __u8 resv2[19];
920 union nvme_data_ptr dptr;
921 __le16 recfmt;
922 __le16 qid;
923 __le16 sqsize;
924 __u8 cattr;
925 __u8 resv3;
926 __le32 kato;
927 __u8 resv4[12];
928};
929
930struct nvmf_connect_data {
8e412263 931 uuid_t hostid;
eb793e2c
CH		 932 __le16 cntlid;
933 char resv4[238];
934 char subsysnqn[NVMF_NQN_FIELD_LEN];
935 char hostnqn[NVMF_NQN_FIELD_LEN];
936 char resv5[256];
937};
938
939struct nvmf_property_set_command {
940 __u8 opcode;
941 __u8 resv1;
942 __u16 command_id;
943 __u8 fctype;
944 __u8 resv2[35];
945 __u8 attrib;
946 __u8 resv3[3];
947 __le32 offset;
948 __le64 value;
949 __u8 resv4[8];
950};
951
952struct nvmf_property_get_command {
953 __u8 opcode;
954 __u8 resv1;
955 __u16 command_id;
956 __u8 fctype;
957 __u8 resv2[35];
958 __u8 attrib;
959 __u8 resv3[3];
960 __le32 offset;
961 __u8 resv4[16];
962};
963
f9f38e33
HK		 964struct nvme_dbbuf {
965 __u8 opcode;
966 __u8 flags;
967 __u16 command_id;
968 __u32 rsvd1[5];
969 __le64 prp1;
970 __le64 prp2;
971 __u32 rsvd12[6];
972};
973
f5d11840 974struct streams_directive_params {
dc1a0afb
CH		 975 __le16 msl;
976 __le16 nssa;
977 __le16 nsso;
f5d11840 978 __u8 rsvd[10];
dc1a0afb
CH		 979 __le32 sws;
980 __le16 sgs;
981 __le16 nsa;
982 __le16 nso;
f5d11840
JA		 983 __u8 rsvd2[6];
984};
985
9d99a8dd
CH		 986struct nvme_command {
987 union {
988 struct nvme_common_command common;
989 struct nvme_rw_command rw;
990 struct nvme_identify identify;
991 struct nvme_features features;
992 struct nvme_create_cq create_cq;
993 struct nvme_create_sq create_sq;
994 struct nvme_delete_queue delete_queue;
995 struct nvme_download_firmware dlfw;
996 struct nvme_format_cmd format;
997 struct nvme_dsm_cmd dsm;
3b7c33b2 998 struct nvme_write_zeroes_cmd write_zeroes;
9d99a8dd 999 struct nvme_abort_cmd abort;
725b3588 1000 struct nvme_get_log_page_command get_log_page;
eb793e2c
CH		 1001 struct nvmf_common_command fabrics;
1002 struct nvmf_connect_command connect;
1003 struct nvmf_property_set_command prop_set;
1004 struct nvmf_property_get_command prop_get;
f9f38e33 1005 struct nvme_dbbuf dbbuf;
f5d11840 1006 struct nvme_directive_cmd directive;
9d99a8dd
CH		 1007 };
1008};
1009
7a5abb4b
CH		 1010static inline bool nvme_is_write(struct nvme_command *cmd)
1011{
eb793e2c
CH		 1012 /*
1013 * What a mess...
1014 *
1015 * Why can't we simply have a Fabrics In and Fabrics out command?
1016 */
1017 if (unlikely(cmd->common.opcode == nvme_fabrics_command))
2fd4167f 1018 return cmd->fabrics.fctype & 1;
7a5abb4b
CH		 1019 return cmd->common.opcode & 1;
1020}
1021
9d99a8dd 1022enum {
eb793e2c
CH		 1023 /*
1024 * Generic Command Status:
1025 */
9d99a8dd
CH		 1026 NVME_SC_SUCCESS = 0x0,
1027 NVME_SC_INVALID_OPCODE = 0x1,
1028 NVME_SC_INVALID_FIELD = 0x2,
1029 NVME_SC_CMDID_CONFLICT = 0x3,
1030 NVME_SC_DATA_XFER_ERROR = 0x4,
1031 NVME_SC_POWER_LOSS = 0x5,
1032 NVME_SC_INTERNAL = 0x6,
1033 NVME_SC_ABORT_REQ = 0x7,
1034 NVME_SC_ABORT_QUEUE = 0x8,
1035 NVME_SC_FUSED_FAIL = 0x9,
1036 NVME_SC_FUSED_MISSING = 0xa,
1037 NVME_SC_INVALID_NS = 0xb,
1038 NVME_SC_CMD_SEQ_ERROR = 0xc,
1039 NVME_SC_SGL_INVALID_LAST = 0xd,
1040 NVME_SC_SGL_INVALID_COUNT = 0xe,
1041 NVME_SC_SGL_INVALID_DATA = 0xf,
1042 NVME_SC_SGL_INVALID_METADATA = 0x10,
1043 NVME_SC_SGL_INVALID_TYPE = 0x11,
eb793e2c
CH		 1044
1045 NVME_SC_SGL_INVALID_OFFSET = 0x16,
1046 NVME_SC_SGL_INVALID_SUBTYPE = 0x17,
1047
9d99a8dd
CH		 1048 NVME_SC_LBA_RANGE = 0x80,
1049 NVME_SC_CAP_EXCEEDED = 0x81,
1050 NVME_SC_NS_NOT_READY = 0x82,
1051 NVME_SC_RESERVATION_CONFLICT = 0x83,
eb793e2c
CH		 1052
1053 /*
1054 * Command Specific Status:
1055 */
9d99a8dd
CH		 1056 NVME_SC_CQ_INVALID = 0x100,
1057 NVME_SC_QID_INVALID = 0x101,
1058 NVME_SC_QUEUE_SIZE = 0x102,
1059 NVME_SC_ABORT_LIMIT = 0x103,
1060 NVME_SC_ABORT_MISSING = 0x104,
1061 NVME_SC_ASYNC_LIMIT = 0x105,
1062 NVME_SC_FIRMWARE_SLOT = 0x106,
1063 NVME_SC_FIRMWARE_IMAGE = 0x107,
1064 NVME_SC_INVALID_VECTOR = 0x108,
1065 NVME_SC_INVALID_LOG_PAGE = 0x109,
1066 NVME_SC_INVALID_FORMAT = 0x10a,
a446c084 1067 NVME_SC_FW_NEEDS_CONV_RESET = 0x10b,
9d99a8dd
CH		 1068 NVME_SC_INVALID_QUEUE = 0x10c,
1069 NVME_SC_FEATURE_NOT_SAVEABLE = 0x10d,
1070 NVME_SC_FEATURE_NOT_CHANGEABLE = 0x10e,
1071 NVME_SC_FEATURE_NOT_PER_NS = 0x10f,
a446c084
CH		 1072 NVME_SC_FW_NEEDS_SUBSYS_RESET = 0x110,
1073 NVME_SC_FW_NEEDS_RESET = 0x111,
1074 NVME_SC_FW_NEEDS_MAX_TIME = 0x112,
1075 NVME_SC_FW_ACIVATE_PROHIBITED = 0x113,
1076 NVME_SC_OVERLAPPING_RANGE = 0x114,
1077 NVME_SC_NS_INSUFFICENT_CAP = 0x115,
1078 NVME_SC_NS_ID_UNAVAILABLE = 0x116,
1079 NVME_SC_NS_ALREADY_ATTACHED = 0x118,
1080 NVME_SC_NS_IS_PRIVATE = 0x119,
1081 NVME_SC_NS_NOT_ATTACHED = 0x11a,
1082 NVME_SC_THIN_PROV_NOT_SUPP = 0x11b,
1083 NVME_SC_CTRL_LIST_INVALID = 0x11c,
eb793e2c
CH		 1084
1085 /*
1086 * I/O Command Set Specific - NVM commands:
1087 */
9d99a8dd
CH		 1088 NVME_SC_BAD_ATTRIBUTES = 0x180,
1089 NVME_SC_INVALID_PI = 0x181,
1090 NVME_SC_READ_ONLY = 0x182,
3b7c33b2 1091 NVME_SC_ONCS_NOT_SUPPORTED = 0x183,
eb793e2c
CH		 1092
1093 /*
1094 * I/O Command Set Specific - Fabrics commands:
1095 */
1096 NVME_SC_CONNECT_FORMAT = 0x180,
1097 NVME_SC_CONNECT_CTRL_BUSY = 0x181,
1098 NVME_SC_CONNECT_INVALID_PARAM = 0x182,
1099 NVME_SC_CONNECT_RESTART_DISC = 0x183,
1100 NVME_SC_CONNECT_INVALID_HOST = 0x184,
1101
1102 NVME_SC_DISCOVERY_RESTART = 0x190,
1103 NVME_SC_AUTH_REQUIRED = 0x191,
1104
1105 /*
1106 * Media and Data Integrity Errors:
1107 */
9d99a8dd
CH		 1108 NVME_SC_WRITE_FAULT = 0x280,
1109 NVME_SC_READ_ERROR = 0x281,
1110 NVME_SC_GUARD_CHECK = 0x282,
1111 NVME_SC_APPTAG_CHECK = 0x283,
1112 NVME_SC_REFTAG_CHECK = 0x284,
1113 NVME_SC_COMPARE_FAILED = 0x285,
1114 NVME_SC_ACCESS_DENIED = 0x286,
a446c084 1115 NVME_SC_UNWRITTEN_BLOCK = 0x287,
eb793e2c 1116
9d99a8dd 1117 NVME_SC_DNR = 0x4000,
cba3bdfd
JS		 1118
1119
1120 /*
1121 * FC Transport-specific error status values for NVME commands
1122 *
1123 * Transport-specific status code values must be in the range 0xB0..0xBF
1124 */
1125
1126 /* Generic FC failure - catchall */
1127 NVME_SC_FC_TRANSPORT_ERROR = 0x00B0,
1128
1129 /* I/O failure due to FC ABTS'd */
1130 NVME_SC_FC_TRANSPORT_ABORTED = 0x00B1,
9d99a8dd
CH		 1131};
1132
1133struct nvme_completion {
eb793e2c
CH		 1134 /*
1135 * Used by Admin and Fabrics commands to return data:
1136 */
d49187e9
CH		 1137 union nvme_result {
1138 __le16 u16;
1139 __le32 u32;
1140 __le64 u64;
1141 } result;
9d99a8dd
CH		 1142 __le16 sq_head; /* how much of this queue may be reclaimed */
1143 __le16 sq_id; /* submission queue that generated this entry */
1144 __u16 command_id; /* of the command which completed */
1145 __le16 status; /* did the command fail, and if so, why? */
1146};
1147
8ef2074d
GKB		 1148#define NVME_VS(major, minor, tertiary) \
1149 (((major) << 16) | ((minor) << 8) | (tertiary))
9d99a8dd 1150
c61d788b
JT		 1151#define NVME_MAJOR(ver) ((ver) >> 16)
1152#define NVME_MINOR(ver) (((ver) >> 8) & 0xff)
1153#define NVME_TERTIARY(ver) ((ver) & 0xff)
1154
b60503ba 1155#endif /* _LINUX_NVME_H */
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