[mirror_ubuntu-artful-kernel.git] / include / linux / omap-dma.h

/*
 * OMAP DMA Engine support
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */
#ifndef __LINUX_OMAP_DMA_H
#define __LINUX_OMAP_DMA_H

struct dma_chan;

#if defined(CONFIG_DMA_OMAP) || defined(CONFIG_DMA_OMAP_MODULE)
bool omap_dma_filter_fn(struct dma_chan *, void *);
#else
static inline bool omap_dma_filter_fn(struct dma_chan *c, void *d)
{
	return false;
}
#endif

/*
 *  Legacy OMAP DMA handling defines and functions
 *
 *  NOTE: Do not use these any longer.
 *
 *  Use the generic dmaengine functions as defined in
 *  include/linux/dmaengine.h.
 *
 *  Copyright (C) 2003 Nokia Corporation
 *  Author: Juha Yrjölä <juha.yrjola@nokia.com>
 *
 */

#include <linux/platform_device.h>

#define INT_DMA_LCD			25

#define OMAP1_DMA_TOUT_IRQ		(1 << 0)
#define OMAP_DMA_DROP_IRQ		(1 << 1)
#define OMAP_DMA_HALF_IRQ		(1 << 2)
#define OMAP_DMA_FRAME_IRQ		(1 << 3)
#define OMAP_DMA_LAST_IRQ		(1 << 4)
#define OMAP_DMA_BLOCK_IRQ		(1 << 5)
#define OMAP1_DMA_SYNC_IRQ		(1 << 6)
#define OMAP2_DMA_PKT_IRQ		(1 << 7)
#define OMAP2_DMA_TRANS_ERR_IRQ		(1 << 8)
#define OMAP2_DMA_SECURE_ERR_IRQ	(1 << 9)
#define OMAP2_DMA_SUPERVISOR_ERR_IRQ	(1 << 10)
#define OMAP2_DMA_MISALIGNED_ERR_IRQ	(1 << 11)

#define OMAP_DMA_CCR_EN			(1 << 7)
#define OMAP_DMA_CCR_RD_ACTIVE		(1 << 9)
#define OMAP_DMA_CCR_WR_ACTIVE		(1 << 10)
#define OMAP_DMA_CCR_SEL_SRC_DST_SYNC	(1 << 24)
#define OMAP_DMA_CCR_BUFFERING_DISABLE	(1 << 25)

#define OMAP_DMA_DATA_TYPE_S8		0x00
#define OMAP_DMA_DATA_TYPE_S16		0x01
#define OMAP_DMA_DATA_TYPE_S32		0x02

#define OMAP_DMA_SYNC_ELEMENT		0x00
#define OMAP_DMA_SYNC_FRAME		0x01
#define OMAP_DMA_SYNC_BLOCK		0x02
#define OMAP_DMA_SYNC_PACKET		0x03

#define OMAP_DMA_DST_SYNC_PREFETCH	0x02
#define OMAP_DMA_SRC_SYNC		0x01
#define OMAP_DMA_DST_SYNC		0x00

#define OMAP_DMA_PORT_EMIFF		0x00
#define OMAP_DMA_PORT_EMIFS		0x01
#define OMAP_DMA_PORT_OCP_T1		0x02
#define OMAP_DMA_PORT_TIPB		0x03
#define OMAP_DMA_PORT_OCP_T2		0x04
#define OMAP_DMA_PORT_MPUI		0x05

#define OMAP_DMA_AMODE_CONSTANT		0x00
#define OMAP_DMA_AMODE_POST_INC		0x01
#define OMAP_DMA_AMODE_SINGLE_IDX	0x02
#define OMAP_DMA_AMODE_DOUBLE_IDX	0x03

#define DMA_DEFAULT_FIFO_DEPTH		0x10
#define DMA_DEFAULT_ARB_RATE		0x01
/* Pass THREAD_RESERVE ORed with THREAD_FIFO for tparams */
#define DMA_THREAD_RESERVE_NORM		(0x00 << 12) /* Def */
#define DMA_THREAD_RESERVE_ONET		(0x01 << 12)
#define DMA_THREAD_RESERVE_TWOT		(0x02 << 12)
#define DMA_THREAD_RESERVE_THREET	(0x03 << 12)
#define DMA_THREAD_FIFO_NONE		(0x00 << 14) /* Def */
#define DMA_THREAD_FIFO_75		(0x01 << 14)
#define DMA_THREAD_FIFO_25		(0x02 << 14)
#define DMA_THREAD_FIFO_50		(0x03 << 14)

/* DMA4_OCP_SYSCONFIG bits */
#define DMA_SYSCONFIG_MIDLEMODE_MASK		(3 << 12)
#define DMA_SYSCONFIG_CLOCKACTIVITY_MASK	(3 << 8)
#define DMA_SYSCONFIG_EMUFREE			(1 << 5)
#define DMA_SYSCONFIG_SIDLEMODE_MASK		(3 << 3)
#define DMA_SYSCONFIG_SOFTRESET			(1 << 2)
#define DMA_SYSCONFIG_AUTOIDLE			(1 << 0)

#define DMA_SYSCONFIG_MIDLEMODE(n)		((n) << 12)
#define DMA_SYSCONFIG_SIDLEMODE(n)		((n) << 3)

#define DMA_IDLEMODE_SMARTIDLE			0x2
#define DMA_IDLEMODE_NO_IDLE			0x1
#define DMA_IDLEMODE_FORCE_IDLE			0x0

/* Chaining modes*/
#ifndef CONFIG_ARCH_OMAP1
#define OMAP_DMA_STATIC_CHAIN		0x1
#define OMAP_DMA_DYNAMIC_CHAIN		0x2
#define OMAP_DMA_CHAIN_ACTIVE		0x1
#define OMAP_DMA_CHAIN_INACTIVE		0x0
#endif

#define DMA_CH_PRIO_HIGH		0x1
#define DMA_CH_PRIO_LOW			0x0 /* Def */

/* Errata handling */
#define IS_DMA_ERRATA(id)		(errata & (id))
#define SET_DMA_ERRATA(id)		(errata |= (id))

#define DMA_ERRATA_IFRAME_BUFFERING	BIT(0x0)
#define DMA_ERRATA_PARALLEL_CHANNELS	BIT(0x1)
#define DMA_ERRATA_i378			BIT(0x2)
#define DMA_ERRATA_i541			BIT(0x3)
#define DMA_ERRATA_i88			BIT(0x4)
#define DMA_ERRATA_3_3			BIT(0x5)
#define DMA_ROMCODE_BUG			BIT(0x6)

/* Attributes for OMAP DMA Contrller */
#define DMA_LINKED_LCH			BIT(0x0)
#define GLOBAL_PRIORITY			BIT(0x1)
#define RESERVE_CHANNEL			BIT(0x2)
#define IS_CSSA_32			BIT(0x3)
#define IS_CDSA_32			BIT(0x4)
#define IS_RW_PRIORITY			BIT(0x5)
#define ENABLE_1510_MODE		BIT(0x6)
#define SRC_PORT			BIT(0x7)
#define DST_PORT			BIT(0x8)
#define SRC_INDEX			BIT(0x9)
#define DST_INDEX			BIT(0xa)
#define IS_BURST_ONLY4			BIT(0xb)
#define CLEAR_CSR_ON_READ		BIT(0xc)
#define IS_WORD_16			BIT(0xd)
#define ENABLE_16XX_MODE		BIT(0xe)
#define HS_CHANNELS_RESERVED		BIT(0xf)

/* Defines for DMA Capabilities */
#define DMA_HAS_TRANSPARENT_CAPS	(0x1 << 18)
#define DMA_HAS_CONSTANT_FILL_CAPS	(0x1 << 19)
#define DMA_HAS_DESCRIPTOR_CAPS		(0x3 << 20)

enum omap_reg_offsets {

GCR,		GSCR,		GRST1,		HW_ID,
PCH2_ID,	PCH0_ID,	PCH1_ID,	PCHG_ID,
PCHD_ID,	CAPS_0,		CAPS_1,		CAPS_2,
CAPS_3,		CAPS_4,		PCH2_SR,	PCH0_SR,
PCH1_SR,	PCHD_SR,	REVISION,	IRQSTATUS_L0,
IRQSTATUS_L1,	IRQSTATUS_L2,	IRQSTATUS_L3,	IRQENABLE_L0,
IRQENABLE_L1,	IRQENABLE_L2,	IRQENABLE_L3,	SYSSTATUS,
OCP_SYSCONFIG,

/* omap1+ specific */
CPC, CCR2, LCH_CTRL,

/* Common registers for all omap's */
CSDP,		CCR,		CICR,		CSR,
CEN,		CFN,		CSFI,		CSEI,
CSAC,		CDAC,		CDEI,
CDFI,		CLNK_CTRL,

/* Channel specific registers */
CSSA,		CDSA,		COLOR,
CCEN,		CCFN,

/* omap3630 and omap4 specific */
CDP,		CNDP,		CCDN,

};

enum omap_dma_burst_mode {
	OMAP_DMA_DATA_BURST_DIS = 0,
	OMAP_DMA_DATA_BURST_4,
	OMAP_DMA_DATA_BURST_8,
	OMAP_DMA_DATA_BURST_16,
};

enum end_type {
	OMAP_DMA_LITTLE_ENDIAN = 0,
	OMAP_DMA_BIG_ENDIAN
};

enum omap_dma_color_mode {
	OMAP_DMA_COLOR_DIS = 0,
	OMAP_DMA_CONSTANT_FILL,
	OMAP_DMA_TRANSPARENT_COPY
};

enum omap_dma_write_mode {
	OMAP_DMA_WRITE_NON_POSTED = 0,
	OMAP_DMA_WRITE_POSTED,
	OMAP_DMA_WRITE_LAST_NON_POSTED
};

enum omap_dma_channel_mode {
	OMAP_DMA_LCH_2D = 0,
	OMAP_DMA_LCH_G,
	OMAP_DMA_LCH_P,
	OMAP_DMA_LCH_PD
};

struct omap_dma_channel_params {
	int data_type;		/* data type 8,16,32 */
	int elem_count;		/* number of elements in a frame */
	int frame_count;	/* number of frames in a element */

	int src_port;		/* Only on OMAP1 REVISIT: Is this needed? */
	int src_amode;		/* constant, post increment, indexed,
					double indexed */
	unsigned long src_start;	/* source address : physical */
	int src_ei;		/* source element index */
	int src_fi;		/* source frame index */

	int dst_port;		/* Only on OMAP1 REVISIT: Is this needed? */
	int dst_amode;		/* constant, post increment, indexed,
					double indexed */
	unsigned long dst_start;	/* source address : physical */
	int dst_ei;		/* source element index */
	int dst_fi;		/* source frame index */

	int trigger;		/* trigger attached if the channel is
					synchronized */
	int sync_mode;		/* sycn on element, frame , block or packet */
	int src_or_dst_synch;	/* source synch(1) or destination synch(0) */

	int ie;			/* interrupt enabled */

	unsigned char read_prio;/* read priority */
	unsigned char write_prio;/* write priority */

#ifndef CONFIG_ARCH_OMAP1
	enum omap_dma_burst_mode burst_mode; /* Burst mode 4/8/16 words */
#endif
};

struct omap_dma_lch {
	int next_lch;
	int dev_id;
	u16 saved_csr;
	u16 enabled_irqs;
	const char *dev_name;
	void (*callback)(int lch, u16 ch_status, void *data);
	void *data;
	long flags;
	/* required for Dynamic chaining */
	int prev_linked_ch;
	int next_linked_ch;
	int state;
	int chain_id;
	int status;
};

struct omap_dma_dev_attr {
	u32 dev_caps;
	u16 lch_count;
	u16 chan_count;
};

enum {
	OMAP_DMA_REG_NONE,
	OMAP_DMA_REG_16BIT,
	OMAP_DMA_REG_2X16BIT,
	OMAP_DMA_REG_32BIT,
};

struct omap_dma_reg {
	u16	offset;
	u8	stride;
	u8	type;
};

/* System DMA platform data structure */
struct omap_system_dma_plat_info {
	const struct omap_dma_reg *reg_map;
	unsigned channel_stride;
	struct omap_dma_dev_attr *dma_attr;
	u32 errata;
	void (*show_dma_caps)(void);
	void (*clear_lch_regs)(int lch);
	void (*clear_dma)(int lch);
	void (*dma_write)(u32 val, int reg, int lch);
	u32 (*dma_read)(int reg, int lch);
};

#ifdef CONFIG_ARCH_OMAP2PLUS
#define dma_omap2plus()	1
#else
#define dma_omap2plus()	0
#endif
#define dma_omap1()	(!dma_omap2plus())
#define __dma_omap15xx(d) (dma_omap1() && (d)->dev_caps & ENABLE_1510_MODE)
#define __dma_omap16xx(d) (dma_omap1() && (d)->dev_caps & ENABLE_16XX_MODE)
#define dma_omap15xx()	__dma_omap15xx(d)
#define dma_omap16xx()	__dma_omap16xx(d)

extern struct omap_system_dma_plat_info *omap_get_plat_info(void);

extern void omap_set_dma_priority(int lch, int dst_port, int priority);
extern int omap_request_dma(int dev_id, const char *dev_name,
			void (*callback)(int lch, u16 ch_status, void *data),
			void *data, int *dma_ch);
extern void omap_enable_dma_irq(int ch, u16 irq_bits);
extern void omap_disable_dma_irq(int ch, u16 irq_bits);
extern void omap_free_dma(int ch);
extern void omap_start_dma(int lch);
extern void omap_stop_dma(int lch);
extern void omap_set_dma_transfer_params(int lch, int data_type,
					 int elem_count, int frame_count,
					 int sync_mode,
					 int dma_trigger, int src_or_dst_synch);
extern void omap_set_dma_color_mode(int lch, enum omap_dma_color_mode mode,
				    u32 color);
extern void omap_set_dma_write_mode(int lch, enum omap_dma_write_mode mode);
extern void omap_set_dma_channel_mode(int lch, enum omap_dma_channel_mode mode);

extern void omap_set_dma_src_params(int lch, int src_port, int src_amode,
				    unsigned long src_start,
				    int src_ei, int src_fi);
extern void omap_set_dma_src_index(int lch, int eidx, int fidx);
extern void omap_set_dma_src_data_pack(int lch, int enable);
extern void omap_set_dma_src_burst_mode(int lch,
					enum omap_dma_burst_mode burst_mode);

extern void omap_set_dma_dest_params(int lch, int dest_port, int dest_amode,
				     unsigned long dest_start,
				     int dst_ei, int dst_fi);
extern void omap_set_dma_dest_index(int lch, int eidx, int fidx);
extern void omap_set_dma_dest_data_pack(int lch, int enable);
extern void omap_set_dma_dest_burst_mode(int lch,
					 enum omap_dma_burst_mode burst_mode);

extern void omap_set_dma_params(int lch,
				struct omap_dma_channel_params *params);

extern void omap_dma_link_lch(int lch_head, int lch_queue);
extern void omap_dma_unlink_lch(int lch_head, int lch_queue);

extern int omap_set_dma_callback(int lch,
			void (*callback)(int lch, u16 ch_status, void *data),
			void *data);
extern dma_addr_t omap_get_dma_src_pos(int lch);
extern dma_addr_t omap_get_dma_dst_pos(int lch);
extern void omap_clear_dma(int lch);
extern int omap_get_dma_active_status(int lch);
extern int omap_dma_running(void);
extern void omap_dma_set_global_params(int arb_rate, int max_fifo_depth,
				       int tparams);
extern int omap_dma_set_prio_lch(int lch, unsigned char read_prio,
				 unsigned char write_prio);
extern void omap_set_dma_dst_endian_type(int lch, enum end_type etype);
extern void omap_set_dma_src_endian_type(int lch, enum end_type etype);
extern int omap_get_dma_index(int lch, int *ei, int *fi);

void omap_dma_global_context_save(void);
void omap_dma_global_context_restore(void);

extern void omap_dma_disable_irq(int lch);

/* Chaining APIs */
#ifndef CONFIG_ARCH_OMAP1
extern int omap_request_dma_chain(int dev_id, const char *dev_name,
				  void (*callback) (int lch, u16 ch_status,
						    void *data),
				  int *chain_id, int no_of_chans,
				  int chain_mode,
				  struct omap_dma_channel_params params);
extern int omap_free_dma_chain(int chain_id);
extern int omap_dma_chain_a_transfer(int chain_id, int src_start,
				     int dest_start, int elem_count,
				     int frame_count, void *callbk_data);
extern int omap_start_dma_chain_transfers(int chain_id);
extern int omap_stop_dma_chain_transfers(int chain_id);
extern int omap_get_dma_chain_index(int chain_id, int *ei, int *fi);
extern int omap_get_dma_chain_dst_pos(int chain_id);
extern int omap_get_dma_chain_src_pos(int chain_id);

extern int omap_modify_dma_chain_params(int chain_id,
					struct omap_dma_channel_params params);
extern int omap_dma_chain_status(int chain_id);
#endif

#if defined(CONFIG_ARCH_OMAP1) && defined(CONFIG_FB_OMAP)
#include <mach/lcd_dma.h>
#else
static inline int omap_lcd_dma_running(void)
{
	return 0;
}
#endif

#endif /* __LINUX_OMAP_DMA_H */
Commit	Line	Data
7bedaa55 RK	1	/*
	2	* OMAP DMA Engine support
	3	*
	4	* This program is free software; you can redistribute it and/or modify
	5	* it under the terms of the GNU General Public License version 2 as
	6	* published by the Free Software Foundation.
	7	*/
	8	#ifndef __LINUX_OMAP_DMA_H
	9	#define __LINUX_OMAP_DMA_H
	10
	11	struct dma_chan;
	12
	13	#if defined(CONFIG_DMA_OMAP) \|\| defined(CONFIG_DMA_OMAP_MODULE)
	14	bool omap_dma_filter_fn(struct dma_chan , void );
	15	#else
	16	static inline bool omap_dma_filter_fn(struct dma_chan c, void d)
	17	{
	18	return false;
	19	}
	20	#endif
	21
45c3eb7d TL	22	/*
	23	* Legacy OMAP DMA handling defines and functions
	24	*
	25	* NOTE: Do not use these any longer.
	26	*
	27	* Use the generic dmaengine functions as defined in
	28	* include/linux/dmaengine.h.
	29	*
	30	* Copyright (C) 2003 Nokia Corporation
	31	* Author: Juha Yrjölä <juha.yrjola@nokia.com>
	32	*
	33	*/
	34
	35	#include <linux/platform_device.h>
	36
	37	#define INT_DMA_LCD 25
	38
	39	#define OMAP1_DMA_TOUT_IRQ (1 << 0)
	40	#define OMAP_DMA_DROP_IRQ (1 << 1)
	41	#define OMAP_DMA_HALF_IRQ (1 << 2)
	42	#define OMAP_DMA_FRAME_IRQ (1 << 3)
	43	#define OMAP_DMA_LAST_IRQ (1 << 4)
	44	#define OMAP_DMA_BLOCK_IRQ (1 << 5)
	45	#define OMAP1_DMA_SYNC_IRQ (1 << 6)
	46	#define OMAP2_DMA_PKT_IRQ (1 << 7)
	47	#define OMAP2_DMA_TRANS_ERR_IRQ (1 << 8)
	48	#define OMAP2_DMA_SECURE_ERR_IRQ (1 << 9)
	49	#define OMAP2_DMA_SUPERVISOR_ERR_IRQ (1 << 10)
	50	#define OMAP2_DMA_MISALIGNED_ERR_IRQ (1 << 11)
	51
	52	#define OMAP_DMA_CCR_EN (1 << 7)
	53	#define OMAP_DMA_CCR_RD_ACTIVE (1 << 9)
	54	#define OMAP_DMA_CCR_WR_ACTIVE (1 << 10)
	55	#define OMAP_DMA_CCR_SEL_SRC_DST_SYNC (1 << 24)
	56	#define OMAP_DMA_CCR_BUFFERING_DISABLE (1 << 25)
	57
	58	#define OMAP_DMA_DATA_TYPE_S8 0x00
	59	#define OMAP_DMA_DATA_TYPE_S16 0x01
	60	#define OMAP_DMA_DATA_TYPE_S32 0x02
	61
	62	#define OMAP_DMA_SYNC_ELEMENT 0x00
	63	#define OMAP_DMA_SYNC_FRAME 0x01
	64	#define OMAP_DMA_SYNC_BLOCK 0x02
	65	#define OMAP_DMA_SYNC_PACKET 0x03
	66
	67	#define OMAP_DMA_DST_SYNC_PREFETCH 0x02
	68	#define OMAP_DMA_SRC_SYNC 0x01
	69	#define OMAP_DMA_DST_SYNC 0x00
	70
	71	#define OMAP_DMA_PORT_EMIFF 0x00
	72	#define OMAP_DMA_PORT_EMIFS 0x01
	73	#define OMAP_DMA_PORT_OCP_T1 0x02
	74	#define OMAP_DMA_PORT_TIPB 0x03
	75	#define OMAP_DMA_PORT_OCP_T2 0x04
	76	#define OMAP_DMA_PORT_MPUI 0x05
	77
	78	#define OMAP_DMA_AMODE_CONSTANT 0x00
	79	#define OMAP_DMA_AMODE_POST_INC 0x01
	80	#define OMAP_DMA_AMODE_SINGLE_IDX 0x02
	81	#define OMAP_DMA_AMODE_DOUBLE_IDX 0x03
	82
	83	#define DMA_DEFAULT_FIFO_DEPTH 0x10
	84	#define DMA_DEFAULT_ARB_RATE 0x01
	85	/* Pass THREAD_RESERVE ORed with THREAD_FIFO for tparams */
86	#define DMA_THREAD_RESERVE_NORM (0x00 << 12) /* Def */
87	#define DMA_THREAD_RESERVE_ONET (0x01 << 12)
88	#define DMA_THREAD_RESERVE_TWOT (0x02 << 12)
89	#define DMA_THREAD_RESERVE_THREET (0x03 << 12)
90	#define DMA_THREAD_FIFO_NONE (0x00 << 14) /* Def */
91	#define DMA_THREAD_FIFO_75 (0x01 << 14)
92	#define DMA_THREAD_FIFO_25 (0x02 << 14)
93	#define DMA_THREAD_FIFO_50 (0x03 << 14)
94
95	/* DMA4_OCP_SYSCONFIG bits */
96	#define DMA_SYSCONFIG_MIDLEMODE_MASK (3 << 12)
97	#define DMA_SYSCONFIG_CLOCKACTIVITY_MASK (3 << 8)
98	#define DMA_SYSCONFIG_EMUFREE (1 << 5)
99	#define DMA_SYSCONFIG_SIDLEMODE_MASK (3 << 3)
100	#define DMA_SYSCONFIG_SOFTRESET (1 << 2)
101	#define DMA_SYSCONFIG_AUTOIDLE (1 << 0)
102
103	#define DMA_SYSCONFIG_MIDLEMODE(n) ((n) << 12)
104	#define DMA_SYSCONFIG_SIDLEMODE(n) ((n) << 3)
105
106	#define DMA_IDLEMODE_SMARTIDLE 0x2
107	#define DMA_IDLEMODE_NO_IDLE 0x1
108	#define DMA_IDLEMODE_FORCE_IDLE 0x0
109
110	/* Chaining modes*/
111	#ifndef CONFIG_ARCH_OMAP1
112	#define OMAP_DMA_STATIC_CHAIN 0x1
113	#define OMAP_DMA_DYNAMIC_CHAIN 0x2
114	#define OMAP_DMA_CHAIN_ACTIVE 0x1
115	#define OMAP_DMA_CHAIN_INACTIVE 0x0
116	#endif
117
118	#define DMA_CH_PRIO_HIGH 0x1
119	#define DMA_CH_PRIO_LOW 0x0 /* Def */
120
121	/* Errata handling */
122	#define IS_DMA_ERRATA(id) (errata & (id))
123	#define SET_DMA_ERRATA(id) (errata \|= (id))
124
125	#define DMA_ERRATA_IFRAME_BUFFERING BIT(0x0)
126	#define DMA_ERRATA_PARALLEL_CHANNELS BIT(0x1)
127	#define DMA_ERRATA_i378 BIT(0x2)
128	#define DMA_ERRATA_i541 BIT(0x3)
129	#define DMA_ERRATA_i88 BIT(0x4)
130	#define DMA_ERRATA_3_3 BIT(0x5)
131	#define DMA_ROMCODE_BUG BIT(0x6)
132
133	/* Attributes for OMAP DMA Contrller */
134	#define DMA_LINKED_LCH BIT(0x0)
135	#define GLOBAL_PRIORITY BIT(0x1)
136	#define RESERVE_CHANNEL BIT(0x2)
137	#define IS_CSSA_32 BIT(0x3)
138	#define IS_CDSA_32 BIT(0x4)
139	#define IS_RW_PRIORITY BIT(0x5)
140	#define ENABLE_1510_MODE BIT(0x6)
141	#define SRC_PORT BIT(0x7)
142	#define DST_PORT BIT(0x8)
143	#define SRC_INDEX BIT(0x9)
144	#define DST_INDEX BIT(0xa)
145	#define IS_BURST_ONLY4 BIT(0xb)
146	#define CLEAR_CSR_ON_READ BIT(0xc)
147	#define IS_WORD_16 BIT(0xd)
148	#define ENABLE_16XX_MODE BIT(0xe)
149	#define HS_CHANNELS_RESERVED BIT(0xf)
150
151	/* Defines for DMA Capabilities */
152	#define DMA_HAS_TRANSPARENT_CAPS (0x1 << 18)
153	#define DMA_HAS_CONSTANT_FILL_CAPS (0x1 << 19)
154	#define DMA_HAS_DESCRIPTOR_CAPS (0x3 << 20)
155
156	enum omap_reg_offsets {
157
158	GCR, GSCR, GRST1, HW_ID,
159	PCH2_ID, PCH0_ID, PCH1_ID, PCHG_ID,
160	PCHD_ID, CAPS_0, CAPS_1, CAPS_2,
161	CAPS_3, CAPS_4, PCH2_SR, PCH0_SR,
162	PCH1_SR, PCHD_SR, REVISION, IRQSTATUS_L0,
163	IRQSTATUS_L1, IRQSTATUS_L2, IRQSTATUS_L3, IRQENABLE_L0,
164	IRQENABLE_L1, IRQENABLE_L2, IRQENABLE_L3, SYSSTATUS,
165	OCP_SYSCONFIG,
166
167	/* omap1+ specific */
168	CPC, CCR2, LCH_CTRL,
169
170	/* Common registers for all omap's */
171	CSDP, CCR, CICR, CSR,
172	CEN, CFN, CSFI, CSEI,
173	CSAC, CDAC, CDEI,
174	CDFI, CLNK_CTRL,
175
176	/* Channel specific registers */
177	CSSA, CDSA, COLOR,
178	CCEN, CCFN,
179
180	/* omap3630 and omap4 specific */
181	CDP, CNDP, CCDN,
182
183	};
184
185	enum omap_dma_burst_mode {
186	OMAP_DMA_DATA_BURST_DIS = 0,
187	OMAP_DMA_DATA_BURST_4,
188	OMAP_DMA_DATA_BURST_8,
189	OMAP_DMA_DATA_BURST_16,
190	};
191
192	enum end_type {
193	OMAP_DMA_LITTLE_ENDIAN = 0,
194	OMAP_DMA_BIG_ENDIAN
195	};
196
197	enum omap_dma_color_mode {
198	OMAP_DMA_COLOR_DIS = 0,
199	OMAP_DMA_CONSTANT_FILL,
200	OMAP_DMA_TRANSPARENT_COPY
201	};
202
203	enum omap_dma_write_mode {
204	OMAP_DMA_WRITE_NON_POSTED = 0,
205	OMAP_DMA_WRITE_POSTED,
206	OMAP_DMA_WRITE_LAST_NON_POSTED
207	};
208
209	enum omap_dma_channel_mode {
210	OMAP_DMA_LCH_2D = 0,
211	OMAP_DMA_LCH_G,
212	OMAP_DMA_LCH_P,
213	OMAP_DMA_LCH_PD
214	};
215
216	struct omap_dma_channel_params {
217	int data_type; /* data type 8,16,32 */
218	int elem_count; /* number of elements in a frame */
219	int frame_count; /* number of frames in a element */
220
221	int src_port; /* Only on OMAP1 REVISIT: Is this needed? */
222	int src_amode; /* constant, post increment, indexed,
223	double indexed */
224	unsigned long src_start; /* source address : physical */
225	int src_ei; /* source element index */
226	int src_fi; /* source frame index */
227
228	int dst_port; /* Only on OMAP1 REVISIT: Is this needed? */
229	int dst_amode; /* constant, post increment, indexed,
230	double indexed */
231	unsigned long dst_start; /* source address : physical */
232	int dst_ei; /* source element index */
233	int dst_fi; /* source frame index */
234
235	int trigger; /* trigger attached if the channel is
236	synchronized */
237	int sync_mode; /* sycn on element, frame , block or packet */
238	int src_or_dst_synch; /* source synch(1) or destination synch(0) */
239
240	int ie; /* interrupt enabled */
241
242	unsigned char read_prio;/* read priority */
243	unsigned char write_prio;/* write priority */
244
245	#ifndef CONFIG_ARCH_OMAP1
246	enum omap_dma_burst_mode burst_mode; /* Burst mode 4/8/16 words */
247	#endif
248	};
249
250	struct omap_dma_lch {
251	int next_lch;
252	int dev_id;
253	u16 saved_csr;
254	u16 enabled_irqs;
255	const char *dev_name;
256	void (callback)(int lch, u16 ch_status, void data);
257	void *data;
258	long flags;
259	/* required for Dynamic chaining */
260	int prev_linked_ch;
261	int next_linked_ch;
262	int state;
263	int chain_id;
264	int status;
265	};
266
267	struct omap_dma_dev_attr {
268	u32 dev_caps;
269	u16 lch_count;
270	u16 chan_count;
45c3eb7d TL	271	};
45c3eb7d TL	272
64a2dc3d RK	273	enum {
	274	OMAP_DMA_REG_NONE,
	275	OMAP_DMA_REG_16BIT,
	276	OMAP_DMA_REG_2X16BIT,
	277	OMAP_DMA_REG_32BIT,
	278	};
	279
	280	struct omap_dma_reg {
	281	u16 offset;
	282	u8 stride;
	283	u8 type;
	284	};
	285
45c3eb7d TL	286	/* System DMA platform data structure */
45c3eb7d TL	287	struct omap_system_dma_plat_info {
596c471b RK	288	const struct omap_dma_reg *reg_map;
596c471b RK	289	unsigned channel_stride;
45c3eb7d TL	290	struct omap_dma_dev_attr *dma_attr;
45c3eb7d TL	291	u32 errata;
45c3eb7d TL	292	void (*show_dma_caps)(void);
	293	void (*clear_lch_regs)(int lch);
	294	void (*clear_dma)(int lch);
	295	void (*dma_write)(u32 val, int reg, int lch);
	296	u32 (*dma_read)(int reg, int lch);
	297	};
	298
	299	#ifdef CONFIG_ARCH_OMAP2PLUS
	300	#define dma_omap2plus() 1
	301	#else
	302	#define dma_omap2plus() 0
7bedaa55	303	#endif
45c3eb7d	304	#define dma_omap1() (!dma_omap2plus())
b9e97822 RK	305	#define __dma_omap15xx(d) (dma_omap1() && (d)->dev_caps & ENABLE_1510_MODE)
	306	#define __dma_omap16xx(d) (dma_omap1() && (d)->dev_caps & ENABLE_16XX_MODE)
	307	#define dma_omap15xx() __dma_omap15xx(d)
	308	#define dma_omap16xx() __dma_omap16xx(d)
45c3eb7d	309
1b416c4b RK	310	extern struct omap_system_dma_plat_info *omap_get_plat_info(void);
1b416c4b RK	311
45c3eb7d TL	312	extern void omap_set_dma_priority(int lch, int dst_port, int priority);
	313	extern int omap_request_dma(int dev_id, const char *dev_name,
	314	void (callback)(int lch, u16 ch_status, void data),
	315	void data, int dma_ch);
	316	extern void omap_enable_dma_irq(int ch, u16 irq_bits);
	317	extern void omap_disable_dma_irq(int ch, u16 irq_bits);
	318	extern void omap_free_dma(int ch);
	319	extern void omap_start_dma(int lch);
	320	extern void omap_stop_dma(int lch);
	321	extern void omap_set_dma_transfer_params(int lch, int data_type,
	322	int elem_count, int frame_count,
	323	int sync_mode,
	324	int dma_trigger, int src_or_dst_synch);
	325	extern void omap_set_dma_color_mode(int lch, enum omap_dma_color_mode mode,
	326	u32 color);
	327	extern void omap_set_dma_write_mode(int lch, enum omap_dma_write_mode mode);
	328	extern void omap_set_dma_channel_mode(int lch, enum omap_dma_channel_mode mode);
	329
	330	extern void omap_set_dma_src_params(int lch, int src_port, int src_amode,
	331	unsigned long src_start,
	332	int src_ei, int src_fi);
	333	extern void omap_set_dma_src_index(int lch, int eidx, int fidx);
	334	extern void omap_set_dma_src_data_pack(int lch, int enable);
	335	extern void omap_set_dma_src_burst_mode(int lch,
	336	enum omap_dma_burst_mode burst_mode);
	337
	338	extern void omap_set_dma_dest_params(int lch, int dest_port, int dest_amode,
	339	unsigned long dest_start,
	340	int dst_ei, int dst_fi);
	341	extern void omap_set_dma_dest_index(int lch, int eidx, int fidx);
	342	extern void omap_set_dma_dest_data_pack(int lch, int enable);
	343	extern void omap_set_dma_dest_burst_mode(int lch,
	344	enum omap_dma_burst_mode burst_mode);
	345
	346	extern void omap_set_dma_params(int lch,
	347	struct omap_dma_channel_params *params);
	348
	349	extern void omap_dma_link_lch(int lch_head, int lch_queue);
	350	extern void omap_dma_unlink_lch(int lch_head, int lch_queue);
	351
	352	extern int omap_set_dma_callback(int lch,
	353	void (callback)(int lch, u16 ch_status, void data),
	354	void *data);
	355	extern dma_addr_t omap_get_dma_src_pos(int lch);
	356	extern dma_addr_t omap_get_dma_dst_pos(int lch);
	357	extern void omap_clear_dma(int lch);
	358	extern int omap_get_dma_active_status(int lch);
	359	extern int omap_dma_running(void);
	360	extern void omap_dma_set_global_params(int arb_rate, int max_fifo_depth,
	361	int tparams);
	362	extern int omap_dma_set_prio_lch(int lch, unsigned char read_prio,
	363	unsigned char write_prio);
	364	extern void omap_set_dma_dst_endian_type(int lch, enum end_type etype);
	365	extern void omap_set_dma_src_endian_type(int lch, enum end_type etype);
	366	extern int omap_get_dma_index(int lch, int ei, int fi);
	367
	368	void omap_dma_global_context_save(void);
	369	void omap_dma_global_context_restore(void);
	370
	371	extern void omap_dma_disable_irq(int lch);
	372
	373	/* Chaining APIs */
	374	#ifndef CONFIG_ARCH_OMAP1
	375	extern int omap_request_dma_chain(int dev_id, const char *dev_name,
376	void (*callback) (int lch, u16 ch_status,
377	void *data),
378	int *chain_id, int no_of_chans,
379	int chain_mode,
380	struct omap_dma_channel_params params);
381	extern int omap_free_dma_chain(int chain_id);
382	extern int omap_dma_chain_a_transfer(int chain_id, int src_start,
383	int dest_start, int elem_count,
384	int frame_count, void *callbk_data);
385	extern int omap_start_dma_chain_transfers(int chain_id);
386	extern int omap_stop_dma_chain_transfers(int chain_id);
387	extern int omap_get_dma_chain_index(int chain_id, int ei, int fi);
388	extern int omap_get_dma_chain_dst_pos(int chain_id);
389	extern int omap_get_dma_chain_src_pos(int chain_id);
390
391	extern int omap_modify_dma_chain_params(int chain_id,
392	struct omap_dma_channel_params params);
393	extern int omap_dma_chain_status(int chain_id);
394	#endif
395
396	#if defined(CONFIG_ARCH_OMAP1) && defined(CONFIG_FB_OMAP)
397	#include <mach/lcd_dma.h>
398	#else
399	static inline int omap_lcd_dma_running(void)
400	{
401	return 0;
402	}
403	#endif
404
405	#endif /* __LINUX_OMAP_DMA_H */