[mirror_ubuntu-bionic-kernel.git] / include / linux / omap-dma.h

/* SPDX-License-Identifier: GPL-2.0 */
#ifndef __LINUX_OMAP_DMA_H
#define __LINUX_OMAP_DMA_H
#include <linux/omap-dmaengine.h>

/*
 *  Legacy OMAP DMA handling defines and functions
 *
 *  NOTE: Do not use these any longer.
 *
 *  Use the generic dmaengine functions as defined in
 *  include/linux/dmaengine.h.
 *
 *  Copyright (C) 2003 Nokia Corporation
 *  Author: Juha Yrjölä <juha.yrjola@nokia.com>
 *
 */

#include <linux/platform_device.h>

#define INT_DMA_LCD			(NR_IRQS_LEGACY + 25)

#define OMAP1_DMA_TOUT_IRQ		(1 << 0)
#define OMAP_DMA_DROP_IRQ		(1 << 1)
#define OMAP_DMA_HALF_IRQ		(1 << 2)
#define OMAP_DMA_FRAME_IRQ		(1 << 3)
#define OMAP_DMA_LAST_IRQ		(1 << 4)
#define OMAP_DMA_BLOCK_IRQ		(1 << 5)
#define OMAP1_DMA_SYNC_IRQ		(1 << 6)
#define OMAP2_DMA_PKT_IRQ		(1 << 7)
#define OMAP2_DMA_TRANS_ERR_IRQ		(1 << 8)
#define OMAP2_DMA_SECURE_ERR_IRQ	(1 << 9)
#define OMAP2_DMA_SUPERVISOR_ERR_IRQ	(1 << 10)
#define OMAP2_DMA_MISALIGNED_ERR_IRQ	(1 << 11)

#define OMAP_DMA_CCR_EN			(1 << 7)
#define OMAP_DMA_CCR_RD_ACTIVE		(1 << 9)
#define OMAP_DMA_CCR_WR_ACTIVE		(1 << 10)
#define OMAP_DMA_CCR_SEL_SRC_DST_SYNC	(1 << 24)
#define OMAP_DMA_CCR_BUFFERING_DISABLE	(1 << 25)

#define OMAP_DMA_DATA_TYPE_S8		0x00
#define OMAP_DMA_DATA_TYPE_S16		0x01
#define OMAP_DMA_DATA_TYPE_S32		0x02

#define OMAP_DMA_SYNC_ELEMENT		0x00
#define OMAP_DMA_SYNC_FRAME		0x01
#define OMAP_DMA_SYNC_BLOCK		0x02
#define OMAP_DMA_SYNC_PACKET		0x03

#define OMAP_DMA_DST_SYNC_PREFETCH	0x02
#define OMAP_DMA_SRC_SYNC		0x01
#define OMAP_DMA_DST_SYNC		0x00

#define OMAP_DMA_PORT_EMIFF		0x00
#define OMAP_DMA_PORT_EMIFS		0x01
#define OMAP_DMA_PORT_OCP_T1		0x02
#define OMAP_DMA_PORT_TIPB		0x03
#define OMAP_DMA_PORT_OCP_T2		0x04
#define OMAP_DMA_PORT_MPUI		0x05

#define OMAP_DMA_AMODE_CONSTANT		0x00
#define OMAP_DMA_AMODE_POST_INC		0x01
#define OMAP_DMA_AMODE_SINGLE_IDX	0x02
#define OMAP_DMA_AMODE_DOUBLE_IDX	0x03

#define DMA_DEFAULT_FIFO_DEPTH		0x10
#define DMA_DEFAULT_ARB_RATE		0x01
/* Pass THREAD_RESERVE ORed with THREAD_FIFO for tparams */
#define DMA_THREAD_RESERVE_NORM		(0x00 << 12) /* Def */
#define DMA_THREAD_RESERVE_ONET		(0x01 << 12)
#define DMA_THREAD_RESERVE_TWOT		(0x02 << 12)
#define DMA_THREAD_RESERVE_THREET	(0x03 << 12)
#define DMA_THREAD_FIFO_NONE		(0x00 << 14) /* Def */
#define DMA_THREAD_FIFO_75		(0x01 << 14)
#define DMA_THREAD_FIFO_25		(0x02 << 14)
#define DMA_THREAD_FIFO_50		(0x03 << 14)

/* DMA4_OCP_SYSCONFIG bits */
#define DMA_SYSCONFIG_MIDLEMODE_MASK		(3 << 12)
#define DMA_SYSCONFIG_CLOCKACTIVITY_MASK	(3 << 8)
#define DMA_SYSCONFIG_EMUFREE			(1 << 5)
#define DMA_SYSCONFIG_SIDLEMODE_MASK		(3 << 3)
#define DMA_SYSCONFIG_SOFTRESET			(1 << 2)
#define DMA_SYSCONFIG_AUTOIDLE			(1 << 0)

#define DMA_SYSCONFIG_MIDLEMODE(n)		((n) << 12)
#define DMA_SYSCONFIG_SIDLEMODE(n)		((n) << 3)

#define DMA_IDLEMODE_SMARTIDLE			0x2
#define DMA_IDLEMODE_NO_IDLE			0x1
#define DMA_IDLEMODE_FORCE_IDLE			0x0

/* Chaining modes*/
#ifndef CONFIG_ARCH_OMAP1
#define OMAP_DMA_STATIC_CHAIN		0x1
#define OMAP_DMA_DYNAMIC_CHAIN		0x2
#define OMAP_DMA_CHAIN_ACTIVE		0x1
#define OMAP_DMA_CHAIN_INACTIVE		0x0
#endif

#define DMA_CH_PRIO_HIGH		0x1
#define DMA_CH_PRIO_LOW			0x0 /* Def */

/* Errata handling */
#define IS_DMA_ERRATA(id)		(errata & (id))
#define SET_DMA_ERRATA(id)		(errata |= (id))

#define DMA_ERRATA_IFRAME_BUFFERING	BIT(0x0)
#define DMA_ERRATA_PARALLEL_CHANNELS	BIT(0x1)
#define DMA_ERRATA_i378			BIT(0x2)
#define DMA_ERRATA_i541			BIT(0x3)
#define DMA_ERRATA_i88			BIT(0x4)
#define DMA_ERRATA_3_3			BIT(0x5)
#define DMA_ROMCODE_BUG			BIT(0x6)

/* Attributes for OMAP DMA Contrller */
#define DMA_LINKED_LCH			BIT(0x0)
#define GLOBAL_PRIORITY			BIT(0x1)
#define RESERVE_CHANNEL			BIT(0x2)
#define IS_CSSA_32			BIT(0x3)
#define IS_CDSA_32			BIT(0x4)
#define IS_RW_PRIORITY			BIT(0x5)
#define ENABLE_1510_MODE		BIT(0x6)
#define SRC_PORT			BIT(0x7)
#define DST_PORT			BIT(0x8)
#define SRC_INDEX			BIT(0x9)
#define DST_INDEX			BIT(0xa)
#define IS_BURST_ONLY4			BIT(0xb)
#define CLEAR_CSR_ON_READ		BIT(0xc)
#define IS_WORD_16			BIT(0xd)
#define ENABLE_16XX_MODE		BIT(0xe)
#define HS_CHANNELS_RESERVED		BIT(0xf)
#define DMA_ENGINE_HANDLE_IRQ		BIT(0x10)

/* Defines for DMA Capabilities */
#define DMA_HAS_TRANSPARENT_CAPS	(0x1 << 18)
#define DMA_HAS_CONSTANT_FILL_CAPS	(0x1 << 19)
#define DMA_HAS_DESCRIPTOR_CAPS		(0x3 << 20)

enum omap_reg_offsets {

GCR,		GSCR,		GRST1,		HW_ID,
PCH2_ID,	PCH0_ID,	PCH1_ID,	PCHG_ID,
PCHD_ID,	CAPS_0,		CAPS_1,		CAPS_2,
CAPS_3,		CAPS_4,		PCH2_SR,	PCH0_SR,
PCH1_SR,	PCHD_SR,	REVISION,	IRQSTATUS_L0,
IRQSTATUS_L1,	IRQSTATUS_L2,	IRQSTATUS_L3,	IRQENABLE_L0,
IRQENABLE_L1,	IRQENABLE_L2,	IRQENABLE_L3,	SYSSTATUS,
OCP_SYSCONFIG,

/* omap1+ specific */
CPC, CCR2, LCH_CTRL,

/* Common registers for all omap's */
CSDP,		CCR,		CICR,		CSR,
CEN,		CFN,		CSFI,		CSEI,
CSAC,		CDAC,		CDEI,
CDFI,		CLNK_CTRL,

/* Channel specific registers */
CSSA,		CDSA,		COLOR,
CCEN,		CCFN,

/* omap3630 and omap4 specific */
CDP,		CNDP,		CCDN,

};

enum omap_dma_burst_mode {
	OMAP_DMA_DATA_BURST_DIS = 0,
	OMAP_DMA_DATA_BURST_4,
	OMAP_DMA_DATA_BURST_8,
	OMAP_DMA_DATA_BURST_16,
};

enum end_type {
	OMAP_DMA_LITTLE_ENDIAN = 0,
	OMAP_DMA_BIG_ENDIAN
};

enum omap_dma_color_mode {
	OMAP_DMA_COLOR_DIS = 0,
	OMAP_DMA_CONSTANT_FILL,
	OMAP_DMA_TRANSPARENT_COPY
};

enum omap_dma_write_mode {
	OMAP_DMA_WRITE_NON_POSTED = 0,
	OMAP_DMA_WRITE_POSTED,
	OMAP_DMA_WRITE_LAST_NON_POSTED
};

enum omap_dma_channel_mode {
	OMAP_DMA_LCH_2D = 0,
	OMAP_DMA_LCH_G,
	OMAP_DMA_LCH_P,
	OMAP_DMA_LCH_PD
};

struct omap_dma_channel_params {
	int data_type;		/* data type 8,16,32 */
	int elem_count;		/* number of elements in a frame */
	int frame_count;	/* number of frames in a element */

	int src_port;		/* Only on OMAP1 REVISIT: Is this needed? */
	int src_amode;		/* constant, post increment, indexed,
					double indexed */
	unsigned long src_start;	/* source address : physical */
	int src_ei;		/* source element index */
	int src_fi;		/* source frame index */

	int dst_port;		/* Only on OMAP1 REVISIT: Is this needed? */
	int dst_amode;		/* constant, post increment, indexed,
					double indexed */
	unsigned long dst_start;	/* source address : physical */
	int dst_ei;		/* source element index */
	int dst_fi;		/* source frame index */

	int trigger;		/* trigger attached if the channel is
					synchronized */
	int sync_mode;		/* sycn on element, frame , block or packet */
	int src_or_dst_synch;	/* source synch(1) or destination synch(0) */

	int ie;			/* interrupt enabled */

	unsigned char read_prio;/* read priority */
	unsigned char write_prio;/* write priority */

#ifndef CONFIG_ARCH_OMAP1
	enum omap_dma_burst_mode burst_mode; /* Burst mode 4/8/16 words */
#endif
};

struct omap_dma_lch {
	int next_lch;
	int dev_id;
	u16 saved_csr;
	u16 enabled_irqs;
	const char *dev_name;
	void (*callback)(int lch, u16 ch_status, void *data);
	void *data;
	long flags;
	/* required for Dynamic chaining */
	int prev_linked_ch;
	int next_linked_ch;
	int state;
	int chain_id;
	int status;
};

struct omap_dma_dev_attr {
	u32 dev_caps;
	u16 lch_count;
	u16 chan_count;
};

enum {
	OMAP_DMA_REG_NONE,
	OMAP_DMA_REG_16BIT,
	OMAP_DMA_REG_2X16BIT,
	OMAP_DMA_REG_32BIT,
};

struct omap_dma_reg {
	u16	offset;
	u8	stride;
	u8	type;
};

#define SDMA_FILTER_PARAM(hw_req)	((int[]) { (hw_req) })
struct dma_slave_map;

/* System DMA platform data structure */
struct omap_system_dma_plat_info {
	const struct omap_dma_reg *reg_map;
	unsigned channel_stride;
	struct omap_dma_dev_attr *dma_attr;
	u32 errata;
	void (*show_dma_caps)(void);
	void (*clear_lch_regs)(int lch);
	void (*clear_dma)(int lch);
	void (*dma_write)(u32 val, int reg, int lch);
	u32 (*dma_read)(int reg, int lch);

	const struct dma_slave_map *slave_map;
	int slavecnt;
};

#ifdef CONFIG_ARCH_OMAP2PLUS
#define dma_omap2plus()	1
#else
#define dma_omap2plus()	0
#endif
#define dma_omap1()	(!dma_omap2plus())
#define __dma_omap15xx(d) (dma_omap1() && (d)->dev_caps & ENABLE_1510_MODE)
#define __dma_omap16xx(d) (dma_omap1() && (d)->dev_caps & ENABLE_16XX_MODE)
#define dma_omap15xx()	__dma_omap15xx(d)
#define dma_omap16xx()	__dma_omap16xx(d)

#if defined(CONFIG_ARCH_OMAP)
extern struct omap_system_dma_plat_info *omap_get_plat_info(void);

extern void omap_set_dma_priority(int lch, int dst_port, int priority);
extern int omap_request_dma(int dev_id, const char *dev_name,
			void (*callback)(int lch, u16 ch_status, void *data),
			void *data, int *dma_ch);
extern void omap_enable_dma_irq(int ch, u16 irq_bits);
extern void omap_disable_dma_irq(int ch, u16 irq_bits);
extern void omap_free_dma(int ch);
extern void omap_start_dma(int lch);
extern void omap_stop_dma(int lch);
extern void omap_set_dma_transfer_params(int lch, int data_type,
					 int elem_count, int frame_count,
					 int sync_mode,
					 int dma_trigger, int src_or_dst_synch);
extern void omap_set_dma_write_mode(int lch, enum omap_dma_write_mode mode);
extern void omap_set_dma_channel_mode(int lch, enum omap_dma_channel_mode mode);

extern void omap_set_dma_src_params(int lch, int src_port, int src_amode,
				    unsigned long src_start,
				    int src_ei, int src_fi);
extern void omap_set_dma_src_data_pack(int lch, int enable);
extern void omap_set_dma_src_burst_mode(int lch,
					enum omap_dma_burst_mode burst_mode);

extern void omap_set_dma_dest_params(int lch, int dest_port, int dest_amode,
				     unsigned long dest_start,
				     int dst_ei, int dst_fi);
extern void omap_set_dma_dest_data_pack(int lch, int enable);
extern void omap_set_dma_dest_burst_mode(int lch,
					 enum omap_dma_burst_mode burst_mode);

extern void omap_set_dma_params(int lch,
				struct omap_dma_channel_params *params);

extern void omap_dma_link_lch(int lch_head, int lch_queue);

extern int omap_set_dma_callback(int lch,
			void (*callback)(int lch, u16 ch_status, void *data),
			void *data);
extern dma_addr_t omap_get_dma_src_pos(int lch);
extern dma_addr_t omap_get_dma_dst_pos(int lch);
extern int omap_get_dma_active_status(int lch);
extern int omap_dma_running(void);
extern void omap_dma_set_global_params(int arb_rate, int max_fifo_depth,
				       int tparams);
void omap_dma_global_context_save(void);
void omap_dma_global_context_restore(void);

#if defined(CONFIG_ARCH_OMAP1) && IS_ENABLED(CONFIG_FB_OMAP)
#include <mach/lcd_dma.h>
#else
static inline int omap_lcd_dma_running(void)
{
	return 0;
}
#endif

#else /* CONFIG_ARCH_OMAP */

static inline struct omap_system_dma_plat_info *omap_get_plat_info(void)
{
	return NULL;
}

static inline int omap_request_dma(int dev_id, const char *dev_name,
			void (*callback)(int lch, u16 ch_status, void *data),
			void *data, int *dma_ch)
{
	return -ENODEV;
}

static inline void omap_free_dma(int ch) { }

#endif /* CONFIG_ARCH_OMAP */

#endif /* __LINUX_OMAP_DMA_H */
Commit	Line	Data
b2441318	1	/* SPDX-License-Identifier: GPL-2.0 */
7bedaa55 RK	2	#ifndef __LINUX_OMAP_DMA_H
7bedaa55 RK	3	#define __LINUX_OMAP_DMA_H
ee526d51	4	#include <linux/omap-dmaengine.h>
7bedaa55	5
45c3eb7d TL	6	/*
	7	* Legacy OMAP DMA handling defines and functions
	8	*
	9	* NOTE: Do not use these any longer.
	10	*
	11	* Use the generic dmaengine functions as defined in
	12	* include/linux/dmaengine.h.
	13	*
	14	* Copyright (C) 2003 Nokia Corporation
	15	* Author: Juha Yrjölä <juha.yrjola@nokia.com>
	16	*
	17	*/
	18
	19	#include <linux/platform_device.h>
	20
1bd5dfe4	21	#define INT_DMA_LCD (NR_IRQS_LEGACY + 25)
45c3eb7d TL	22
	23	#define OMAP1_DMA_TOUT_IRQ (1 << 0)
	24	#define OMAP_DMA_DROP_IRQ (1 << 1)
	25	#define OMAP_DMA_HALF_IRQ (1 << 2)
	26	#define OMAP_DMA_FRAME_IRQ (1 << 3)
	27	#define OMAP_DMA_LAST_IRQ (1 << 4)
	28	#define OMAP_DMA_BLOCK_IRQ (1 << 5)
	29	#define OMAP1_DMA_SYNC_IRQ (1 << 6)
	30	#define OMAP2_DMA_PKT_IRQ (1 << 7)
	31	#define OMAP2_DMA_TRANS_ERR_IRQ (1 << 8)
	32	#define OMAP2_DMA_SECURE_ERR_IRQ (1 << 9)
	33	#define OMAP2_DMA_SUPERVISOR_ERR_IRQ (1 << 10)
	34	#define OMAP2_DMA_MISALIGNED_ERR_IRQ (1 << 11)
	35
	36	#define OMAP_DMA_CCR_EN (1 << 7)
	37	#define OMAP_DMA_CCR_RD_ACTIVE (1 << 9)
	38	#define OMAP_DMA_CCR_WR_ACTIVE (1 << 10)
	39	#define OMAP_DMA_CCR_SEL_SRC_DST_SYNC (1 << 24)
	40	#define OMAP_DMA_CCR_BUFFERING_DISABLE (1 << 25)
	41
	42	#define OMAP_DMA_DATA_TYPE_S8 0x00
	43	#define OMAP_DMA_DATA_TYPE_S16 0x01
	44	#define OMAP_DMA_DATA_TYPE_S32 0x02
	45
	46	#define OMAP_DMA_SYNC_ELEMENT 0x00
	47	#define OMAP_DMA_SYNC_FRAME 0x01
	48	#define OMAP_DMA_SYNC_BLOCK 0x02
	49	#define OMAP_DMA_SYNC_PACKET 0x03
	50
	51	#define OMAP_DMA_DST_SYNC_PREFETCH 0x02
	52	#define OMAP_DMA_SRC_SYNC 0x01
	53	#define OMAP_DMA_DST_SYNC 0x00
	54
	55	#define OMAP_DMA_PORT_EMIFF 0x00
	56	#define OMAP_DMA_PORT_EMIFS 0x01
	57	#define OMAP_DMA_PORT_OCP_T1 0x02
	58	#define OMAP_DMA_PORT_TIPB 0x03
	59	#define OMAP_DMA_PORT_OCP_T2 0x04
	60	#define OMAP_DMA_PORT_MPUI 0x05
	61
	62	#define OMAP_DMA_AMODE_CONSTANT 0x00
	63	#define OMAP_DMA_AMODE_POST_INC 0x01
	64	#define OMAP_DMA_AMODE_SINGLE_IDX 0x02
	65	#define OMAP_DMA_AMODE_DOUBLE_IDX 0x03
	66
	67	#define DMA_DEFAULT_FIFO_DEPTH 0x10
	68	#define DMA_DEFAULT_ARB_RATE 0x01
	69	/* Pass THREAD_RESERVE ORed with THREAD_FIFO for tparams */
	70	#define DMA_THREAD_RESERVE_NORM (0x00 << 12) /* Def */
	71	#define DMA_THREAD_RESERVE_ONET (0x01 << 12)
	72	#define DMA_THREAD_RESERVE_TWOT (0x02 << 12)
	73	#define DMA_THREAD_RESERVE_THREET (0x03 << 12)
	74	#define DMA_THREAD_FIFO_NONE (0x00 << 14) /* Def */
	75	#define DMA_THREAD_FIFO_75 (0x01 << 14)
	76	#define DMA_THREAD_FIFO_25 (0x02 << 14)
	77	#define DMA_THREAD_FIFO_50 (0x03 << 14)
	78
	79	/* DMA4_OCP_SYSCONFIG bits */
	80	#define DMA_SYSCONFIG_MIDLEMODE_MASK (3 << 12)
	81	#define DMA_SYSCONFIG_CLOCKACTIVITY_MASK (3 << 8)
	82	#define DMA_SYSCONFIG_EMUFREE (1 << 5)
	83	#define DMA_SYSCONFIG_SIDLEMODE_MASK (3 << 3)
	84	#define DMA_SYSCONFIG_SOFTRESET (1 << 2)
	85	#define DMA_SYSCONFIG_AUTOIDLE (1 << 0)
86
87	#define DMA_SYSCONFIG_MIDLEMODE(n) ((n) << 12)
88	#define DMA_SYSCONFIG_SIDLEMODE(n) ((n) << 3)
89
90	#define DMA_IDLEMODE_SMARTIDLE 0x2
91	#define DMA_IDLEMODE_NO_IDLE 0x1
92	#define DMA_IDLEMODE_FORCE_IDLE 0x0
93
94	/* Chaining modes*/
95	#ifndef CONFIG_ARCH_OMAP1
96	#define OMAP_DMA_STATIC_CHAIN 0x1
97	#define OMAP_DMA_DYNAMIC_CHAIN 0x2
98	#define OMAP_DMA_CHAIN_ACTIVE 0x1
99	#define OMAP_DMA_CHAIN_INACTIVE 0x0
100	#endif
101
102	#define DMA_CH_PRIO_HIGH 0x1
103	#define DMA_CH_PRIO_LOW 0x0 /* Def */
104
105	/* Errata handling */
106	#define IS_DMA_ERRATA(id) (errata & (id))
107	#define SET_DMA_ERRATA(id) (errata \|= (id))
108
109	#define DMA_ERRATA_IFRAME_BUFFERING BIT(0x0)
110	#define DMA_ERRATA_PARALLEL_CHANNELS BIT(0x1)
111	#define DMA_ERRATA_i378 BIT(0x2)
112	#define DMA_ERRATA_i541 BIT(0x3)
113	#define DMA_ERRATA_i88 BIT(0x4)
114	#define DMA_ERRATA_3_3 BIT(0x5)
115	#define DMA_ROMCODE_BUG BIT(0x6)
116
117	/* Attributes for OMAP DMA Contrller */
118	#define DMA_LINKED_LCH BIT(0x0)
119	#define GLOBAL_PRIORITY BIT(0x1)
120	#define RESERVE_CHANNEL BIT(0x2)
121	#define IS_CSSA_32 BIT(0x3)
122	#define IS_CDSA_32 BIT(0x4)
123	#define IS_RW_PRIORITY BIT(0x5)
124	#define ENABLE_1510_MODE BIT(0x6)
125	#define SRC_PORT BIT(0x7)
126	#define DST_PORT BIT(0x8)
127	#define SRC_INDEX BIT(0x9)
128	#define DST_INDEX BIT(0xa)
129	#define IS_BURST_ONLY4 BIT(0xb)
130	#define CLEAR_CSR_ON_READ BIT(0xc)
131	#define IS_WORD_16 BIT(0xd)
132	#define ENABLE_16XX_MODE BIT(0xe)
133	#define HS_CHANNELS_RESERVED BIT(0xf)
76be4a54	134	#define DMA_ENGINE_HANDLE_IRQ BIT(0x10)
45c3eb7d TL	135
	136	/* Defines for DMA Capabilities */
	137	#define DMA_HAS_TRANSPARENT_CAPS (0x1 << 18)
	138	#define DMA_HAS_CONSTANT_FILL_CAPS (0x1 << 19)
	139	#define DMA_HAS_DESCRIPTOR_CAPS (0x3 << 20)
	140
	141	enum omap_reg_offsets {
	142
	143	GCR, GSCR, GRST1, HW_ID,
	144	PCH2_ID, PCH0_ID, PCH1_ID, PCHG_ID,
	145	PCHD_ID, CAPS_0, CAPS_1, CAPS_2,
	146	CAPS_3, CAPS_4, PCH2_SR, PCH0_SR,
	147	PCH1_SR, PCHD_SR, REVISION, IRQSTATUS_L0,
	148	IRQSTATUS_L1, IRQSTATUS_L2, IRQSTATUS_L3, IRQENABLE_L0,
	149	IRQENABLE_L1, IRQENABLE_L2, IRQENABLE_L3, SYSSTATUS,
	150	OCP_SYSCONFIG,
	151
	152	/* omap1+ specific */
	153	CPC, CCR2, LCH_CTRL,
	154
	155	/* Common registers for all omap's */
	156	CSDP, CCR, CICR, CSR,
	157	CEN, CFN, CSFI, CSEI,
	158	CSAC, CDAC, CDEI,
	159	CDFI, CLNK_CTRL,
	160
	161	/* Channel specific registers */
	162	CSSA, CDSA, COLOR,
	163	CCEN, CCFN,
	164
	165	/* omap3630 and omap4 specific */
	166	CDP, CNDP, CCDN,
	167
	168	};
	169
	170	enum omap_dma_burst_mode {
	171	OMAP_DMA_DATA_BURST_DIS = 0,
	172	OMAP_DMA_DATA_BURST_4,
	173	OMAP_DMA_DATA_BURST_8,
	174	OMAP_DMA_DATA_BURST_16,
	175	};
	176
	177	enum end_type {
	178	OMAP_DMA_LITTLE_ENDIAN = 0,
	179	OMAP_DMA_BIG_ENDIAN
	180	};
	181
	182	enum omap_dma_color_mode {
	183	OMAP_DMA_COLOR_DIS = 0,
	184	OMAP_DMA_CONSTANT_FILL,
	185	OMAP_DMA_TRANSPARENT_COPY
	186	};
	187
	188	enum omap_dma_write_mode {
	189	OMAP_DMA_WRITE_NON_POSTED = 0,
	190	OMAP_DMA_WRITE_POSTED,
	191	OMAP_DMA_WRITE_LAST_NON_POSTED
	192	};
	193
	194	enum omap_dma_channel_mode {
	195	OMAP_DMA_LCH_2D = 0,
	196	OMAP_DMA_LCH_G,
	197	OMAP_DMA_LCH_P,
	198	OMAP_DMA_LCH_PD
199	};
200
201	struct omap_dma_channel_params {
202	int data_type; /* data type 8,16,32 */
203	int elem_count; /* number of elements in a frame */
204	int frame_count; /* number of frames in a element */
205
206	int src_port; /* Only on OMAP1 REVISIT: Is this needed? */
207	int src_amode; /* constant, post increment, indexed,
208	double indexed */
209	unsigned long src_start; /* source address : physical */
210	int src_ei; /* source element index */
211	int src_fi; /* source frame index */
212
213	int dst_port; /* Only on OMAP1 REVISIT: Is this needed? */
214	int dst_amode; /* constant, post increment, indexed,
215	double indexed */
216	unsigned long dst_start; /* source address : physical */
217	int dst_ei; /* source element index */
218	int dst_fi; /* source frame index */
219
220	int trigger; /* trigger attached if the channel is
221	synchronized */
222	int sync_mode; /* sycn on element, frame , block or packet */
223	int src_or_dst_synch; /* source synch(1) or destination synch(0) */
224
225	int ie; /* interrupt enabled */
226
227	unsigned char read_prio;/* read priority */
228	unsigned char write_prio;/* write priority */
229
230	#ifndef CONFIG_ARCH_OMAP1
231	enum omap_dma_burst_mode burst_mode; /* Burst mode 4/8/16 words */
232	#endif
233	};
234
235	struct omap_dma_lch {
236	int next_lch;
237	int dev_id;
238	u16 saved_csr;
239	u16 enabled_irqs;
240	const char *dev_name;
241	void (callback)(int lch, u16 ch_status, void data);
242	void *data;
243	long flags;
244	/* required for Dynamic chaining */
245	int prev_linked_ch;
246	int next_linked_ch;
247	int state;
248	int chain_id;
249	int status;
250	};
251
252	struct omap_dma_dev_attr {
253	u32 dev_caps;
254	u16 lch_count;
255	u16 chan_count;
45c3eb7d TL	256	};
45c3eb7d TL	257
64a2dc3d RK	258	enum {
	259	OMAP_DMA_REG_NONE,
	260	OMAP_DMA_REG_16BIT,
	261	OMAP_DMA_REG_2X16BIT,
	262	OMAP_DMA_REG_32BIT,
	263	};
	264
	265	struct omap_dma_reg {
	266	u16 offset;
	267	u8 stride;
	268	u8 type;
	269	};
	270
020c62ae PU	271	#define SDMA_FILTER_PARAM(hw_req) ((int[]) { (hw_req) })
	272	struct dma_slave_map;
	273
45c3eb7d TL	274	/* System DMA platform data structure */
45c3eb7d TL	275	struct omap_system_dma_plat_info {
596c471b RK	276	const struct omap_dma_reg *reg_map;
596c471b RK	277	unsigned channel_stride;
45c3eb7d TL	278	struct omap_dma_dev_attr *dma_attr;
45c3eb7d TL	279	u32 errata;
45c3eb7d TL	280	void (*show_dma_caps)(void);
	281	void (*clear_lch_regs)(int lch);
	282	void (*clear_dma)(int lch);
	283	void (*dma_write)(u32 val, int reg, int lch);
	284	u32 (*dma_read)(int reg, int lch);
020c62ae PU	285
	286	const struct dma_slave_map *slave_map;
	287	int slavecnt;
45c3eb7d TL	288	};
	289
	290	#ifdef CONFIG_ARCH_OMAP2PLUS
	291	#define dma_omap2plus() 1
	292	#else
	293	#define dma_omap2plus() 0
7bedaa55	294	#endif
45c3eb7d	295	#define dma_omap1() (!dma_omap2plus())
b9e97822 RK	296	#define __dma_omap15xx(d) (dma_omap1() && (d)->dev_caps & ENABLE_1510_MODE)
	297	#define __dma_omap16xx(d) (dma_omap1() && (d)->dev_caps & ENABLE_16XX_MODE)
	298	#define dma_omap15xx() __dma_omap15xx(d)
	299	#define dma_omap16xx() __dma_omap16xx(d)
45c3eb7d	300
a8db115e	301	#if defined(CONFIG_ARCH_OMAP)
1b416c4b RK	302	extern struct omap_system_dma_plat_info *omap_get_plat_info(void);
1b416c4b RK	303
45c3eb7d TL	304	extern void omap_set_dma_priority(int lch, int dst_port, int priority);
	305	extern int omap_request_dma(int dev_id, const char *dev_name,
	306	void (callback)(int lch, u16 ch_status, void data),
	307	void data, int dma_ch);
	308	extern void omap_enable_dma_irq(int ch, u16 irq_bits);
	309	extern void omap_disable_dma_irq(int ch, u16 irq_bits);
	310	extern void omap_free_dma(int ch);
	311	extern void omap_start_dma(int lch);
	312	extern void omap_stop_dma(int lch);
	313	extern void omap_set_dma_transfer_params(int lch, int data_type,
	314	int elem_count, int frame_count,
	315	int sync_mode,
	316	int dma_trigger, int src_or_dst_synch);
45c3eb7d TL	317	extern void omap_set_dma_write_mode(int lch, enum omap_dma_write_mode mode);
	318	extern void omap_set_dma_channel_mode(int lch, enum omap_dma_channel_mode mode);
	319
	320	extern void omap_set_dma_src_params(int lch, int src_port, int src_amode,
	321	unsigned long src_start,
	322	int src_ei, int src_fi);
45c3eb7d TL	323	extern void omap_set_dma_src_data_pack(int lch, int enable);
	324	extern void omap_set_dma_src_burst_mode(int lch,
	325	enum omap_dma_burst_mode burst_mode);
	326
	327	extern void omap_set_dma_dest_params(int lch, int dest_port, int dest_amode,
	328	unsigned long dest_start,
	329	int dst_ei, int dst_fi);
45c3eb7d TL	330	extern void omap_set_dma_dest_data_pack(int lch, int enable);
	331	extern void omap_set_dma_dest_burst_mode(int lch,
	332	enum omap_dma_burst_mode burst_mode);
	333
	334	extern void omap_set_dma_params(int lch,
	335	struct omap_dma_channel_params *params);
	336
	337	extern void omap_dma_link_lch(int lch_head, int lch_queue);
45c3eb7d TL	338
	339	extern int omap_set_dma_callback(int lch,
	340	void (callback)(int lch, u16 ch_status, void data),
	341	void *data);
	342	extern dma_addr_t omap_get_dma_src_pos(int lch);
	343	extern dma_addr_t omap_get_dma_dst_pos(int lch);
45c3eb7d TL	344	extern int omap_get_dma_active_status(int lch);
	345	extern int omap_dma_running(void);
	346	extern void omap_dma_set_global_params(int arb_rate, int max_fifo_depth,
	347	int tparams);
45c3eb7d TL	348	void omap_dma_global_context_save(void);
	349	void omap_dma_global_context_restore(void);
	350
81c44c2b	351	#if defined(CONFIG_ARCH_OMAP1) && IS_ENABLED(CONFIG_FB_OMAP)
45c3eb7d TL	352	#include <mach/lcd_dma.h>
	353	#else
	354	static inline int omap_lcd_dma_running(void)
	355	{
	356	return 0;
	357	}
	358	#endif
	359
a8db115e PU	360	#else /* CONFIG_ARCH_OMAP */
	361
	362	static inline struct omap_system_dma_plat_info *omap_get_plat_info(void)
	363	{
	364	return NULL;
	365	}
	366
	367	static inline int omap_request_dma(int dev_id, const char *dev_name,
	368	void (callback)(int lch, u16 ch_status, void data),
	369	void data, int dma_ch)
	370	{
	371	return -ENODEV;
	372	}
	373
	374	static inline void omap_free_dma(int ch) { }
	375
	376	#endif /* CONFIG_ARCH_OMAP */
	377
45c3eb7d	378	#endif /* __LINUX_OMAP_DMA_H */