[mirror_ubuntu-jammy-kernel.git] / include / linux / pci-epc.h

/* SPDX-License-Identifier: GPL-2.0 */
/**
 * PCI Endpoint *Controller* (EPC) header file
 *
 * Copyright (C) 2017 Texas Instruments
 * Author: Kishon Vijay Abraham I <kishon@ti.com>
 */

#ifndef __LINUX_PCI_EPC_H
#define __LINUX_PCI_EPC_H

#include <linux/pci-epf.h>

struct pci_epc;

enum pci_epc_irq_type {
	PCI_EPC_IRQ_UNKNOWN,
	PCI_EPC_IRQ_LEGACY,
	PCI_EPC_IRQ_MSI,
	PCI_EPC_IRQ_MSIX,
};

/**
 * struct pci_epc_ops - set of function pointers for performing EPC operations
 * @write_header: ops to populate configuration space header
 * @set_bar: ops to configure the BAR
 * @clear_bar: ops to reset the BAR
 * @map_addr: ops to map CPU address to PCI address
 * @unmap_addr: ops to unmap CPU address and PCI address
 * @set_msi: ops to set the requested number of MSI interrupts in the MSI
 *	     capability register
 * @get_msi: ops to get the number of MSI interrupts allocated by the RC from
 *	     the MSI capability register
 * @set_msix: ops to set the requested number of MSI-X interrupts in the
 *	     MSI-X capability register
 * @get_msix: ops to get the number of MSI-X interrupts allocated by the RC
 *	     from the MSI-X capability register
 * @raise_irq: ops to raise a legacy, MSI or MSI-X interrupt
 * @start: ops to start the PCI link
 * @stop: ops to stop the PCI link
 * @owner: the module owner containing the ops
 */
struct pci_epc_ops {
	int	(*write_header)(struct pci_epc *epc, u8 func_no,
				struct pci_epf_header *hdr);
	int	(*set_bar)(struct pci_epc *epc, u8 func_no,
			   struct pci_epf_bar *epf_bar);
	void	(*clear_bar)(struct pci_epc *epc, u8 func_no,
			     struct pci_epf_bar *epf_bar);
	int	(*map_addr)(struct pci_epc *epc, u8 func_no,
			    phys_addr_t addr, u64 pci_addr, size_t size);
	void	(*unmap_addr)(struct pci_epc *epc, u8 func_no,
			      phys_addr_t addr);
	int	(*set_msi)(struct pci_epc *epc, u8 func_no, u8 interrupts);
	int	(*get_msi)(struct pci_epc *epc, u8 func_no);
	int	(*set_msix)(struct pci_epc *epc, u8 func_no, u16 interrupts,
			    enum pci_barno, u32 offset);
	int	(*get_msix)(struct pci_epc *epc, u8 func_no);
	int	(*raise_irq)(struct pci_epc *epc, u8 func_no,
			     enum pci_epc_irq_type type, u16 interrupt_num);
	int	(*start)(struct pci_epc *epc);
	void	(*stop)(struct pci_epc *epc);
	const struct pci_epc_features* (*get_features)(struct pci_epc *epc,
						       u8 func_no);
	struct module *owner;
};

/**
 * struct pci_epc_mem_window - address window of the endpoint controller
 * @phys_base: physical base address of the PCI address window
 * @size: the size of the PCI address window
 * @page_size: size of each page
 */
struct pci_epc_mem_window {
	phys_addr_t	phys_base;
	size_t		size;
	size_t		page_size;
};

/**
 * struct pci_epc_mem - address space of the endpoint controller
 * @window: address window of the endpoint controller
 * @bitmap: bitmap to manage the PCI address space
 * @pages: number of bits representing the address region
 * @lock: mutex to protect bitmap
 */
struct pci_epc_mem {
	struct pci_epc_mem_window window;
	unsigned long	*bitmap;
	int		pages;
	/* mutex to protect against concurrent access for memory allocation*/
	struct mutex	lock;
};

/**
 * struct pci_epc - represents the PCI EPC device
 * @dev: PCI EPC device
 * @pci_epf: list of endpoint functions present in this EPC device
 * @ops: function pointers for performing endpoint operations
 * @windows: array of address space of the endpoint controller
 * @mem: first window of the endpoint controller, which corresponds to
 *       default address space of the endpoint controller supporting
 *       single window.
 * @num_windows: number of windows supported by device
 * @max_functions: max number of functions that can be configured in this EPC
 * @group: configfs group representing the PCI EPC device
 * @lock: mutex to protect pci_epc ops
 * @function_num_map: bitmap to manage physical function number
 * @notifier: used to notify EPF of any EPC events (like linkup)
 */
struct pci_epc {
	struct device			dev;
	struct list_head		pci_epf;
	const struct pci_epc_ops	*ops;
	struct pci_epc_mem		**windows;
	struct pci_epc_mem		*mem;
	unsigned int			num_windows;
	u8				max_functions;
	struct config_group		*group;
	/* mutex to protect against concurrent access of EP controller */
	struct mutex			lock;
	unsigned long			function_num_map;
	struct atomic_notifier_head	notifier;
};

/**
 * struct pci_epc_features - features supported by a EPC device per function
 * @linkup_notifier: indicate if the EPC device can notify EPF driver on link up
 * @msi_capable: indicate if the endpoint function has MSI capability
 * @msix_capable: indicate if the endpoint function has MSI-X capability
 * @reserved_bar: bitmap to indicate reserved BAR unavailable to function driver
 * @bar_fixed_64bit: bitmap to indicate fixed 64bit BARs
 * @bar_fixed_size: Array specifying the size supported by each BAR
 * @align: alignment size required for BAR buffer allocation
 */
struct pci_epc_features {
	unsigned int	linkup_notifier : 1;
	unsigned int	core_init_notifier : 1;
	unsigned int	msi_capable : 1;
	unsigned int	msix_capable : 1;
	u8	reserved_bar;
	u8	bar_fixed_64bit;
	u64	bar_fixed_size[PCI_STD_NUM_BARS];
	size_t	align;
};

#define to_pci_epc(device) container_of((device), struct pci_epc, dev)

#define pci_epc_create(dev, ops)    \
		__pci_epc_create((dev), (ops), THIS_MODULE)
#define devm_pci_epc_create(dev, ops)    \
		__devm_pci_epc_create((dev), (ops), THIS_MODULE)

static inline void epc_set_drvdata(struct pci_epc *epc, void *data)
{
	dev_set_drvdata(&epc->dev, data);
}

static inline void *epc_get_drvdata(struct pci_epc *epc)
{
	return dev_get_drvdata(&epc->dev);
}

static inline int
pci_epc_register_notifier(struct pci_epc *epc, struct notifier_block *nb)
{
	return atomic_notifier_chain_register(&epc->notifier, nb);
}

struct pci_epc *
__devm_pci_epc_create(struct device *dev, const struct pci_epc_ops *ops,
		      struct module *owner);
struct pci_epc *
__pci_epc_create(struct device *dev, const struct pci_epc_ops *ops,
		 struct module *owner);
void devm_pci_epc_destroy(struct device *dev, struct pci_epc *epc);
void pci_epc_destroy(struct pci_epc *epc);
int pci_epc_add_epf(struct pci_epc *epc, struct pci_epf *epf);
void pci_epc_linkup(struct pci_epc *epc);
void pci_epc_init_notify(struct pci_epc *epc);
void pci_epc_remove_epf(struct pci_epc *epc, struct pci_epf *epf);
int pci_epc_write_header(struct pci_epc *epc, u8 func_no,
			 struct pci_epf_header *hdr);
int pci_epc_set_bar(struct pci_epc *epc, u8 func_no,
		    struct pci_epf_bar *epf_bar);
void pci_epc_clear_bar(struct pci_epc *epc, u8 func_no,
		       struct pci_epf_bar *epf_bar);
int pci_epc_map_addr(struct pci_epc *epc, u8 func_no,
		     phys_addr_t phys_addr,
		     u64 pci_addr, size_t size);
void pci_epc_unmap_addr(struct pci_epc *epc, u8 func_no,
			phys_addr_t phys_addr);
int pci_epc_set_msi(struct pci_epc *epc, u8 func_no, u8 interrupts);
int pci_epc_get_msi(struct pci_epc *epc, u8 func_no);
int pci_epc_set_msix(struct pci_epc *epc, u8 func_no, u16 interrupts,
		     enum pci_barno, u32 offset);
int pci_epc_get_msix(struct pci_epc *epc, u8 func_no);
int pci_epc_raise_irq(struct pci_epc *epc, u8 func_no,
		      enum pci_epc_irq_type type, u16 interrupt_num);
int pci_epc_start(struct pci_epc *epc);
void pci_epc_stop(struct pci_epc *epc);
const struct pci_epc_features *pci_epc_get_features(struct pci_epc *epc,
						    u8 func_no);
unsigned int pci_epc_get_first_free_bar(const struct pci_epc_features
					*epc_features);
struct pci_epc *pci_epc_get(const char *epc_name);
void pci_epc_put(struct pci_epc *epc);

int pci_epc_mem_init(struct pci_epc *epc, phys_addr_t base,
		     size_t size, size_t page_size);
int pci_epc_multi_mem_init(struct pci_epc *epc,
			   struct pci_epc_mem_window *window,
			   unsigned int num_windows);
void pci_epc_mem_exit(struct pci_epc *epc);
void __iomem *pci_epc_mem_alloc_addr(struct pci_epc *epc,
				     phys_addr_t *phys_addr, size_t size);
void pci_epc_mem_free_addr(struct pci_epc *epc, phys_addr_t phys_addr,
			   void __iomem *virt_addr, size_t size);
#endif /* __LINUX_PCI_EPC_H */
Commit	Line	Data
8cfab3cf	1	/* SPDX-License-Identifier: GPL-2.0 */
5e8cb403 KVA	2	/**
	3	* PCI Endpoint Controller (EPC) header file
	4	*
	5	* Copyright (C) 2017 Texas Instruments
	6	* Author: Kishon Vijay Abraham I <kishon@ti.com>
5e8cb403 KVA	7	*/
	8
	9	#ifndef __LINUX_PCI_EPC_H
	10	#define __LINUX_PCI_EPC_H
	11
	12	#include <linux/pci-epf.h>
	13
	14	struct pci_epc;
	15
	16	enum pci_epc_irq_type {
	17	PCI_EPC_IRQ_UNKNOWN,
	18	PCI_EPC_IRQ_LEGACY,
	19	PCI_EPC_IRQ_MSI,
8963106e	20	PCI_EPC_IRQ_MSIX,
5e8cb403 KVA	21	};
	22
	23	/**
	24	* struct pci_epc_ops - set of function pointers for performing EPC operations
	25	* @write_header: ops to populate configuration space header
	26	* @set_bar: ops to configure the BAR
	27	* @clear_bar: ops to reset the BAR
	28	* @map_addr: ops to map CPU address to PCI address
	29	* @unmap_addr: ops to unmap CPU address and PCI address
	30	* @set_msi: ops to set the requested number of MSI interrupts in the MSI
	31	* capability register
	32	* @get_msi: ops to get the number of MSI interrupts allocated by the RC from
	33	* the MSI capability register
8963106e GP	34	* @set_msix: ops to set the requested number of MSI-X interrupts in the
	35	* MSI-X capability register
	36	* @get_msix: ops to get the number of MSI-X interrupts allocated by the RC
	37	* from the MSI-X capability register
d3c70a98	38	* @raise_irq: ops to raise a legacy, MSI or MSI-X interrupt
5e8cb403 KVA	39	* @start: ops to start the PCI link
	40	* @stop: ops to stop the PCI link
	41	* @owner: the module owner containing the ops
	42	*/
	43	struct pci_epc_ops {
4494738d	44	int (write_header)(struct pci_epc epc, u8 func_no,
5e8cb403	45	struct pci_epf_header *hdr);
4494738d	46	int (set_bar)(struct pci_epc epc, u8 func_no,
bc4a4897	47	struct pci_epf_bar *epf_bar);
4494738d	48	void (clear_bar)(struct pci_epc epc, u8 func_no,
77d08dbd	49	struct pci_epf_bar *epf_bar);
4494738d CP	50	int (map_addr)(struct pci_epc epc, u8 func_no,
	51	phys_addr_t addr, u64 pci_addr, size_t size);
	52	void (unmap_addr)(struct pci_epc epc, u8 func_no,
	53	phys_addr_t addr);
	54	int (set_msi)(struct pci_epc epc, u8 func_no, u8 interrupts);
	55	int (get_msi)(struct pci_epc epc, u8 func_no);
83153d9f KVA	56	int (set_msix)(struct pci_epc epc, u8 func_no, u16 interrupts,
83153d9f KVA	57	enum pci_barno, u32 offset);
8963106e	58	int (get_msix)(struct pci_epc epc, u8 func_no);
4494738d	59	int (raise_irq)(struct pci_epc epc, u8 func_no,
d3c70a98	60	enum pci_epc_irq_type type, u16 interrupt_num);
5e8cb403 KVA	61	int (start)(struct pci_epc epc);
5e8cb403 KVA	62	void (stop)(struct pci_epc epc);
41cb8d18 KVA	63	const struct pci_epc_features* (get_features)(struct pci_epc epc,
41cb8d18 KVA	64	u8 func_no);
5e8cb403 KVA	65	struct module *owner;
	66	};
	67
d45e3c1a LP	68	/**
	69	* struct pci_epc_mem_window - address window of the endpoint controller
	70	* @phys_base: physical base address of the PCI address window
	71	* @size: the size of the PCI address window
	72	* @page_size: size of each page
	73	*/
	74	struct pci_epc_mem_window {
	75	phys_addr_t phys_base;
	76	size_t size;
	77	size_t page_size;
	78	};
	79
5e8cb403 KVA	80	/**
5e8cb403 KVA	81	* struct pci_epc_mem - address space of the endpoint controller
d45e3c1a	82	* @window: address window of the endpoint controller
5e8cb403 KVA	83	* @bitmap: bitmap to manage the PCI address space
5e8cb403 KVA	84	* @pages: number of bits representing the address region
04e046ca	85	* @lock: mutex to protect bitmap
5e8cb403 KVA	86	*/
5e8cb403 KVA	87	struct pci_epc_mem {
d45e3c1a	88	struct pci_epc_mem_window window;
5e8cb403 KVA	89	unsigned long *bitmap;
5e8cb403 KVA	90	int pages;
04e046ca KVA	91	/* mutex to protect against concurrent access for memory allocation*/
04e046ca KVA	92	struct mutex lock;
5e8cb403 KVA	93	};
	94
	95	/**
	96	* struct pci_epc - represents the PCI EPC device
	97	* @dev: PCI EPC device
	98	* @pci_epf: list of endpoint functions present in this EPC device
	99	* @ops: function pointers for performing endpoint operations
d45e3c1a LP	100	* @windows: array of address space of the endpoint controller
	101	* @mem: first window of the endpoint controller, which corresponds to
	102	* default address space of the endpoint controller supporting
	103	* single window.
	104	* @num_windows: number of windows supported by device
5e8cb403	105	* @max_functions: max number of functions that can be configured in this EPC
3a401a2c	106	* @group: configfs group representing the PCI EPC device
3d3248db	107	* @lock: mutex to protect pci_epc ops
2499ee84	108	* @function_num_map: bitmap to manage physical function number
5779dd0a	109	* @notifier: used to notify EPF of any EPC events (like linkup)
5e8cb403 KVA	110	*/
	111	struct pci_epc {
	112	struct device dev;
	113	struct list_head pci_epf;
	114	const struct pci_epc_ops *ops;
d45e3c1a	115	struct pci_epc_mem **windows;
5e8cb403	116	struct pci_epc_mem *mem;
d45e3c1a	117	unsigned int num_windows;
5e8cb403	118	u8 max_functions;
3a401a2c	119	struct config_group *group;
3d3248db KVA	120	/* mutex to protect against concurrent access of EP controller */
3d3248db KVA	121	struct mutex lock;
2499ee84	122	unsigned long function_num_map;
5779dd0a	123	struct atomic_notifier_head notifier;
5e8cb403 KVA	124	};
5e8cb403 KVA	125
41cb8d18 KVA	126	/**
	127	* struct pci_epc_features - features supported by a EPC device per function
	128	* @linkup_notifier: indicate if the EPC device can notify EPF driver on link up
	129	* @msi_capable: indicate if the endpoint function has MSI capability
	130	* @msix_capable: indicate if the endpoint function has MSI-X capability
	131	* @reserved_bar: bitmap to indicate reserved BAR unavailable to function driver
	132	* @bar_fixed_64bit: bitmap to indicate fixed 64bit BARs
	133	* @bar_fixed_size: Array specifying the size supported by each BAR
2a9a8016	134	* @align: alignment size required for BAR buffer allocation
41cb8d18 KVA	135	*/
	136	struct pci_epc_features {
	137	unsigned int linkup_notifier : 1;
3d5f7d9f	138	unsigned int core_init_notifier : 1;
41cb8d18 KVA	139	unsigned int msi_capable : 1;
	140	unsigned int msix_capable : 1;
	141	u8 reserved_bar;
	142	u8 bar_fixed_64bit;
c9c13ba4	143	u64 bar_fixed_size[PCI_STD_NUM_BARS];
2a9a8016	144	size_t align;
41cb8d18 KVA	145	};
41cb8d18 KVA	146
5e8cb403 KVA	147	#define to_pci_epc(device) container_of((device), struct pci_epc, dev)
	148
	149	#define pci_epc_create(dev, ops) \
	150	__pci_epc_create((dev), (ops), THIS_MODULE)
	151	#define devm_pci_epc_create(dev, ops) \
	152	__devm_pci_epc_create((dev), (ops), THIS_MODULE)
	153
	154	static inline void epc_set_drvdata(struct pci_epc epc, void data)
	155	{
	156	dev_set_drvdata(&epc->dev, data);
	157	}
	158
	159	static inline void epc_get_drvdata(struct pci_epc epc)
	160	{
	161	return dev_get_drvdata(&epc->dev);
	162	}
	163
5779dd0a KVA	164	static inline int
	165	pci_epc_register_notifier(struct pci_epc epc, struct notifier_block nb)
	166	{
	167	return atomic_notifier_chain_register(&epc->notifier, nb);
	168	}
	169
5e8cb403 KVA	170	struct pci_epc *
	171	__devm_pci_epc_create(struct device dev, const struct pci_epc_ops ops,
	172	struct module *owner);
	173	struct pci_epc *
	174	__pci_epc_create(struct device dev, const struct pci_epc_ops ops,
	175	struct module *owner);
	176	void devm_pci_epc_destroy(struct device dev, struct pci_epc epc);
	177	void pci_epc_destroy(struct pci_epc *epc);
	178	int pci_epc_add_epf(struct pci_epc epc, struct pci_epf epf);
	179	void pci_epc_linkup(struct pci_epc *epc);
0ef22dcf	180	void pci_epc_init_notify(struct pci_epc *epc);
5e8cb403	181	void pci_epc_remove_epf(struct pci_epc epc, struct pci_epf epf);
4494738d CP	182	int pci_epc_write_header(struct pci_epc *epc, u8 func_no,
	183	struct pci_epf_header *hdr);
	184	int pci_epc_set_bar(struct pci_epc *epc, u8 func_no,
bc4a4897	185	struct pci_epf_bar *epf_bar);
77d08dbd NC	186	void pci_epc_clear_bar(struct pci_epc *epc, u8 func_no,
77d08dbd NC	187	struct pci_epf_bar *epf_bar);
4494738d CP	188	int pci_epc_map_addr(struct pci_epc *epc, u8 func_no,
4494738d CP	189	phys_addr_t phys_addr,
5e8cb403	190	u64 pci_addr, size_t size);
4494738d CP	191	void pci_epc_unmap_addr(struct pci_epc *epc, u8 func_no,
	192	phys_addr_t phys_addr);
	193	int pci_epc_set_msi(struct pci_epc *epc, u8 func_no, u8 interrupts);
	194	int pci_epc_get_msi(struct pci_epc *epc, u8 func_no);
83153d9f KVA	195	int pci_epc_set_msix(struct pci_epc *epc, u8 func_no, u16 interrupts,
83153d9f KVA	196	enum pci_barno, u32 offset);
8963106e	197	int pci_epc_get_msix(struct pci_epc *epc, u8 func_no);
4494738d	198	int pci_epc_raise_irq(struct pci_epc *epc, u8 func_no,
d3c70a98	199	enum pci_epc_irq_type type, u16 interrupt_num);
5e8cb403 KVA	200	int pci_epc_start(struct pci_epc *epc);
5e8cb403 KVA	201	void pci_epc_stop(struct pci_epc *epc);
41cb8d18 KVA	202	const struct pci_epc_features pci_epc_get_features(struct pci_epc epc,
41cb8d18 KVA	203	u8 func_no);
1e9efe6c KVA	204	unsigned int pci_epc_get_first_free_bar(const struct pci_epc_features
1e9efe6c KVA	205	*epc_features);
5e8cb403 KVA	206	struct pci_epc pci_epc_get(const char epc_name);
	207	void pci_epc_put(struct pci_epc *epc);
	208
975cf23e LP	209	int pci_epc_mem_init(struct pci_epc *epc, phys_addr_t base,
975cf23e LP	210	size_t size, size_t page_size);
d45e3c1a LP	211	int pci_epc_multi_mem_init(struct pci_epc *epc,
	212	struct pci_epc_mem_window *window,
	213	unsigned int num_windows);
5e8cb403 KVA	214	void pci_epc_mem_exit(struct pci_epc *epc);
	215	void __iomem pci_epc_mem_alloc_addr(struct pci_epc epc,
	216	phys_addr_t *phys_addr, size_t size);
	217	void pci_epc_mem_free_addr(struct pci_epc *epc, phys_addr_t phys_addr,
	218	void __iomem *virt_addr, size_t size);
	219	#endif /* __LINUX_PCI_EPC_H */