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Commit | Line | Data |
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1da177e4 LT |
1 | /* |
2 | * pci.h | |
3 | * | |
4 | * PCI defines and function prototypes | |
5 | * Copyright 1994, Drew Eckhardt | |
6 | * Copyright 1997--1999 Martin Mares <mj@ucw.cz> | |
7 | * | |
8 | * For more information, please consult the following manuals (look at | |
9 | * http://www.pcisig.com/ for how to get them): | |
10 | * | |
11 | * PCI BIOS Specification | |
12 | * PCI Local Bus Specification | |
13 | * PCI to PCI Bridge Specification | |
14 | * PCI System Design Guide | |
15 | */ | |
1da177e4 LT |
16 | #ifndef LINUX_PCI_H |
17 | #define LINUX_PCI_H | |
18 | ||
1da177e4 | 19 | |
778382e0 DW |
20 | #include <linux/mod_devicetable.h> |
21 | ||
1da177e4 | 22 | #include <linux/types.h> |
98db6f19 | 23 | #include <linux/init.h> |
1da177e4 LT |
24 | #include <linux/ioport.h> |
25 | #include <linux/list.h> | |
4a7fb636 | 26 | #include <linux/compiler.h> |
1da177e4 | 27 | #include <linux/errno.h> |
f46753c5 | 28 | #include <linux/kobject.h> |
60063497 | 29 | #include <linux/atomic.h> |
1da177e4 | 30 | #include <linux/device.h> |
1388cc96 | 31 | #include <linux/io.h> |
14d76b68 | 32 | #include <linux/resource_ext.h> |
607ca46e | 33 | #include <uapi/linux/pci.h> |
1da177e4 | 34 | |
7e7a43c3 AB |
35 | #include <linux/pci_ids.h> |
36 | ||
85467136 SK |
37 | /* |
38 | * The PCI interface treats multi-function devices as independent | |
39 | * devices. The slot/function address of each device is encoded | |
40 | * in a single byte as follows: | |
41 | * | |
42 | * 7:3 = slot | |
43 | * 2:0 = function | |
f7625980 BH |
44 | * |
45 | * PCI_DEVFN(), PCI_SLOT(), and PCI_FUNC() are defined in uapi/linux/pci.h. | |
85467136 | 46 | * In the interest of not exposing interfaces to user-space unnecessarily, |
f7625980 | 47 | * the following kernel-only defines are being added here. |
85467136 | 48 | */ |
63ddc0b8 | 49 | #define PCI_DEVID(bus, devfn) ((((u16)(bus)) << 8) | (devfn)) |
85467136 SK |
50 | /* return bus from PCI devid = ((u16)bus_number) << 8) | devfn */ |
51 | #define PCI_BUS_NUM(x) (((x) >> 8) & 0xff) | |
52 | ||
f46753c5 AC |
53 | /* pci_slot represents a physical slot */ |
54 | struct pci_slot { | |
55 | struct pci_bus *bus; /* The bus this slot is on */ | |
56 | struct list_head list; /* node in list of slots on this bus */ | |
57 | struct hotplug_slot *hotplug; /* Hotplug info (migrate over time) */ | |
58 | unsigned char number; /* PCI_SLOT(pci_dev->devfn) */ | |
59 | struct kobject kobj; | |
60 | }; | |
61 | ||
0ad772ec AC |
62 | static inline const char *pci_slot_name(const struct pci_slot *slot) |
63 | { | |
64 | return kobject_name(&slot->kobj); | |
65 | } | |
66 | ||
1da177e4 LT |
67 | /* File state for mmap()s on /proc/bus/pci/X/Y */ |
68 | enum pci_mmap_state { | |
69 | pci_mmap_io, | |
70 | pci_mmap_mem | |
71 | }; | |
72 | ||
73 | /* This defines the direction arg to the DMA mapping routines. */ | |
74 | #define PCI_DMA_BIDIRECTIONAL 0 | |
75 | #define PCI_DMA_TODEVICE 1 | |
76 | #define PCI_DMA_FROMDEVICE 2 | |
77 | #define PCI_DMA_NONE 3 | |
78 | ||
fde09c6d YZ |
79 | /* |
80 | * For PCI devices, the region numbers are assigned this way: | |
81 | */ | |
82 | enum { | |
83 | /* #0-5: standard PCI resources */ | |
84 | PCI_STD_RESOURCES, | |
85 | PCI_STD_RESOURCE_END = 5, | |
86 | ||
87 | /* #6: expansion ROM resource */ | |
88 | PCI_ROM_RESOURCE, | |
89 | ||
d1b054da YZ |
90 | /* device specific resources */ |
91 | #ifdef CONFIG_PCI_IOV | |
92 | PCI_IOV_RESOURCES, | |
93 | PCI_IOV_RESOURCE_END = PCI_IOV_RESOURCES + PCI_SRIOV_NUM_BARS - 1, | |
94 | #endif | |
95 | ||
fde09c6d YZ |
96 | /* resources assigned to buses behind the bridge */ |
97 | #define PCI_BRIDGE_RESOURCE_NUM 4 | |
98 | ||
99 | PCI_BRIDGE_RESOURCES, | |
100 | PCI_BRIDGE_RESOURCE_END = PCI_BRIDGE_RESOURCES + | |
101 | PCI_BRIDGE_RESOURCE_NUM - 1, | |
102 | ||
103 | /* total resources associated with a PCI device */ | |
104 | PCI_NUM_RESOURCES, | |
105 | ||
106 | /* preserve this for compatibility */ | |
cda57bf9 | 107 | DEVICE_COUNT_RESOURCE = PCI_NUM_RESOURCES, |
fde09c6d | 108 | }; |
1da177e4 LT |
109 | |
110 | typedef int __bitwise pci_power_t; | |
111 | ||
4352dfd5 GKH |
112 | #define PCI_D0 ((pci_power_t __force) 0) |
113 | #define PCI_D1 ((pci_power_t __force) 1) | |
114 | #define PCI_D2 ((pci_power_t __force) 2) | |
1da177e4 LT |
115 | #define PCI_D3hot ((pci_power_t __force) 3) |
116 | #define PCI_D3cold ((pci_power_t __force) 4) | |
3fe9d19f | 117 | #define PCI_UNKNOWN ((pci_power_t __force) 5) |
438510f6 | 118 | #define PCI_POWER_ERROR ((pci_power_t __force) -1) |
1da177e4 | 119 | |
00240c38 AS |
120 | /* Remember to update this when the list above changes! */ |
121 | extern const char *pci_power_names[]; | |
122 | ||
123 | static inline const char *pci_power_name(pci_power_t state) | |
124 | { | |
125 | return pci_power_names[1 + (int) state]; | |
126 | } | |
127 | ||
448bd857 HY |
128 | #define PCI_PM_D2_DELAY 200 |
129 | #define PCI_PM_D3_WAIT 10 | |
130 | #define PCI_PM_D3COLD_WAIT 100 | |
131 | #define PCI_PM_BUS_WAIT 50 | |
aa8c6c93 | 132 | |
392a1ce7 LV |
133 | /** The pci_channel state describes connectivity between the CPU and |
134 | * the pci device. If some PCI bus between here and the pci device | |
135 | * has crashed or locked up, this info is reflected here. | |
136 | */ | |
137 | typedef unsigned int __bitwise pci_channel_state_t; | |
138 | ||
139 | enum pci_channel_state { | |
140 | /* I/O channel is in normal state */ | |
141 | pci_channel_io_normal = (__force pci_channel_state_t) 1, | |
142 | ||
143 | /* I/O to channel is blocked */ | |
144 | pci_channel_io_frozen = (__force pci_channel_state_t) 2, | |
145 | ||
146 | /* PCI card is dead */ | |
147 | pci_channel_io_perm_failure = (__force pci_channel_state_t) 3, | |
148 | }; | |
149 | ||
f7bdd12d BK |
150 | typedef unsigned int __bitwise pcie_reset_state_t; |
151 | ||
152 | enum pcie_reset_state { | |
153 | /* Reset is NOT asserted (Use to deassert reset) */ | |
154 | pcie_deassert_reset = (__force pcie_reset_state_t) 1, | |
155 | ||
f7625980 | 156 | /* Use #PERST to reset PCIe device */ |
f7bdd12d BK |
157 | pcie_warm_reset = (__force pcie_reset_state_t) 2, |
158 | ||
f7625980 | 159 | /* Use PCIe Hot Reset to reset device */ |
f7bdd12d BK |
160 | pcie_hot_reset = (__force pcie_reset_state_t) 3 |
161 | }; | |
162 | ||
ba698ad4 DM |
163 | typedef unsigned short __bitwise pci_dev_flags_t; |
164 | enum pci_dev_flags { | |
165 | /* INTX_DISABLE in PCI_COMMAND register disables MSI | |
166 | * generation too. | |
167 | */ | |
6b121592 | 168 | PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG = (__force pci_dev_flags_t) (1 << 0), |
979b1791 | 169 | /* Device configuration is irrevocably lost if disabled into D3 */ |
6b121592 | 170 | PCI_DEV_FLAGS_NO_D3 = (__force pci_dev_flags_t) (1 << 1), |
6777829c | 171 | /* Provide indication device is assigned by a Virtual Machine Manager */ |
6b121592 | 172 | PCI_DEV_FLAGS_ASSIGNED = (__force pci_dev_flags_t) (1 << 2), |
5757a769 | 173 | /* Flag for quirk use to store if quirk-specific ACS is enabled */ |
6b121592 | 174 | PCI_DEV_FLAGS_ACS_ENABLED_QUIRK = (__force pci_dev_flags_t) (1 << 3), |
31c2b815 AW |
175 | /* Flag to indicate the device uses dma_alias_devfn */ |
176 | PCI_DEV_FLAGS_DMA_ALIAS_DEVFN = (__force pci_dev_flags_t) (1 << 4), | |
c8fe16e3 AW |
177 | /* Use a PCIe-to-PCI bridge alias even if !pci_is_pcie */ |
178 | PCI_DEV_FLAG_PCIE_BRIDGE_ALIAS = (__force pci_dev_flags_t) (1 << 5), | |
f331a859 AW |
179 | /* Do not use bus resets for device */ |
180 | PCI_DEV_FLAGS_NO_BUS_RESET = (__force pci_dev_flags_t) (1 << 6), | |
51e53738 AW |
181 | /* Do not use PM reset even if device advertises NoSoftRst- */ |
182 | PCI_DEV_FLAGS_NO_PM_RESET = (__force pci_dev_flags_t) (1 << 7), | |
ba698ad4 DM |
183 | }; |
184 | ||
e1d3a908 SA |
185 | enum pci_irq_reroute_variant { |
186 | INTEL_IRQ_REROUTE_VARIANT = 1, | |
187 | MAX_IRQ_REROUTE_VARIANTS = 3 | |
188 | }; | |
189 | ||
6e325a62 MT |
190 | typedef unsigned short __bitwise pci_bus_flags_t; |
191 | enum pci_bus_flags { | |
d556ad4b PO |
192 | PCI_BUS_FLAGS_NO_MSI = (__force pci_bus_flags_t) 1, |
193 | PCI_BUS_FLAGS_NO_MMRBC = (__force pci_bus_flags_t) 2, | |
6e325a62 MT |
194 | }; |
195 | ||
59da381e JK |
196 | /* These values come from the PCI Express Spec */ |
197 | enum pcie_link_width { | |
198 | PCIE_LNK_WIDTH_RESRV = 0x00, | |
199 | PCIE_LNK_X1 = 0x01, | |
200 | PCIE_LNK_X2 = 0x02, | |
201 | PCIE_LNK_X4 = 0x04, | |
202 | PCIE_LNK_X8 = 0x08, | |
203 | PCIE_LNK_X12 = 0x0C, | |
204 | PCIE_LNK_X16 = 0x10, | |
205 | PCIE_LNK_X32 = 0x20, | |
206 | PCIE_LNK_WIDTH_UNKNOWN = 0xFF, | |
207 | }; | |
208 | ||
536c8cb4 MW |
209 | /* Based on the PCI Hotplug Spec, but some values are made up by us */ |
210 | enum pci_bus_speed { | |
211 | PCI_SPEED_33MHz = 0x00, | |
212 | PCI_SPEED_66MHz = 0x01, | |
213 | PCI_SPEED_66MHz_PCIX = 0x02, | |
214 | PCI_SPEED_100MHz_PCIX = 0x03, | |
215 | PCI_SPEED_133MHz_PCIX = 0x04, | |
216 | PCI_SPEED_66MHz_PCIX_ECC = 0x05, | |
217 | PCI_SPEED_100MHz_PCIX_ECC = 0x06, | |
218 | PCI_SPEED_133MHz_PCIX_ECC = 0x07, | |
219 | PCI_SPEED_66MHz_PCIX_266 = 0x09, | |
220 | PCI_SPEED_100MHz_PCIX_266 = 0x0a, | |
221 | PCI_SPEED_133MHz_PCIX_266 = 0x0b, | |
45b4cdd5 MW |
222 | AGP_UNKNOWN = 0x0c, |
223 | AGP_1X = 0x0d, | |
224 | AGP_2X = 0x0e, | |
225 | AGP_4X = 0x0f, | |
226 | AGP_8X = 0x10, | |
536c8cb4 MW |
227 | PCI_SPEED_66MHz_PCIX_533 = 0x11, |
228 | PCI_SPEED_100MHz_PCIX_533 = 0x12, | |
229 | PCI_SPEED_133MHz_PCIX_533 = 0x13, | |
230 | PCIE_SPEED_2_5GT = 0x14, | |
231 | PCIE_SPEED_5_0GT = 0x15, | |
9dfd97fe | 232 | PCIE_SPEED_8_0GT = 0x16, |
536c8cb4 MW |
233 | PCI_SPEED_UNKNOWN = 0xff, |
234 | }; | |
235 | ||
24a4742f | 236 | struct pci_cap_saved_data { |
fd0f7f73 AW |
237 | u16 cap_nr; |
238 | bool cap_extended; | |
24a4742f | 239 | unsigned int size; |
41017f0c SL |
240 | u32 data[0]; |
241 | }; | |
242 | ||
24a4742f AW |
243 | struct pci_cap_saved_state { |
244 | struct hlist_node next; | |
245 | struct pci_cap_saved_data cap; | |
246 | }; | |
247 | ||
7d715a6c | 248 | struct pcie_link_state; |
ee69439c | 249 | struct pci_vpd; |
d1b054da | 250 | struct pci_sriov; |
302b4215 | 251 | struct pci_ats; |
ee69439c | 252 | |
1da177e4 LT |
253 | /* |
254 | * The pci_dev structure is used to describe PCI devices. | |
255 | */ | |
256 | struct pci_dev { | |
1da177e4 LT |
257 | struct list_head bus_list; /* node in per-bus list */ |
258 | struct pci_bus *bus; /* bus this device is on */ | |
259 | struct pci_bus *subordinate; /* bus this device bridges to */ | |
260 | ||
261 | void *sysdata; /* hook for sys-specific extension */ | |
262 | struct proc_dir_entry *procent; /* device entry in /proc/bus/pci */ | |
f46753c5 | 263 | struct pci_slot *slot; /* Physical slot this device is in */ |
1da177e4 LT |
264 | |
265 | unsigned int devfn; /* encoded device & function index */ | |
266 | unsigned short vendor; | |
267 | unsigned short device; | |
268 | unsigned short subsystem_vendor; | |
269 | unsigned short subsystem_device; | |
270 | unsigned int class; /* 3 bytes: (base,sub,prog-if) */ | |
b8a3a521 | 271 | u8 revision; /* PCI revision, low byte of class word */ |
1da177e4 | 272 | u8 hdr_type; /* PCI header type (`multi' flag masked out) */ |
f7625980 | 273 | u8 pcie_cap; /* PCIe capability offset */ |
e375b561 GS |
274 | u8 msi_cap; /* MSI capability offset */ |
275 | u8 msix_cap; /* MSI-X capability offset */ | |
f7625980 | 276 | u8 pcie_mpss:3; /* PCIe Max Payload Size Supported */ |
1da177e4 | 277 | u8 rom_base_reg; /* which config register controls the ROM */ |
f7625980 BH |
278 | u8 pin; /* which interrupt pin this device uses */ |
279 | u16 pcie_flags_reg; /* cached PCIe Capabilities Register */ | |
31c2b815 | 280 | u8 dma_alias_devfn;/* devfn of DMA alias, if any */ |
1da177e4 LT |
281 | |
282 | struct pci_driver *driver; /* which driver has allocated this device */ | |
283 | u64 dma_mask; /* Mask of the bits of bus address this | |
284 | device implements. Normally this is | |
285 | 0xffffffff. You only need to change | |
286 | this if your device has broken DMA | |
287 | or supports 64-bit transfers. */ | |
288 | ||
4d57cdfa FT |
289 | struct device_dma_parameters dma_parms; |
290 | ||
1da177e4 LT |
291 | pci_power_t current_state; /* Current operating state. In ACPI-speak, |
292 | this is D0-D3, D0 being fully functional, | |
293 | and D3 being off. */ | |
703860ed | 294 | u8 pm_cap; /* PM capability offset */ |
337001b6 RW |
295 | unsigned int pme_support:5; /* Bitmask of states from which PME# |
296 | can be generated */ | |
c7f48656 | 297 | unsigned int pme_interrupt:1; |
379021d5 | 298 | unsigned int pme_poll:1; /* Poll device's PME status bit */ |
337001b6 RW |
299 | unsigned int d1_support:1; /* Low power state D1 is supported */ |
300 | unsigned int d2_support:1; /* Low power state D2 is supported */ | |
448bd857 HY |
301 | unsigned int no_d1d2:1; /* D1 and D2 are forbidden */ |
302 | unsigned int no_d3cold:1; /* D3cold is forbidden */ | |
303 | unsigned int d3cold_allowed:1; /* D3cold is allowed by user */ | |
253d2e54 JP |
304 | unsigned int mmio_always_on:1; /* disallow turning off io/mem |
305 | decoding during bar sizing */ | |
e80bb09d | 306 | unsigned int wakeup_prepared:1; |
448bd857 HY |
307 | unsigned int runtime_d3cold:1; /* whether go through runtime |
308 | D3cold, not set for devices | |
309 | powered on/off by the | |
310 | corresponding bridge */ | |
b440bde7 | 311 | unsigned int ignore_hotplug:1; /* Ignore hotplug events */ |
1ae861e6 | 312 | unsigned int d3_delay; /* D3->D0 transition time in ms */ |
448bd857 | 313 | unsigned int d3cold_delay; /* D3cold->D0 transition time in ms */ |
1da177e4 | 314 | |
7d715a6c | 315 | #ifdef CONFIG_PCIEASPM |
f7625980 | 316 | struct pcie_link_state *link_state; /* ASPM link state */ |
7d715a6c SL |
317 | #endif |
318 | ||
392a1ce7 | 319 | pci_channel_state_t error_state; /* current connectivity state */ |
1da177e4 LT |
320 | struct device dev; /* Generic device interface */ |
321 | ||
1da177e4 LT |
322 | int cfg_size; /* Size of configuration space */ |
323 | ||
324 | /* | |
325 | * Instead of touching interrupt line and base address registers | |
326 | * directly, use the values stored here. They might be different! | |
327 | */ | |
328 | unsigned int irq; | |
329 | struct resource resource[DEVICE_COUNT_RESOURCE]; /* I/O and memory regions + expansion ROMs */ | |
330 | ||
58d9a38f | 331 | bool match_driver; /* Skip attaching driver */ |
1da177e4 | 332 | /* These fields are used by common fixups */ |
f7625980 | 333 | unsigned int transparent:1; /* Subtractive decode PCI bridge */ |
1da177e4 LT |
334 | unsigned int multifunction:1;/* Part of multi-function device */ |
335 | /* keep track of device state */ | |
8a1bc901 | 336 | unsigned int is_added:1; |
1da177e4 | 337 | unsigned int is_busmaster:1; /* device is busmaster */ |
4602b88d | 338 | unsigned int no_msi:1; /* device may not use msi */ |
f144d149 | 339 | unsigned int no_64bit_msi:1; /* device may only use 32-bit MSIs */ |
fb51ccbf | 340 | unsigned int block_cfg_access:1; /* config space access is blocked */ |
bd8481e1 | 341 | unsigned int broken_parity_status:1; /* Device generates false positive parity */ |
e1d3a908 | 342 | unsigned int irq_reroute_variant:2; /* device needs IRQ rerouting variant */ |
f7625980 | 343 | unsigned int msi_enabled:1; |
99dc804d | 344 | unsigned int msix_enabled:1; |
58c3a727 | 345 | unsigned int ari_enabled:1; /* ARI forwarding */ |
9ac7849e | 346 | unsigned int is_managed:1; |
260d703a | 347 | unsigned int needs_freset:1; /* Dev requires fundamental reset */ |
aa8c6c93 | 348 | unsigned int state_saved:1; |
d1b054da | 349 | unsigned int is_physfn:1; |
dd7cc44d | 350 | unsigned int is_virtfn:1; |
711d5779 | 351 | unsigned int reset_fn:1; |
28760489 | 352 | unsigned int is_hotplug_bridge:1; |
affb72c3 HY |
353 | unsigned int __aer_firmware_first_valid:1; |
354 | unsigned int __aer_firmware_first:1; | |
fbebb9fd | 355 | unsigned int broken_intx_masking:1; |
2b28ae19 | 356 | unsigned int io_window_1k:1; /* Intel P2P bridge 1K I/O windows */ |
cffe0a2b | 357 | unsigned int irq_managed:1; |
ba698ad4 | 358 | pci_dev_flags_t dev_flags; |
bae94d02 | 359 | atomic_t enable_cnt; /* pci_enable_device has been called */ |
4602b88d | 360 | |
1da177e4 | 361 | u32 saved_config_space[16]; /* config space saved at suspend time */ |
41017f0c | 362 | struct hlist_head saved_cap_space; |
1da177e4 LT |
363 | struct bin_attribute *rom_attr; /* attribute descriptor for sysfs ROM entry */ |
364 | int rom_attr_enabled; /* has display of the rom attribute been enabled? */ | |
365 | struct bin_attribute *res_attr[DEVICE_COUNT_RESOURCE]; /* sysfs file for resources */ | |
45aec1ae | 366 | struct bin_attribute *res_attr_wc[DEVICE_COUNT_RESOURCE]; /* sysfs file for WC mapping of resources */ |
ded86d8d | 367 | #ifdef CONFIG_PCI_MSI |
4aa9bc95 | 368 | struct list_head msi_list; |
1c51b50c | 369 | const struct attribute_group **msi_irq_groups; |
ded86d8d | 370 | #endif |
94e61088 | 371 | struct pci_vpd *vpd; |
466b3ddf | 372 | #ifdef CONFIG_PCI_ATS |
dd7cc44d YZ |
373 | union { |
374 | struct pci_sriov *sriov; /* SR-IOV capability related */ | |
375 | struct pci_dev *physfn; /* the PF this VF is associated with */ | |
376 | }; | |
302b4215 | 377 | struct pci_ats *ats; /* Address Translation Service */ |
d1b054da | 378 | #endif |
dbd3fc33 | 379 | phys_addr_t rom; /* Physical address of ROM if it's not from the BAR */ |
84c1b80e | 380 | size_t romlen; /* Length of ROM if it's not from the BAR */ |
782a985d | 381 | char *driver_override; /* Driver name to force a match */ |
1da177e4 LT |
382 | }; |
383 | ||
dda56549 Y |
384 | static inline struct pci_dev *pci_physfn(struct pci_dev *dev) |
385 | { | |
386 | #ifdef CONFIG_PCI_IOV | |
387 | if (dev->is_virtfn) | |
388 | dev = dev->physfn; | |
389 | #endif | |
dda56549 Y |
390 | return dev; |
391 | } | |
392 | ||
3c6e6ae7 | 393 | struct pci_dev *pci_alloc_dev(struct pci_bus *bus); |
65891215 | 394 | |
1da177e4 LT |
395 | #define to_pci_dev(n) container_of(n, struct pci_dev, dev) |
396 | #define for_each_pci_dev(d) while ((d = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, d)) != NULL) | |
397 | ||
a7369f1f LV |
398 | static inline int pci_channel_offline(struct pci_dev *pdev) |
399 | { | |
400 | return (pdev->error_state != pci_channel_io_normal); | |
401 | } | |
402 | ||
5a21d70d | 403 | struct pci_host_bridge { |
7b543663 | 404 | struct device dev; |
5a21d70d | 405 | struct pci_bus *bus; /* root bus */ |
14d76b68 | 406 | struct list_head windows; /* resource_entry */ |
4fa2649a YL |
407 | void (*release_fn)(struct pci_host_bridge *); |
408 | void *release_data; | |
5a21d70d | 409 | }; |
41017f0c | 410 | |
7b543663 | 411 | #define to_pci_host_bridge(n) container_of(n, struct pci_host_bridge, dev) |
4fa2649a YL |
412 | void pci_set_host_bridge_release(struct pci_host_bridge *bridge, |
413 | void (*release_fn)(struct pci_host_bridge *), | |
414 | void *release_data); | |
7b543663 | 415 | |
6c0cc950 RW |
416 | int pcibios_root_bridge_prepare(struct pci_host_bridge *bridge); |
417 | ||
2fe2abf8 BH |
418 | /* |
419 | * The first PCI_BRIDGE_RESOURCE_NUM PCI bus resources (those that correspond | |
420 | * to P2P or CardBus bridge windows) go in a table. Additional ones (for | |
421 | * buses below host bridges or subtractive decode bridges) go in the list. | |
422 | * Use pci_bus_for_each_resource() to iterate through all the resources. | |
423 | */ | |
424 | ||
425 | /* | |
426 | * PCI_SUBTRACTIVE_DECODE means the bridge forwards the window implicitly | |
427 | * and there's no way to program the bridge with the details of the window. | |
428 | * This does not apply to ACPI _CRS windows, even with the _DEC subtractive- | |
429 | * decode bit set, because they are explicit and can be programmed with _SRS. | |
430 | */ | |
431 | #define PCI_SUBTRACTIVE_DECODE 0x1 | |
432 | ||
433 | struct pci_bus_resource { | |
434 | struct list_head list; | |
435 | struct resource *res; | |
436 | unsigned int flags; | |
437 | }; | |
4352dfd5 GKH |
438 | |
439 | #define PCI_REGION_FLAG_MASK 0x0fU /* These bits of resource flags tell us the PCI region flags */ | |
1da177e4 LT |
440 | |
441 | struct pci_bus { | |
442 | struct list_head node; /* node in list of buses */ | |
443 | struct pci_bus *parent; /* parent bus this bridge is on */ | |
444 | struct list_head children; /* list of child buses */ | |
445 | struct list_head devices; /* list of devices on this bus */ | |
446 | struct pci_dev *self; /* bridge device as seen by parent */ | |
f46753c5 | 447 | struct list_head slots; /* list of slots on this bus */ |
2fe2abf8 BH |
448 | struct resource *resource[PCI_BRIDGE_RESOURCE_NUM]; |
449 | struct list_head resources; /* address space routed to this bus */ | |
92f02430 | 450 | struct resource busn_res; /* bus numbers routed to this bus */ |
1da177e4 LT |
451 | |
452 | struct pci_ops *ops; /* configuration access functions */ | |
c2791b80 | 453 | struct msi_controller *msi; /* MSI controller */ |
1da177e4 LT |
454 | void *sysdata; /* hook for sys-specific extension */ |
455 | struct proc_dir_entry *procdir; /* directory entry in /proc/bus/pci */ | |
456 | ||
457 | unsigned char number; /* bus number */ | |
458 | unsigned char primary; /* number of primary bridge */ | |
3749c51a MW |
459 | unsigned char max_bus_speed; /* enum pci_bus_speed */ |
460 | unsigned char cur_bus_speed; /* enum pci_bus_speed */ | |
670ba0c8 CM |
461 | #ifdef CONFIG_PCI_DOMAINS_GENERIC |
462 | int domain_nr; | |
463 | #endif | |
1da177e4 LT |
464 | |
465 | char name[48]; | |
466 | ||
467 | unsigned short bridge_ctl; /* manage NO_ISA/FBB/et al behaviors */ | |
f7625980 | 468 | pci_bus_flags_t bus_flags; /* inherited by child buses */ |
1da177e4 | 469 | struct device *bridge; |
fd7d1ced | 470 | struct device dev; |
1da177e4 LT |
471 | struct bin_attribute *legacy_io; /* legacy I/O for this bus */ |
472 | struct bin_attribute *legacy_mem; /* legacy mem */ | |
cc74d96f | 473 | unsigned int is_added:1; |
1da177e4 LT |
474 | }; |
475 | ||
fd7d1ced | 476 | #define to_pci_bus(n) container_of(n, struct pci_bus, dev) |
1da177e4 | 477 | |
79af72d7 | 478 | /* |
f7625980 | 479 | * Returns true if the PCI bus is root (behind host-PCI bridge), |
79af72d7 | 480 | * false otherwise |
77a0dfcd BH |
481 | * |
482 | * Some code assumes that "bus->self == NULL" means that bus is a root bus. | |
483 | * This is incorrect because "virtual" buses added for SR-IOV (via | |
484 | * virtfn_add_bus()) have "bus->self == NULL" but are not root buses. | |
79af72d7 KK |
485 | */ |
486 | static inline bool pci_is_root_bus(struct pci_bus *pbus) | |
487 | { | |
488 | return !(pbus->parent); | |
489 | } | |
490 | ||
1c86438c YW |
491 | /** |
492 | * pci_is_bridge - check if the PCI device is a bridge | |
493 | * @dev: PCI device | |
494 | * | |
495 | * Return true if the PCI device is bridge whether it has subordinate | |
496 | * or not. | |
497 | */ | |
498 | static inline bool pci_is_bridge(struct pci_dev *dev) | |
499 | { | |
500 | return dev->hdr_type == PCI_HEADER_TYPE_BRIDGE || | |
501 | dev->hdr_type == PCI_HEADER_TYPE_CARDBUS; | |
502 | } | |
503 | ||
c6bde215 BH |
504 | static inline struct pci_dev *pci_upstream_bridge(struct pci_dev *dev) |
505 | { | |
506 | dev = pci_physfn(dev); | |
507 | if (pci_is_root_bus(dev->bus)) | |
508 | return NULL; | |
509 | ||
510 | return dev->bus->self; | |
511 | } | |
512 | ||
16cf0ebc RW |
513 | #ifdef CONFIG_PCI_MSI |
514 | static inline bool pci_dev_msi_enabled(struct pci_dev *pci_dev) | |
515 | { | |
516 | return pci_dev->msi_enabled || pci_dev->msix_enabled; | |
517 | } | |
518 | #else | |
519 | static inline bool pci_dev_msi_enabled(struct pci_dev *pci_dev) { return false; } | |
520 | #endif | |
521 | ||
1da177e4 LT |
522 | /* |
523 | * Error values that may be returned by PCI functions. | |
524 | */ | |
525 | #define PCIBIOS_SUCCESSFUL 0x00 | |
526 | #define PCIBIOS_FUNC_NOT_SUPPORTED 0x81 | |
527 | #define PCIBIOS_BAD_VENDOR_ID 0x83 | |
528 | #define PCIBIOS_DEVICE_NOT_FOUND 0x86 | |
529 | #define PCIBIOS_BAD_REGISTER_NUMBER 0x87 | |
530 | #define PCIBIOS_SET_FAILED 0x88 | |
531 | #define PCIBIOS_BUFFER_TOO_SMALL 0x89 | |
532 | ||
a6961651 | 533 | /* |
f7625980 | 534 | * Translate above to generic errno for passing back through non-PCI code. |
a6961651 AW |
535 | */ |
536 | static inline int pcibios_err_to_errno(int err) | |
537 | { | |
538 | if (err <= PCIBIOS_SUCCESSFUL) | |
539 | return err; /* Assume already errno */ | |
540 | ||
541 | switch (err) { | |
542 | case PCIBIOS_FUNC_NOT_SUPPORTED: | |
543 | return -ENOENT; | |
544 | case PCIBIOS_BAD_VENDOR_ID: | |
d97ffe23 | 545 | return -ENOTTY; |
a6961651 AW |
546 | case PCIBIOS_DEVICE_NOT_FOUND: |
547 | return -ENODEV; | |
548 | case PCIBIOS_BAD_REGISTER_NUMBER: | |
549 | return -EFAULT; | |
550 | case PCIBIOS_SET_FAILED: | |
551 | return -EIO; | |
552 | case PCIBIOS_BUFFER_TOO_SMALL: | |
553 | return -ENOSPC; | |
554 | } | |
555 | ||
d97ffe23 | 556 | return -ERANGE; |
a6961651 AW |
557 | } |
558 | ||
1da177e4 LT |
559 | /* Low-level architecture-dependent routines */ |
560 | ||
561 | struct pci_ops { | |
1f94a94f | 562 | void __iomem *(*map_bus)(struct pci_bus *bus, unsigned int devfn, int where); |
1da177e4 LT |
563 | int (*read)(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 *val); |
564 | int (*write)(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 val); | |
565 | }; | |
566 | ||
b6ce068a MW |
567 | /* |
568 | * ACPI needs to be able to access PCI config space before we've done a | |
569 | * PCI bus scan and created pci_bus structures. | |
570 | */ | |
f39d5b72 BH |
571 | int raw_pci_read(unsigned int domain, unsigned int bus, unsigned int devfn, |
572 | int reg, int len, u32 *val); | |
573 | int raw_pci_write(unsigned int domain, unsigned int bus, unsigned int devfn, | |
574 | int reg, int len, u32 val); | |
1da177e4 LT |
575 | |
576 | struct pci_bus_region { | |
0a5ef7b9 BH |
577 | dma_addr_t start; |
578 | dma_addr_t end; | |
1da177e4 LT |
579 | }; |
580 | ||
581 | struct pci_dynids { | |
582 | spinlock_t lock; /* protects list, index */ | |
583 | struct list_head list; /* for IDs added at runtime */ | |
1da177e4 LT |
584 | }; |
585 | ||
f7625980 BH |
586 | |
587 | /* | |
588 | * PCI Error Recovery System (PCI-ERS). If a PCI device driver provides | |
589 | * a set of callbacks in struct pci_error_handlers, that device driver | |
590 | * will be notified of PCI bus errors, and will be driven to recovery | |
591 | * when an error occurs. | |
392a1ce7 LV |
592 | */ |
593 | ||
594 | typedef unsigned int __bitwise pci_ers_result_t; | |
595 | ||
596 | enum pci_ers_result { | |
597 | /* no result/none/not supported in device driver */ | |
598 | PCI_ERS_RESULT_NONE = (__force pci_ers_result_t) 1, | |
599 | ||
600 | /* Device driver can recover without slot reset */ | |
601 | PCI_ERS_RESULT_CAN_RECOVER = (__force pci_ers_result_t) 2, | |
602 | ||
603 | /* Device driver wants slot to be reset. */ | |
604 | PCI_ERS_RESULT_NEED_RESET = (__force pci_ers_result_t) 3, | |
605 | ||
606 | /* Device has completely failed, is unrecoverable */ | |
607 | PCI_ERS_RESULT_DISCONNECT = (__force pci_ers_result_t) 4, | |
608 | ||
609 | /* Device driver is fully recovered and operational */ | |
610 | PCI_ERS_RESULT_RECOVERED = (__force pci_ers_result_t) 5, | |
918b4053 VMP |
611 | |
612 | /* No AER capabilities registered for the driver */ | |
613 | PCI_ERS_RESULT_NO_AER_DRIVER = (__force pci_ers_result_t) 6, | |
392a1ce7 LV |
614 | }; |
615 | ||
616 | /* PCI bus error event callbacks */ | |
05cca6e5 | 617 | struct pci_error_handlers { |
392a1ce7 LV |
618 | /* PCI bus error detected on this device */ |
619 | pci_ers_result_t (*error_detected)(struct pci_dev *dev, | |
05cca6e5 | 620 | enum pci_channel_state error); |
392a1ce7 LV |
621 | |
622 | /* MMIO has been re-enabled, but not DMA */ | |
623 | pci_ers_result_t (*mmio_enabled)(struct pci_dev *dev); | |
624 | ||
625 | /* PCI Express link has been reset */ | |
626 | pci_ers_result_t (*link_reset)(struct pci_dev *dev); | |
627 | ||
628 | /* PCI slot has been reset */ | |
629 | pci_ers_result_t (*slot_reset)(struct pci_dev *dev); | |
630 | ||
3ebe7f9f KB |
631 | /* PCI function reset prepare or completed */ |
632 | void (*reset_notify)(struct pci_dev *dev, bool prepare); | |
633 | ||
392a1ce7 LV |
634 | /* Device driver may resume normal operations */ |
635 | void (*resume)(struct pci_dev *dev); | |
636 | }; | |
637 | ||
392a1ce7 | 638 | |
1da177e4 LT |
639 | struct module; |
640 | struct pci_driver { | |
641 | struct list_head node; | |
42b21932 | 642 | const char *name; |
1da177e4 LT |
643 | const struct pci_device_id *id_table; /* must be non-NULL for probe to be called */ |
644 | int (*probe) (struct pci_dev *dev, const struct pci_device_id *id); /* New device inserted */ | |
645 | void (*remove) (struct pci_dev *dev); /* Device removed (NULL if not a hot-plug capable driver) */ | |
646 | int (*suspend) (struct pci_dev *dev, pm_message_t state); /* Device suspended */ | |
cbd69dbb LT |
647 | int (*suspend_late) (struct pci_dev *dev, pm_message_t state); |
648 | int (*resume_early) (struct pci_dev *dev); | |
1da177e4 | 649 | int (*resume) (struct pci_dev *dev); /* Device woken up */ |
c8958177 | 650 | void (*shutdown) (struct pci_dev *dev); |
1789382a | 651 | int (*sriov_configure) (struct pci_dev *dev, int num_vfs); /* PF pdev */ |
49453028 | 652 | const struct pci_error_handlers *err_handler; |
1da177e4 LT |
653 | struct device_driver driver; |
654 | struct pci_dynids dynids; | |
655 | }; | |
656 | ||
05cca6e5 | 657 | #define to_pci_driver(drv) container_of(drv, struct pci_driver, driver) |
1da177e4 | 658 | |
90a1ba0c | 659 | /** |
9f9351bb | 660 | * DEFINE_PCI_DEVICE_TABLE - macro used to describe a pci device table |
90a1ba0c JB |
661 | * @_table: device table name |
662 | * | |
92e112fd | 663 | * This macro is deprecated and should not be used in new code. |
90a1ba0c | 664 | */ |
9f9351bb | 665 | #define DEFINE_PCI_DEVICE_TABLE(_table) \ |
15856ad5 | 666 | const struct pci_device_id _table[] |
90a1ba0c | 667 | |
1da177e4 LT |
668 | /** |
669 | * PCI_DEVICE - macro used to describe a specific pci device | |
670 | * @vend: the 16 bit PCI Vendor ID | |
671 | * @dev: the 16 bit PCI Device ID | |
672 | * | |
673 | * This macro is used to create a struct pci_device_id that matches a | |
674 | * specific device. The subvendor and subdevice fields will be set to | |
675 | * PCI_ANY_ID. | |
676 | */ | |
677 | #define PCI_DEVICE(vend,dev) \ | |
678 | .vendor = (vend), .device = (dev), \ | |
679 | .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID | |
680 | ||
3d567e0e NNS |
681 | /** |
682 | * PCI_DEVICE_SUB - macro used to describe a specific pci device with subsystem | |
683 | * @vend: the 16 bit PCI Vendor ID | |
684 | * @dev: the 16 bit PCI Device ID | |
685 | * @subvend: the 16 bit PCI Subvendor ID | |
686 | * @subdev: the 16 bit PCI Subdevice ID | |
687 | * | |
688 | * This macro is used to create a struct pci_device_id that matches a | |
689 | * specific device with subsystem information. | |
690 | */ | |
691 | #define PCI_DEVICE_SUB(vend, dev, subvend, subdev) \ | |
692 | .vendor = (vend), .device = (dev), \ | |
693 | .subvendor = (subvend), .subdevice = (subdev) | |
694 | ||
1da177e4 LT |
695 | /** |
696 | * PCI_DEVICE_CLASS - macro used to describe a specific pci device class | |
697 | * @dev_class: the class, subclass, prog-if triple for this device | |
698 | * @dev_class_mask: the class mask for this device | |
699 | * | |
700 | * This macro is used to create a struct pci_device_id that matches a | |
4352dfd5 | 701 | * specific PCI class. The vendor, device, subvendor, and subdevice |
1da177e4 LT |
702 | * fields will be set to PCI_ANY_ID. |
703 | */ | |
704 | #define PCI_DEVICE_CLASS(dev_class,dev_class_mask) \ | |
705 | .class = (dev_class), .class_mask = (dev_class_mask), \ | |
706 | .vendor = PCI_ANY_ID, .device = PCI_ANY_ID, \ | |
707 | .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID | |
708 | ||
1597cacb AC |
709 | /** |
710 | * PCI_VDEVICE - macro used to describe a specific pci device in short form | |
c1309040 MR |
711 | * @vend: the vendor name |
712 | * @dev: the 16 bit PCI Device ID | |
1597cacb AC |
713 | * |
714 | * This macro is used to create a struct pci_device_id that matches a | |
715 | * specific PCI device. The subvendor, and subdevice fields will be set | |
716 | * to PCI_ANY_ID. The macro allows the next field to follow as the device | |
717 | * private data. | |
718 | */ | |
719 | ||
c1309040 MR |
720 | #define PCI_VDEVICE(vend, dev) \ |
721 | .vendor = PCI_VENDOR_ID_##vend, .device = (dev), \ | |
722 | .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID, 0, 0 | |
1597cacb | 723 | |
1da177e4 LT |
724 | /* these external functions are only available when PCI support is enabled */ |
725 | #ifdef CONFIG_PCI | |
726 | ||
a58674ff | 727 | void pcie_bus_configure_settings(struct pci_bus *bus); |
b03e7495 JM |
728 | |
729 | enum pcie_bus_config_types { | |
5f39e670 | 730 | PCIE_BUS_TUNE_OFF, |
b03e7495 | 731 | PCIE_BUS_SAFE, |
5f39e670 | 732 | PCIE_BUS_PERFORMANCE, |
b03e7495 JM |
733 | PCIE_BUS_PEER2PEER, |
734 | }; | |
735 | ||
736 | extern enum pcie_bus_config_types pcie_bus_config; | |
737 | ||
1da177e4 LT |
738 | extern struct bus_type pci_bus_type; |
739 | ||
f7625980 BH |
740 | /* Do NOT directly access these two variables, unless you are arch-specific PCI |
741 | * code, or PCI core code. */ | |
1da177e4 | 742 | extern struct list_head pci_root_buses; /* list of all known PCI buses */ |
f7625980 | 743 | /* Some device drivers need know if PCI is initiated */ |
f39d5b72 | 744 | int no_pci_devices(void); |
1da177e4 | 745 | |
3c449ed0 | 746 | void pcibios_resource_survey_bus(struct pci_bus *bus); |
10a95747 JL |
747 | void pcibios_add_bus(struct pci_bus *bus); |
748 | void pcibios_remove_bus(struct pci_bus *bus); | |
1da177e4 | 749 | void pcibios_fixup_bus(struct pci_bus *); |
4a7fb636 | 750 | int __must_check pcibios_enable_device(struct pci_dev *, int mask); |
f7625980 | 751 | /* Architecture-specific versions may override this (weak) */ |
05cca6e5 | 752 | char *pcibios_setup(char *str); |
1da177e4 LT |
753 | |
754 | /* Used only when drivers/pci/setup.c is used */ | |
3b7a17fc | 755 | resource_size_t pcibios_align_resource(void *, const struct resource *, |
b26b2d49 | 756 | resource_size_t, |
e31dd6e4 | 757 | resource_size_t); |
1da177e4 LT |
758 | void pcibios_update_irq(struct pci_dev *, int irq); |
759 | ||
2d1c8618 BH |
760 | /* Weak but can be overriden by arch */ |
761 | void pci_fixup_cardbus(struct pci_bus *); | |
762 | ||
1da177e4 LT |
763 | /* Generic PCI functions used internally */ |
764 | ||
fc279850 | 765 | void pcibios_resource_to_bus(struct pci_bus *bus, struct pci_bus_region *region, |
36a66cd6 | 766 | struct resource *res); |
fc279850 | 767 | void pcibios_bus_to_resource(struct pci_bus *bus, struct resource *res, |
36a66cd6 | 768 | struct pci_bus_region *region); |
d1fd4fb6 | 769 | void pcibios_scan_specific_bus(int busn); |
f39d5b72 | 770 | struct pci_bus *pci_find_bus(int domain, int busnr); |
c48f1670 | 771 | void pci_bus_add_devices(const struct pci_bus *bus); |
05cca6e5 GKH |
772 | struct pci_bus *pci_scan_bus_parented(struct device *parent, int bus, |
773 | struct pci_ops *ops, void *sysdata); | |
de4b2f76 | 774 | struct pci_bus *pci_scan_bus(int bus, struct pci_ops *ops, void *sysdata); |
166c6370 BH |
775 | struct pci_bus *pci_create_root_bus(struct device *parent, int bus, |
776 | struct pci_ops *ops, void *sysdata, | |
777 | struct list_head *resources); | |
98a35831 YL |
778 | int pci_bus_insert_busn_res(struct pci_bus *b, int bus, int busmax); |
779 | int pci_bus_update_busn_res_end(struct pci_bus *b, int busmax); | |
780 | void pci_bus_release_busn_res(struct pci_bus *b); | |
15856ad5 | 781 | struct pci_bus *pci_scan_root_bus(struct device *parent, int bus, |
a2ebb827 BH |
782 | struct pci_ops *ops, void *sysdata, |
783 | struct list_head *resources); | |
05cca6e5 GKH |
784 | struct pci_bus *pci_add_new_bus(struct pci_bus *parent, struct pci_dev *dev, |
785 | int busnr); | |
3749c51a | 786 | void pcie_update_link_speed(struct pci_bus *bus, u16 link_status); |
f46753c5 | 787 | struct pci_slot *pci_create_slot(struct pci_bus *parent, int slot_nr, |
828f3768 AC |
788 | const char *name, |
789 | struct hotplug_slot *hotplug); | |
f46753c5 | 790 | void pci_destroy_slot(struct pci_slot *slot); |
1da177e4 | 791 | int pci_scan_slot(struct pci_bus *bus, int devfn); |
05cca6e5 | 792 | struct pci_dev *pci_scan_single_device(struct pci_bus *bus, int devfn); |
cdb9b9f7 | 793 | void pci_device_add(struct pci_dev *dev, struct pci_bus *bus); |
1da177e4 | 794 | unsigned int pci_scan_child_bus(struct pci_bus *bus); |
c893d133 | 795 | void pci_bus_add_device(struct pci_dev *dev); |
1da177e4 | 796 | void pci_read_bridge_bases(struct pci_bus *child); |
05cca6e5 GKH |
797 | struct resource *pci_find_parent_resource(const struct pci_dev *dev, |
798 | struct resource *res); | |
3df425f3 | 799 | u8 pci_swizzle_interrupt_pin(const struct pci_dev *dev, u8 pin); |
1da177e4 | 800 | int pci_get_interrupt_pin(struct pci_dev *dev, struct pci_dev **bridge); |
68feac87 | 801 | u8 pci_common_swizzle(struct pci_dev *dev, u8 *pinp); |
f39d5b72 BH |
802 | struct pci_dev *pci_dev_get(struct pci_dev *dev); |
803 | void pci_dev_put(struct pci_dev *dev); | |
804 | void pci_remove_bus(struct pci_bus *b); | |
805 | void pci_stop_and_remove_bus_device(struct pci_dev *dev); | |
9d16947b | 806 | void pci_stop_and_remove_bus_device_locked(struct pci_dev *dev); |
cdfcc572 YL |
807 | void pci_stop_root_bus(struct pci_bus *bus); |
808 | void pci_remove_root_bus(struct pci_bus *bus); | |
b3743fa4 | 809 | void pci_setup_cardbus(struct pci_bus *bus); |
f39d5b72 | 810 | void pci_sort_breadthfirst(void); |
fb8a0d9d WM |
811 | #define dev_is_pci(d) ((d)->bus == &pci_bus_type) |
812 | #define dev_is_pf(d) ((dev_is_pci(d) ? to_pci_dev(d)->is_physfn : false)) | |
813 | #define dev_num_vf(d) ((dev_is_pci(d) ? pci_num_vf(to_pci_dev(d)) : 0)) | |
1da177e4 LT |
814 | |
815 | /* Generic PCI functions exported to card drivers */ | |
816 | ||
388c8c16 JB |
817 | enum pci_lost_interrupt_reason { |
818 | PCI_LOST_IRQ_NO_INFORMATION = 0, | |
819 | PCI_LOST_IRQ_DISABLE_MSI, | |
820 | PCI_LOST_IRQ_DISABLE_MSIX, | |
821 | PCI_LOST_IRQ_DISABLE_ACPI, | |
822 | }; | |
823 | enum pci_lost_interrupt_reason pci_lost_interrupt(struct pci_dev *dev); | |
05cca6e5 GKH |
824 | int pci_find_capability(struct pci_dev *dev, int cap); |
825 | int pci_find_next_capability(struct pci_dev *dev, u8 pos, int cap); | |
826 | int pci_find_ext_capability(struct pci_dev *dev, int cap); | |
44a9a36f | 827 | int pci_find_next_ext_capability(struct pci_dev *dev, int pos, int cap); |
05cca6e5 GKH |
828 | int pci_find_ht_capability(struct pci_dev *dev, int ht_cap); |
829 | int pci_find_next_ht_capability(struct pci_dev *dev, int pos, int ht_cap); | |
29f3eb64 | 830 | struct pci_bus *pci_find_next_bus(const struct pci_bus *from); |
1da177e4 | 831 | |
d42552c3 AM |
832 | struct pci_dev *pci_get_device(unsigned int vendor, unsigned int device, |
833 | struct pci_dev *from); | |
05cca6e5 | 834 | struct pci_dev *pci_get_subsys(unsigned int vendor, unsigned int device, |
1da177e4 | 835 | unsigned int ss_vendor, unsigned int ss_device, |
b08508c4 | 836 | struct pci_dev *from); |
05cca6e5 | 837 | struct pci_dev *pci_get_slot(struct pci_bus *bus, unsigned int devfn); |
3c299dc2 AP |
838 | struct pci_dev *pci_get_domain_bus_and_slot(int domain, unsigned int bus, |
839 | unsigned int devfn); | |
840 | static inline struct pci_dev *pci_get_bus_and_slot(unsigned int bus, | |
841 | unsigned int devfn) | |
842 | { | |
843 | return pci_get_domain_bus_and_slot(0, bus, devfn); | |
844 | } | |
05cca6e5 | 845 | struct pci_dev *pci_get_class(unsigned int class, struct pci_dev *from); |
1da177e4 LT |
846 | int pci_dev_present(const struct pci_device_id *ids); |
847 | ||
05cca6e5 GKH |
848 | int pci_bus_read_config_byte(struct pci_bus *bus, unsigned int devfn, |
849 | int where, u8 *val); | |
850 | int pci_bus_read_config_word(struct pci_bus *bus, unsigned int devfn, | |
851 | int where, u16 *val); | |
852 | int pci_bus_read_config_dword(struct pci_bus *bus, unsigned int devfn, | |
853 | int where, u32 *val); | |
854 | int pci_bus_write_config_byte(struct pci_bus *bus, unsigned int devfn, | |
855 | int where, u8 val); | |
856 | int pci_bus_write_config_word(struct pci_bus *bus, unsigned int devfn, | |
857 | int where, u16 val); | |
858 | int pci_bus_write_config_dword(struct pci_bus *bus, unsigned int devfn, | |
859 | int where, u32 val); | |
1f94a94f RH |
860 | |
861 | int pci_generic_config_read(struct pci_bus *bus, unsigned int devfn, | |
862 | int where, int size, u32 *val); | |
863 | int pci_generic_config_write(struct pci_bus *bus, unsigned int devfn, | |
864 | int where, int size, u32 val); | |
865 | int pci_generic_config_read32(struct pci_bus *bus, unsigned int devfn, | |
866 | int where, int size, u32 *val); | |
867 | int pci_generic_config_write32(struct pci_bus *bus, unsigned int devfn, | |
868 | int where, int size, u32 val); | |
869 | ||
a72b46c3 | 870 | struct pci_ops *pci_bus_set_ops(struct pci_bus *bus, struct pci_ops *ops); |
1da177e4 | 871 | |
bf362f75 | 872 | static inline int pci_read_config_byte(const struct pci_dev *dev, int where, u8 *val) |
1da177e4 | 873 | { |
05cca6e5 | 874 | return pci_bus_read_config_byte(dev->bus, dev->devfn, where, val); |
1da177e4 | 875 | } |
bf362f75 | 876 | static inline int pci_read_config_word(const struct pci_dev *dev, int where, u16 *val) |
1da177e4 | 877 | { |
05cca6e5 | 878 | return pci_bus_read_config_word(dev->bus, dev->devfn, where, val); |
1da177e4 | 879 | } |
bf362f75 | 880 | static inline int pci_read_config_dword(const struct pci_dev *dev, int where, |
05cca6e5 | 881 | u32 *val) |
1da177e4 | 882 | { |
05cca6e5 | 883 | return pci_bus_read_config_dword(dev->bus, dev->devfn, where, val); |
1da177e4 | 884 | } |
bf362f75 | 885 | static inline int pci_write_config_byte(const struct pci_dev *dev, int where, u8 val) |
1da177e4 | 886 | { |
05cca6e5 | 887 | return pci_bus_write_config_byte(dev->bus, dev->devfn, where, val); |
1da177e4 | 888 | } |
bf362f75 | 889 | static inline int pci_write_config_word(const struct pci_dev *dev, int where, u16 val) |
1da177e4 | 890 | { |
05cca6e5 | 891 | return pci_bus_write_config_word(dev->bus, dev->devfn, where, val); |
1da177e4 | 892 | } |
bf362f75 | 893 | static inline int pci_write_config_dword(const struct pci_dev *dev, int where, |
05cca6e5 | 894 | u32 val) |
1da177e4 | 895 | { |
05cca6e5 | 896 | return pci_bus_write_config_dword(dev->bus, dev->devfn, where, val); |
1da177e4 LT |
897 | } |
898 | ||
8c0d3a02 JL |
899 | int pcie_capability_read_word(struct pci_dev *dev, int pos, u16 *val); |
900 | int pcie_capability_read_dword(struct pci_dev *dev, int pos, u32 *val); | |
901 | int pcie_capability_write_word(struct pci_dev *dev, int pos, u16 val); | |
902 | int pcie_capability_write_dword(struct pci_dev *dev, int pos, u32 val); | |
903 | int pcie_capability_clear_and_set_word(struct pci_dev *dev, int pos, | |
904 | u16 clear, u16 set); | |
905 | int pcie_capability_clear_and_set_dword(struct pci_dev *dev, int pos, | |
906 | u32 clear, u32 set); | |
907 | ||
908 | static inline int pcie_capability_set_word(struct pci_dev *dev, int pos, | |
909 | u16 set) | |
910 | { | |
911 | return pcie_capability_clear_and_set_word(dev, pos, 0, set); | |
912 | } | |
913 | ||
914 | static inline int pcie_capability_set_dword(struct pci_dev *dev, int pos, | |
915 | u32 set) | |
916 | { | |
917 | return pcie_capability_clear_and_set_dword(dev, pos, 0, set); | |
918 | } | |
919 | ||
920 | static inline int pcie_capability_clear_word(struct pci_dev *dev, int pos, | |
921 | u16 clear) | |
922 | { | |
923 | return pcie_capability_clear_and_set_word(dev, pos, clear, 0); | |
924 | } | |
925 | ||
926 | static inline int pcie_capability_clear_dword(struct pci_dev *dev, int pos, | |
927 | u32 clear) | |
928 | { | |
929 | return pcie_capability_clear_and_set_dword(dev, pos, clear, 0); | |
930 | } | |
931 | ||
c63587d7 AW |
932 | /* user-space driven config access */ |
933 | int pci_user_read_config_byte(struct pci_dev *dev, int where, u8 *val); | |
934 | int pci_user_read_config_word(struct pci_dev *dev, int where, u16 *val); | |
935 | int pci_user_read_config_dword(struct pci_dev *dev, int where, u32 *val); | |
936 | int pci_user_write_config_byte(struct pci_dev *dev, int where, u8 val); | |
937 | int pci_user_write_config_word(struct pci_dev *dev, int where, u16 val); | |
938 | int pci_user_write_config_dword(struct pci_dev *dev, int where, u32 val); | |
939 | ||
4a7fb636 | 940 | int __must_check pci_enable_device(struct pci_dev *dev); |
b718989d BH |
941 | int __must_check pci_enable_device_io(struct pci_dev *dev); |
942 | int __must_check pci_enable_device_mem(struct pci_dev *dev); | |
0b62e13b | 943 | int __must_check pci_reenable_device(struct pci_dev *); |
9ac7849e TH |
944 | int __must_check pcim_enable_device(struct pci_dev *pdev); |
945 | void pcim_pin_device(struct pci_dev *pdev); | |
946 | ||
296ccb08 YS |
947 | static inline int pci_is_enabled(struct pci_dev *pdev) |
948 | { | |
949 | return (atomic_read(&pdev->enable_cnt) > 0); | |
950 | } | |
951 | ||
9ac7849e TH |
952 | static inline int pci_is_managed(struct pci_dev *pdev) |
953 | { | |
954 | return pdev->is_managed; | |
955 | } | |
956 | ||
1da177e4 | 957 | void pci_disable_device(struct pci_dev *dev); |
96c55900 MS |
958 | |
959 | extern unsigned int pcibios_max_latency; | |
1da177e4 | 960 | void pci_set_master(struct pci_dev *dev); |
6a479079 | 961 | void pci_clear_master(struct pci_dev *dev); |
96c55900 | 962 | |
f7bdd12d | 963 | int pci_set_pcie_reset_state(struct pci_dev *dev, enum pcie_reset_state state); |
15ea76d4 | 964 | int pci_set_cacheline_size(struct pci_dev *dev); |
1da177e4 | 965 | #define HAVE_PCI_SET_MWI |
4a7fb636 | 966 | int __must_check pci_set_mwi(struct pci_dev *dev); |
694625c0 | 967 | int pci_try_set_mwi(struct pci_dev *dev); |
1da177e4 | 968 | void pci_clear_mwi(struct pci_dev *dev); |
a04ce0ff | 969 | void pci_intx(struct pci_dev *dev, int enable); |
a2e27787 JK |
970 | bool pci_intx_mask_supported(struct pci_dev *dev); |
971 | bool pci_check_and_mask_intx(struct pci_dev *dev); | |
972 | bool pci_check_and_unmask_intx(struct pci_dev *dev); | |
f5f2b131 | 973 | void pci_msi_off(struct pci_dev *dev); |
4d57cdfa | 974 | int pci_set_dma_max_seg_size(struct pci_dev *dev, unsigned int size); |
59fc67de | 975 | int pci_set_dma_seg_boundary(struct pci_dev *dev, unsigned long mask); |
157e876f | 976 | int pci_wait_for_pending(struct pci_dev *dev, int pos, u16 mask); |
3775a209 | 977 | int pci_wait_for_pending_transaction(struct pci_dev *dev); |
d556ad4b PO |
978 | int pcix_get_max_mmrbc(struct pci_dev *dev); |
979 | int pcix_get_mmrbc(struct pci_dev *dev); | |
980 | int pcix_set_mmrbc(struct pci_dev *dev, int mmrbc); | |
2637e5b5 | 981 | int pcie_get_readrq(struct pci_dev *dev); |
d556ad4b | 982 | int pcie_set_readrq(struct pci_dev *dev, int rq); |
b03e7495 JM |
983 | int pcie_get_mps(struct pci_dev *dev); |
984 | int pcie_set_mps(struct pci_dev *dev, int mps); | |
81377c8d JK |
985 | int pcie_get_minimum_link(struct pci_dev *dev, enum pci_bus_speed *speed, |
986 | enum pcie_link_width *width); | |
8c1c699f | 987 | int __pci_reset_function(struct pci_dev *dev); |
a96d627a | 988 | int __pci_reset_function_locked(struct pci_dev *dev); |
8dd7f803 | 989 | int pci_reset_function(struct pci_dev *dev); |
61cf16d8 | 990 | int pci_try_reset_function(struct pci_dev *dev); |
9a3d2b9b | 991 | int pci_probe_reset_slot(struct pci_slot *slot); |
090a3c53 | 992 | int pci_reset_slot(struct pci_slot *slot); |
61cf16d8 | 993 | int pci_try_reset_slot(struct pci_slot *slot); |
9a3d2b9b | 994 | int pci_probe_reset_bus(struct pci_bus *bus); |
090a3c53 | 995 | int pci_reset_bus(struct pci_bus *bus); |
61cf16d8 | 996 | int pci_try_reset_bus(struct pci_bus *bus); |
9e33002f GS |
997 | void pci_reset_secondary_bus(struct pci_dev *dev); |
998 | void pcibios_reset_secondary_bus(struct pci_dev *dev); | |
64e8674f | 999 | void pci_reset_bridge_secondary_bus(struct pci_dev *dev); |
14add80b | 1000 | void pci_update_resource(struct pci_dev *dev, int resno); |
4a7fb636 | 1001 | int __must_check pci_assign_resource(struct pci_dev *dev, int i); |
2bbc6942 | 1002 | int __must_check pci_reassign_resource(struct pci_dev *dev, int i, resource_size_t add_size, resource_size_t align); |
c87deff7 | 1003 | int pci_select_bars(struct pci_dev *dev, unsigned long flags); |
8496e85c | 1004 | bool pci_device_is_present(struct pci_dev *pdev); |
1da177e4 LT |
1005 | |
1006 | /* ROM control related routines */ | |
e416de5e AC |
1007 | int pci_enable_rom(struct pci_dev *pdev); |
1008 | void pci_disable_rom(struct pci_dev *pdev); | |
144a50ea | 1009 | void __iomem __must_check *pci_map_rom(struct pci_dev *pdev, size_t *size); |
1da177e4 | 1010 | void pci_unmap_rom(struct pci_dev *pdev, void __iomem *rom); |
97c44836 | 1011 | size_t pci_get_rom_size(struct pci_dev *pdev, void __iomem *rom, size_t size); |
fffe01f7 | 1012 | void __iomem __must_check *pci_platform_rom(struct pci_dev *pdev, size_t *size); |
1da177e4 LT |
1013 | |
1014 | /* Power management related routines */ | |
1015 | int pci_save_state(struct pci_dev *dev); | |
1d3c16a8 | 1016 | void pci_restore_state(struct pci_dev *dev); |
ffbdd3f7 | 1017 | struct pci_saved_state *pci_store_saved_state(struct pci_dev *dev); |
98d9b271 KRW |
1018 | int pci_load_saved_state(struct pci_dev *dev, |
1019 | struct pci_saved_state *state); | |
ffbdd3f7 AW |
1020 | int pci_load_and_free_saved_state(struct pci_dev *dev, |
1021 | struct pci_saved_state **state); | |
fd0f7f73 AW |
1022 | struct pci_cap_saved_state *pci_find_saved_cap(struct pci_dev *dev, char cap); |
1023 | struct pci_cap_saved_state *pci_find_saved_ext_cap(struct pci_dev *dev, | |
1024 | u16 cap); | |
1025 | int pci_add_cap_save_buffer(struct pci_dev *dev, char cap, unsigned int size); | |
1026 | int pci_add_ext_cap_save_buffer(struct pci_dev *dev, | |
1027 | u16 cap, unsigned int size); | |
0e5dd46b | 1028 | int __pci_complete_power_transition(struct pci_dev *dev, pci_power_t state); |
9c8550ee LT |
1029 | int pci_set_power_state(struct pci_dev *dev, pci_power_t state); |
1030 | pci_power_t pci_choose_state(struct pci_dev *dev, pm_message_t state); | |
e5899e1b | 1031 | bool pci_pme_capable(struct pci_dev *dev, pci_power_t state); |
5a6c9b60 | 1032 | void pci_pme_active(struct pci_dev *dev, bool enable); |
6cbf8214 RW |
1033 | int __pci_enable_wake(struct pci_dev *dev, pci_power_t state, |
1034 | bool runtime, bool enable); | |
0235c4fc | 1035 | int pci_wake_from_d3(struct pci_dev *dev, bool enable); |
404cc2d8 RW |
1036 | int pci_prepare_to_sleep(struct pci_dev *dev); |
1037 | int pci_back_from_sleep(struct pci_dev *dev); | |
b67ea761 | 1038 | bool pci_dev_run_wake(struct pci_dev *dev); |
bf4d2908 | 1039 | bool pci_check_pme_status(struct pci_dev *dev); |
bf4d2908 | 1040 | void pci_pme_wakeup_bus(struct pci_bus *bus); |
1da177e4 | 1041 | |
b440bde7 BH |
1042 | static inline void pci_ignore_hotplug(struct pci_dev *dev) |
1043 | { | |
1044 | dev->ignore_hotplug = 1; | |
1045 | } | |
1046 | ||
6cbf8214 RW |
1047 | static inline int pci_enable_wake(struct pci_dev *dev, pci_power_t state, |
1048 | bool enable) | |
1049 | { | |
1050 | return __pci_enable_wake(dev, state, false, enable); | |
1051 | } | |
1da177e4 | 1052 | |
425c1b22 AW |
1053 | /* PCI Virtual Channel */ |
1054 | int pci_save_vc_state(struct pci_dev *dev); | |
1055 | void pci_restore_vc_state(struct pci_dev *dev); | |
1056 | void pci_allocate_vc_save_buffers(struct pci_dev *dev); | |
51c2e0a7 | 1057 | |
bb209c82 BH |
1058 | /* For use by arch with custom probe code */ |
1059 | void set_pcie_port_type(struct pci_dev *pdev); | |
1060 | void set_pcie_hotplug_bridge(struct pci_dev *pdev); | |
1061 | ||
ce5ccdef | 1062 | /* Functions for PCI Hotplug drivers to use */ |
05cca6e5 | 1063 | int pci_bus_find_capability(struct pci_bus *bus, unsigned int devfn, int cap); |
2f320521 | 1064 | unsigned int pci_rescan_bus_bridge_resize(struct pci_dev *bridge); |
3ed4fd96 | 1065 | unsigned int pci_rescan_bus(struct pci_bus *bus); |
9d16947b RW |
1066 | void pci_lock_rescan_remove(void); |
1067 | void pci_unlock_rescan_remove(void); | |
ce5ccdef | 1068 | |
287d19ce SH |
1069 | /* Vital product data routines */ |
1070 | ssize_t pci_read_vpd(struct pci_dev *dev, loff_t pos, size_t count, void *buf); | |
1071 | ssize_t pci_write_vpd(struct pci_dev *dev, loff_t pos, size_t count, const void *buf); | |
1072 | ||
1da177e4 | 1073 | /* Helper functions for low-level code (drivers/pci/setup-[bus,res].c) */ |
925845bd | 1074 | resource_size_t pcibios_retrieve_fw_addr(struct pci_dev *dev, int idx); |
ea741551 | 1075 | void pci_bus_assign_resources(const struct pci_bus *bus); |
1da177e4 LT |
1076 | void pci_bus_size_bridges(struct pci_bus *bus); |
1077 | int pci_claim_resource(struct pci_dev *, int); | |
8505e729 | 1078 | int pci_claim_bridge_resource(struct pci_dev *bridge, int i); |
1da177e4 | 1079 | void pci_assign_unassigned_resources(void); |
6841ec68 | 1080 | void pci_assign_unassigned_bridge_resources(struct pci_dev *bridge); |
17787940 | 1081 | void pci_assign_unassigned_bus_resources(struct pci_bus *bus); |
39772038 | 1082 | void pci_assign_unassigned_root_bus_resources(struct pci_bus *bus); |
1da177e4 | 1083 | void pdev_enable_device(struct pci_dev *); |
842de40d | 1084 | int pci_enable_resources(struct pci_dev *, int mask); |
1da177e4 | 1085 | void pci_fixup_irqs(u8 (*)(struct pci_dev *, u8 *), |
d5341942 | 1086 | int (*)(const struct pci_dev *, u8, u8)); |
1da177e4 | 1087 | #define HAVE_PCI_REQ_REGIONS 2 |
4a7fb636 | 1088 | int __must_check pci_request_regions(struct pci_dev *, const char *); |
e8de1481 | 1089 | int __must_check pci_request_regions_exclusive(struct pci_dev *, const char *); |
1da177e4 | 1090 | void pci_release_regions(struct pci_dev *); |
4a7fb636 | 1091 | int __must_check pci_request_region(struct pci_dev *, int, const char *); |
e8de1481 | 1092 | int __must_check pci_request_region_exclusive(struct pci_dev *, int, const char *); |
1da177e4 | 1093 | void pci_release_region(struct pci_dev *, int); |
c87deff7 | 1094 | int pci_request_selected_regions(struct pci_dev *, int, const char *); |
e8de1481 | 1095 | int pci_request_selected_regions_exclusive(struct pci_dev *, int, const char *); |
c87deff7 | 1096 | void pci_release_selected_regions(struct pci_dev *, int); |
1da177e4 LT |
1097 | |
1098 | /* drivers/pci/bus.c */ | |
fe830ef6 JL |
1099 | struct pci_bus *pci_bus_get(struct pci_bus *bus); |
1100 | void pci_bus_put(struct pci_bus *bus); | |
45ca9e97 | 1101 | void pci_add_resource(struct list_head *resources, struct resource *res); |
0efd5aab BH |
1102 | void pci_add_resource_offset(struct list_head *resources, struct resource *res, |
1103 | resource_size_t offset); | |
45ca9e97 | 1104 | void pci_free_resource_list(struct list_head *resources); |
2fe2abf8 BH |
1105 | void pci_bus_add_resource(struct pci_bus *bus, struct resource *res, unsigned int flags); |
1106 | struct resource *pci_bus_resource_n(const struct pci_bus *bus, int n); | |
1107 | void pci_bus_remove_resources(struct pci_bus *bus); | |
1108 | ||
89a74ecc | 1109 | #define pci_bus_for_each_resource(bus, res, i) \ |
2fe2abf8 BH |
1110 | for (i = 0; \ |
1111 | (res = pci_bus_resource_n(bus, i)) || i < PCI_BRIDGE_RESOURCE_NUM; \ | |
1112 | i++) | |
89a74ecc | 1113 | |
4a7fb636 AM |
1114 | int __must_check pci_bus_alloc_resource(struct pci_bus *bus, |
1115 | struct resource *res, resource_size_t size, | |
1116 | resource_size_t align, resource_size_t min, | |
664c2848 | 1117 | unsigned long type_mask, |
3b7a17fc DB |
1118 | resource_size_t (*alignf)(void *, |
1119 | const struct resource *, | |
b26b2d49 DB |
1120 | resource_size_t, |
1121 | resource_size_t), | |
4a7fb636 | 1122 | void *alignf_data); |
1da177e4 | 1123 | |
8b921acf LD |
1124 | |
1125 | int pci_remap_iospace(const struct resource *res, phys_addr_t phys_addr); | |
1126 | ||
06cf56e4 BH |
1127 | static inline dma_addr_t pci_bus_address(struct pci_dev *pdev, int bar) |
1128 | { | |
1129 | struct pci_bus_region region; | |
1130 | ||
1131 | pcibios_resource_to_bus(pdev->bus, ®ion, &pdev->resource[bar]); | |
1132 | return region.start; | |
1133 | } | |
1134 | ||
863b18f4 | 1135 | /* Proper probing supporting hot-pluggable devices */ |
725522b5 GKH |
1136 | int __must_check __pci_register_driver(struct pci_driver *, struct module *, |
1137 | const char *mod_name); | |
bba81165 AM |
1138 | |
1139 | /* | |
1140 | * pci_register_driver must be a macro so that KBUILD_MODNAME can be expanded | |
1141 | */ | |
1142 | #define pci_register_driver(driver) \ | |
1143 | __pci_register_driver(driver, THIS_MODULE, KBUILD_MODNAME) | |
863b18f4 | 1144 | |
05cca6e5 | 1145 | void pci_unregister_driver(struct pci_driver *dev); |
aad4f400 GKH |
1146 | |
1147 | /** | |
1148 | * module_pci_driver() - Helper macro for registering a PCI driver | |
1149 | * @__pci_driver: pci_driver struct | |
1150 | * | |
1151 | * Helper macro for PCI drivers which do not do anything special in module | |
1152 | * init/exit. This eliminates a lot of boilerplate. Each module may only | |
1153 | * use this macro once, and calling it replaces module_init() and module_exit() | |
1154 | */ | |
1155 | #define module_pci_driver(__pci_driver) \ | |
1156 | module_driver(__pci_driver, pci_register_driver, \ | |
1157 | pci_unregister_driver) | |
1158 | ||
05cca6e5 | 1159 | struct pci_driver *pci_dev_driver(const struct pci_dev *dev); |
9dba910e TH |
1160 | int pci_add_dynid(struct pci_driver *drv, |
1161 | unsigned int vendor, unsigned int device, | |
1162 | unsigned int subvendor, unsigned int subdevice, | |
1163 | unsigned int class, unsigned int class_mask, | |
1164 | unsigned long driver_data); | |
05cca6e5 GKH |
1165 | const struct pci_device_id *pci_match_id(const struct pci_device_id *ids, |
1166 | struct pci_dev *dev); | |
1167 | int pci_scan_bridge(struct pci_bus *bus, struct pci_dev *dev, int max, | |
1168 | int pass); | |
1da177e4 | 1169 | |
70298c6e | 1170 | void pci_walk_bus(struct pci_bus *top, int (*cb)(struct pci_dev *, void *), |
cecf4864 | 1171 | void *userdata); |
ac7dc65a | 1172 | int pci_cfg_space_size(struct pci_dev *dev); |
05cca6e5 | 1173 | unsigned char pci_bus_max_busnr(struct pci_bus *bus); |
e2444273 | 1174 | void pci_setup_bridge(struct pci_bus *bus); |
ac5ad93e GS |
1175 | resource_size_t pcibios_window_alignment(struct pci_bus *bus, |
1176 | unsigned long type); | |
cecf4864 | 1177 | |
3448a19d DA |
1178 | #define PCI_VGA_STATE_CHANGE_BRIDGE (1 << 0) |
1179 | #define PCI_VGA_STATE_CHANGE_DECODES (1 << 1) | |
1180 | ||
deb2d2ec | 1181 | int pci_set_vga_state(struct pci_dev *pdev, bool decode, |
3448a19d | 1182 | unsigned int command_bits, u32 flags); |
1da177e4 LT |
1183 | /* kmem_cache style wrapper around pci_alloc_consistent() */ |
1184 | ||
f41b1771 | 1185 | #include <linux/pci-dma.h> |
1da177e4 LT |
1186 | #include <linux/dmapool.h> |
1187 | ||
1188 | #define pci_pool dma_pool | |
1189 | #define pci_pool_create(name, pdev, size, align, allocation) \ | |
1190 | dma_pool_create(name, &pdev->dev, size, align, allocation) | |
1191 | #define pci_pool_destroy(pool) dma_pool_destroy(pool) | |
1192 | #define pci_pool_alloc(pool, flags, handle) dma_pool_alloc(pool, flags, handle) | |
1193 | #define pci_pool_free(pool, vaddr, addr) dma_pool_free(pool, vaddr, addr) | |
1194 | ||
e24c2d96 DM |
1195 | enum pci_dma_burst_strategy { |
1196 | PCI_DMA_BURST_INFINITY, /* make bursts as large as possible, | |
1197 | strategy_parameter is N/A */ | |
1198 | PCI_DMA_BURST_BOUNDARY, /* disconnect at every strategy_parameter | |
1199 | byte boundaries */ | |
1200 | PCI_DMA_BURST_MULTIPLE, /* disconnect at some multiple of | |
1201 | strategy_parameter byte boundaries */ | |
1202 | }; | |
1203 | ||
1da177e4 | 1204 | struct msix_entry { |
16dbef4a | 1205 | u32 vector; /* kernel uses to write allocated vector */ |
1da177e4 LT |
1206 | u16 entry; /* driver uses to specify entry, OS writes */ |
1207 | }; | |
1208 | ||
0366f8f7 | 1209 | |
4c859804 BH |
1210 | #ifdef CONFIG_PCI_MSI |
1211 | int pci_msi_vec_count(struct pci_dev *dev); | |
f39d5b72 BH |
1212 | void pci_msi_shutdown(struct pci_dev *dev); |
1213 | void pci_disable_msi(struct pci_dev *dev); | |
4c859804 | 1214 | int pci_msix_vec_count(struct pci_dev *dev); |
f39d5b72 BH |
1215 | int pci_enable_msix(struct pci_dev *dev, struct msix_entry *entries, int nvec); |
1216 | void pci_msix_shutdown(struct pci_dev *dev); | |
1217 | void pci_disable_msix(struct pci_dev *dev); | |
f39d5b72 BH |
1218 | void pci_restore_msi_state(struct pci_dev *dev); |
1219 | int pci_msi_enabled(void); | |
4c859804 | 1220 | int pci_enable_msi_range(struct pci_dev *dev, int minvec, int maxvec); |
f7fc32cb AG |
1221 | static inline int pci_enable_msi_exact(struct pci_dev *dev, int nvec) |
1222 | { | |
1223 | int rc = pci_enable_msi_range(dev, nvec, nvec); | |
1224 | if (rc < 0) | |
1225 | return rc; | |
1226 | return 0; | |
1227 | } | |
4c859804 BH |
1228 | int pci_enable_msix_range(struct pci_dev *dev, struct msix_entry *entries, |
1229 | int minvec, int maxvec); | |
f7fc32cb AG |
1230 | static inline int pci_enable_msix_exact(struct pci_dev *dev, |
1231 | struct msix_entry *entries, int nvec) | |
1232 | { | |
1233 | int rc = pci_enable_msix_range(dev, entries, nvec, nvec); | |
1234 | if (rc < 0) | |
1235 | return rc; | |
1236 | return 0; | |
1237 | } | |
4c859804 | 1238 | #else |
2ee546c4 | 1239 | static inline int pci_msi_vec_count(struct pci_dev *dev) { return -ENOSYS; } |
2ee546c4 BH |
1240 | static inline void pci_msi_shutdown(struct pci_dev *dev) { } |
1241 | static inline void pci_disable_msi(struct pci_dev *dev) { } | |
1242 | static inline int pci_msix_vec_count(struct pci_dev *dev) { return -ENOSYS; } | |
05cca6e5 GKH |
1243 | static inline int pci_enable_msix(struct pci_dev *dev, |
1244 | struct msix_entry *entries, int nvec) | |
2ee546c4 BH |
1245 | { return -ENOSYS; } |
1246 | static inline void pci_msix_shutdown(struct pci_dev *dev) { } | |
1247 | static inline void pci_disable_msix(struct pci_dev *dev) { } | |
2ee546c4 BH |
1248 | static inline void pci_restore_msi_state(struct pci_dev *dev) { } |
1249 | static inline int pci_msi_enabled(void) { return 0; } | |
302a2523 AG |
1250 | static inline int pci_enable_msi_range(struct pci_dev *dev, int minvec, |
1251 | int maxvec) | |
2ee546c4 | 1252 | { return -ENOSYS; } |
f7fc32cb AG |
1253 | static inline int pci_enable_msi_exact(struct pci_dev *dev, int nvec) |
1254 | { return -ENOSYS; } | |
302a2523 AG |
1255 | static inline int pci_enable_msix_range(struct pci_dev *dev, |
1256 | struct msix_entry *entries, int minvec, int maxvec) | |
2ee546c4 | 1257 | { return -ENOSYS; } |
f7fc32cb AG |
1258 | static inline int pci_enable_msix_exact(struct pci_dev *dev, |
1259 | struct msix_entry *entries, int nvec) | |
1260 | { return -ENOSYS; } | |
1da177e4 LT |
1261 | #endif |
1262 | ||
ab0724ff | 1263 | #ifdef CONFIG_PCIEPORTBUS |
415e12b2 RW |
1264 | extern bool pcie_ports_disabled; |
1265 | extern bool pcie_ports_auto; | |
ab0724ff MT |
1266 | #else |
1267 | #define pcie_ports_disabled true | |
1268 | #define pcie_ports_auto false | |
1269 | #endif | |
415e12b2 | 1270 | |
4c859804 | 1271 | #ifdef CONFIG_PCIEASPM |
f39d5b72 | 1272 | bool pcie_aspm_support_enabled(void); |
4c859804 BH |
1273 | #else |
1274 | static inline bool pcie_aspm_support_enabled(void) { return false; } | |
3e1b1600 AP |
1275 | #endif |
1276 | ||
415e12b2 RW |
1277 | #ifdef CONFIG_PCIEAER |
1278 | void pci_no_aer(void); | |
1279 | bool pci_aer_available(void); | |
1280 | #else | |
1281 | static inline void pci_no_aer(void) { } | |
1282 | static inline bool pci_aer_available(void) { return false; } | |
1283 | #endif | |
1284 | ||
4c859804 | 1285 | #ifdef CONFIG_PCIE_ECRC |
f39d5b72 BH |
1286 | void pcie_set_ecrc_checking(struct pci_dev *dev); |
1287 | void pcie_ecrc_get_policy(char *str); | |
4c859804 | 1288 | #else |
2ee546c4 BH |
1289 | static inline void pcie_set_ecrc_checking(struct pci_dev *dev) { } |
1290 | static inline void pcie_ecrc_get_policy(char *str) { } | |
43c16408 AP |
1291 | #endif |
1292 | ||
034cd97e | 1293 | #define pci_enable_msi(pdev) pci_enable_msi_exact(pdev, 1) |
1c8d7b0a | 1294 | |
8b955b0d | 1295 | #ifdef CONFIG_HT_IRQ |
8b955b0d EB |
1296 | /* The functions a driver should call */ |
1297 | int ht_create_irq(struct pci_dev *dev, int idx); | |
1298 | void ht_destroy_irq(unsigned int irq); | |
8b955b0d EB |
1299 | #endif /* CONFIG_HT_IRQ */ |
1300 | ||
f39d5b72 BH |
1301 | void pci_cfg_access_lock(struct pci_dev *dev); |
1302 | bool pci_cfg_access_trylock(struct pci_dev *dev); | |
1303 | void pci_cfg_access_unlock(struct pci_dev *dev); | |
e04b0ea2 | 1304 | |
4352dfd5 GKH |
1305 | /* |
1306 | * PCI domain support. Sometimes called PCI segment (eg by ACPI), | |
f7625980 | 1307 | * a PCI domain is defined to be a set of PCI buses which share |
4352dfd5 GKH |
1308 | * configuration space. |
1309 | */ | |
32a2eea7 JG |
1310 | #ifdef CONFIG_PCI_DOMAINS |
1311 | extern int pci_domains_supported; | |
41e5c0f8 | 1312 | int pci_get_new_domain_nr(void); |
32a2eea7 JG |
1313 | #else |
1314 | enum { pci_domains_supported = 0 }; | |
2ee546c4 BH |
1315 | static inline int pci_domain_nr(struct pci_bus *bus) { return 0; } |
1316 | static inline int pci_proc_domain(struct pci_bus *bus) { return 0; } | |
41e5c0f8 | 1317 | static inline int pci_get_new_domain_nr(void) { return -ENOSYS; } |
32a2eea7 | 1318 | #endif /* CONFIG_PCI_DOMAINS */ |
1da177e4 | 1319 | |
670ba0c8 CM |
1320 | /* |
1321 | * Generic implementation for PCI domain support. If your | |
1322 | * architecture does not need custom management of PCI | |
1323 | * domains then this implementation will be used | |
1324 | */ | |
1325 | #ifdef CONFIG_PCI_DOMAINS_GENERIC | |
1326 | static inline int pci_domain_nr(struct pci_bus *bus) | |
1327 | { | |
1328 | return bus->domain_nr; | |
1329 | } | |
1330 | void pci_bus_assign_domain_nr(struct pci_bus *bus, struct device *parent); | |
1331 | #else | |
1332 | static inline void pci_bus_assign_domain_nr(struct pci_bus *bus, | |
1333 | struct device *parent) | |
1334 | { | |
1335 | } | |
1336 | #endif | |
1337 | ||
95a8b6ef MT |
1338 | /* some architectures require additional setup to direct VGA traffic */ |
1339 | typedef int (*arch_set_vga_state_t)(struct pci_dev *pdev, bool decode, | |
3448a19d | 1340 | unsigned int command_bits, u32 flags); |
f39d5b72 | 1341 | void pci_register_set_vga_state(arch_set_vga_state_t func); |
95a8b6ef | 1342 | |
4352dfd5 | 1343 | #else /* CONFIG_PCI is not enabled */ |
1da177e4 LT |
1344 | |
1345 | /* | |
1346 | * If the system does not have PCI, clearly these return errors. Define | |
1347 | * these as simple inline functions to avoid hair in drivers. | |
1348 | */ | |
1349 | ||
05cca6e5 GKH |
1350 | #define _PCI_NOP(o, s, t) \ |
1351 | static inline int pci_##o##_config_##s(struct pci_dev *dev, \ | |
1352 | int where, t val) \ | |
1da177e4 | 1353 | { return PCIBIOS_FUNC_NOT_SUPPORTED; } |
05cca6e5 GKH |
1354 | |
1355 | #define _PCI_NOP_ALL(o, x) _PCI_NOP(o, byte, u8 x) \ | |
1356 | _PCI_NOP(o, word, u16 x) \ | |
1357 | _PCI_NOP(o, dword, u32 x) | |
1da177e4 LT |
1358 | _PCI_NOP_ALL(read, *) |
1359 | _PCI_NOP_ALL(write,) | |
1360 | ||
d42552c3 | 1361 | static inline struct pci_dev *pci_get_device(unsigned int vendor, |
05cca6e5 GKH |
1362 | unsigned int device, |
1363 | struct pci_dev *from) | |
2ee546c4 | 1364 | { return NULL; } |
d42552c3 | 1365 | |
05cca6e5 GKH |
1366 | static inline struct pci_dev *pci_get_subsys(unsigned int vendor, |
1367 | unsigned int device, | |
1368 | unsigned int ss_vendor, | |
1369 | unsigned int ss_device, | |
b08508c4 | 1370 | struct pci_dev *from) |
2ee546c4 | 1371 | { return NULL; } |
1da177e4 | 1372 | |
05cca6e5 GKH |
1373 | static inline struct pci_dev *pci_get_class(unsigned int class, |
1374 | struct pci_dev *from) | |
2ee546c4 | 1375 | { return NULL; } |
1da177e4 LT |
1376 | |
1377 | #define pci_dev_present(ids) (0) | |
ed4aaadb | 1378 | #define no_pci_devices() (1) |
1da177e4 LT |
1379 | #define pci_dev_put(dev) do { } while (0) |
1380 | ||
2ee546c4 BH |
1381 | static inline void pci_set_master(struct pci_dev *dev) { } |
1382 | static inline int pci_enable_device(struct pci_dev *dev) { return -EIO; } | |
1383 | static inline void pci_disable_device(struct pci_dev *dev) { } | |
05cca6e5 | 1384 | static inline int pci_set_dma_mask(struct pci_dev *dev, u64 mask) |
2ee546c4 | 1385 | { return -EIO; } |
80be0385 | 1386 | static inline int pci_set_consistent_dma_mask(struct pci_dev *dev, u64 mask) |
2ee546c4 | 1387 | { return -EIO; } |
4d57cdfa FT |
1388 | static inline int pci_set_dma_max_seg_size(struct pci_dev *dev, |
1389 | unsigned int size) | |
2ee546c4 | 1390 | { return -EIO; } |
59fc67de FT |
1391 | static inline int pci_set_dma_seg_boundary(struct pci_dev *dev, |
1392 | unsigned long mask) | |
2ee546c4 | 1393 | { return -EIO; } |
05cca6e5 | 1394 | static inline int pci_assign_resource(struct pci_dev *dev, int i) |
2ee546c4 | 1395 | { return -EBUSY; } |
05cca6e5 GKH |
1396 | static inline int __pci_register_driver(struct pci_driver *drv, |
1397 | struct module *owner) | |
2ee546c4 | 1398 | { return 0; } |
05cca6e5 | 1399 | static inline int pci_register_driver(struct pci_driver *drv) |
2ee546c4 BH |
1400 | { return 0; } |
1401 | static inline void pci_unregister_driver(struct pci_driver *drv) { } | |
05cca6e5 | 1402 | static inline int pci_find_capability(struct pci_dev *dev, int cap) |
2ee546c4 | 1403 | { return 0; } |
05cca6e5 GKH |
1404 | static inline int pci_find_next_capability(struct pci_dev *dev, u8 post, |
1405 | int cap) | |
2ee546c4 | 1406 | { return 0; } |
05cca6e5 | 1407 | static inline int pci_find_ext_capability(struct pci_dev *dev, int cap) |
2ee546c4 | 1408 | { return 0; } |
05cca6e5 | 1409 | |
1da177e4 | 1410 | /* Power management related routines */ |
2ee546c4 BH |
1411 | static inline int pci_save_state(struct pci_dev *dev) { return 0; } |
1412 | static inline void pci_restore_state(struct pci_dev *dev) { } | |
05cca6e5 | 1413 | static inline int pci_set_power_state(struct pci_dev *dev, pci_power_t state) |
2ee546c4 | 1414 | { return 0; } |
3449248c | 1415 | static inline int pci_wake_from_d3(struct pci_dev *dev, bool enable) |
2ee546c4 | 1416 | { return 0; } |
05cca6e5 GKH |
1417 | static inline pci_power_t pci_choose_state(struct pci_dev *dev, |
1418 | pm_message_t state) | |
2ee546c4 | 1419 | { return PCI_D0; } |
05cca6e5 GKH |
1420 | static inline int pci_enable_wake(struct pci_dev *dev, pci_power_t state, |
1421 | int enable) | |
2ee546c4 | 1422 | { return 0; } |
48a92a81 | 1423 | |
05cca6e5 | 1424 | static inline int pci_request_regions(struct pci_dev *dev, const char *res_name) |
2ee546c4 BH |
1425 | { return -EIO; } |
1426 | static inline void pci_release_regions(struct pci_dev *dev) { } | |
0da0ead9 | 1427 | |
a46e8126 KG |
1428 | #define pci_dma_burst_advice(pdev, strat, strategy_parameter) do { } while (0) |
1429 | ||
2ee546c4 | 1430 | static inline void pci_block_cfg_access(struct pci_dev *dev) { } |
fb51ccbf JK |
1431 | static inline int pci_block_cfg_access_in_atomic(struct pci_dev *dev) |
1432 | { return 0; } | |
2ee546c4 | 1433 | static inline void pci_unblock_cfg_access(struct pci_dev *dev) { } |
e04b0ea2 | 1434 | |
d80d0217 RD |
1435 | static inline struct pci_bus *pci_find_next_bus(const struct pci_bus *from) |
1436 | { return NULL; } | |
d80d0217 RD |
1437 | static inline struct pci_dev *pci_get_slot(struct pci_bus *bus, |
1438 | unsigned int devfn) | |
1439 | { return NULL; } | |
d80d0217 RD |
1440 | static inline struct pci_dev *pci_get_bus_and_slot(unsigned int bus, |
1441 | unsigned int devfn) | |
1442 | { return NULL; } | |
1443 | ||
2ee546c4 BH |
1444 | static inline int pci_domain_nr(struct pci_bus *bus) { return 0; } |
1445 | static inline struct pci_dev *pci_dev_get(struct pci_dev *dev) { return NULL; } | |
41e5c0f8 | 1446 | static inline int pci_get_new_domain_nr(void) { return -ENOSYS; } |
12ea6cad | 1447 | |
fb8a0d9d WM |
1448 | #define dev_is_pci(d) (false) |
1449 | #define dev_is_pf(d) (false) | |
1450 | #define dev_num_vf(d) (0) | |
4352dfd5 | 1451 | #endif /* CONFIG_PCI */ |
1da177e4 | 1452 | |
4352dfd5 GKH |
1453 | /* Include architecture-dependent settings and functions */ |
1454 | ||
1455 | #include <asm/pci.h> | |
1da177e4 LT |
1456 | |
1457 | /* these helpers provide future and backwards compatibility | |
1458 | * for accessing popular PCI BAR info */ | |
05cca6e5 GKH |
1459 | #define pci_resource_start(dev, bar) ((dev)->resource[(bar)].start) |
1460 | #define pci_resource_end(dev, bar) ((dev)->resource[(bar)].end) | |
1461 | #define pci_resource_flags(dev, bar) ((dev)->resource[(bar)].flags) | |
1da177e4 | 1462 | #define pci_resource_len(dev,bar) \ |
05cca6e5 GKH |
1463 | ((pci_resource_start((dev), (bar)) == 0 && \ |
1464 | pci_resource_end((dev), (bar)) == \ | |
1465 | pci_resource_start((dev), (bar))) ? 0 : \ | |
1466 | \ | |
1467 | (pci_resource_end((dev), (bar)) - \ | |
1468 | pci_resource_start((dev), (bar)) + 1)) | |
1da177e4 LT |
1469 | |
1470 | /* Similar to the helpers above, these manipulate per-pci_dev | |
1471 | * driver-specific data. They are really just a wrapper around | |
1472 | * the generic device structure functions of these calls. | |
1473 | */ | |
05cca6e5 | 1474 | static inline void *pci_get_drvdata(struct pci_dev *pdev) |
1da177e4 LT |
1475 | { |
1476 | return dev_get_drvdata(&pdev->dev); | |
1477 | } | |
1478 | ||
05cca6e5 | 1479 | static inline void pci_set_drvdata(struct pci_dev *pdev, void *data) |
1da177e4 LT |
1480 | { |
1481 | dev_set_drvdata(&pdev->dev, data); | |
1482 | } | |
1483 | ||
1484 | /* If you want to know what to call your pci_dev, ask this function. | |
1485 | * Again, it's a wrapper around the generic device. | |
1486 | */ | |
2fc90f61 | 1487 | static inline const char *pci_name(const struct pci_dev *pdev) |
1da177e4 | 1488 | { |
c6c4f070 | 1489 | return dev_name(&pdev->dev); |
1da177e4 LT |
1490 | } |
1491 | ||
2311b1f2 ME |
1492 | |
1493 | /* Some archs don't want to expose struct resource to userland as-is | |
1494 | * in sysfs and /proc | |
1495 | */ | |
1496 | #ifndef HAVE_ARCH_PCI_RESOURCE_TO_USER | |
1497 | static inline void pci_resource_to_user(const struct pci_dev *dev, int bar, | |
05cca6e5 | 1498 | const struct resource *rsrc, resource_size_t *start, |
e31dd6e4 | 1499 | resource_size_t *end) |
2311b1f2 ME |
1500 | { |
1501 | *start = rsrc->start; | |
1502 | *end = rsrc->end; | |
1503 | } | |
1504 | #endif /* HAVE_ARCH_PCI_RESOURCE_TO_USER */ | |
1505 | ||
1506 | ||
1da177e4 LT |
1507 | /* |
1508 | * The world is not perfect and supplies us with broken PCI devices. | |
1509 | * For at least a part of these bugs we need a work-around, so both | |
1510 | * generic (drivers/pci/quirks.c) and per-architecture code can define | |
1511 | * fixup hooks to be called for particular buggy devices. | |
1512 | */ | |
1513 | ||
1514 | struct pci_fixup { | |
f4ca5c6a YL |
1515 | u16 vendor; /* You can use PCI_ANY_ID here of course */ |
1516 | u16 device; /* You can use PCI_ANY_ID here of course */ | |
1517 | u32 class; /* You can use PCI_ANY_ID here too */ | |
1518 | unsigned int class_shift; /* should be 0, 8, 16 */ | |
1da177e4 LT |
1519 | void (*hook)(struct pci_dev *dev); |
1520 | }; | |
1521 | ||
1522 | enum pci_fixup_pass { | |
1523 | pci_fixup_early, /* Before probing BARs */ | |
1524 | pci_fixup_header, /* After reading configuration header */ | |
1525 | pci_fixup_final, /* Final phase of device fixups */ | |
1526 | pci_fixup_enable, /* pci_enable_device() time */ | |
e1a2a51e | 1527 | pci_fixup_resume, /* pci_device_resume() */ |
7d2a01b8 | 1528 | pci_fixup_suspend, /* pci_device_suspend() */ |
e1a2a51e | 1529 | pci_fixup_resume_early, /* pci_device_resume_early() */ |
7d2a01b8 | 1530 | pci_fixup_suspend_late, /* pci_device_suspend_late() */ |
1da177e4 LT |
1531 | }; |
1532 | ||
1533 | /* Anonymous variables would be nice... */ | |
f4ca5c6a YL |
1534 | #define DECLARE_PCI_FIXUP_SECTION(section, name, vendor, device, class, \ |
1535 | class_shift, hook) \ | |
ecf61c78 | 1536 | static const struct pci_fixup __PASTE(__pci_fixup_##name,__LINE__) __used \ |
f4ca5c6a YL |
1537 | __attribute__((__section__(#section), aligned((sizeof(void *))))) \ |
1538 | = { vendor, device, class, class_shift, hook }; | |
1539 | ||
1540 | #define DECLARE_PCI_FIXUP_CLASS_EARLY(vendor, device, class, \ | |
1541 | class_shift, hook) \ | |
1542 | DECLARE_PCI_FIXUP_SECTION(.pci_fixup_early, \ | |
ecf61c78 | 1543 | hook, vendor, device, class, class_shift, hook) |
f4ca5c6a YL |
1544 | #define DECLARE_PCI_FIXUP_CLASS_HEADER(vendor, device, class, \ |
1545 | class_shift, hook) \ | |
1546 | DECLARE_PCI_FIXUP_SECTION(.pci_fixup_header, \ | |
ecf61c78 | 1547 | hook, vendor, device, class, class_shift, hook) |
f4ca5c6a YL |
1548 | #define DECLARE_PCI_FIXUP_CLASS_FINAL(vendor, device, class, \ |
1549 | class_shift, hook) \ | |
1550 | DECLARE_PCI_FIXUP_SECTION(.pci_fixup_final, \ | |
ecf61c78 | 1551 | hook, vendor, device, class, class_shift, hook) |
f4ca5c6a YL |
1552 | #define DECLARE_PCI_FIXUP_CLASS_ENABLE(vendor, device, class, \ |
1553 | class_shift, hook) \ | |
1554 | DECLARE_PCI_FIXUP_SECTION(.pci_fixup_enable, \ | |
ecf61c78 | 1555 | hook, vendor, device, class, class_shift, hook) |
f4ca5c6a YL |
1556 | #define DECLARE_PCI_FIXUP_CLASS_RESUME(vendor, device, class, \ |
1557 | class_shift, hook) \ | |
1558 | DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume, \ | |
ecf61c78 | 1559 | resume##hook, vendor, device, class, \ |
f4ca5c6a YL |
1560 | class_shift, hook) |
1561 | #define DECLARE_PCI_FIXUP_CLASS_RESUME_EARLY(vendor, device, class, \ | |
1562 | class_shift, hook) \ | |
1563 | DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume_early, \ | |
ecf61c78 | 1564 | resume_early##hook, vendor, device, \ |
f4ca5c6a YL |
1565 | class, class_shift, hook) |
1566 | #define DECLARE_PCI_FIXUP_CLASS_SUSPEND(vendor, device, class, \ | |
1567 | class_shift, hook) \ | |
1568 | DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend, \ | |
ecf61c78 | 1569 | suspend##hook, vendor, device, class, \ |
f4ca5c6a | 1570 | class_shift, hook) |
7d2a01b8 AN |
1571 | #define DECLARE_PCI_FIXUP_CLASS_SUSPEND_LATE(vendor, device, class, \ |
1572 | class_shift, hook) \ | |
1573 | DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend_late, \ | |
1574 | suspend_late##hook, vendor, device, \ | |
1575 | class, class_shift, hook) | |
f4ca5c6a | 1576 | |
1da177e4 LT |
1577 | #define DECLARE_PCI_FIXUP_EARLY(vendor, device, hook) \ |
1578 | DECLARE_PCI_FIXUP_SECTION(.pci_fixup_early, \ | |
ecf61c78 | 1579 | hook, vendor, device, PCI_ANY_ID, 0, hook) |
1da177e4 LT |
1580 | #define DECLARE_PCI_FIXUP_HEADER(vendor, device, hook) \ |
1581 | DECLARE_PCI_FIXUP_SECTION(.pci_fixup_header, \ | |
ecf61c78 | 1582 | hook, vendor, device, PCI_ANY_ID, 0, hook) |
1da177e4 LT |
1583 | #define DECLARE_PCI_FIXUP_FINAL(vendor, device, hook) \ |
1584 | DECLARE_PCI_FIXUP_SECTION(.pci_fixup_final, \ | |
ecf61c78 | 1585 | hook, vendor, device, PCI_ANY_ID, 0, hook) |
1da177e4 LT |
1586 | #define DECLARE_PCI_FIXUP_ENABLE(vendor, device, hook) \ |
1587 | DECLARE_PCI_FIXUP_SECTION(.pci_fixup_enable, \ | |
ecf61c78 | 1588 | hook, vendor, device, PCI_ANY_ID, 0, hook) |
1597cacb AC |
1589 | #define DECLARE_PCI_FIXUP_RESUME(vendor, device, hook) \ |
1590 | DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume, \ | |
ecf61c78 | 1591 | resume##hook, vendor, device, \ |
f4ca5c6a | 1592 | PCI_ANY_ID, 0, hook) |
e1a2a51e RW |
1593 | #define DECLARE_PCI_FIXUP_RESUME_EARLY(vendor, device, hook) \ |
1594 | DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume_early, \ | |
ecf61c78 | 1595 | resume_early##hook, vendor, device, \ |
f4ca5c6a | 1596 | PCI_ANY_ID, 0, hook) |
e1a2a51e RW |
1597 | #define DECLARE_PCI_FIXUP_SUSPEND(vendor, device, hook) \ |
1598 | DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend, \ | |
ecf61c78 | 1599 | suspend##hook, vendor, device, \ |
f4ca5c6a | 1600 | PCI_ANY_ID, 0, hook) |
7d2a01b8 AN |
1601 | #define DECLARE_PCI_FIXUP_SUSPEND_LATE(vendor, device, hook) \ |
1602 | DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend_late, \ | |
1603 | suspend_late##hook, vendor, device, \ | |
1604 | PCI_ANY_ID, 0, hook) | |
1da177e4 | 1605 | |
93177a74 | 1606 | #ifdef CONFIG_PCI_QUIRKS |
1da177e4 | 1607 | void pci_fixup_device(enum pci_fixup_pass pass, struct pci_dev *dev); |
ad805758 | 1608 | int pci_dev_specific_acs_enabled(struct pci_dev *dev, u16 acs_flags); |
2c744244 | 1609 | void pci_dev_specific_enable_acs(struct pci_dev *dev); |
93177a74 RW |
1610 | #else |
1611 | static inline void pci_fixup_device(enum pci_fixup_pass pass, | |
2ee546c4 | 1612 | struct pci_dev *dev) { } |
ad805758 AW |
1613 | static inline int pci_dev_specific_acs_enabled(struct pci_dev *dev, |
1614 | u16 acs_flags) | |
1615 | { | |
1616 | return -ENOTTY; | |
1617 | } | |
2c744244 | 1618 | static inline void pci_dev_specific_enable_acs(struct pci_dev *dev) { } |
93177a74 | 1619 | #endif |
1da177e4 | 1620 | |
05cca6e5 | 1621 | void __iomem *pcim_iomap(struct pci_dev *pdev, int bar, unsigned long maxlen); |
5ea81769 | 1622 | void pcim_iounmap(struct pci_dev *pdev, void __iomem *addr); |
05cca6e5 | 1623 | void __iomem * const *pcim_iomap_table(struct pci_dev *pdev); |
fb7ebfe4 YL |
1624 | int pcim_iomap_regions(struct pci_dev *pdev, int mask, const char *name); |
1625 | int pcim_iomap_regions_request_all(struct pci_dev *pdev, int mask, | |
916fbfb7 | 1626 | const char *name); |
fb7ebfe4 | 1627 | void pcim_iounmap_regions(struct pci_dev *pdev, int mask); |
5ea81769 | 1628 | |
1da177e4 | 1629 | extern int pci_pci_problems; |
236561e5 | 1630 | #define PCIPCI_FAIL 1 /* No PCI PCI DMA */ |
1da177e4 LT |
1631 | #define PCIPCI_TRITON 2 |
1632 | #define PCIPCI_NATOMA 4 | |
1633 | #define PCIPCI_VIAETBF 8 | |
1634 | #define PCIPCI_VSFX 16 | |
236561e5 AC |
1635 | #define PCIPCI_ALIMAGIK 32 /* Need low latency setting */ |
1636 | #define PCIAGP_FAIL 64 /* No PCI to AGP DMA */ | |
1da177e4 | 1637 | |
4516a618 AN |
1638 | extern unsigned long pci_cardbus_io_size; |
1639 | extern unsigned long pci_cardbus_mem_size; | |
15856ad5 | 1640 | extern u8 pci_dfl_cache_line_size; |
ac1aa47b | 1641 | extern u8 pci_cache_line_size; |
4516a618 | 1642 | |
28760489 EB |
1643 | extern unsigned long pci_hotplug_io_size; |
1644 | extern unsigned long pci_hotplug_mem_size; | |
1645 | ||
f7625980 | 1646 | /* Architecture-specific versions may override these (weak) */ |
19792a08 | 1647 | void pcibios_disable_device(struct pci_dev *dev); |
cfce9fb8 | 1648 | void pcibios_set_master(struct pci_dev *dev); |
19792a08 AB |
1649 | int pcibios_set_pcie_reset_state(struct pci_dev *dev, |
1650 | enum pcie_reset_state state); | |
eca0d467 | 1651 | int pcibios_add_device(struct pci_dev *dev); |
6ae32c53 | 1652 | void pcibios_release_device(struct pci_dev *dev); |
a43ae58c | 1653 | void pcibios_penalize_isa_irq(int irq, int active); |
575e3348 | 1654 | |
699c1985 SO |
1655 | #ifdef CONFIG_HIBERNATE_CALLBACKS |
1656 | extern struct dev_pm_ops pcibios_pm_ops; | |
1657 | #endif | |
1658 | ||
7752d5cf | 1659 | #ifdef CONFIG_PCI_MMCONFIG |
f39d5b72 BH |
1660 | void __init pci_mmcfg_early_init(void); |
1661 | void __init pci_mmcfg_late_init(void); | |
7752d5cf | 1662 | #else |
bb63b421 | 1663 | static inline void pci_mmcfg_early_init(void) { } |
7752d5cf RH |
1664 | static inline void pci_mmcfg_late_init(void) { } |
1665 | #endif | |
1666 | ||
642c92da | 1667 | int pci_ext_cfg_avail(void); |
0ef5f8f6 | 1668 | |
1684f5dd | 1669 | void __iomem *pci_ioremap_bar(struct pci_dev *pdev, int bar); |
aa42d7c6 | 1670 | |
dd7cc44d | 1671 | #ifdef CONFIG_PCI_IOV |
f39d5b72 BH |
1672 | int pci_enable_sriov(struct pci_dev *dev, int nr_virtfn); |
1673 | void pci_disable_sriov(struct pci_dev *dev); | |
f39d5b72 | 1674 | int pci_num_vf(struct pci_dev *dev); |
5a8eb242 | 1675 | int pci_vfs_assigned(struct pci_dev *dev); |
f39d5b72 BH |
1676 | int pci_sriov_set_totalvfs(struct pci_dev *dev, u16 numvfs); |
1677 | int pci_sriov_get_totalvfs(struct pci_dev *dev); | |
dd7cc44d YZ |
1678 | #else |
1679 | static inline int pci_enable_sriov(struct pci_dev *dev, int nr_virtfn) | |
2ee546c4 BH |
1680 | { return -ENODEV; } |
1681 | static inline void pci_disable_sriov(struct pci_dev *dev) { } | |
2ee546c4 | 1682 | static inline int pci_num_vf(struct pci_dev *dev) { return 0; } |
5a8eb242 | 1683 | static inline int pci_vfs_assigned(struct pci_dev *dev) |
2ee546c4 | 1684 | { return 0; } |
bff73156 | 1685 | static inline int pci_sriov_set_totalvfs(struct pci_dev *dev, u16 numvfs) |
2ee546c4 | 1686 | { return 0; } |
bff73156 | 1687 | static inline int pci_sriov_get_totalvfs(struct pci_dev *dev) |
2ee546c4 | 1688 | { return 0; } |
dd7cc44d YZ |
1689 | #endif |
1690 | ||
c825bc94 | 1691 | #if defined(CONFIG_HOTPLUG_PCI) || defined(CONFIG_HOTPLUG_PCI_MODULE) |
f39d5b72 BH |
1692 | void pci_hp_create_module_link(struct pci_slot *pci_slot); |
1693 | void pci_hp_remove_module_link(struct pci_slot *pci_slot); | |
c825bc94 KK |
1694 | #endif |
1695 | ||
d7b7e605 KK |
1696 | /** |
1697 | * pci_pcie_cap - get the saved PCIe capability offset | |
1698 | * @dev: PCI device | |
1699 | * | |
1700 | * PCIe capability offset is calculated at PCI device initialization | |
1701 | * time and saved in the data structure. This function returns saved | |
1702 | * PCIe capability offset. Using this instead of pci_find_capability() | |
1703 | * reduces unnecessary search in the PCI configuration space. If you | |
1704 | * need to calculate PCIe capability offset from raw device for some | |
1705 | * reasons, please use pci_find_capability() instead. | |
1706 | */ | |
1707 | static inline int pci_pcie_cap(struct pci_dev *dev) | |
1708 | { | |
1709 | return dev->pcie_cap; | |
1710 | } | |
1711 | ||
7eb776c4 KK |
1712 | /** |
1713 | * pci_is_pcie - check if the PCI device is PCI Express capable | |
1714 | * @dev: PCI device | |
1715 | * | |
a895c28a | 1716 | * Returns: true if the PCI device is PCI Express capable, false otherwise. |
7eb776c4 KK |
1717 | */ |
1718 | static inline bool pci_is_pcie(struct pci_dev *dev) | |
1719 | { | |
a895c28a | 1720 | return pci_pcie_cap(dev); |
7eb776c4 KK |
1721 | } |
1722 | ||
7c9c003c MS |
1723 | /** |
1724 | * pcie_caps_reg - get the PCIe Capabilities Register | |
1725 | * @dev: PCI device | |
1726 | */ | |
1727 | static inline u16 pcie_caps_reg(const struct pci_dev *dev) | |
1728 | { | |
1729 | return dev->pcie_flags_reg; | |
1730 | } | |
1731 | ||
786e2288 YW |
1732 | /** |
1733 | * pci_pcie_type - get the PCIe device/port type | |
1734 | * @dev: PCI device | |
1735 | */ | |
1736 | static inline int pci_pcie_type(const struct pci_dev *dev) | |
1737 | { | |
1c531d82 | 1738 | return (pcie_caps_reg(dev) & PCI_EXP_FLAGS_TYPE) >> 4; |
786e2288 YW |
1739 | } |
1740 | ||
5d990b62 | 1741 | void pci_request_acs(void); |
ad805758 AW |
1742 | bool pci_acs_enabled(struct pci_dev *pdev, u16 acs_flags); |
1743 | bool pci_acs_path_enabled(struct pci_dev *start, | |
1744 | struct pci_dev *end, u16 acs_flags); | |
a2ce7662 | 1745 | |
7ad506fa | 1746 | #define PCI_VPD_LRDT 0x80 /* Large Resource Data Type */ |
63ddc0b8 | 1747 | #define PCI_VPD_LRDT_ID(x) ((x) | PCI_VPD_LRDT) |
7ad506fa MC |
1748 | |
1749 | /* Large Resource Data Type Tag Item Names */ | |
1750 | #define PCI_VPD_LTIN_ID_STRING 0x02 /* Identifier String */ | |
1751 | #define PCI_VPD_LTIN_RO_DATA 0x10 /* Read-Only Data */ | |
1752 | #define PCI_VPD_LTIN_RW_DATA 0x11 /* Read-Write Data */ | |
1753 | ||
1754 | #define PCI_VPD_LRDT_ID_STRING PCI_VPD_LRDT_ID(PCI_VPD_LTIN_ID_STRING) | |
1755 | #define PCI_VPD_LRDT_RO_DATA PCI_VPD_LRDT_ID(PCI_VPD_LTIN_RO_DATA) | |
1756 | #define PCI_VPD_LRDT_RW_DATA PCI_VPD_LRDT_ID(PCI_VPD_LTIN_RW_DATA) | |
1757 | ||
1758 | /* Small Resource Data Type Tag Item Names */ | |
1759 | #define PCI_VPD_STIN_END 0x78 /* End */ | |
1760 | ||
1761 | #define PCI_VPD_SRDT_END PCI_VPD_STIN_END | |
1762 | ||
1763 | #define PCI_VPD_SRDT_TIN_MASK 0x78 | |
1764 | #define PCI_VPD_SRDT_LEN_MASK 0x07 | |
1765 | ||
1766 | #define PCI_VPD_LRDT_TAG_SIZE 3 | |
1767 | #define PCI_VPD_SRDT_TAG_SIZE 1 | |
a2ce7662 | 1768 | |
e1d5bdab MC |
1769 | #define PCI_VPD_INFO_FLD_HDR_SIZE 3 |
1770 | ||
4067a854 MC |
1771 | #define PCI_VPD_RO_KEYWORD_PARTNO "PN" |
1772 | #define PCI_VPD_RO_KEYWORD_MFR_ID "MN" | |
1773 | #define PCI_VPD_RO_KEYWORD_VENDOR0 "V0" | |
d4894f3e | 1774 | #define PCI_VPD_RO_KEYWORD_CHKSUM "RV" |
4067a854 | 1775 | |
a2ce7662 MC |
1776 | /** |
1777 | * pci_vpd_lrdt_size - Extracts the Large Resource Data Type length | |
1778 | * @lrdt: Pointer to the beginning of the Large Resource Data Type tag | |
1779 | * | |
1780 | * Returns the extracted Large Resource Data Type length. | |
1781 | */ | |
1782 | static inline u16 pci_vpd_lrdt_size(const u8 *lrdt) | |
1783 | { | |
1784 | return (u16)lrdt[1] + ((u16)lrdt[2] << 8); | |
1785 | } | |
1786 | ||
7ad506fa MC |
1787 | /** |
1788 | * pci_vpd_srdt_size - Extracts the Small Resource Data Type length | |
1789 | * @lrdt: Pointer to the beginning of the Small Resource Data Type tag | |
1790 | * | |
1791 | * Returns the extracted Small Resource Data Type length. | |
1792 | */ | |
1793 | static inline u8 pci_vpd_srdt_size(const u8 *srdt) | |
1794 | { | |
1795 | return (*srdt) & PCI_VPD_SRDT_LEN_MASK; | |
1796 | } | |
1797 | ||
e1d5bdab MC |
1798 | /** |
1799 | * pci_vpd_info_field_size - Extracts the information field length | |
1800 | * @lrdt: Pointer to the beginning of an information field header | |
1801 | * | |
1802 | * Returns the extracted information field length. | |
1803 | */ | |
1804 | static inline u8 pci_vpd_info_field_size(const u8 *info_field) | |
1805 | { | |
1806 | return info_field[2]; | |
1807 | } | |
1808 | ||
b55ac1b2 MC |
1809 | /** |
1810 | * pci_vpd_find_tag - Locates the Resource Data Type tag provided | |
1811 | * @buf: Pointer to buffered vpd data | |
1812 | * @off: The offset into the buffer at which to begin the search | |
1813 | * @len: The length of the vpd buffer | |
1814 | * @rdt: The Resource Data Type to search for | |
1815 | * | |
1816 | * Returns the index where the Resource Data Type was found or | |
1817 | * -ENOENT otherwise. | |
1818 | */ | |
1819 | int pci_vpd_find_tag(const u8 *buf, unsigned int off, unsigned int len, u8 rdt); | |
1820 | ||
4067a854 MC |
1821 | /** |
1822 | * pci_vpd_find_info_keyword - Locates an information field keyword in the VPD | |
1823 | * @buf: Pointer to buffered vpd data | |
1824 | * @off: The offset into the buffer at which to begin the search | |
1825 | * @len: The length of the buffer area, relative to off, in which to search | |
1826 | * @kw: The keyword to search for | |
1827 | * | |
1828 | * Returns the index where the information field keyword was found or | |
1829 | * -ENOENT otherwise. | |
1830 | */ | |
1831 | int pci_vpd_find_info_keyword(const u8 *buf, unsigned int off, | |
1832 | unsigned int len, const char *kw); | |
1833 | ||
98d9f30c BH |
1834 | /* PCI <-> OF binding helpers */ |
1835 | #ifdef CONFIG_OF | |
1836 | struct device_node; | |
f39d5b72 BH |
1837 | void pci_set_of_node(struct pci_dev *dev); |
1838 | void pci_release_of_node(struct pci_dev *dev); | |
1839 | void pci_set_bus_of_node(struct pci_bus *bus); | |
1840 | void pci_release_bus_of_node(struct pci_bus *bus); | |
98d9f30c BH |
1841 | |
1842 | /* Arch may override this (weak) */ | |
723ec4d0 | 1843 | struct device_node *pcibios_get_phb_of_node(struct pci_bus *bus); |
98d9f30c | 1844 | |
3df425f3 JC |
1845 | static inline struct device_node * |
1846 | pci_device_to_OF_node(const struct pci_dev *pdev) | |
64099d98 BH |
1847 | { |
1848 | return pdev ? pdev->dev.of_node : NULL; | |
1849 | } | |
1850 | ||
ef3b4f8c BH |
1851 | static inline struct device_node *pci_bus_to_OF_node(struct pci_bus *bus) |
1852 | { | |
1853 | return bus ? bus->dev.of_node : NULL; | |
1854 | } | |
1855 | ||
98d9f30c BH |
1856 | #else /* CONFIG_OF */ |
1857 | static inline void pci_set_of_node(struct pci_dev *dev) { } | |
1858 | static inline void pci_release_of_node(struct pci_dev *dev) { } | |
1859 | static inline void pci_set_bus_of_node(struct pci_bus *bus) { } | |
1860 | static inline void pci_release_bus_of_node(struct pci_bus *bus) { } | |
f0b66a2c KH |
1861 | static inline struct device_node * |
1862 | pci_device_to_OF_node(const struct pci_dev *pdev) { return NULL; } | |
98d9f30c BH |
1863 | #endif /* CONFIG_OF */ |
1864 | ||
eb740b5f GS |
1865 | #ifdef CONFIG_EEH |
1866 | static inline struct eeh_dev *pci_dev_to_eeh_dev(struct pci_dev *pdev) | |
1867 | { | |
1868 | return pdev->dev.archdata.edev; | |
1869 | } | |
1870 | #endif | |
1871 | ||
c25dc828 AW |
1872 | int pci_for_each_dma_alias(struct pci_dev *pdev, |
1873 | int (*fn)(struct pci_dev *pdev, | |
1874 | u16 alias, void *data), void *data); | |
1875 | ||
ce052984 EZ |
1876 | /* helper functions for operation of device flag */ |
1877 | static inline void pci_set_dev_assigned(struct pci_dev *pdev) | |
1878 | { | |
1879 | pdev->dev_flags |= PCI_DEV_FLAGS_ASSIGNED; | |
1880 | } | |
1881 | static inline void pci_clear_dev_assigned(struct pci_dev *pdev) | |
1882 | { | |
1883 | pdev->dev_flags &= ~PCI_DEV_FLAGS_ASSIGNED; | |
1884 | } | |
1885 | static inline bool pci_is_dev_assigned(struct pci_dev *pdev) | |
1886 | { | |
1887 | return (pdev->dev_flags & PCI_DEV_FLAGS_ASSIGNED) == PCI_DEV_FLAGS_ASSIGNED; | |
1888 | } | |
1da177e4 | 1889 | #endif /* LINUX_PCI_H */ |