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Commit | Line | Data |
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b2441318 | 1 | /* SPDX-License-Identifier: GPL-2.0 */ |
1da177e4 LT |
2 | /* |
3 | * pci.h | |
4 | * | |
5 | * PCI defines and function prototypes | |
6 | * Copyright 1994, Drew Eckhardt | |
7 | * Copyright 1997--1999 Martin Mares <mj@ucw.cz> | |
8 | * | |
9 | * For more information, please consult the following manuals (look at | |
10 | * http://www.pcisig.com/ for how to get them): | |
11 | * | |
12 | * PCI BIOS Specification | |
13 | * PCI Local Bus Specification | |
14 | * PCI to PCI Bridge Specification | |
15 | * PCI System Design Guide | |
16 | */ | |
1da177e4 LT |
17 | #ifndef LINUX_PCI_H |
18 | #define LINUX_PCI_H | |
19 | ||
1da177e4 | 20 | |
778382e0 DW |
21 | #include <linux/mod_devicetable.h> |
22 | ||
1da177e4 | 23 | #include <linux/types.h> |
98db6f19 | 24 | #include <linux/init.h> |
1da177e4 LT |
25 | #include <linux/ioport.h> |
26 | #include <linux/list.h> | |
4a7fb636 | 27 | #include <linux/compiler.h> |
1da177e4 | 28 | #include <linux/errno.h> |
f46753c5 | 29 | #include <linux/kobject.h> |
60063497 | 30 | #include <linux/atomic.h> |
1da177e4 | 31 | #include <linux/device.h> |
704e8953 | 32 | #include <linux/interrupt.h> |
1388cc96 | 33 | #include <linux/io.h> |
14d76b68 | 34 | #include <linux/resource_ext.h> |
607ca46e | 35 | #include <uapi/linux/pci.h> |
1da177e4 | 36 | |
7e7a43c3 AB |
37 | #include <linux/pci_ids.h> |
38 | ||
85467136 SK |
39 | /* |
40 | * The PCI interface treats multi-function devices as independent | |
41 | * devices. The slot/function address of each device is encoded | |
42 | * in a single byte as follows: | |
43 | * | |
44 | * 7:3 = slot | |
45 | * 2:0 = function | |
f7625980 BH |
46 | * |
47 | * PCI_DEVFN(), PCI_SLOT(), and PCI_FUNC() are defined in uapi/linux/pci.h. | |
85467136 | 48 | * In the interest of not exposing interfaces to user-space unnecessarily, |
f7625980 | 49 | * the following kernel-only defines are being added here. |
85467136 | 50 | */ |
0aa0f5d1 | 51 | #define PCI_DEVID(bus, devfn) ((((u16)(bus)) << 8) | (devfn)) |
85467136 SK |
52 | /* return bus from PCI devid = ((u16)bus_number) << 8) | devfn */ |
53 | #define PCI_BUS_NUM(x) (((x) >> 8) & 0xff) | |
54 | ||
f46753c5 AC |
55 | /* pci_slot represents a physical slot */ |
56 | struct pci_slot { | |
0aa0f5d1 BH |
57 | struct pci_bus *bus; /* Bus this slot is on */ |
58 | struct list_head list; /* Node in list of slots */ | |
59 | struct hotplug_slot *hotplug; /* Hotplug info (move here) */ | |
60 | unsigned char number; /* PCI_SLOT(pci_dev->devfn) */ | |
61 | struct kobject kobj; | |
f46753c5 AC |
62 | }; |
63 | ||
0ad772ec AC |
64 | static inline const char *pci_slot_name(const struct pci_slot *slot) |
65 | { | |
66 | return kobject_name(&slot->kobj); | |
67 | } | |
68 | ||
1da177e4 LT |
69 | /* File state for mmap()s on /proc/bus/pci/X/Y */ |
70 | enum pci_mmap_state { | |
71 | pci_mmap_io, | |
72 | pci_mmap_mem | |
73 | }; | |
74 | ||
0aa0f5d1 | 75 | /* For PCI devices, the region numbers are assigned this way: */ |
fde09c6d YZ |
76 | enum { |
77 | /* #0-5: standard PCI resources */ | |
78 | PCI_STD_RESOURCES, | |
79 | PCI_STD_RESOURCE_END = 5, | |
80 | ||
81 | /* #6: expansion ROM resource */ | |
82 | PCI_ROM_RESOURCE, | |
83 | ||
0aa0f5d1 | 84 | /* Device-specific resources */ |
d1b054da YZ |
85 | #ifdef CONFIG_PCI_IOV |
86 | PCI_IOV_RESOURCES, | |
87 | PCI_IOV_RESOURCE_END = PCI_IOV_RESOURCES + PCI_SRIOV_NUM_BARS - 1, | |
88 | #endif | |
89 | ||
0aa0f5d1 | 90 | /* Resources assigned to buses behind the bridge */ |
fde09c6d YZ |
91 | #define PCI_BRIDGE_RESOURCE_NUM 4 |
92 | ||
93 | PCI_BRIDGE_RESOURCES, | |
94 | PCI_BRIDGE_RESOURCE_END = PCI_BRIDGE_RESOURCES + | |
95 | PCI_BRIDGE_RESOURCE_NUM - 1, | |
96 | ||
0aa0f5d1 | 97 | /* Total resources associated with a PCI device */ |
fde09c6d YZ |
98 | PCI_NUM_RESOURCES, |
99 | ||
0aa0f5d1 | 100 | /* Preserve this for compatibility */ |
cda57bf9 | 101 | DEVICE_COUNT_RESOURCE = PCI_NUM_RESOURCES, |
fde09c6d | 102 | }; |
1da177e4 | 103 | |
b352baf1 PB |
104 | /** |
105 | * enum pci_interrupt_pin - PCI INTx interrupt values | |
106 | * @PCI_INTERRUPT_UNKNOWN: Unknown or unassigned interrupt | |
107 | * @PCI_INTERRUPT_INTA: PCI INTA pin | |
108 | * @PCI_INTERRUPT_INTB: PCI INTB pin | |
109 | * @PCI_INTERRUPT_INTC: PCI INTC pin | |
110 | * @PCI_INTERRUPT_INTD: PCI INTD pin | |
111 | * | |
112 | * Corresponds to values for legacy PCI INTx interrupts, as can be found in the | |
113 | * PCI_INTERRUPT_PIN register. | |
114 | */ | |
115 | enum pci_interrupt_pin { | |
116 | PCI_INTERRUPT_UNKNOWN, | |
117 | PCI_INTERRUPT_INTA, | |
118 | PCI_INTERRUPT_INTB, | |
119 | PCI_INTERRUPT_INTC, | |
120 | PCI_INTERRUPT_INTD, | |
121 | }; | |
122 | ||
123 | /* The number of legacy PCI INTx interrupts */ | |
124 | #define PCI_NUM_INTX 4 | |
125 | ||
224abb67 BH |
126 | /* |
127 | * pci_power_t values must match the bits in the Capabilities PME_Support | |
128 | * and Control/Status PowerState fields in the Power Management capability. | |
129 | */ | |
1da177e4 LT |
130 | typedef int __bitwise pci_power_t; |
131 | ||
4352dfd5 GKH |
132 | #define PCI_D0 ((pci_power_t __force) 0) |
133 | #define PCI_D1 ((pci_power_t __force) 1) | |
134 | #define PCI_D2 ((pci_power_t __force) 2) | |
1da177e4 LT |
135 | #define PCI_D3hot ((pci_power_t __force) 3) |
136 | #define PCI_D3cold ((pci_power_t __force) 4) | |
3fe9d19f | 137 | #define PCI_UNKNOWN ((pci_power_t __force) 5) |
438510f6 | 138 | #define PCI_POWER_ERROR ((pci_power_t __force) -1) |
1da177e4 | 139 | |
00240c38 AS |
140 | /* Remember to update this when the list above changes! */ |
141 | extern const char *pci_power_names[]; | |
142 | ||
143 | static inline const char *pci_power_name(pci_power_t state) | |
144 | { | |
9661e783 | 145 | return pci_power_names[1 + (__force int) state]; |
00240c38 AS |
146 | } |
147 | ||
448bd857 HY |
148 | #define PCI_PM_D2_DELAY 200 |
149 | #define PCI_PM_D3_WAIT 10 | |
150 | #define PCI_PM_D3COLD_WAIT 100 | |
151 | #define PCI_PM_BUS_WAIT 50 | |
aa8c6c93 | 152 | |
0aa0f5d1 BH |
153 | /** |
154 | * The pci_channel state describes connectivity between the CPU and | |
155 | * the PCI device. If some PCI bus between here and the PCI device | |
156 | * has crashed or locked up, this info is reflected here. | |
392a1ce7 LV |
157 | */ |
158 | typedef unsigned int __bitwise pci_channel_state_t; | |
159 | ||
160 | enum pci_channel_state { | |
161 | /* I/O channel is in normal state */ | |
162 | pci_channel_io_normal = (__force pci_channel_state_t) 1, | |
163 | ||
164 | /* I/O to channel is blocked */ | |
165 | pci_channel_io_frozen = (__force pci_channel_state_t) 2, | |
166 | ||
167 | /* PCI card is dead */ | |
168 | pci_channel_io_perm_failure = (__force pci_channel_state_t) 3, | |
169 | }; | |
170 | ||
f7bdd12d BK |
171 | typedef unsigned int __bitwise pcie_reset_state_t; |
172 | ||
173 | enum pcie_reset_state { | |
174 | /* Reset is NOT asserted (Use to deassert reset) */ | |
175 | pcie_deassert_reset = (__force pcie_reset_state_t) 1, | |
176 | ||
f7625980 | 177 | /* Use #PERST to reset PCIe device */ |
f7bdd12d BK |
178 | pcie_warm_reset = (__force pcie_reset_state_t) 2, |
179 | ||
f7625980 | 180 | /* Use PCIe Hot Reset to reset device */ |
f7bdd12d BK |
181 | pcie_hot_reset = (__force pcie_reset_state_t) 3 |
182 | }; | |
183 | ||
ba698ad4 DM |
184 | typedef unsigned short __bitwise pci_dev_flags_t; |
185 | enum pci_dev_flags { | |
0aa0f5d1 | 186 | /* INTX_DISABLE in PCI_COMMAND register disables MSI too */ |
6b121592 | 187 | PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG = (__force pci_dev_flags_t) (1 << 0), |
979b1791 | 188 | /* Device configuration is irrevocably lost if disabled into D3 */ |
6b121592 | 189 | PCI_DEV_FLAGS_NO_D3 = (__force pci_dev_flags_t) (1 << 1), |
6777829c | 190 | /* Provide indication device is assigned by a Virtual Machine Manager */ |
6b121592 | 191 | PCI_DEV_FLAGS_ASSIGNED = (__force pci_dev_flags_t) (1 << 2), |
5757a769 | 192 | /* Flag for quirk use to store if quirk-specific ACS is enabled */ |
6b121592 | 193 | PCI_DEV_FLAGS_ACS_ENABLED_QUIRK = (__force pci_dev_flags_t) (1 << 3), |
c8fe16e3 AW |
194 | /* Use a PCIe-to-PCI bridge alias even if !pci_is_pcie */ |
195 | PCI_DEV_FLAG_PCIE_BRIDGE_ALIAS = (__force pci_dev_flags_t) (1 << 5), | |
f331a859 AW |
196 | /* Do not use bus resets for device */ |
197 | PCI_DEV_FLAGS_NO_BUS_RESET = (__force pci_dev_flags_t) (1 << 6), | |
51e53738 AW |
198 | /* Do not use PM reset even if device advertises NoSoftRst- */ |
199 | PCI_DEV_FLAGS_NO_PM_RESET = (__force pci_dev_flags_t) (1 << 7), | |
932c435c MR |
200 | /* Get VPD from function 0 VPD */ |
201 | PCI_DEV_FLAGS_VPD_REF_F0 = (__force pci_dev_flags_t) (1 << 8), | |
0aa0f5d1 | 202 | /* A non-root bridge where translation occurs, stop alias search here */ |
ffff8858 | 203 | PCI_DEV_FLAGS_BRIDGE_XLATE_ROOT = (__force pci_dev_flags_t) (1 << 9), |
f65fd1aa SN |
204 | /* Do not use FLR even if device advertises PCI_AF_CAP */ |
205 | PCI_DEV_FLAGS_NO_FLR_RESET = (__force pci_dev_flags_t) (1 << 10), | |
a99b646a | 206 | /* Don't use Relaxed Ordering for TLPs directed at this device */ |
c2eac4d3 | 207 | PCI_DEV_FLAGS_NO_RELAXED_ORDERING = (__force pci_dev_flags_t) (1 << 11), |
ba698ad4 DM |
208 | }; |
209 | ||
e1d3a908 SA |
210 | enum pci_irq_reroute_variant { |
211 | INTEL_IRQ_REROUTE_VARIANT = 1, | |
212 | MAX_IRQ_REROUTE_VARIANTS = 3 | |
213 | }; | |
214 | ||
6e325a62 MT |
215 | typedef unsigned short __bitwise pci_bus_flags_t; |
216 | enum pci_bus_flags { | |
032c3d86 JD |
217 | PCI_BUS_FLAGS_NO_MSI = (__force pci_bus_flags_t) 1, |
218 | PCI_BUS_FLAGS_NO_MMRBC = (__force pci_bus_flags_t) 2, | |
219 | PCI_BUS_FLAGS_NO_AERSID = (__force pci_bus_flags_t) 4, | |
17e8f0d4 | 220 | PCI_BUS_FLAGS_NO_EXTCFG = (__force pci_bus_flags_t) 8, |
6e325a62 MT |
221 | }; |
222 | ||
0aa0f5d1 | 223 | /* Values from Link Status register, PCIe r3.1, sec 7.8.8 */ |
59da381e JK |
224 | enum pcie_link_width { |
225 | PCIE_LNK_WIDTH_RESRV = 0x00, | |
226 | PCIE_LNK_X1 = 0x01, | |
227 | PCIE_LNK_X2 = 0x02, | |
228 | PCIE_LNK_X4 = 0x04, | |
229 | PCIE_LNK_X8 = 0x08, | |
0aa0f5d1 | 230 | PCIE_LNK_X12 = 0x0c, |
59da381e JK |
231 | PCIE_LNK_X16 = 0x10, |
232 | PCIE_LNK_X32 = 0x20, | |
0aa0f5d1 | 233 | PCIE_LNK_WIDTH_UNKNOWN = 0xff, |
59da381e JK |
234 | }; |
235 | ||
536c8cb4 MW |
236 | /* Based on the PCI Hotplug Spec, but some values are made up by us */ |
237 | enum pci_bus_speed { | |
238 | PCI_SPEED_33MHz = 0x00, | |
239 | PCI_SPEED_66MHz = 0x01, | |
240 | PCI_SPEED_66MHz_PCIX = 0x02, | |
241 | PCI_SPEED_100MHz_PCIX = 0x03, | |
242 | PCI_SPEED_133MHz_PCIX = 0x04, | |
243 | PCI_SPEED_66MHz_PCIX_ECC = 0x05, | |
244 | PCI_SPEED_100MHz_PCIX_ECC = 0x06, | |
245 | PCI_SPEED_133MHz_PCIX_ECC = 0x07, | |
246 | PCI_SPEED_66MHz_PCIX_266 = 0x09, | |
247 | PCI_SPEED_100MHz_PCIX_266 = 0x0a, | |
248 | PCI_SPEED_133MHz_PCIX_266 = 0x0b, | |
45b4cdd5 MW |
249 | AGP_UNKNOWN = 0x0c, |
250 | AGP_1X = 0x0d, | |
251 | AGP_2X = 0x0e, | |
252 | AGP_4X = 0x0f, | |
253 | AGP_8X = 0x10, | |
536c8cb4 MW |
254 | PCI_SPEED_66MHz_PCIX_533 = 0x11, |
255 | PCI_SPEED_100MHz_PCIX_533 = 0x12, | |
256 | PCI_SPEED_133MHz_PCIX_533 = 0x13, | |
257 | PCIE_SPEED_2_5GT = 0x14, | |
258 | PCIE_SPEED_5_0GT = 0x15, | |
9dfd97fe | 259 | PCIE_SPEED_8_0GT = 0x16, |
1acfb9b7 | 260 | PCIE_SPEED_16_0GT = 0x17, |
536c8cb4 MW |
261 | PCI_SPEED_UNKNOWN = 0xff, |
262 | }; | |
263 | ||
576c7218 AD |
264 | enum pci_bus_speed pcie_get_speed_cap(struct pci_dev *dev); |
265 | enum pcie_link_width pcie_get_width_cap(struct pci_dev *dev); | |
266 | ||
24a4742f | 267 | struct pci_cap_saved_data { |
0aa0f5d1 BH |
268 | u16 cap_nr; |
269 | bool cap_extended; | |
270 | unsigned int size; | |
271 | u32 data[0]; | |
41017f0c SL |
272 | }; |
273 | ||
24a4742f | 274 | struct pci_cap_saved_state { |
0aa0f5d1 BH |
275 | struct hlist_node next; |
276 | struct pci_cap_saved_data cap; | |
24a4742f AW |
277 | }; |
278 | ||
402723ad | 279 | struct irq_affinity; |
7d715a6c | 280 | struct pcie_link_state; |
ee69439c | 281 | struct pci_vpd; |
d1b054da | 282 | struct pci_sriov; |
302b4215 | 283 | struct pci_ats; |
52916982 | 284 | struct pci_p2pdma; |
ee69439c | 285 | |
0aa0f5d1 | 286 | /* The pci_dev structure describes PCI devices */ |
1da177e4 | 287 | struct pci_dev { |
0aa0f5d1 BH |
288 | struct list_head bus_list; /* Node in per-bus list */ |
289 | struct pci_bus *bus; /* Bus this device is on */ | |
290 | struct pci_bus *subordinate; /* Bus this device bridges to */ | |
1da177e4 | 291 | |
0aa0f5d1 BH |
292 | void *sysdata; /* Hook for sys-specific extension */ |
293 | struct proc_dir_entry *procent; /* Device entry in /proc/bus/pci */ | |
f46753c5 | 294 | struct pci_slot *slot; /* Physical slot this device is in */ |
1da177e4 | 295 | |
0aa0f5d1 | 296 | unsigned int devfn; /* Encoded device & function index */ |
1da177e4 LT |
297 | unsigned short vendor; |
298 | unsigned short device; | |
299 | unsigned short subsystem_vendor; | |
300 | unsigned short subsystem_device; | |
301 | unsigned int class; /* 3 bytes: (base,sub,prog-if) */ | |
b8a3a521 | 302 | u8 revision; /* PCI revision, low byte of class word */ |
1da177e4 | 303 | u8 hdr_type; /* PCI header type (`multi' flag masked out) */ |
66b80809 KB |
304 | #ifdef CONFIG_PCIEAER |
305 | u16 aer_cap; /* AER capability offset */ | |
db89ccbe | 306 | struct aer_stats *aer_stats; /* AER stats for this device */ |
66b80809 | 307 | #endif |
f7625980 | 308 | u8 pcie_cap; /* PCIe capability offset */ |
e375b561 GS |
309 | u8 msi_cap; /* MSI capability offset */ |
310 | u8 msix_cap; /* MSI-X capability offset */ | |
f7625980 | 311 | u8 pcie_mpss:3; /* PCIe Max Payload Size Supported */ |
0aa0f5d1 BH |
312 | u8 rom_base_reg; /* Config register controlling ROM */ |
313 | u8 pin; /* Interrupt pin this device uses */ | |
314 | u16 pcie_flags_reg; /* Cached PCIe Capabilities Register */ | |
315 | unsigned long *dma_alias_mask;/* Mask of enabled devfn aliases */ | |
1da177e4 | 316 | |
0aa0f5d1 | 317 | struct pci_driver *driver; /* Driver bound to this device */ |
1da177e4 LT |
318 | u64 dma_mask; /* Mask of the bits of bus address this |
319 | device implements. Normally this is | |
320 | 0xffffffff. You only need to change | |
321 | this if your device has broken DMA | |
322 | or supports 64-bit transfers. */ | |
323 | ||
4d57cdfa FT |
324 | struct device_dma_parameters dma_parms; |
325 | ||
0aa0f5d1 BH |
326 | pci_power_t current_state; /* Current operating state. In ACPI, |
327 | this is D0-D3, D0 being fully | |
328 | functional, and D3 being off. */ | |
d6112f8d | 329 | unsigned int imm_ready:1; /* Supports Immediate Readiness */ |
703860ed | 330 | u8 pm_cap; /* PM capability offset */ |
337001b6 RW |
331 | unsigned int pme_support:5; /* Bitmask of states from which PME# |
332 | can be generated */ | |
379021d5 | 333 | unsigned int pme_poll:1; /* Poll device's PME status bit */ |
337001b6 RW |
334 | unsigned int d1_support:1; /* Low power state D1 is supported */ |
335 | unsigned int d2_support:1; /* Low power state D2 is supported */ | |
448bd857 HY |
336 | unsigned int no_d1d2:1; /* D1 and D2 are forbidden */ |
337 | unsigned int no_d3cold:1; /* D3cold is forbidden */ | |
9d26d3a8 | 338 | unsigned int bridge_d3:1; /* Allow D3 for bridge */ |
448bd857 | 339 | unsigned int d3cold_allowed:1; /* D3cold is allowed by user */ |
0aa0f5d1 BH |
340 | unsigned int mmio_always_on:1; /* Disallow turning off io/mem |
341 | decoding during BAR sizing */ | |
e80bb09d | 342 | unsigned int wakeup_prepared:1; |
0aa0f5d1 | 343 | unsigned int runtime_d3cold:1; /* Whether go through runtime |
448bd857 HY |
344 | D3cold, not set for devices |
345 | powered on/off by the | |
346 | corresponding bridge */ | |
d491f2b7 | 347 | unsigned int skip_bus_pm:1; /* Internal: Skip bus-level PM */ |
b440bde7 | 348 | unsigned int ignore_hotplug:1; /* Ignore hotplug events */ |
576243b3 KB |
349 | unsigned int hotplug_user_indicators:1; /* SlotCtl indicators |
350 | controlled exclusively by | |
351 | user sysfs */ | |
4ec73791 SM |
352 | unsigned int clear_retrain_link:1; /* Need to clear Retrain Link |
353 | bit manually */ | |
1ae861e6 | 354 | unsigned int d3_delay; /* D3->D0 transition time in ms */ |
448bd857 | 355 | unsigned int d3cold_delay; /* D3cold->D0 transition time in ms */ |
1da177e4 | 356 | |
7d715a6c | 357 | #ifdef CONFIG_PCIEASPM |
f7625980 | 358 | struct pcie_link_state *link_state; /* ASPM link state */ |
c46fd358 BH |
359 | unsigned int ltr_path:1; /* Latency Tolerance Reporting |
360 | supported from root to here */ | |
7d715a6c | 361 | #endif |
7ce3f912 | 362 | unsigned int eetlp_prefix_path:1; /* End-to-End TLP Prefix */ |
7d715a6c | 363 | |
0aa0f5d1 BH |
364 | pci_channel_state_t error_state; /* Current connectivity state */ |
365 | struct device dev; /* Generic device interface */ | |
1da177e4 | 366 | |
0aa0f5d1 | 367 | int cfg_size; /* Size of config space */ |
1da177e4 LT |
368 | |
369 | /* | |
370 | * Instead of touching interrupt line and base address registers | |
371 | * directly, use the values stored here. They might be different! | |
372 | */ | |
373 | unsigned int irq; | |
374 | struct resource resource[DEVICE_COUNT_RESOURCE]; /* I/O and memory regions + expansion ROMs */ | |
375 | ||
0aa0f5d1 BH |
376 | bool match_driver; /* Skip attaching driver */ |
377 | ||
378 | unsigned int transparent:1; /* Subtractive decode bridge */ | |
51c48b31 BH |
379 | unsigned int io_window:1; /* Bridge has I/O window */ |
380 | unsigned int pref_window:1; /* Bridge has pref mem window */ | |
381 | unsigned int pref_64_window:1; /* Pref mem window is 64-bit */ | |
0aa0f5d1 BH |
382 | unsigned int multifunction:1; /* Multi-function device */ |
383 | ||
0aa0f5d1 BH |
384 | unsigned int is_busmaster:1; /* Is busmaster */ |
385 | unsigned int no_msi:1; /* May not use MSI */ | |
386 | unsigned int no_64bit_msi:1; /* May only use 32-bit MSIs */ | |
387 | unsigned int block_cfg_access:1; /* Config space access blocked */ | |
388 | unsigned int broken_parity_status:1; /* Generates false positive parity */ | |
389 | unsigned int irq_reroute_variant:2; /* Needs IRQ rerouting variant */ | |
f7625980 | 390 | unsigned int msi_enabled:1; |
99dc804d | 391 | unsigned int msix_enabled:1; |
0aa0f5d1 BH |
392 | unsigned int ari_enabled:1; /* ARI forwarding */ |
393 | unsigned int ats_enabled:1; /* Address Translation Svc */ | |
a4f4fa68 JPB |
394 | unsigned int pasid_enabled:1; /* Process Address Space ID */ |
395 | unsigned int pri_enabled:1; /* Page Request Interface */ | |
9ac7849e | 396 | unsigned int is_managed:1; |
0aa0f5d1 | 397 | unsigned int needs_freset:1; /* Requires fundamental reset */ |
aa8c6c93 | 398 | unsigned int state_saved:1; |
d1b054da | 399 | unsigned int is_physfn:1; |
dd7cc44d | 400 | unsigned int is_virtfn:1; |
711d5779 | 401 | unsigned int reset_fn:1; |
0aa0f5d1 | 402 | unsigned int is_hotplug_bridge:1; |
b03799b0 | 403 | unsigned int shpc_managed:1; /* SHPC owned by shpchp */ |
0aa0f5d1 | 404 | unsigned int is_thunderbolt:1; /* Thunderbolt controller */ |
617654aa MW |
405 | /* |
406 | * Devices marked being untrusted are the ones that can potentially | |
407 | * execute DMA attacks and similar. They are typically connected | |
408 | * through external ports such as Thunderbolt but not limited to | |
409 | * that. When an IOMMU is enabled they should be getting full | |
410 | * mappings to make sure they cannot access arbitrary memory. | |
411 | */ | |
412 | unsigned int untrusted:1; | |
0aa0f5d1 | 413 | unsigned int __aer_firmware_first_valid:1; |
affb72c3 | 414 | unsigned int __aer_firmware_first:1; |
0aa0f5d1 BH |
415 | unsigned int broken_intx_masking:1; /* INTx masking can't be used */ |
416 | unsigned int io_window_1k:1; /* Intel bridge 1K I/O windows */ | |
cffe0a2b | 417 | unsigned int irq_managed:1; |
d0751b98 | 418 | unsigned int has_secondary_link:1; |
0aa0f5d1 BH |
419 | unsigned int non_compliant_bars:1; /* Broken BARs; ignore them */ |
420 | unsigned int is_probed:1; /* Device probing in progress */ | |
f0157160 | 421 | unsigned int link_active_reporting:1;/* Device capable of reporting link active */ |
aff68a5a | 422 | unsigned int no_vf_scan:1; /* Don't scan for VFs after IOV enablement */ |
ba698ad4 | 423 | pci_dev_flags_t dev_flags; |
bae94d02 | 424 | atomic_t enable_cnt; /* pci_enable_device has been called */ |
4602b88d | 425 | |
0aa0f5d1 | 426 | u32 saved_config_space[16]; /* Config space saved at suspend time */ |
41017f0c | 427 | struct hlist_head saved_cap_space; |
0aa0f5d1 BH |
428 | struct bin_attribute *rom_attr; /* Attribute descriptor for sysfs ROM entry */ |
429 | int rom_attr_enabled; /* Display of ROM attribute enabled? */ | |
1da177e4 | 430 | struct bin_attribute *res_attr[DEVICE_COUNT_RESOURCE]; /* sysfs file for resources */ |
45aec1ae | 431 | struct bin_attribute *res_attr_wc[DEVICE_COUNT_RESOURCE]; /* sysfs file for WC mapping of resources */ |
9bb04a0c | 432 | |
d22b3621 BH |
433 | #ifdef CONFIG_HOTPLUG_PCI_PCIE |
434 | unsigned int broken_cmd_compl:1; /* No compl for some cmds */ | |
435 | #endif | |
9bb04a0c JY |
436 | #ifdef CONFIG_PCIE_PTM |
437 | unsigned int ptm_root:1; | |
438 | unsigned int ptm_enabled:1; | |
8b2ec318 | 439 | u8 ptm_granularity; |
9bb04a0c | 440 | #endif |
ded86d8d | 441 | #ifdef CONFIG_PCI_MSI |
1c51b50c | 442 | const struct attribute_group **msi_irq_groups; |
ded86d8d | 443 | #endif |
94e61088 | 444 | struct pci_vpd *vpd; |
466b3ddf | 445 | #ifdef CONFIG_PCI_ATS |
dd7cc44d | 446 | union { |
0aa0f5d1 BH |
447 | struct pci_sriov *sriov; /* PF: SR-IOV info */ |
448 | struct pci_dev *physfn; /* VF: related PF */ | |
dd7cc44d | 449 | }; |
67930995 BH |
450 | u16 ats_cap; /* ATS Capability offset */ |
451 | u8 ats_stu; /* ATS Smallest Translation Unit */ | |
0aa0f5d1 | 452 | atomic_t ats_ref_cnt; /* Number of VFs with ATS enabled */ |
4ebeb1ec CT |
453 | #endif |
454 | #ifdef CONFIG_PCI_PRI | |
455 | u32 pri_reqs_alloc; /* Number of PRI requests allocated */ | |
456 | #endif | |
457 | #ifdef CONFIG_PCI_PASID | |
458 | u16 pasid_features; | |
52916982 LG |
459 | #endif |
460 | #ifdef CONFIG_PCI_P2PDMA | |
461 | struct pci_p2pdma *p2pdma; | |
d1b054da | 462 | #endif |
0aa0f5d1 BH |
463 | phys_addr_t rom; /* Physical address if not from BAR */ |
464 | size_t romlen; /* Length if not from BAR */ | |
465 | char *driver_override; /* Driver name to force a match */ | |
89ee9f76 | 466 | |
0aa0f5d1 | 467 | unsigned long priv_flags; /* Private flags for the PCI driver */ |
1da177e4 LT |
468 | }; |
469 | ||
dda56549 Y |
470 | static inline struct pci_dev *pci_physfn(struct pci_dev *dev) |
471 | { | |
472 | #ifdef CONFIG_PCI_IOV | |
473 | if (dev->is_virtfn) | |
474 | dev = dev->physfn; | |
475 | #endif | |
dda56549 Y |
476 | return dev; |
477 | } | |
478 | ||
3c6e6ae7 | 479 | struct pci_dev *pci_alloc_dev(struct pci_bus *bus); |
65891215 | 480 | |
1da177e4 LT |
481 | #define to_pci_dev(n) container_of(n, struct pci_dev, dev) |
482 | #define for_each_pci_dev(d) while ((d = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, d)) != NULL) | |
483 | ||
a7369f1f LV |
484 | static inline int pci_channel_offline(struct pci_dev *pdev) |
485 | { | |
486 | return (pdev->error_state != pci_channel_io_normal); | |
487 | } | |
488 | ||
5a21d70d | 489 | struct pci_host_bridge { |
0aa0f5d1 BH |
490 | struct device dev; |
491 | struct pci_bus *bus; /* Root bus */ | |
492 | struct pci_ops *ops; | |
493 | void *sysdata; | |
494 | int busnr; | |
14d76b68 | 495 | struct list_head windows; /* resource_entry */ |
e80a91ad | 496 | struct list_head dma_ranges; /* dma ranges resource list */ |
0aa0f5d1 | 497 | u8 (*swizzle_irq)(struct pci_dev *, u8 *); /* Platform IRQ swizzler */ |
3aa8a41e | 498 | int (*map_irq)(const struct pci_dev *, u8, u8); |
4fa2649a | 499 | void (*release_fn)(struct pci_host_bridge *); |
0aa0f5d1 | 500 | void *release_data; |
37d6a0a6 | 501 | struct msi_controller *msi; |
0aa0f5d1 BH |
502 | unsigned int ignore_reset_delay:1; /* For entire hierarchy */ |
503 | unsigned int no_ext_tags:1; /* No Extended Tags */ | |
02bfeb48 | 504 | unsigned int native_aer:1; /* OS may use PCIe AER */ |
9310f0dc | 505 | unsigned int native_pcie_hotplug:1; /* OS may use PCIe hotplug */ |
1df81a6d | 506 | unsigned int native_shpc_hotplug:1; /* OS may use SHPC hotplug */ |
02bfeb48 | 507 | unsigned int native_pme:1; /* OS may use PCIe PME */ |
af8bb9f8 | 508 | unsigned int native_ltr:1; /* OS may use PCIe LTR */ |
7c7a0e94 GP |
509 | /* Resource alignment requirements */ |
510 | resource_size_t (*align_resource)(struct pci_dev *dev, | |
511 | const struct resource *res, | |
512 | resource_size_t start, | |
513 | resource_size_t size, | |
514 | resource_size_t align); | |
0aa0f5d1 | 515 | unsigned long private[0] ____cacheline_aligned; |
5a21d70d | 516 | }; |
41017f0c | 517 | |
7b543663 | 518 | #define to_pci_host_bridge(n) container_of(n, struct pci_host_bridge, dev) |
7c7a0e94 | 519 | |
59094065 TR |
520 | static inline void *pci_host_bridge_priv(struct pci_host_bridge *bridge) |
521 | { | |
522 | return (void *)bridge->private; | |
523 | } | |
524 | ||
525 | static inline struct pci_host_bridge *pci_host_bridge_from_priv(void *priv) | |
526 | { | |
527 | return container_of(priv, struct pci_host_bridge, private); | |
528 | } | |
529 | ||
a52d1443 | 530 | struct pci_host_bridge *pci_alloc_host_bridge(size_t priv); |
5c3f18cc LP |
531 | struct pci_host_bridge *devm_pci_alloc_host_bridge(struct device *dev, |
532 | size_t priv); | |
dff79b91 | 533 | void pci_free_host_bridge(struct pci_host_bridge *bridge); |
7c7a0e94 GP |
534 | struct pci_host_bridge *pci_find_host_bridge(struct pci_bus *bus); |
535 | ||
4fa2649a | 536 | void pci_set_host_bridge_release(struct pci_host_bridge *bridge, |
0aa0f5d1 BH |
537 | void (*release_fn)(struct pci_host_bridge *), |
538 | void *release_data); | |
7b543663 | 539 | |
6c0cc950 RW |
540 | int pcibios_root_bridge_prepare(struct pci_host_bridge *bridge); |
541 | ||
2fe2abf8 BH |
542 | /* |
543 | * The first PCI_BRIDGE_RESOURCE_NUM PCI bus resources (those that correspond | |
544 | * to P2P or CardBus bridge windows) go in a table. Additional ones (for | |
545 | * buses below host bridges or subtractive decode bridges) go in the list. | |
546 | * Use pci_bus_for_each_resource() to iterate through all the resources. | |
547 | */ | |
548 | ||
549 | /* | |
550 | * PCI_SUBTRACTIVE_DECODE means the bridge forwards the window implicitly | |
551 | * and there's no way to program the bridge with the details of the window. | |
552 | * This does not apply to ACPI _CRS windows, even with the _DEC subtractive- | |
553 | * decode bit set, because they are explicit and can be programmed with _SRS. | |
554 | */ | |
555 | #define PCI_SUBTRACTIVE_DECODE 0x1 | |
556 | ||
557 | struct pci_bus_resource { | |
0aa0f5d1 BH |
558 | struct list_head list; |
559 | struct resource *res; | |
560 | unsigned int flags; | |
2fe2abf8 | 561 | }; |
4352dfd5 GKH |
562 | |
563 | #define PCI_REGION_FLAG_MASK 0x0fU /* These bits of resource flags tell us the PCI region flags */ | |
1da177e4 LT |
564 | |
565 | struct pci_bus { | |
0aa0f5d1 BH |
566 | struct list_head node; /* Node in list of buses */ |
567 | struct pci_bus *parent; /* Parent bus this bridge is on */ | |
568 | struct list_head children; /* List of child buses */ | |
569 | struct list_head devices; /* List of devices on this bus */ | |
570 | struct pci_dev *self; /* Bridge device as seen by parent */ | |
571 | struct list_head slots; /* List of slots on this bus; | |
67546762 | 572 | protected by pci_slot_mutex */ |
2fe2abf8 | 573 | struct resource *resource[PCI_BRIDGE_RESOURCE_NUM]; |
0aa0f5d1 BH |
574 | struct list_head resources; /* Address space routed to this bus */ |
575 | struct resource busn_res; /* Bus numbers routed to this bus */ | |
1da177e4 | 576 | |
0aa0f5d1 | 577 | struct pci_ops *ops; /* Configuration access functions */ |
c2791b80 | 578 | struct msi_controller *msi; /* MSI controller */ |
0aa0f5d1 BH |
579 | void *sysdata; /* Hook for sys-specific extension */ |
580 | struct proc_dir_entry *procdir; /* Directory entry in /proc/bus/pci */ | |
1da177e4 | 581 | |
0aa0f5d1 BH |
582 | unsigned char number; /* Bus number */ |
583 | unsigned char primary; /* Number of primary bridge */ | |
3749c51a MW |
584 | unsigned char max_bus_speed; /* enum pci_bus_speed */ |
585 | unsigned char cur_bus_speed; /* enum pci_bus_speed */ | |
670ba0c8 CM |
586 | #ifdef CONFIG_PCI_DOMAINS_GENERIC |
587 | int domain_nr; | |
588 | #endif | |
1da177e4 LT |
589 | |
590 | char name[48]; | |
591 | ||
0aa0f5d1 BH |
592 | unsigned short bridge_ctl; /* Manage NO_ISA/FBB/et al behaviors */ |
593 | pci_bus_flags_t bus_flags; /* Inherited by child buses */ | |
1da177e4 | 594 | struct device *bridge; |
fd7d1ced | 595 | struct device dev; |
0aa0f5d1 BH |
596 | struct bin_attribute *legacy_io; /* Legacy I/O for this bus */ |
597 | struct bin_attribute *legacy_mem; /* Legacy mem */ | |
cc74d96f | 598 | unsigned int is_added:1; |
1da177e4 LT |
599 | }; |
600 | ||
fd7d1ced | 601 | #define to_pci_bus(n) container_of(n, struct pci_bus, dev) |
1da177e4 | 602 | |
4e544bac HK |
603 | static inline u16 pci_dev_id(struct pci_dev *dev) |
604 | { | |
605 | return PCI_DEVID(dev->bus->number, dev->devfn); | |
606 | } | |
607 | ||
79af72d7 | 608 | /* |
f7625980 | 609 | * Returns true if the PCI bus is root (behind host-PCI bridge), |
79af72d7 | 610 | * false otherwise |
77a0dfcd BH |
611 | * |
612 | * Some code assumes that "bus->self == NULL" means that bus is a root bus. | |
613 | * This is incorrect because "virtual" buses added for SR-IOV (via | |
614 | * virtfn_add_bus()) have "bus->self == NULL" but are not root buses. | |
79af72d7 KK |
615 | */ |
616 | static inline bool pci_is_root_bus(struct pci_bus *pbus) | |
617 | { | |
618 | return !(pbus->parent); | |
619 | } | |
620 | ||
1c86438c YW |
621 | /** |
622 | * pci_is_bridge - check if the PCI device is a bridge | |
623 | * @dev: PCI device | |
624 | * | |
625 | * Return true if the PCI device is bridge whether it has subordinate | |
626 | * or not. | |
627 | */ | |
628 | static inline bool pci_is_bridge(struct pci_dev *dev) | |
629 | { | |
630 | return dev->hdr_type == PCI_HEADER_TYPE_BRIDGE || | |
631 | dev->hdr_type == PCI_HEADER_TYPE_CARDBUS; | |
632 | } | |
633 | ||
24a0c654 AS |
634 | #define for_each_pci_bridge(dev, bus) \ |
635 | list_for_each_entry(dev, &bus->devices, bus_list) \ | |
636 | if (!pci_is_bridge(dev)) {} else | |
637 | ||
c6bde215 BH |
638 | static inline struct pci_dev *pci_upstream_bridge(struct pci_dev *dev) |
639 | { | |
640 | dev = pci_physfn(dev); | |
641 | if (pci_is_root_bus(dev->bus)) | |
642 | return NULL; | |
643 | ||
644 | return dev->bus->self; | |
645 | } | |
646 | ||
6675a601 MK |
647 | struct device *pci_get_host_bridge_device(struct pci_dev *dev); |
648 | void pci_put_host_bridge_device(struct device *dev); | |
649 | ||
16cf0ebc RW |
650 | #ifdef CONFIG_PCI_MSI |
651 | static inline bool pci_dev_msi_enabled(struct pci_dev *pci_dev) | |
652 | { | |
653 | return pci_dev->msi_enabled || pci_dev->msix_enabled; | |
654 | } | |
655 | #else | |
656 | static inline bool pci_dev_msi_enabled(struct pci_dev *pci_dev) { return false; } | |
657 | #endif | |
658 | ||
0aa0f5d1 | 659 | /* Error values that may be returned by PCI functions */ |
1da177e4 LT |
660 | #define PCIBIOS_SUCCESSFUL 0x00 |
661 | #define PCIBIOS_FUNC_NOT_SUPPORTED 0x81 | |
662 | #define PCIBIOS_BAD_VENDOR_ID 0x83 | |
663 | #define PCIBIOS_DEVICE_NOT_FOUND 0x86 | |
664 | #define PCIBIOS_BAD_REGISTER_NUMBER 0x87 | |
665 | #define PCIBIOS_SET_FAILED 0x88 | |
666 | #define PCIBIOS_BUFFER_TOO_SMALL 0x89 | |
667 | ||
0aa0f5d1 | 668 | /* Translate above to generic errno for passing back through non-PCI code */ |
a6961651 AW |
669 | static inline int pcibios_err_to_errno(int err) |
670 | { | |
671 | if (err <= PCIBIOS_SUCCESSFUL) | |
672 | return err; /* Assume already errno */ | |
673 | ||
674 | switch (err) { | |
675 | case PCIBIOS_FUNC_NOT_SUPPORTED: | |
676 | return -ENOENT; | |
677 | case PCIBIOS_BAD_VENDOR_ID: | |
d97ffe23 | 678 | return -ENOTTY; |
a6961651 AW |
679 | case PCIBIOS_DEVICE_NOT_FOUND: |
680 | return -ENODEV; | |
681 | case PCIBIOS_BAD_REGISTER_NUMBER: | |
682 | return -EFAULT; | |
683 | case PCIBIOS_SET_FAILED: | |
684 | return -EIO; | |
685 | case PCIBIOS_BUFFER_TOO_SMALL: | |
686 | return -ENOSPC; | |
687 | } | |
688 | ||
d97ffe23 | 689 | return -ERANGE; |
a6961651 AW |
690 | } |
691 | ||
1da177e4 LT |
692 | /* Low-level architecture-dependent routines */ |
693 | ||
694 | struct pci_ops { | |
057bd2e0 TR |
695 | int (*add_bus)(struct pci_bus *bus); |
696 | void (*remove_bus)(struct pci_bus *bus); | |
1f94a94f | 697 | void __iomem *(*map_bus)(struct pci_bus *bus, unsigned int devfn, int where); |
1da177e4 LT |
698 | int (*read)(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 *val); |
699 | int (*write)(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 val); | |
700 | }; | |
701 | ||
b6ce068a MW |
702 | /* |
703 | * ACPI needs to be able to access PCI config space before we've done a | |
704 | * PCI bus scan and created pci_bus structures. | |
705 | */ | |
f39d5b72 BH |
706 | int raw_pci_read(unsigned int domain, unsigned int bus, unsigned int devfn, |
707 | int reg, int len, u32 *val); | |
708 | int raw_pci_write(unsigned int domain, unsigned int bus, unsigned int devfn, | |
709 | int reg, int len, u32 val); | |
1da177e4 | 710 | |
8e639079 | 711 | #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT |
3a9ad0b4 YL |
712 | typedef u64 pci_bus_addr_t; |
713 | #else | |
714 | typedef u32 pci_bus_addr_t; | |
715 | #endif | |
716 | ||
1da177e4 | 717 | struct pci_bus_region { |
0aa0f5d1 BH |
718 | pci_bus_addr_t start; |
719 | pci_bus_addr_t end; | |
1da177e4 LT |
720 | }; |
721 | ||
722 | struct pci_dynids { | |
0aa0f5d1 BH |
723 | spinlock_t lock; /* Protects list, index */ |
724 | struct list_head list; /* For IDs added at runtime */ | |
1da177e4 LT |
725 | }; |
726 | ||
f7625980 BH |
727 | |
728 | /* | |
729 | * PCI Error Recovery System (PCI-ERS). If a PCI device driver provides | |
730 | * a set of callbacks in struct pci_error_handlers, that device driver | |
731 | * will be notified of PCI bus errors, and will be driven to recovery | |
732 | * when an error occurs. | |
392a1ce7 LV |
733 | */ |
734 | ||
735 | typedef unsigned int __bitwise pci_ers_result_t; | |
736 | ||
737 | enum pci_ers_result { | |
0aa0f5d1 | 738 | /* No result/none/not supported in device driver */ |
392a1ce7 LV |
739 | PCI_ERS_RESULT_NONE = (__force pci_ers_result_t) 1, |
740 | ||
741 | /* Device driver can recover without slot reset */ | |
742 | PCI_ERS_RESULT_CAN_RECOVER = (__force pci_ers_result_t) 2, | |
743 | ||
0aa0f5d1 | 744 | /* Device driver wants slot to be reset */ |
392a1ce7 LV |
745 | PCI_ERS_RESULT_NEED_RESET = (__force pci_ers_result_t) 3, |
746 | ||
747 | /* Device has completely failed, is unrecoverable */ | |
748 | PCI_ERS_RESULT_DISCONNECT = (__force pci_ers_result_t) 4, | |
749 | ||
750 | /* Device driver is fully recovered and operational */ | |
751 | PCI_ERS_RESULT_RECOVERED = (__force pci_ers_result_t) 5, | |
918b4053 VMP |
752 | |
753 | /* No AER capabilities registered for the driver */ | |
754 | PCI_ERS_RESULT_NO_AER_DRIVER = (__force pci_ers_result_t) 6, | |
392a1ce7 LV |
755 | }; |
756 | ||
757 | /* PCI bus error event callbacks */ | |
05cca6e5 | 758 | struct pci_error_handlers { |
392a1ce7 LV |
759 | /* PCI bus error detected on this device */ |
760 | pci_ers_result_t (*error_detected)(struct pci_dev *dev, | |
05cca6e5 | 761 | enum pci_channel_state error); |
392a1ce7 LV |
762 | |
763 | /* MMIO has been re-enabled, but not DMA */ | |
764 | pci_ers_result_t (*mmio_enabled)(struct pci_dev *dev); | |
765 | ||
392a1ce7 LV |
766 | /* PCI slot has been reset */ |
767 | pci_ers_result_t (*slot_reset)(struct pci_dev *dev); | |
768 | ||
3ebe7f9f | 769 | /* PCI function reset prepare or completed */ |
775755ed CH |
770 | void (*reset_prepare)(struct pci_dev *dev); |
771 | void (*reset_done)(struct pci_dev *dev); | |
3ebe7f9f | 772 | |
392a1ce7 LV |
773 | /* Device driver may resume normal operations */ |
774 | void (*resume)(struct pci_dev *dev); | |
775 | }; | |
776 | ||
392a1ce7 | 777 | |
1da177e4 LT |
778 | struct module; |
779 | struct pci_driver { | |
0aa0f5d1 BH |
780 | struct list_head node; |
781 | const char *name; | |
782 | const struct pci_device_id *id_table; /* Must be non-NULL for probe to be called */ | |
783 | int (*probe)(struct pci_dev *dev, const struct pci_device_id *id); /* New device inserted */ | |
784 | void (*remove)(struct pci_dev *dev); /* Device removed (NULL if not a hot-plug capable driver) */ | |
785 | int (*suspend)(struct pci_dev *dev, pm_message_t state); /* Device suspended */ | |
786 | int (*suspend_late)(struct pci_dev *dev, pm_message_t state); | |
787 | int (*resume_early)(struct pci_dev *dev); | |
7cb30264 BY |
788 | int (*resume)(struct pci_dev *dev); /* Device woken up */ |
789 | void (*shutdown)(struct pci_dev *dev); | |
790 | int (*sriov_configure)(struct pci_dev *dev, int num_vfs); /* On PF */ | |
49453028 | 791 | const struct pci_error_handlers *err_handler; |
92d50fc1 | 792 | const struct attribute_group **groups; |
1da177e4 | 793 | struct device_driver driver; |
0aa0f5d1 | 794 | struct pci_dynids dynids; |
1da177e4 LT |
795 | }; |
796 | ||
05cca6e5 | 797 | #define to_pci_driver(drv) container_of(drv, struct pci_driver, driver) |
1da177e4 LT |
798 | |
799 | /** | |
0aa0f5d1 | 800 | * PCI_DEVICE - macro used to describe a specific PCI device |
1da177e4 LT |
801 | * @vend: the 16 bit PCI Vendor ID |
802 | * @dev: the 16 bit PCI Device ID | |
803 | * | |
804 | * This macro is used to create a struct pci_device_id that matches a | |
805 | * specific device. The subvendor and subdevice fields will be set to | |
806 | * PCI_ANY_ID. | |
807 | */ | |
808 | #define PCI_DEVICE(vend,dev) \ | |
809 | .vendor = (vend), .device = (dev), \ | |
810 | .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID | |
811 | ||
3d567e0e | 812 | /** |
0aa0f5d1 | 813 | * PCI_DEVICE_SUB - macro used to describe a specific PCI device with subsystem |
3d567e0e NNS |
814 | * @vend: the 16 bit PCI Vendor ID |
815 | * @dev: the 16 bit PCI Device ID | |
816 | * @subvend: the 16 bit PCI Subvendor ID | |
817 | * @subdev: the 16 bit PCI Subdevice ID | |
818 | * | |
819 | * This macro is used to create a struct pci_device_id that matches a | |
820 | * specific device with subsystem information. | |
821 | */ | |
822 | #define PCI_DEVICE_SUB(vend, dev, subvend, subdev) \ | |
823 | .vendor = (vend), .device = (dev), \ | |
824 | .subvendor = (subvend), .subdevice = (subdev) | |
825 | ||
1da177e4 | 826 | /** |
0aa0f5d1 | 827 | * PCI_DEVICE_CLASS - macro used to describe a specific PCI device class |
1da177e4 LT |
828 | * @dev_class: the class, subclass, prog-if triple for this device |
829 | * @dev_class_mask: the class mask for this device | |
830 | * | |
831 | * This macro is used to create a struct pci_device_id that matches a | |
4352dfd5 | 832 | * specific PCI class. The vendor, device, subvendor, and subdevice |
1da177e4 LT |
833 | * fields will be set to PCI_ANY_ID. |
834 | */ | |
835 | #define PCI_DEVICE_CLASS(dev_class,dev_class_mask) \ | |
836 | .class = (dev_class), .class_mask = (dev_class_mask), \ | |
837 | .vendor = PCI_ANY_ID, .device = PCI_ANY_ID, \ | |
838 | .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID | |
839 | ||
1597cacb | 840 | /** |
0aa0f5d1 | 841 | * PCI_VDEVICE - macro used to describe a specific PCI device in short form |
c1309040 MR |
842 | * @vend: the vendor name |
843 | * @dev: the 16 bit PCI Device ID | |
1597cacb AC |
844 | * |
845 | * This macro is used to create a struct pci_device_id that matches a | |
846 | * specific PCI device. The subvendor, and subdevice fields will be set | |
847 | * to PCI_ANY_ID. The macro allows the next field to follow as the device | |
848 | * private data. | |
849 | */ | |
c1309040 MR |
850 | #define PCI_VDEVICE(vend, dev) \ |
851 | .vendor = PCI_VENDOR_ID_##vend, .device = (dev), \ | |
852 | .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID, 0, 0 | |
1597cacb | 853 | |
b72ae8ca AS |
854 | /** |
855 | * PCI_DEVICE_DATA - macro used to describe a specific PCI device in very short form | |
856 | * @vend: the vendor name (without PCI_VENDOR_ID_ prefix) | |
857 | * @dev: the device name (without PCI_DEVICE_ID_<vend>_ prefix) | |
858 | * @data: the driver data to be filled | |
859 | * | |
860 | * This macro is used to create a struct pci_device_id that matches a | |
861 | * specific PCI device. The subvendor, and subdevice fields will be set | |
862 | * to PCI_ANY_ID. | |
863 | */ | |
864 | #define PCI_DEVICE_DATA(vend, dev, data) \ | |
865 | .vendor = PCI_VENDOR_ID_##vend, .device = PCI_DEVICE_ID_##vend##_##dev, \ | |
866 | .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID, 0, 0, \ | |
867 | .driver_data = (kernel_ulong_t)(data) | |
868 | ||
5bbe029f | 869 | enum { |
0aa0f5d1 BH |
870 | PCI_REASSIGN_ALL_RSRC = 0x00000001, /* Ignore firmware setup */ |
871 | PCI_REASSIGN_ALL_BUS = 0x00000002, /* Reassign all bus numbers */ | |
872 | PCI_PROBE_ONLY = 0x00000004, /* Use existing setup */ | |
873 | PCI_CAN_SKIP_ISA_ALIGN = 0x00000008, /* Don't do ISA alignment */ | |
874 | PCI_ENABLE_PROC_DOMAINS = 0x00000010, /* Enable domains in /proc */ | |
5bbe029f | 875 | PCI_COMPAT_DOMAIN_0 = 0x00000020, /* ... except domain 0 */ |
0aa0f5d1 | 876 | PCI_SCAN_ALL_PCIE_DEVS = 0x00000040, /* Scan all, not just dev 0 */ |
5bbe029f BH |
877 | }; |
878 | ||
0aa0f5d1 | 879 | /* These external functions are only available when PCI support is enabled */ |
1da177e4 LT |
880 | #ifdef CONFIG_PCI |
881 | ||
5bbe029f BH |
882 | extern unsigned int pci_flags; |
883 | ||
884 | static inline void pci_set_flags(int flags) { pci_flags = flags; } | |
885 | static inline void pci_add_flags(int flags) { pci_flags |= flags; } | |
886 | static inline void pci_clear_flags(int flags) { pci_flags &= ~flags; } | |
887 | static inline int pci_has_flag(int flag) { return pci_flags & flag; } | |
888 | ||
a58674ff | 889 | void pcie_bus_configure_settings(struct pci_bus *bus); |
b03e7495 JM |
890 | |
891 | enum pcie_bus_config_types { | |
0aa0f5d1 BH |
892 | PCIE_BUS_TUNE_OFF, /* Don't touch MPS at all */ |
893 | PCIE_BUS_DEFAULT, /* Ensure MPS matches upstream bridge */ | |
894 | PCIE_BUS_SAFE, /* Use largest MPS boot-time devices support */ | |
895 | PCIE_BUS_PERFORMANCE, /* Use MPS and MRRS for best performance */ | |
896 | PCIE_BUS_PEER2PEER, /* Set MPS = 128 for all devices */ | |
b03e7495 JM |
897 | }; |
898 | ||
899 | extern enum pcie_bus_config_types pcie_bus_config; | |
900 | ||
1da177e4 LT |
901 | extern struct bus_type pci_bus_type; |
902 | ||
f7625980 BH |
903 | /* Do NOT directly access these two variables, unless you are arch-specific PCI |
904 | * code, or PCI core code. */ | |
0aa0f5d1 | 905 | extern struct list_head pci_root_buses; /* List of all known PCI buses */ |
f7625980 | 906 | /* Some device drivers need know if PCI is initiated */ |
f39d5b72 | 907 | int no_pci_devices(void); |
1da177e4 | 908 | |
3c449ed0 | 909 | void pcibios_resource_survey_bus(struct pci_bus *bus); |
7b77061f | 910 | void pcibios_bus_add_device(struct pci_dev *pdev); |
10a95747 JL |
911 | void pcibios_add_bus(struct pci_bus *bus); |
912 | void pcibios_remove_bus(struct pci_bus *bus); | |
1da177e4 | 913 | void pcibios_fixup_bus(struct pci_bus *); |
4a7fb636 | 914 | int __must_check pcibios_enable_device(struct pci_dev *, int mask); |
f7625980 | 915 | /* Architecture-specific versions may override this (weak) */ |
05cca6e5 | 916 | char *pcibios_setup(char *str); |
1da177e4 LT |
917 | |
918 | /* Used only when drivers/pci/setup.c is used */ | |
3b7a17fc | 919 | resource_size_t pcibios_align_resource(void *, const struct resource *, |
b26b2d49 | 920 | resource_size_t, |
e31dd6e4 | 921 | resource_size_t); |
1da177e4 | 922 | |
2d1c8618 BH |
923 | /* Weak but can be overriden by arch */ |
924 | void pci_fixup_cardbus(struct pci_bus *); | |
925 | ||
1da177e4 LT |
926 | /* Generic PCI functions used internally */ |
927 | ||
fc279850 | 928 | void pcibios_resource_to_bus(struct pci_bus *bus, struct pci_bus_region *region, |
36a66cd6 | 929 | struct resource *res); |
fc279850 | 930 | void pcibios_bus_to_resource(struct pci_bus *bus, struct resource *res, |
36a66cd6 | 931 | struct pci_bus_region *region); |
d1fd4fb6 | 932 | void pcibios_scan_specific_bus(int busn); |
f39d5b72 | 933 | struct pci_bus *pci_find_bus(int domain, int busnr); |
c48f1670 | 934 | void pci_bus_add_devices(const struct pci_bus *bus); |
de4b2f76 | 935 | struct pci_bus *pci_scan_bus(int bus, struct pci_ops *ops, void *sysdata); |
166c6370 BH |
936 | struct pci_bus *pci_create_root_bus(struct device *parent, int bus, |
937 | struct pci_ops *ops, void *sysdata, | |
938 | struct list_head *resources); | |
49b8e3f3 | 939 | int pci_host_probe(struct pci_host_bridge *bridge); |
98a35831 YL |
940 | int pci_bus_insert_busn_res(struct pci_bus *b, int bus, int busmax); |
941 | int pci_bus_update_busn_res_end(struct pci_bus *b, int busmax); | |
942 | void pci_bus_release_busn_res(struct pci_bus *b); | |
15856ad5 | 943 | struct pci_bus *pci_scan_root_bus(struct device *parent, int bus, |
0aa0f5d1 BH |
944 | struct pci_ops *ops, void *sysdata, |
945 | struct list_head *resources); | |
1228c4b6 | 946 | int pci_scan_root_bus_bridge(struct pci_host_bridge *bridge); |
05cca6e5 GKH |
947 | struct pci_bus *pci_add_new_bus(struct pci_bus *parent, struct pci_dev *dev, |
948 | int busnr); | |
3749c51a | 949 | void pcie_update_link_speed(struct pci_bus *bus, u16 link_status); |
f46753c5 | 950 | struct pci_slot *pci_create_slot(struct pci_bus *parent, int slot_nr, |
828f3768 AC |
951 | const char *name, |
952 | struct hotplug_slot *hotplug); | |
f46753c5 | 953 | void pci_destroy_slot(struct pci_slot *slot); |
017ffe64 YW |
954 | #ifdef CONFIG_SYSFS |
955 | void pci_dev_assign_slot(struct pci_dev *dev); | |
956 | #else | |
957 | static inline void pci_dev_assign_slot(struct pci_dev *dev) { } | |
958 | #endif | |
1da177e4 | 959 | int pci_scan_slot(struct pci_bus *bus, int devfn); |
05cca6e5 | 960 | struct pci_dev *pci_scan_single_device(struct pci_bus *bus, int devfn); |
cdb9b9f7 | 961 | void pci_device_add(struct pci_dev *dev, struct pci_bus *bus); |
1da177e4 | 962 | unsigned int pci_scan_child_bus(struct pci_bus *bus); |
c893d133 | 963 | void pci_bus_add_device(struct pci_dev *dev); |
1da177e4 | 964 | void pci_read_bridge_bases(struct pci_bus *child); |
05cca6e5 GKH |
965 | struct resource *pci_find_parent_resource(const struct pci_dev *dev, |
966 | struct resource *res); | |
c56d4450 | 967 | struct pci_dev *pci_find_pcie_root_port(struct pci_dev *dev); |
3df425f3 | 968 | u8 pci_swizzle_interrupt_pin(const struct pci_dev *dev, u8 pin); |
1da177e4 | 969 | int pci_get_interrupt_pin(struct pci_dev *dev, struct pci_dev **bridge); |
68feac87 | 970 | u8 pci_common_swizzle(struct pci_dev *dev, u8 *pinp); |
f39d5b72 BH |
971 | struct pci_dev *pci_dev_get(struct pci_dev *dev); |
972 | void pci_dev_put(struct pci_dev *dev); | |
973 | void pci_remove_bus(struct pci_bus *b); | |
974 | void pci_stop_and_remove_bus_device(struct pci_dev *dev); | |
9d16947b | 975 | void pci_stop_and_remove_bus_device_locked(struct pci_dev *dev); |
cdfcc572 YL |
976 | void pci_stop_root_bus(struct pci_bus *bus); |
977 | void pci_remove_root_bus(struct pci_bus *bus); | |
b3743fa4 | 978 | void pci_setup_cardbus(struct pci_bus *bus); |
d366d28c | 979 | void pcibios_setup_bridge(struct pci_bus *bus, unsigned long type); |
f39d5b72 | 980 | void pci_sort_breadthfirst(void); |
fb8a0d9d WM |
981 | #define dev_is_pci(d) ((d)->bus == &pci_bus_type) |
982 | #define dev_is_pf(d) ((dev_is_pci(d) ? to_pci_dev(d)->is_physfn : false)) | |
1da177e4 LT |
983 | |
984 | /* Generic PCI functions exported to card drivers */ | |
985 | ||
388c8c16 JB |
986 | enum pci_lost_interrupt_reason { |
987 | PCI_LOST_IRQ_NO_INFORMATION = 0, | |
988 | PCI_LOST_IRQ_DISABLE_MSI, | |
989 | PCI_LOST_IRQ_DISABLE_MSIX, | |
990 | PCI_LOST_IRQ_DISABLE_ACPI, | |
991 | }; | |
992 | enum pci_lost_interrupt_reason pci_lost_interrupt(struct pci_dev *dev); | |
05cca6e5 GKH |
993 | int pci_find_capability(struct pci_dev *dev, int cap); |
994 | int pci_find_next_capability(struct pci_dev *dev, u8 pos, int cap); | |
995 | int pci_find_ext_capability(struct pci_dev *dev, int cap); | |
44a9a36f | 996 | int pci_find_next_ext_capability(struct pci_dev *dev, int pos, int cap); |
05cca6e5 GKH |
997 | int pci_find_ht_capability(struct pci_dev *dev, int ht_cap); |
998 | int pci_find_next_ht_capability(struct pci_dev *dev, int pos, int ht_cap); | |
29f3eb64 | 999 | struct pci_bus *pci_find_next_bus(const struct pci_bus *from); |
1da177e4 | 1000 | |
d42552c3 | 1001 | struct pci_dev *pci_get_device(unsigned int vendor, unsigned int device, |
0aa0f5d1 | 1002 | struct pci_dev *from); |
05cca6e5 | 1003 | struct pci_dev *pci_get_subsys(unsigned int vendor, unsigned int device, |
0aa0f5d1 BH |
1004 | unsigned int ss_vendor, unsigned int ss_device, |
1005 | struct pci_dev *from); | |
05cca6e5 | 1006 | struct pci_dev *pci_get_slot(struct pci_bus *bus, unsigned int devfn); |
3c299dc2 AP |
1007 | struct pci_dev *pci_get_domain_bus_and_slot(int domain, unsigned int bus, |
1008 | unsigned int devfn); | |
05cca6e5 | 1009 | struct pci_dev *pci_get_class(unsigned int class, struct pci_dev *from); |
1da177e4 LT |
1010 | int pci_dev_present(const struct pci_device_id *ids); |
1011 | ||
05cca6e5 GKH |
1012 | int pci_bus_read_config_byte(struct pci_bus *bus, unsigned int devfn, |
1013 | int where, u8 *val); | |
1014 | int pci_bus_read_config_word(struct pci_bus *bus, unsigned int devfn, | |
1015 | int where, u16 *val); | |
1016 | int pci_bus_read_config_dword(struct pci_bus *bus, unsigned int devfn, | |
1017 | int where, u32 *val); | |
1018 | int pci_bus_write_config_byte(struct pci_bus *bus, unsigned int devfn, | |
1019 | int where, u8 val); | |
1020 | int pci_bus_write_config_word(struct pci_bus *bus, unsigned int devfn, | |
1021 | int where, u16 val); | |
1022 | int pci_bus_write_config_dword(struct pci_bus *bus, unsigned int devfn, | |
1023 | int where, u32 val); | |
1f94a94f RH |
1024 | |
1025 | int pci_generic_config_read(struct pci_bus *bus, unsigned int devfn, | |
1026 | int where, int size, u32 *val); | |
1027 | int pci_generic_config_write(struct pci_bus *bus, unsigned int devfn, | |
1028 | int where, int size, u32 val); | |
1029 | int pci_generic_config_read32(struct pci_bus *bus, unsigned int devfn, | |
1030 | int where, int size, u32 *val); | |
1031 | int pci_generic_config_write32(struct pci_bus *bus, unsigned int devfn, | |
1032 | int where, int size, u32 val); | |
1033 | ||
a72b46c3 | 1034 | struct pci_ops *pci_bus_set_ops(struct pci_bus *bus, struct pci_ops *ops); |
1da177e4 | 1035 | |
d3881e50 KB |
1036 | int pci_read_config_byte(const struct pci_dev *dev, int where, u8 *val); |
1037 | int pci_read_config_word(const struct pci_dev *dev, int where, u16 *val); | |
1038 | int pci_read_config_dword(const struct pci_dev *dev, int where, u32 *val); | |
1039 | int pci_write_config_byte(const struct pci_dev *dev, int where, u8 val); | |
1040 | int pci_write_config_word(const struct pci_dev *dev, int where, u16 val); | |
1041 | int pci_write_config_dword(const struct pci_dev *dev, int where, u32 val); | |
1da177e4 | 1042 | |
8c0d3a02 JL |
1043 | int pcie_capability_read_word(struct pci_dev *dev, int pos, u16 *val); |
1044 | int pcie_capability_read_dword(struct pci_dev *dev, int pos, u32 *val); | |
1045 | int pcie_capability_write_word(struct pci_dev *dev, int pos, u16 val); | |
1046 | int pcie_capability_write_dword(struct pci_dev *dev, int pos, u32 val); | |
1047 | int pcie_capability_clear_and_set_word(struct pci_dev *dev, int pos, | |
1048 | u16 clear, u16 set); | |
1049 | int pcie_capability_clear_and_set_dword(struct pci_dev *dev, int pos, | |
1050 | u32 clear, u32 set); | |
1051 | ||
1052 | static inline int pcie_capability_set_word(struct pci_dev *dev, int pos, | |
1053 | u16 set) | |
1054 | { | |
1055 | return pcie_capability_clear_and_set_word(dev, pos, 0, set); | |
1056 | } | |
1057 | ||
1058 | static inline int pcie_capability_set_dword(struct pci_dev *dev, int pos, | |
1059 | u32 set) | |
1060 | { | |
1061 | return pcie_capability_clear_and_set_dword(dev, pos, 0, set); | |
1062 | } | |
1063 | ||
1064 | static inline int pcie_capability_clear_word(struct pci_dev *dev, int pos, | |
1065 | u16 clear) | |
1066 | { | |
1067 | return pcie_capability_clear_and_set_word(dev, pos, clear, 0); | |
1068 | } | |
1069 | ||
1070 | static inline int pcie_capability_clear_dword(struct pci_dev *dev, int pos, | |
1071 | u32 clear) | |
1072 | { | |
1073 | return pcie_capability_clear_and_set_dword(dev, pos, clear, 0); | |
1074 | } | |
1075 | ||
0aa0f5d1 | 1076 | /* User-space driven config access */ |
c63587d7 AW |
1077 | int pci_user_read_config_byte(struct pci_dev *dev, int where, u8 *val); |
1078 | int pci_user_read_config_word(struct pci_dev *dev, int where, u16 *val); | |
1079 | int pci_user_read_config_dword(struct pci_dev *dev, int where, u32 *val); | |
1080 | int pci_user_write_config_byte(struct pci_dev *dev, int where, u8 val); | |
1081 | int pci_user_write_config_word(struct pci_dev *dev, int where, u16 val); | |
1082 | int pci_user_write_config_dword(struct pci_dev *dev, int where, u32 val); | |
1083 | ||
4a7fb636 | 1084 | int __must_check pci_enable_device(struct pci_dev *dev); |
b718989d BH |
1085 | int __must_check pci_enable_device_io(struct pci_dev *dev); |
1086 | int __must_check pci_enable_device_mem(struct pci_dev *dev); | |
0b62e13b | 1087 | int __must_check pci_reenable_device(struct pci_dev *); |
9ac7849e TH |
1088 | int __must_check pcim_enable_device(struct pci_dev *pdev); |
1089 | void pcim_pin_device(struct pci_dev *pdev); | |
1090 | ||
99b3c58f PG |
1091 | static inline bool pci_intx_mask_supported(struct pci_dev *pdev) |
1092 | { | |
1093 | /* | |
1094 | * INTx masking is supported if PCI_COMMAND_INTX_DISABLE is | |
1095 | * writable and no quirk has marked the feature broken. | |
1096 | */ | |
1097 | return !pdev->broken_intx_masking; | |
1098 | } | |
1099 | ||
296ccb08 YS |
1100 | static inline int pci_is_enabled(struct pci_dev *pdev) |
1101 | { | |
1102 | return (atomic_read(&pdev->enable_cnt) > 0); | |
1103 | } | |
1104 | ||
9ac7849e TH |
1105 | static inline int pci_is_managed(struct pci_dev *pdev) |
1106 | { | |
1107 | return pdev->is_managed; | |
1108 | } | |
1109 | ||
1da177e4 | 1110 | void pci_disable_device(struct pci_dev *dev); |
96c55900 MS |
1111 | |
1112 | extern unsigned int pcibios_max_latency; | |
1da177e4 | 1113 | void pci_set_master(struct pci_dev *dev); |
6a479079 | 1114 | void pci_clear_master(struct pci_dev *dev); |
96c55900 | 1115 | |
f7bdd12d | 1116 | int pci_set_pcie_reset_state(struct pci_dev *dev, enum pcie_reset_state state); |
15ea76d4 | 1117 | int pci_set_cacheline_size(struct pci_dev *dev); |
1da177e4 | 1118 | #define HAVE_PCI_SET_MWI |
4a7fb636 | 1119 | int __must_check pci_set_mwi(struct pci_dev *dev); |
fc0f9f4d | 1120 | int __must_check pcim_set_mwi(struct pci_dev *dev); |
694625c0 | 1121 | int pci_try_set_mwi(struct pci_dev *dev); |
1da177e4 | 1122 | void pci_clear_mwi(struct pci_dev *dev); |
a04ce0ff | 1123 | void pci_intx(struct pci_dev *dev, int enable); |
a2e27787 JK |
1124 | bool pci_check_and_mask_intx(struct pci_dev *dev); |
1125 | bool pci_check_and_unmask_intx(struct pci_dev *dev); | |
157e876f | 1126 | int pci_wait_for_pending(struct pci_dev *dev, int pos, u16 mask); |
3775a209 | 1127 | int pci_wait_for_pending_transaction(struct pci_dev *dev); |
d556ad4b PO |
1128 | int pcix_get_max_mmrbc(struct pci_dev *dev); |
1129 | int pcix_get_mmrbc(struct pci_dev *dev); | |
1130 | int pcix_set_mmrbc(struct pci_dev *dev, int mmrbc); | |
2637e5b5 | 1131 | int pcie_get_readrq(struct pci_dev *dev); |
d556ad4b | 1132 | int pcie_set_readrq(struct pci_dev *dev, int rq); |
b03e7495 JM |
1133 | int pcie_get_mps(struct pci_dev *dev); |
1134 | int pcie_set_mps(struct pci_dev *dev, int mps); | |
6db79a88 TG |
1135 | u32 pcie_bandwidth_available(struct pci_dev *dev, struct pci_dev **limiting_dev, |
1136 | enum pci_bus_speed *speed, | |
1137 | enum pcie_link_width *width); | |
9e506a7b | 1138 | void pcie_print_link_status(struct pci_dev *dev); |
2d2917f7 | 1139 | bool pcie_has_flr(struct pci_dev *dev); |
91295d79 | 1140 | int pcie_flr(struct pci_dev *dev); |
a96d627a | 1141 | int __pci_reset_function_locked(struct pci_dev *dev); |
8dd7f803 | 1142 | int pci_reset_function(struct pci_dev *dev); |
a477b9cd | 1143 | int pci_reset_function_locked(struct pci_dev *dev); |
61cf16d8 | 1144 | int pci_try_reset_function(struct pci_dev *dev); |
9a3d2b9b | 1145 | int pci_probe_reset_slot(struct pci_slot *slot); |
9a3d2b9b | 1146 | int pci_probe_reset_bus(struct pci_bus *bus); |
c6a44ba9 | 1147 | int pci_reset_bus(struct pci_dev *dev); |
9e33002f GS |
1148 | void pci_reset_secondary_bus(struct pci_dev *dev); |
1149 | void pcibios_reset_secondary_bus(struct pci_dev *dev); | |
14add80b | 1150 | void pci_update_resource(struct pci_dev *dev, int resno); |
4a7fb636 | 1151 | int __must_check pci_assign_resource(struct pci_dev *dev, int i); |
2bbc6942 | 1152 | int __must_check pci_reassign_resource(struct pci_dev *dev, int i, resource_size_t add_size, resource_size_t align); |
8bb705e3 CK |
1153 | void pci_release_resource(struct pci_dev *dev, int resno); |
1154 | int __must_check pci_resize_resource(struct pci_dev *dev, int i, int size); | |
c87deff7 | 1155 | int pci_select_bars(struct pci_dev *dev, unsigned long flags); |
8496e85c | 1156 | bool pci_device_is_present(struct pci_dev *pdev); |
08249651 | 1157 | void pci_ignore_hotplug(struct pci_dev *dev); |
1da177e4 | 1158 | |
704e8953 CH |
1159 | int __printf(6, 7) pci_request_irq(struct pci_dev *dev, unsigned int nr, |
1160 | irq_handler_t handler, irq_handler_t thread_fn, void *dev_id, | |
1161 | const char *fmt, ...); | |
1162 | void pci_free_irq(struct pci_dev *dev, unsigned int nr, void *dev_id); | |
1163 | ||
1da177e4 | 1164 | /* ROM control related routines */ |
e416de5e AC |
1165 | int pci_enable_rom(struct pci_dev *pdev); |
1166 | void pci_disable_rom(struct pci_dev *pdev); | |
144a50ea | 1167 | void __iomem __must_check *pci_map_rom(struct pci_dev *pdev, size_t *size); |
1da177e4 | 1168 | void pci_unmap_rom(struct pci_dev *pdev, void __iomem *rom); |
fffe01f7 | 1169 | void __iomem __must_check *pci_platform_rom(struct pci_dev *pdev, size_t *size); |
1da177e4 LT |
1170 | |
1171 | /* Power management related routines */ | |
1172 | int pci_save_state(struct pci_dev *dev); | |
1d3c16a8 | 1173 | void pci_restore_state(struct pci_dev *dev); |
ffbdd3f7 | 1174 | struct pci_saved_state *pci_store_saved_state(struct pci_dev *dev); |
98d9b271 KRW |
1175 | int pci_load_saved_state(struct pci_dev *dev, |
1176 | struct pci_saved_state *state); | |
ffbdd3f7 AW |
1177 | int pci_load_and_free_saved_state(struct pci_dev *dev, |
1178 | struct pci_saved_state **state); | |
fd0f7f73 AW |
1179 | struct pci_cap_saved_state *pci_find_saved_cap(struct pci_dev *dev, char cap); |
1180 | struct pci_cap_saved_state *pci_find_saved_ext_cap(struct pci_dev *dev, | |
1181 | u16 cap); | |
1182 | int pci_add_cap_save_buffer(struct pci_dev *dev, char cap, unsigned int size); | |
1183 | int pci_add_ext_cap_save_buffer(struct pci_dev *dev, | |
1184 | u16 cap, unsigned int size); | |
0e5dd46b | 1185 | int __pci_complete_power_transition(struct pci_dev *dev, pci_power_t state); |
9c8550ee LT |
1186 | int pci_set_power_state(struct pci_dev *dev, pci_power_t state); |
1187 | pci_power_t pci_choose_state(struct pci_dev *dev, pm_message_t state); | |
e5899e1b | 1188 | bool pci_pme_capable(struct pci_dev *dev, pci_power_t state); |
5a6c9b60 | 1189 | void pci_pme_active(struct pci_dev *dev, bool enable); |
0847684c | 1190 | int pci_enable_wake(struct pci_dev *dev, pci_power_t state, bool enable); |
0235c4fc | 1191 | int pci_wake_from_d3(struct pci_dev *dev, bool enable); |
404cc2d8 RW |
1192 | int pci_prepare_to_sleep(struct pci_dev *dev); |
1193 | int pci_back_from_sleep(struct pci_dev *dev); | |
b67ea761 | 1194 | bool pci_dev_run_wake(struct pci_dev *dev); |
bf4d2908 | 1195 | bool pci_check_pme_status(struct pci_dev *dev); |
bf4d2908 | 1196 | void pci_pme_wakeup_bus(struct pci_bus *bus); |
9d26d3a8 MW |
1197 | void pci_d3cold_enable(struct pci_dev *dev); |
1198 | void pci_d3cold_disable(struct pci_dev *dev); | |
a99b646a | 1199 | bool pcie_relaxed_ordering_enabled(struct pci_dev *dev); |
2a4d2c42 LW |
1200 | void pci_wakeup_bus(struct pci_bus *bus); |
1201 | void pci_bus_set_current_state(struct pci_bus *bus, pci_power_t state); | |
1da177e4 | 1202 | |
425c1b22 AW |
1203 | /* PCI Virtual Channel */ |
1204 | int pci_save_vc_state(struct pci_dev *dev); | |
1205 | void pci_restore_vc_state(struct pci_dev *dev); | |
1206 | void pci_allocate_vc_save_buffers(struct pci_dev *dev); | |
51c2e0a7 | 1207 | |
bb209c82 BH |
1208 | /* For use by arch with custom probe code */ |
1209 | void set_pcie_port_type(struct pci_dev *pdev); | |
1210 | void set_pcie_hotplug_bridge(struct pci_dev *pdev); | |
1211 | ||
ce5ccdef | 1212 | /* Functions for PCI Hotplug drivers to use */ |
05cca6e5 | 1213 | int pci_bus_find_capability(struct pci_bus *bus, unsigned int devfn, int cap); |
2f320521 | 1214 | unsigned int pci_rescan_bus_bridge_resize(struct pci_dev *bridge); |
3ed4fd96 | 1215 | unsigned int pci_rescan_bus(struct pci_bus *bus); |
9d16947b RW |
1216 | void pci_lock_rescan_remove(void); |
1217 | void pci_unlock_rescan_remove(void); | |
ce5ccdef | 1218 | |
0aa0f5d1 | 1219 | /* Vital Product Data routines */ |
287d19ce SH |
1220 | ssize_t pci_read_vpd(struct pci_dev *dev, loff_t pos, size_t count, void *buf); |
1221 | ssize_t pci_write_vpd(struct pci_dev *dev, loff_t pos, size_t count, const void *buf); | |
cb92148b | 1222 | int pci_set_vpd_size(struct pci_dev *dev, size_t len); |
287d19ce | 1223 | |
1da177e4 | 1224 | /* Helper functions for low-level code (drivers/pci/setup-[bus,res].c) */ |
925845bd | 1225 | resource_size_t pcibios_retrieve_fw_addr(struct pci_dev *dev, int idx); |
ea741551 | 1226 | void pci_bus_assign_resources(const struct pci_bus *bus); |
765bf9b7 | 1227 | void pci_bus_claim_resources(struct pci_bus *bus); |
1da177e4 LT |
1228 | void pci_bus_size_bridges(struct pci_bus *bus); |
1229 | int pci_claim_resource(struct pci_dev *, int); | |
8505e729 | 1230 | int pci_claim_bridge_resource(struct pci_dev *bridge, int i); |
1da177e4 | 1231 | void pci_assign_unassigned_resources(void); |
6841ec68 | 1232 | void pci_assign_unassigned_bridge_resources(struct pci_dev *bridge); |
17787940 | 1233 | void pci_assign_unassigned_bus_resources(struct pci_bus *bus); |
39772038 | 1234 | void pci_assign_unassigned_root_bus_resources(struct pci_bus *bus); |
8bb705e3 | 1235 | int pci_reassign_bridge_resources(struct pci_dev *bridge, unsigned long type); |
1da177e4 | 1236 | void pdev_enable_device(struct pci_dev *); |
842de40d | 1237 | int pci_enable_resources(struct pci_dev *, int mask); |
47a650f2 | 1238 | void pci_assign_irq(struct pci_dev *dev); |
afd29f90 | 1239 | struct resource *pci_find_resource(struct pci_dev *dev, struct resource *res); |
1da177e4 | 1240 | #define HAVE_PCI_REQ_REGIONS 2 |
4a7fb636 | 1241 | int __must_check pci_request_regions(struct pci_dev *, const char *); |
e8de1481 | 1242 | int __must_check pci_request_regions_exclusive(struct pci_dev *, const char *); |
1da177e4 | 1243 | void pci_release_regions(struct pci_dev *); |
4a7fb636 | 1244 | int __must_check pci_request_region(struct pci_dev *, int, const char *); |
1da177e4 | 1245 | void pci_release_region(struct pci_dev *, int); |
c87deff7 | 1246 | int pci_request_selected_regions(struct pci_dev *, int, const char *); |
e8de1481 | 1247 | int pci_request_selected_regions_exclusive(struct pci_dev *, int, const char *); |
c87deff7 | 1248 | void pci_release_selected_regions(struct pci_dev *, int); |
1da177e4 LT |
1249 | |
1250 | /* drivers/pci/bus.c */ | |
fe830ef6 JL |
1251 | struct pci_bus *pci_bus_get(struct pci_bus *bus); |
1252 | void pci_bus_put(struct pci_bus *bus); | |
45ca9e97 | 1253 | void pci_add_resource(struct list_head *resources, struct resource *res); |
0efd5aab BH |
1254 | void pci_add_resource_offset(struct list_head *resources, struct resource *res, |
1255 | resource_size_t offset); | |
45ca9e97 | 1256 | void pci_free_resource_list(struct list_head *resources); |
950334bc BH |
1257 | void pci_bus_add_resource(struct pci_bus *bus, struct resource *res, |
1258 | unsigned int flags); | |
2fe2abf8 BH |
1259 | struct resource *pci_bus_resource_n(const struct pci_bus *bus, int n); |
1260 | void pci_bus_remove_resources(struct pci_bus *bus); | |
950334bc BH |
1261 | int devm_request_pci_bus_resources(struct device *dev, |
1262 | struct list_head *resources); | |
2fe2abf8 | 1263 | |
bfc45606 DD |
1264 | /* Temporary until new and working PCI SBR API in place */ |
1265 | int pci_bridge_secondary_bus_reset(struct pci_dev *dev); | |
1266 | ||
89a74ecc | 1267 | #define pci_bus_for_each_resource(bus, res, i) \ |
2fe2abf8 BH |
1268 | for (i = 0; \ |
1269 | (res = pci_bus_resource_n(bus, i)) || i < PCI_BRIDGE_RESOURCE_NUM; \ | |
1270 | i++) | |
89a74ecc | 1271 | |
4a7fb636 AM |
1272 | int __must_check pci_bus_alloc_resource(struct pci_bus *bus, |
1273 | struct resource *res, resource_size_t size, | |
1274 | resource_size_t align, resource_size_t min, | |
664c2848 | 1275 | unsigned long type_mask, |
3b7a17fc DB |
1276 | resource_size_t (*alignf)(void *, |
1277 | const struct resource *, | |
b26b2d49 DB |
1278 | resource_size_t, |
1279 | resource_size_t), | |
4a7fb636 | 1280 | void *alignf_data); |
1da177e4 | 1281 | |
8b921acf | 1282 | |
fcfaab30 GP |
1283 | int pci_register_io_range(struct fwnode_handle *fwnode, phys_addr_t addr, |
1284 | resource_size_t size); | |
c5076cfe TN |
1285 | unsigned long pci_address_to_pio(phys_addr_t addr); |
1286 | phys_addr_t pci_pio_to_address(unsigned long pio); | |
8b921acf | 1287 | int pci_remap_iospace(const struct resource *res, phys_addr_t phys_addr); |
a5fb9fb0 SS |
1288 | int devm_pci_remap_iospace(struct device *dev, const struct resource *res, |
1289 | phys_addr_t phys_addr); | |
4d3f1384 | 1290 | void pci_unmap_iospace(struct resource *res); |
490cb6dd LP |
1291 | void __iomem *devm_pci_remap_cfgspace(struct device *dev, |
1292 | resource_size_t offset, | |
1293 | resource_size_t size); | |
1294 | void __iomem *devm_pci_remap_cfg_resource(struct device *dev, | |
1295 | struct resource *res); | |
8b921acf | 1296 | |
3a9ad0b4 | 1297 | static inline pci_bus_addr_t pci_bus_address(struct pci_dev *pdev, int bar) |
06cf56e4 BH |
1298 | { |
1299 | struct pci_bus_region region; | |
1300 | ||
1301 | pcibios_resource_to_bus(pdev->bus, ®ion, &pdev->resource[bar]); | |
1302 | return region.start; | |
1303 | } | |
1304 | ||
863b18f4 | 1305 | /* Proper probing supporting hot-pluggable devices */ |
725522b5 GKH |
1306 | int __must_check __pci_register_driver(struct pci_driver *, struct module *, |
1307 | const char *mod_name); | |
bba81165 | 1308 | |
0aa0f5d1 | 1309 | /* pci_register_driver() must be a macro so KBUILD_MODNAME can be expanded */ |
bba81165 AM |
1310 | #define pci_register_driver(driver) \ |
1311 | __pci_register_driver(driver, THIS_MODULE, KBUILD_MODNAME) | |
863b18f4 | 1312 | |
05cca6e5 | 1313 | void pci_unregister_driver(struct pci_driver *dev); |
aad4f400 GKH |
1314 | |
1315 | /** | |
1316 | * module_pci_driver() - Helper macro for registering a PCI driver | |
1317 | * @__pci_driver: pci_driver struct | |
1318 | * | |
1319 | * Helper macro for PCI drivers which do not do anything special in module | |
1320 | * init/exit. This eliminates a lot of boilerplate. Each module may only | |
1321 | * use this macro once, and calling it replaces module_init() and module_exit() | |
1322 | */ | |
1323 | #define module_pci_driver(__pci_driver) \ | |
0aa0f5d1 | 1324 | module_driver(__pci_driver, pci_register_driver, pci_unregister_driver) |
aad4f400 | 1325 | |
b4eb6cdb PG |
1326 | /** |
1327 | * builtin_pci_driver() - Helper macro for registering a PCI driver | |
1328 | * @__pci_driver: pci_driver struct | |
1329 | * | |
1330 | * Helper macro for PCI drivers which do not do anything special in their | |
1331 | * init code. This eliminates a lot of boilerplate. Each driver may only | |
1332 | * use this macro once, and calling it replaces device_initcall(...) | |
1333 | */ | |
1334 | #define builtin_pci_driver(__pci_driver) \ | |
1335 | builtin_driver(__pci_driver, pci_register_driver) | |
1336 | ||
05cca6e5 | 1337 | struct pci_driver *pci_dev_driver(const struct pci_dev *dev); |
9dba910e TH |
1338 | int pci_add_dynid(struct pci_driver *drv, |
1339 | unsigned int vendor, unsigned int device, | |
1340 | unsigned int subvendor, unsigned int subdevice, | |
1341 | unsigned int class, unsigned int class_mask, | |
1342 | unsigned long driver_data); | |
05cca6e5 GKH |
1343 | const struct pci_device_id *pci_match_id(const struct pci_device_id *ids, |
1344 | struct pci_dev *dev); | |
1345 | int pci_scan_bridge(struct pci_bus *bus, struct pci_dev *dev, int max, | |
1346 | int pass); | |
1da177e4 | 1347 | |
70298c6e | 1348 | void pci_walk_bus(struct pci_bus *top, int (*cb)(struct pci_dev *, void *), |
cecf4864 | 1349 | void *userdata); |
ac7dc65a | 1350 | int pci_cfg_space_size(struct pci_dev *dev); |
05cca6e5 | 1351 | unsigned char pci_bus_max_busnr(struct pci_bus *bus); |
e2444273 | 1352 | void pci_setup_bridge(struct pci_bus *bus); |
ac5ad93e GS |
1353 | resource_size_t pcibios_window_alignment(struct pci_bus *bus, |
1354 | unsigned long type); | |
cecf4864 | 1355 | |
3448a19d DA |
1356 | #define PCI_VGA_STATE_CHANGE_BRIDGE (1 << 0) |
1357 | #define PCI_VGA_STATE_CHANGE_DECODES (1 << 1) | |
1358 | ||
deb2d2ec | 1359 | int pci_set_vga_state(struct pci_dev *pdev, bool decode, |
3448a19d | 1360 | unsigned int command_bits, u32 flags); |
fe537670 | 1361 | |
0aa0f5d1 BH |
1362 | #define PCI_IRQ_LEGACY (1 << 0) /* Allow legacy interrupts */ |
1363 | #define PCI_IRQ_MSI (1 << 1) /* Allow MSI interrupts */ | |
1364 | #define PCI_IRQ_MSIX (1 << 2) /* Allow MSI-X interrupts */ | |
1365 | #define PCI_IRQ_AFFINITY (1 << 3) /* Auto-assign affinity */ | |
4fe0d154 CH |
1366 | #define PCI_IRQ_ALL_TYPES \ |
1367 | (PCI_IRQ_LEGACY | PCI_IRQ_MSI | PCI_IRQ_MSIX) | |
aff17164 | 1368 | |
1da177e4 LT |
1369 | /* kmem_cache style wrapper around pci_alloc_consistent() */ |
1370 | ||
1371 | #include <linux/dmapool.h> | |
1372 | ||
1373 | #define pci_pool dma_pool | |
1374 | #define pci_pool_create(name, pdev, size, align, allocation) \ | |
1375 | dma_pool_create(name, &pdev->dev, size, align, allocation) | |
1376 | #define pci_pool_destroy(pool) dma_pool_destroy(pool) | |
1377 | #define pci_pool_alloc(pool, flags, handle) dma_pool_alloc(pool, flags, handle) | |
01a7fd33 SS |
1378 | #define pci_pool_zalloc(pool, flags, handle) \ |
1379 | dma_pool_zalloc(pool, flags, handle) | |
1da177e4 LT |
1380 | #define pci_pool_free(pool, vaddr, addr) dma_pool_free(pool, vaddr, addr) |
1381 | ||
1da177e4 | 1382 | struct msix_entry { |
0aa0f5d1 BH |
1383 | u32 vector; /* Kernel uses to write allocated vector */ |
1384 | u16 entry; /* Driver uses to specify entry, OS writes */ | |
1da177e4 LT |
1385 | }; |
1386 | ||
4c859804 BH |
1387 | #ifdef CONFIG_PCI_MSI |
1388 | int pci_msi_vec_count(struct pci_dev *dev); | |
f39d5b72 | 1389 | void pci_disable_msi(struct pci_dev *dev); |
4c859804 | 1390 | int pci_msix_vec_count(struct pci_dev *dev); |
f39d5b72 | 1391 | void pci_disable_msix(struct pci_dev *dev); |
f39d5b72 BH |
1392 | void pci_restore_msi_state(struct pci_dev *dev); |
1393 | int pci_msi_enabled(void); | |
4fe03955 | 1394 | int pci_enable_msi(struct pci_dev *dev); |
4c859804 BH |
1395 | int pci_enable_msix_range(struct pci_dev *dev, struct msix_entry *entries, |
1396 | int minvec, int maxvec); | |
f7fc32cb AG |
1397 | static inline int pci_enable_msix_exact(struct pci_dev *dev, |
1398 | struct msix_entry *entries, int nvec) | |
1399 | { | |
1400 | int rc = pci_enable_msix_range(dev, entries, nvec, nvec); | |
1401 | if (rc < 0) | |
1402 | return rc; | |
1403 | return 0; | |
1404 | } | |
402723ad CH |
1405 | int pci_alloc_irq_vectors_affinity(struct pci_dev *dev, unsigned int min_vecs, |
1406 | unsigned int max_vecs, unsigned int flags, | |
c66d4bd1 | 1407 | struct irq_affinity *affd); |
402723ad | 1408 | |
aff17164 CH |
1409 | void pci_free_irq_vectors(struct pci_dev *dev); |
1410 | int pci_irq_vector(struct pci_dev *dev, unsigned int nr); | |
ee8d41e5 | 1411 | const struct cpumask *pci_irq_get_affinity(struct pci_dev *pdev, int vec); |
27ddb689 | 1412 | int pci_irq_get_node(struct pci_dev *pdev, int vec); |
aff17164 | 1413 | |
4c859804 | 1414 | #else |
2ee546c4 | 1415 | static inline int pci_msi_vec_count(struct pci_dev *dev) { return -ENOSYS; } |
2ee546c4 BH |
1416 | static inline void pci_disable_msi(struct pci_dev *dev) { } |
1417 | static inline int pci_msix_vec_count(struct pci_dev *dev) { return -ENOSYS; } | |
2ee546c4 | 1418 | static inline void pci_disable_msix(struct pci_dev *dev) { } |
2ee546c4 BH |
1419 | static inline void pci_restore_msi_state(struct pci_dev *dev) { } |
1420 | static inline int pci_msi_enabled(void) { return 0; } | |
4fe03955 | 1421 | static inline int pci_enable_msi(struct pci_dev *dev) |
f7fc32cb | 1422 | { return -ENOSYS; } |
302a2523 | 1423 | static inline int pci_enable_msix_range(struct pci_dev *dev, |
0aa0f5d1 | 1424 | struct msix_entry *entries, int minvec, int maxvec) |
2ee546c4 | 1425 | { return -ENOSYS; } |
f7fc32cb | 1426 | static inline int pci_enable_msix_exact(struct pci_dev *dev, |
0aa0f5d1 | 1427 | struct msix_entry *entries, int nvec) |
f7fc32cb | 1428 | { return -ENOSYS; } |
402723ad CH |
1429 | |
1430 | static inline int | |
1431 | pci_alloc_irq_vectors_affinity(struct pci_dev *dev, unsigned int min_vecs, | |
1432 | unsigned int max_vecs, unsigned int flags, | |
c66d4bd1 | 1433 | struct irq_affinity *aff_desc) |
aff17164 | 1434 | { |
83b4605b CH |
1435 | if ((flags & PCI_IRQ_LEGACY) && min_vecs == 1 && dev->irq) |
1436 | return 1; | |
1437 | return -ENOSPC; | |
aff17164 | 1438 | } |
402723ad | 1439 | |
aff17164 CH |
1440 | static inline void pci_free_irq_vectors(struct pci_dev *dev) |
1441 | { | |
1442 | } | |
1443 | ||
1444 | static inline int pci_irq_vector(struct pci_dev *dev, unsigned int nr) | |
1445 | { | |
1446 | if (WARN_ON_ONCE(nr > 0)) | |
1447 | return -EINVAL; | |
1448 | return dev->irq; | |
1449 | } | |
ee8d41e5 TG |
1450 | static inline const struct cpumask *pci_irq_get_affinity(struct pci_dev *pdev, |
1451 | int vec) | |
1452 | { | |
1453 | return cpu_possible_mask; | |
1454 | } | |
27ddb689 SL |
1455 | |
1456 | static inline int pci_irq_get_node(struct pci_dev *pdev, int vec) | |
1457 | { | |
1458 | return first_online_node; | |
1459 | } | |
1da177e4 LT |
1460 | #endif |
1461 | ||
402723ad CH |
1462 | static inline int |
1463 | pci_alloc_irq_vectors(struct pci_dev *dev, unsigned int min_vecs, | |
1464 | unsigned int max_vecs, unsigned int flags) | |
1465 | { | |
1466 | return pci_alloc_irq_vectors_affinity(dev, min_vecs, max_vecs, flags, | |
1467 | NULL); | |
1468 | } | |
1469 | ||
0d58e6c1 PB |
1470 | /** |
1471 | * pci_irqd_intx_xlate() - Translate PCI INTx value to an IRQ domain hwirq | |
1472 | * @d: the INTx IRQ domain | |
1473 | * @node: the DT node for the device whose interrupt we're translating | |
1474 | * @intspec: the interrupt specifier data from the DT | |
1475 | * @intsize: the number of entries in @intspec | |
1476 | * @out_hwirq: pointer at which to write the hwirq number | |
1477 | * @out_type: pointer at which to write the interrupt type | |
1478 | * | |
1479 | * Translate a PCI INTx interrupt number from device tree in the range 1-4, as | |
1480 | * stored in the standard PCI_INTERRUPT_PIN register, to a value in the range | |
1481 | * 0-3 suitable for use in a 4 entry IRQ domain. That is, subtract one from the | |
1482 | * INTx value to obtain the hwirq number. | |
1483 | * | |
1484 | * Returns 0 on success, or -EINVAL if the interrupt specifier is out of range. | |
1485 | */ | |
1486 | static inline int pci_irqd_intx_xlate(struct irq_domain *d, | |
1487 | struct device_node *node, | |
1488 | const u32 *intspec, | |
1489 | unsigned int intsize, | |
1490 | unsigned long *out_hwirq, | |
1491 | unsigned int *out_type) | |
1492 | { | |
1493 | const u32 intx = intspec[0]; | |
1494 | ||
1495 | if (intx < PCI_INTERRUPT_INTA || intx > PCI_INTERRUPT_INTD) | |
1496 | return -EINVAL; | |
1497 | ||
1498 | *out_hwirq = intx - PCI_INTERRUPT_INTA; | |
1499 | return 0; | |
1500 | } | |
1501 | ||
ab0724ff | 1502 | #ifdef CONFIG_PCIEPORTBUS |
415e12b2 | 1503 | extern bool pcie_ports_disabled; |
5352a44a | 1504 | extern bool pcie_ports_native; |
ab0724ff MT |
1505 | #else |
1506 | #define pcie_ports_disabled true | |
5352a44a | 1507 | #define pcie_ports_native false |
ab0724ff | 1508 | #endif |
415e12b2 | 1509 | |
4c859804 | 1510 | #ifdef CONFIG_PCIEASPM |
f39d5b72 | 1511 | bool pcie_aspm_support_enabled(void); |
4c859804 BH |
1512 | #else |
1513 | static inline bool pcie_aspm_support_enabled(void) { return false; } | |
3e1b1600 AP |
1514 | #endif |
1515 | ||
415e12b2 | 1516 | #ifdef CONFIG_PCIEAER |
415e12b2 RW |
1517 | bool pci_aer_available(void); |
1518 | #else | |
415e12b2 RW |
1519 | static inline bool pci_aer_available(void) { return false; } |
1520 | #endif | |
1521 | ||
4c859804 | 1522 | #ifdef CONFIG_PCIE_ECRC |
f39d5b72 BH |
1523 | void pcie_set_ecrc_checking(struct pci_dev *dev); |
1524 | void pcie_ecrc_get_policy(char *str); | |
4c859804 | 1525 | #else |
2ee546c4 BH |
1526 | static inline void pcie_set_ecrc_checking(struct pci_dev *dev) { } |
1527 | static inline void pcie_ecrc_get_policy(char *str) { } | |
43c16408 AP |
1528 | #endif |
1529 | ||
cef74409 GK |
1530 | bool pci_ats_disabled(void); |
1531 | ||
eec097d4 BH |
1532 | #ifdef CONFIG_PCIE_PTM |
1533 | int pci_enable_ptm(struct pci_dev *dev, u8 *granularity); | |
1534 | #else | |
1535 | static inline int pci_enable_ptm(struct pci_dev *dev, u8 *granularity) | |
1536 | { return -EINVAL; } | |
1537 | #endif | |
1538 | ||
f39d5b72 BH |
1539 | void pci_cfg_access_lock(struct pci_dev *dev); |
1540 | bool pci_cfg_access_trylock(struct pci_dev *dev); | |
1541 | void pci_cfg_access_unlock(struct pci_dev *dev); | |
e04b0ea2 | 1542 | |
4352dfd5 GKH |
1543 | /* |
1544 | * PCI domain support. Sometimes called PCI segment (eg by ACPI), | |
f7625980 | 1545 | * a PCI domain is defined to be a set of PCI buses which share |
4352dfd5 GKH |
1546 | * configuration space. |
1547 | */ | |
32a2eea7 JG |
1548 | #ifdef CONFIG_PCI_DOMAINS |
1549 | extern int pci_domains_supported; | |
1550 | #else | |
1551 | enum { pci_domains_supported = 0 }; | |
2ee546c4 BH |
1552 | static inline int pci_domain_nr(struct pci_bus *bus) { return 0; } |
1553 | static inline int pci_proc_domain(struct pci_bus *bus) { return 0; } | |
32a2eea7 | 1554 | #endif /* CONFIG_PCI_DOMAINS */ |
1da177e4 | 1555 | |
670ba0c8 CM |
1556 | /* |
1557 | * Generic implementation for PCI domain support. If your | |
1558 | * architecture does not need custom management of PCI | |
1559 | * domains then this implementation will be used | |
1560 | */ | |
1561 | #ifdef CONFIG_PCI_DOMAINS_GENERIC | |
1562 | static inline int pci_domain_nr(struct pci_bus *bus) | |
1563 | { | |
1564 | return bus->domain_nr; | |
1565 | } | |
2ab51dde TN |
1566 | #ifdef CONFIG_ACPI |
1567 | int acpi_pci_bus_find_domain_nr(struct pci_bus *bus); | |
670ba0c8 | 1568 | #else |
2ab51dde TN |
1569 | static inline int acpi_pci_bus_find_domain_nr(struct pci_bus *bus) |
1570 | { return 0; } | |
1571 | #endif | |
9c7cb891 | 1572 | int pci_bus_find_domain_nr(struct pci_bus *bus, struct device *parent); |
670ba0c8 CM |
1573 | #endif |
1574 | ||
0aa0f5d1 | 1575 | /* Some architectures require additional setup to direct VGA traffic */ |
95a8b6ef | 1576 | typedef int (*arch_set_vga_state_t)(struct pci_dev *pdev, bool decode, |
0aa0f5d1 | 1577 | unsigned int command_bits, u32 flags); |
f39d5b72 | 1578 | void pci_register_set_vga_state(arch_set_vga_state_t func); |
95a8b6ef | 1579 | |
be9d2e89 JT |
1580 | static inline int |
1581 | pci_request_io_regions(struct pci_dev *pdev, const char *name) | |
1582 | { | |
1583 | return pci_request_selected_regions(pdev, | |
1584 | pci_select_bars(pdev, IORESOURCE_IO), name); | |
1585 | } | |
1586 | ||
1587 | static inline void | |
1588 | pci_release_io_regions(struct pci_dev *pdev) | |
1589 | { | |
1590 | return pci_release_selected_regions(pdev, | |
1591 | pci_select_bars(pdev, IORESOURCE_IO)); | |
1592 | } | |
1593 | ||
1594 | static inline int | |
1595 | pci_request_mem_regions(struct pci_dev *pdev, const char *name) | |
1596 | { | |
1597 | return pci_request_selected_regions(pdev, | |
1598 | pci_select_bars(pdev, IORESOURCE_MEM), name); | |
1599 | } | |
1600 | ||
1601 | static inline void | |
1602 | pci_release_mem_regions(struct pci_dev *pdev) | |
1603 | { | |
1604 | return pci_release_selected_regions(pdev, | |
1605 | pci_select_bars(pdev, IORESOURCE_MEM)); | |
1606 | } | |
1607 | ||
4352dfd5 | 1608 | #else /* CONFIG_PCI is not enabled */ |
1da177e4 | 1609 | |
5bbe029f BH |
1610 | static inline void pci_set_flags(int flags) { } |
1611 | static inline void pci_add_flags(int flags) { } | |
1612 | static inline void pci_clear_flags(int flags) { } | |
1613 | static inline int pci_has_flag(int flag) { return 0; } | |
1614 | ||
1da177e4 | 1615 | /* |
0aa0f5d1 BH |
1616 | * If the system does not have PCI, clearly these return errors. Define |
1617 | * these as simple inline functions to avoid hair in drivers. | |
1da177e4 | 1618 | */ |
05cca6e5 GKH |
1619 | #define _PCI_NOP(o, s, t) \ |
1620 | static inline int pci_##o##_config_##s(struct pci_dev *dev, \ | |
1621 | int where, t val) \ | |
1da177e4 | 1622 | { return PCIBIOS_FUNC_NOT_SUPPORTED; } |
05cca6e5 GKH |
1623 | |
1624 | #define _PCI_NOP_ALL(o, x) _PCI_NOP(o, byte, u8 x) \ | |
1625 | _PCI_NOP(o, word, u16 x) \ | |
1626 | _PCI_NOP(o, dword, u32 x) | |
1da177e4 LT |
1627 | _PCI_NOP_ALL(read, *) |
1628 | _PCI_NOP_ALL(write,) | |
1629 | ||
d42552c3 | 1630 | static inline struct pci_dev *pci_get_device(unsigned int vendor, |
05cca6e5 GKH |
1631 | unsigned int device, |
1632 | struct pci_dev *from) | |
2ee546c4 | 1633 | { return NULL; } |
d42552c3 | 1634 | |
05cca6e5 GKH |
1635 | static inline struct pci_dev *pci_get_subsys(unsigned int vendor, |
1636 | unsigned int device, | |
1637 | unsigned int ss_vendor, | |
1638 | unsigned int ss_device, | |
b08508c4 | 1639 | struct pci_dev *from) |
2ee546c4 | 1640 | { return NULL; } |
1da177e4 | 1641 | |
05cca6e5 GKH |
1642 | static inline struct pci_dev *pci_get_class(unsigned int class, |
1643 | struct pci_dev *from) | |
2ee546c4 | 1644 | { return NULL; } |
1da177e4 LT |
1645 | |
1646 | #define pci_dev_present(ids) (0) | |
ed4aaadb | 1647 | #define no_pci_devices() (1) |
1da177e4 LT |
1648 | #define pci_dev_put(dev) do { } while (0) |
1649 | ||
2ee546c4 BH |
1650 | static inline void pci_set_master(struct pci_dev *dev) { } |
1651 | static inline int pci_enable_device(struct pci_dev *dev) { return -EIO; } | |
1652 | static inline void pci_disable_device(struct pci_dev *dev) { } | |
05cca6e5 | 1653 | static inline int pci_assign_resource(struct pci_dev *dev, int i) |
2ee546c4 | 1654 | { return -EBUSY; } |
05cca6e5 GKH |
1655 | static inline int __pci_register_driver(struct pci_driver *drv, |
1656 | struct module *owner) | |
2ee546c4 | 1657 | { return 0; } |
05cca6e5 | 1658 | static inline int pci_register_driver(struct pci_driver *drv) |
2ee546c4 BH |
1659 | { return 0; } |
1660 | static inline void pci_unregister_driver(struct pci_driver *drv) { } | |
05cca6e5 | 1661 | static inline int pci_find_capability(struct pci_dev *dev, int cap) |
2ee546c4 | 1662 | { return 0; } |
05cca6e5 GKH |
1663 | static inline int pci_find_next_capability(struct pci_dev *dev, u8 post, |
1664 | int cap) | |
2ee546c4 | 1665 | { return 0; } |
05cca6e5 | 1666 | static inline int pci_find_ext_capability(struct pci_dev *dev, int cap) |
2ee546c4 | 1667 | { return 0; } |
05cca6e5 | 1668 | |
1da177e4 | 1669 | /* Power management related routines */ |
2ee546c4 BH |
1670 | static inline int pci_save_state(struct pci_dev *dev) { return 0; } |
1671 | static inline void pci_restore_state(struct pci_dev *dev) { } | |
05cca6e5 | 1672 | static inline int pci_set_power_state(struct pci_dev *dev, pci_power_t state) |
2ee546c4 | 1673 | { return 0; } |
3449248c | 1674 | static inline int pci_wake_from_d3(struct pci_dev *dev, bool enable) |
2ee546c4 | 1675 | { return 0; } |
05cca6e5 GKH |
1676 | static inline pci_power_t pci_choose_state(struct pci_dev *dev, |
1677 | pm_message_t state) | |
2ee546c4 | 1678 | { return PCI_D0; } |
05cca6e5 GKH |
1679 | static inline int pci_enable_wake(struct pci_dev *dev, pci_power_t state, |
1680 | int enable) | |
2ee546c4 | 1681 | { return 0; } |
48a92a81 | 1682 | |
afd29f90 MW |
1683 | static inline struct resource *pci_find_resource(struct pci_dev *dev, |
1684 | struct resource *res) | |
1685 | { return NULL; } | |
05cca6e5 | 1686 | static inline int pci_request_regions(struct pci_dev *dev, const char *res_name) |
2ee546c4 BH |
1687 | { return -EIO; } |
1688 | static inline void pci_release_regions(struct pci_dev *dev) { } | |
0da0ead9 | 1689 | |
c5076cfe TN |
1690 | static inline unsigned long pci_address_to_pio(phys_addr_t addr) { return -1; } |
1691 | ||
2ee546c4 | 1692 | static inline void pci_block_cfg_access(struct pci_dev *dev) { } |
fb51ccbf JK |
1693 | static inline int pci_block_cfg_access_in_atomic(struct pci_dev *dev) |
1694 | { return 0; } | |
2ee546c4 | 1695 | static inline void pci_unblock_cfg_access(struct pci_dev *dev) { } |
e04b0ea2 | 1696 | |
d80d0217 RD |
1697 | static inline struct pci_bus *pci_find_next_bus(const struct pci_bus *from) |
1698 | { return NULL; } | |
d80d0217 RD |
1699 | static inline struct pci_dev *pci_get_slot(struct pci_bus *bus, |
1700 | unsigned int devfn) | |
1701 | { return NULL; } | |
7912af5c RD |
1702 | static inline struct pci_dev *pci_get_domain_bus_and_slot(int domain, |
1703 | unsigned int bus, unsigned int devfn) | |
1704 | { return NULL; } | |
d80d0217 | 1705 | |
2ee546c4 BH |
1706 | static inline int pci_domain_nr(struct pci_bus *bus) { return 0; } |
1707 | static inline struct pci_dev *pci_dev_get(struct pci_dev *dev) { return NULL; } | |
12ea6cad | 1708 | |
fb8a0d9d WM |
1709 | #define dev_is_pci(d) (false) |
1710 | #define dev_is_pf(d) (false) | |
fe594932 GU |
1711 | static inline bool pci_acs_enabled(struct pci_dev *pdev, u16 acs_flags) |
1712 | { return false; } | |
80db6f08 NC |
1713 | static inline int pci_irqd_intx_xlate(struct irq_domain *d, |
1714 | struct device_node *node, | |
1715 | const u32 *intspec, | |
1716 | unsigned int intsize, | |
1717 | unsigned long *out_hwirq, | |
1718 | unsigned int *out_type) | |
1719 | { return -EINVAL; } | |
9c212009 LR |
1720 | |
1721 | static inline const struct pci_device_id *pci_match_id(const struct pci_device_id *ids, | |
1722 | struct pci_dev *dev) | |
1723 | { return NULL; } | |
b9ae16d8 | 1724 | static inline bool pci_ats_disabled(void) { return true; } |
4352dfd5 | 1725 | #endif /* CONFIG_PCI */ |
1da177e4 | 1726 | |
6e1ffbb7 JPB |
1727 | #ifdef CONFIG_PCI_ATS |
1728 | /* Address Translation Service */ | |
1729 | void pci_ats_init(struct pci_dev *dev); | |
1730 | int pci_enable_ats(struct pci_dev *dev, int ps); | |
1731 | void pci_disable_ats(struct pci_dev *dev); | |
1732 | int pci_ats_queue_depth(struct pci_dev *dev); | |
1733 | int pci_ats_page_aligned(struct pci_dev *dev); | |
1734 | #else | |
1735 | static inline void pci_ats_init(struct pci_dev *d) { } | |
1736 | static inline int pci_enable_ats(struct pci_dev *d, int ps) { return -ENODEV; } | |
1737 | static inline void pci_disable_ats(struct pci_dev *d) { } | |
1738 | static inline int pci_ats_queue_depth(struct pci_dev *d) { return -ENODEV; } | |
1739 | static inline int pci_ats_page_aligned(struct pci_dev *dev) { return 0; } | |
1740 | #endif | |
1741 | ||
4352dfd5 GKH |
1742 | /* Include architecture-dependent settings and functions */ |
1743 | ||
1744 | #include <asm/pci.h> | |
1da177e4 | 1745 | |
f7195824 DW |
1746 | /* These two functions provide almost identical functionality. Depennding |
1747 | * on the architecture, one will be implemented as a wrapper around the | |
1748 | * other (in drivers/pci/mmap.c). | |
1749 | * | |
1750 | * pci_mmap_resource_range() maps a specific BAR, and vm->vm_pgoff | |
1751 | * is expected to be an offset within that region. | |
1752 | * | |
1753 | * pci_mmap_page_range() is the legacy architecture-specific interface, | |
1754 | * which accepts a "user visible" resource address converted by | |
1755 | * pci_resource_to_user(), as used in the legacy mmap() interface in | |
1756 | * /proc/bus/pci/. | |
1757 | */ | |
1758 | int pci_mmap_resource_range(struct pci_dev *dev, int bar, | |
1759 | struct vm_area_struct *vma, | |
1760 | enum pci_mmap_state mmap_state, int write_combine); | |
f66e2258 DW |
1761 | int pci_mmap_page_range(struct pci_dev *pdev, int bar, |
1762 | struct vm_area_struct *vma, | |
11df1954 DW |
1763 | enum pci_mmap_state mmap_state, int write_combine); |
1764 | ||
ae749c7a DW |
1765 | #ifndef arch_can_pci_mmap_wc |
1766 | #define arch_can_pci_mmap_wc() 0 | |
1767 | #endif | |
2bea36fd | 1768 | |
e854d8b2 DW |
1769 | #ifndef arch_can_pci_mmap_io |
1770 | #define arch_can_pci_mmap_io() 0 | |
2bea36fd DW |
1771 | #define pci_iobar_pfn(pdev, bar, vma) (-EINVAL) |
1772 | #else | |
1773 | int pci_iobar_pfn(struct pci_dev *pdev, int bar, struct vm_area_struct *vma); | |
e854d8b2 | 1774 | #endif |
ae749c7a | 1775 | |
92016ba5 JO |
1776 | #ifndef pci_root_bus_fwnode |
1777 | #define pci_root_bus_fwnode(bus) NULL | |
1778 | #endif | |
1779 | ||
0aa0f5d1 BH |
1780 | /* |
1781 | * These helpers provide future and backwards compatibility | |
1782 | * for accessing popular PCI BAR info | |
1783 | */ | |
05cca6e5 GKH |
1784 | #define pci_resource_start(dev, bar) ((dev)->resource[(bar)].start) |
1785 | #define pci_resource_end(dev, bar) ((dev)->resource[(bar)].end) | |
1786 | #define pci_resource_flags(dev, bar) ((dev)->resource[(bar)].flags) | |
1da177e4 | 1787 | #define pci_resource_len(dev,bar) \ |
05cca6e5 GKH |
1788 | ((pci_resource_start((dev), (bar)) == 0 && \ |
1789 | pci_resource_end((dev), (bar)) == \ | |
1790 | pci_resource_start((dev), (bar))) ? 0 : \ | |
1791 | \ | |
1792 | (pci_resource_end((dev), (bar)) - \ | |
1793 | pci_resource_start((dev), (bar)) + 1)) | |
1da177e4 | 1794 | |
0aa0f5d1 BH |
1795 | /* |
1796 | * Similar to the helpers above, these manipulate per-pci_dev | |
1da177e4 LT |
1797 | * driver-specific data. They are really just a wrapper around |
1798 | * the generic device structure functions of these calls. | |
1799 | */ | |
05cca6e5 | 1800 | static inline void *pci_get_drvdata(struct pci_dev *pdev) |
1da177e4 LT |
1801 | { |
1802 | return dev_get_drvdata(&pdev->dev); | |
1803 | } | |
1804 | ||
05cca6e5 | 1805 | static inline void pci_set_drvdata(struct pci_dev *pdev, void *data) |
1da177e4 LT |
1806 | { |
1807 | dev_set_drvdata(&pdev->dev, data); | |
1808 | } | |
1809 | ||
2fc90f61 | 1810 | static inline const char *pci_name(const struct pci_dev *pdev) |
1da177e4 | 1811 | { |
c6c4f070 | 1812 | return dev_name(&pdev->dev); |
1da177e4 LT |
1813 | } |
1814 | ||
2311b1f2 | 1815 | |
0aa0f5d1 BH |
1816 | /* |
1817 | * Some archs don't want to expose struct resource to userland as-is | |
2311b1f2 ME |
1818 | * in sysfs and /proc |
1819 | */ | |
8221a013 BH |
1820 | #ifdef HAVE_ARCH_PCI_RESOURCE_TO_USER |
1821 | void pci_resource_to_user(const struct pci_dev *dev, int bar, | |
1822 | const struct resource *rsrc, | |
1823 | resource_size_t *start, resource_size_t *end); | |
1824 | #else | |
2311b1f2 | 1825 | static inline void pci_resource_to_user(const struct pci_dev *dev, int bar, |
05cca6e5 | 1826 | const struct resource *rsrc, resource_size_t *start, |
e31dd6e4 | 1827 | resource_size_t *end) |
2311b1f2 ME |
1828 | { |
1829 | *start = rsrc->start; | |
1830 | *end = rsrc->end; | |
1831 | } | |
1832 | #endif /* HAVE_ARCH_PCI_RESOURCE_TO_USER */ | |
1833 | ||
1834 | ||
1da177e4 | 1835 | /* |
0aa0f5d1 BH |
1836 | * The world is not perfect and supplies us with broken PCI devices. |
1837 | * For at least a part of these bugs we need a work-around, so both | |
1838 | * generic (drivers/pci/quirks.c) and per-architecture code can define | |
1839 | * fixup hooks to be called for particular buggy devices. | |
1da177e4 LT |
1840 | */ |
1841 | ||
1842 | struct pci_fixup { | |
0aa0f5d1 BH |
1843 | u16 vendor; /* Or PCI_ANY_ID */ |
1844 | u16 device; /* Or PCI_ANY_ID */ | |
1845 | u32 class; /* Or PCI_ANY_ID */ | |
f4ca5c6a | 1846 | unsigned int class_shift; /* should be 0, 8, 16 */ |
c9d8b55f AB |
1847 | #ifdef CONFIG_HAVE_ARCH_PREL32_RELOCATIONS |
1848 | int hook_offset; | |
1849 | #else | |
1da177e4 | 1850 | void (*hook)(struct pci_dev *dev); |
c9d8b55f | 1851 | #endif |
1da177e4 LT |
1852 | }; |
1853 | ||
1854 | enum pci_fixup_pass { | |
1855 | pci_fixup_early, /* Before probing BARs */ | |
1856 | pci_fixup_header, /* After reading configuration header */ | |
1857 | pci_fixup_final, /* Final phase of device fixups */ | |
1858 | pci_fixup_enable, /* pci_enable_device() time */ | |
e1a2a51e | 1859 | pci_fixup_resume, /* pci_device_resume() */ |
7d2a01b8 | 1860 | pci_fixup_suspend, /* pci_device_suspend() */ |
e1a2a51e | 1861 | pci_fixup_resume_early, /* pci_device_resume_early() */ |
7d2a01b8 | 1862 | pci_fixup_suspend_late, /* pci_device_suspend_late() */ |
1da177e4 LT |
1863 | }; |
1864 | ||
c9d8b55f AB |
1865 | #ifdef CONFIG_HAVE_ARCH_PREL32_RELOCATIONS |
1866 | #define __DECLARE_PCI_FIXUP_SECTION(sec, name, vendor, device, class, \ | |
1867 | class_shift, hook) \ | |
1868 | __ADDRESSABLE(hook) \ | |
1869 | asm(".section " #sec ", \"a\" \n" \ | |
1870 | ".balign 16 \n" \ | |
1871 | ".short " #vendor ", " #device " \n" \ | |
1872 | ".long " #class ", " #class_shift " \n" \ | |
1873 | ".long " #hook " - . \n" \ | |
1874 | ".previous \n"); | |
1875 | #define DECLARE_PCI_FIXUP_SECTION(sec, name, vendor, device, class, \ | |
1876 | class_shift, hook) \ | |
1877 | __DECLARE_PCI_FIXUP_SECTION(sec, name, vendor, device, class, \ | |
1878 | class_shift, hook) | |
1879 | #else | |
1da177e4 | 1880 | /* Anonymous variables would be nice... */ |
f4ca5c6a YL |
1881 | #define DECLARE_PCI_FIXUP_SECTION(section, name, vendor, device, class, \ |
1882 | class_shift, hook) \ | |
ecf61c78 | 1883 | static const struct pci_fixup __PASTE(__pci_fixup_##name,__LINE__) __used \ |
f4ca5c6a YL |
1884 | __attribute__((__section__(#section), aligned((sizeof(void *))))) \ |
1885 | = { vendor, device, class, class_shift, hook }; | |
c9d8b55f | 1886 | #endif |
f4ca5c6a YL |
1887 | |
1888 | #define DECLARE_PCI_FIXUP_CLASS_EARLY(vendor, device, class, \ | |
1889 | class_shift, hook) \ | |
1890 | DECLARE_PCI_FIXUP_SECTION(.pci_fixup_early, \ | |
ecf61c78 | 1891 | hook, vendor, device, class, class_shift, hook) |
f4ca5c6a YL |
1892 | #define DECLARE_PCI_FIXUP_CLASS_HEADER(vendor, device, class, \ |
1893 | class_shift, hook) \ | |
1894 | DECLARE_PCI_FIXUP_SECTION(.pci_fixup_header, \ | |
ecf61c78 | 1895 | hook, vendor, device, class, class_shift, hook) |
f4ca5c6a YL |
1896 | #define DECLARE_PCI_FIXUP_CLASS_FINAL(vendor, device, class, \ |
1897 | class_shift, hook) \ | |
1898 | DECLARE_PCI_FIXUP_SECTION(.pci_fixup_final, \ | |
ecf61c78 | 1899 | hook, vendor, device, class, class_shift, hook) |
f4ca5c6a YL |
1900 | #define DECLARE_PCI_FIXUP_CLASS_ENABLE(vendor, device, class, \ |
1901 | class_shift, hook) \ | |
1902 | DECLARE_PCI_FIXUP_SECTION(.pci_fixup_enable, \ | |
ecf61c78 | 1903 | hook, vendor, device, class, class_shift, hook) |
f4ca5c6a YL |
1904 | #define DECLARE_PCI_FIXUP_CLASS_RESUME(vendor, device, class, \ |
1905 | class_shift, hook) \ | |
1906 | DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume, \ | |
0aa0f5d1 | 1907 | resume##hook, vendor, device, class, class_shift, hook) |
f4ca5c6a YL |
1908 | #define DECLARE_PCI_FIXUP_CLASS_RESUME_EARLY(vendor, device, class, \ |
1909 | class_shift, hook) \ | |
1910 | DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume_early, \ | |
0aa0f5d1 | 1911 | resume_early##hook, vendor, device, class, class_shift, hook) |
f4ca5c6a YL |
1912 | #define DECLARE_PCI_FIXUP_CLASS_SUSPEND(vendor, device, class, \ |
1913 | class_shift, hook) \ | |
1914 | DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend, \ | |
0aa0f5d1 | 1915 | suspend##hook, vendor, device, class, class_shift, hook) |
7d2a01b8 AN |
1916 | #define DECLARE_PCI_FIXUP_CLASS_SUSPEND_LATE(vendor, device, class, \ |
1917 | class_shift, hook) \ | |
1918 | DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend_late, \ | |
0aa0f5d1 | 1919 | suspend_late##hook, vendor, device, class, class_shift, hook) |
f4ca5c6a | 1920 | |
1da177e4 LT |
1921 | #define DECLARE_PCI_FIXUP_EARLY(vendor, device, hook) \ |
1922 | DECLARE_PCI_FIXUP_SECTION(.pci_fixup_early, \ | |
ecf61c78 | 1923 | hook, vendor, device, PCI_ANY_ID, 0, hook) |
1da177e4 LT |
1924 | #define DECLARE_PCI_FIXUP_HEADER(vendor, device, hook) \ |
1925 | DECLARE_PCI_FIXUP_SECTION(.pci_fixup_header, \ | |
ecf61c78 | 1926 | hook, vendor, device, PCI_ANY_ID, 0, hook) |
1da177e4 LT |
1927 | #define DECLARE_PCI_FIXUP_FINAL(vendor, device, hook) \ |
1928 | DECLARE_PCI_FIXUP_SECTION(.pci_fixup_final, \ | |
ecf61c78 | 1929 | hook, vendor, device, PCI_ANY_ID, 0, hook) |
1da177e4 LT |
1930 | #define DECLARE_PCI_FIXUP_ENABLE(vendor, device, hook) \ |
1931 | DECLARE_PCI_FIXUP_SECTION(.pci_fixup_enable, \ | |
ecf61c78 | 1932 | hook, vendor, device, PCI_ANY_ID, 0, hook) |
1597cacb AC |
1933 | #define DECLARE_PCI_FIXUP_RESUME(vendor, device, hook) \ |
1934 | DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume, \ | |
0aa0f5d1 | 1935 | resume##hook, vendor, device, PCI_ANY_ID, 0, hook) |
e1a2a51e RW |
1936 | #define DECLARE_PCI_FIXUP_RESUME_EARLY(vendor, device, hook) \ |
1937 | DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume_early, \ | |
0aa0f5d1 | 1938 | resume_early##hook, vendor, device, PCI_ANY_ID, 0, hook) |
e1a2a51e RW |
1939 | #define DECLARE_PCI_FIXUP_SUSPEND(vendor, device, hook) \ |
1940 | DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend, \ | |
0aa0f5d1 | 1941 | suspend##hook, vendor, device, PCI_ANY_ID, 0, hook) |
7d2a01b8 AN |
1942 | #define DECLARE_PCI_FIXUP_SUSPEND_LATE(vendor, device, hook) \ |
1943 | DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend_late, \ | |
0aa0f5d1 | 1944 | suspend_late##hook, vendor, device, PCI_ANY_ID, 0, hook) |
1da177e4 | 1945 | |
93177a74 | 1946 | #ifdef CONFIG_PCI_QUIRKS |
1da177e4 | 1947 | void pci_fixup_device(enum pci_fixup_pass pass, struct pci_dev *dev); |
93177a74 RW |
1948 | #else |
1949 | static inline void pci_fixup_device(enum pci_fixup_pass pass, | |
2ee546c4 | 1950 | struct pci_dev *dev) { } |
93177a74 | 1951 | #endif |
1da177e4 | 1952 | |
05cca6e5 | 1953 | void __iomem *pcim_iomap(struct pci_dev *pdev, int bar, unsigned long maxlen); |
5ea81769 | 1954 | void pcim_iounmap(struct pci_dev *pdev, void __iomem *addr); |
05cca6e5 | 1955 | void __iomem * const *pcim_iomap_table(struct pci_dev *pdev); |
fb7ebfe4 YL |
1956 | int pcim_iomap_regions(struct pci_dev *pdev, int mask, const char *name); |
1957 | int pcim_iomap_regions_request_all(struct pci_dev *pdev, int mask, | |
916fbfb7 | 1958 | const char *name); |
fb7ebfe4 | 1959 | void pcim_iounmap_regions(struct pci_dev *pdev, int mask); |
5ea81769 | 1960 | |
1da177e4 | 1961 | extern int pci_pci_problems; |
236561e5 | 1962 | #define PCIPCI_FAIL 1 /* No PCI PCI DMA */ |
1da177e4 LT |
1963 | #define PCIPCI_TRITON 2 |
1964 | #define PCIPCI_NATOMA 4 | |
1965 | #define PCIPCI_VIAETBF 8 | |
1966 | #define PCIPCI_VSFX 16 | |
236561e5 AC |
1967 | #define PCIPCI_ALIMAGIK 32 /* Need low latency setting */ |
1968 | #define PCIAGP_FAIL 64 /* No PCI to AGP DMA */ | |
1da177e4 | 1969 | |
4516a618 AN |
1970 | extern unsigned long pci_cardbus_io_size; |
1971 | extern unsigned long pci_cardbus_mem_size; | |
15856ad5 | 1972 | extern u8 pci_dfl_cache_line_size; |
ac1aa47b | 1973 | extern u8 pci_cache_line_size; |
4516a618 | 1974 | |
28760489 EB |
1975 | extern unsigned long pci_hotplug_io_size; |
1976 | extern unsigned long pci_hotplug_mem_size; | |
e16b4660 | 1977 | extern unsigned long pci_hotplug_bus_size; |
28760489 | 1978 | |
f7625980 | 1979 | /* Architecture-specific versions may override these (weak) */ |
19792a08 | 1980 | void pcibios_disable_device(struct pci_dev *dev); |
cfce9fb8 | 1981 | void pcibios_set_master(struct pci_dev *dev); |
19792a08 AB |
1982 | int pcibios_set_pcie_reset_state(struct pci_dev *dev, |
1983 | enum pcie_reset_state state); | |
eca0d467 | 1984 | int pcibios_add_device(struct pci_dev *dev); |
6ae32c53 | 1985 | void pcibios_release_device(struct pci_dev *dev); |
5d32a665 | 1986 | #ifdef CONFIG_PCI |
a43ae58c | 1987 | void pcibios_penalize_isa_irq(int irq, int active); |
5d32a665 SK |
1988 | #else |
1989 | static inline void pcibios_penalize_isa_irq(int irq, int active) {} | |
1990 | #endif | |
890e4847 JL |
1991 | int pcibios_alloc_irq(struct pci_dev *dev); |
1992 | void pcibios_free_irq(struct pci_dev *dev); | |
619e6f34 | 1993 | resource_size_t pcibios_default_alignment(void); |
575e3348 | 1994 | |
699c1985 SO |
1995 | #ifdef CONFIG_HIBERNATE_CALLBACKS |
1996 | extern struct dev_pm_ops pcibios_pm_ops; | |
1997 | #endif | |
1998 | ||
935c760e | 1999 | #if defined(CONFIG_PCI_MMCONFIG) || defined(CONFIG_ACPI_MCFG) |
f39d5b72 BH |
2000 | void __init pci_mmcfg_early_init(void); |
2001 | void __init pci_mmcfg_late_init(void); | |
7752d5cf | 2002 | #else |
bb63b421 | 2003 | static inline void pci_mmcfg_early_init(void) { } |
7752d5cf RH |
2004 | static inline void pci_mmcfg_late_init(void) { } |
2005 | #endif | |
2006 | ||
642c92da | 2007 | int pci_ext_cfg_avail(void); |
0ef5f8f6 | 2008 | |
1684f5dd | 2009 | void __iomem *pci_ioremap_bar(struct pci_dev *pdev, int bar); |
c43996f4 | 2010 | void __iomem *pci_ioremap_wc_bar(struct pci_dev *pdev, int bar); |
aa42d7c6 | 2011 | |
dd7cc44d | 2012 | #ifdef CONFIG_PCI_IOV |
b07579c0 WY |
2013 | int pci_iov_virtfn_bus(struct pci_dev *dev, int id); |
2014 | int pci_iov_virtfn_devfn(struct pci_dev *dev, int id); | |
2015 | ||
f39d5b72 BH |
2016 | int pci_enable_sriov(struct pci_dev *dev, int nr_virtfn); |
2017 | void pci_disable_sriov(struct pci_dev *dev); | |
753f6124 JS |
2018 | int pci_iov_add_virtfn(struct pci_dev *dev, int id); |
2019 | void pci_iov_remove_virtfn(struct pci_dev *dev, int id); | |
f39d5b72 | 2020 | int pci_num_vf(struct pci_dev *dev); |
5a8eb242 | 2021 | int pci_vfs_assigned(struct pci_dev *dev); |
f39d5b72 BH |
2022 | int pci_sriov_set_totalvfs(struct pci_dev *dev, u16 numvfs); |
2023 | int pci_sriov_get_totalvfs(struct pci_dev *dev); | |
8effc395 | 2024 | int pci_sriov_configure_simple(struct pci_dev *dev, int nr_virtfn); |
0e6c9122 | 2025 | resource_size_t pci_iov_resource_size(struct pci_dev *dev, int resno); |
608c0d88 | 2026 | void pci_vf_drivers_autoprobe(struct pci_dev *dev, bool probe); |
619e6f34 MM |
2027 | |
2028 | /* Arch may override these (weak) */ | |
2029 | int pcibios_sriov_enable(struct pci_dev *pdev, u16 num_vfs); | |
2030 | int pcibios_sriov_disable(struct pci_dev *pdev); | |
2031 | resource_size_t pcibios_iov_resource_alignment(struct pci_dev *dev, int resno); | |
dd7cc44d | 2032 | #else |
b07579c0 WY |
2033 | static inline int pci_iov_virtfn_bus(struct pci_dev *dev, int id) |
2034 | { | |
2035 | return -ENOSYS; | |
2036 | } | |
2037 | static inline int pci_iov_virtfn_devfn(struct pci_dev *dev, int id) | |
2038 | { | |
2039 | return -ENOSYS; | |
2040 | } | |
dd7cc44d | 2041 | static inline int pci_enable_sriov(struct pci_dev *dev, int nr_virtfn) |
2ee546c4 | 2042 | { return -ENODEV; } |
753f6124 | 2043 | static inline int pci_iov_add_virtfn(struct pci_dev *dev, int id) |
c194f7ea WY |
2044 | { |
2045 | return -ENOSYS; | |
2046 | } | |
2047 | static inline void pci_iov_remove_virtfn(struct pci_dev *dev, | |
753f6124 | 2048 | int id) { } |
2ee546c4 | 2049 | static inline void pci_disable_sriov(struct pci_dev *dev) { } |
2ee546c4 | 2050 | static inline int pci_num_vf(struct pci_dev *dev) { return 0; } |
5a8eb242 | 2051 | static inline int pci_vfs_assigned(struct pci_dev *dev) |
2ee546c4 | 2052 | { return 0; } |
bff73156 | 2053 | static inline int pci_sriov_set_totalvfs(struct pci_dev *dev, u16 numvfs) |
2ee546c4 | 2054 | { return 0; } |
bff73156 | 2055 | static inline int pci_sriov_get_totalvfs(struct pci_dev *dev) |
2ee546c4 | 2056 | { return 0; } |
8effc395 | 2057 | #define pci_sriov_configure_simple NULL |
0e6c9122 WY |
2058 | static inline resource_size_t pci_iov_resource_size(struct pci_dev *dev, int resno) |
2059 | { return 0; } | |
608c0d88 | 2060 | static inline void pci_vf_drivers_autoprobe(struct pci_dev *dev, bool probe) { } |
dd7cc44d YZ |
2061 | #endif |
2062 | ||
c825bc94 | 2063 | #if defined(CONFIG_HOTPLUG_PCI) || defined(CONFIG_HOTPLUG_PCI_MODULE) |
f39d5b72 BH |
2064 | void pci_hp_create_module_link(struct pci_slot *pci_slot); |
2065 | void pci_hp_remove_module_link(struct pci_slot *pci_slot); | |
c825bc94 KK |
2066 | #endif |
2067 | ||
d7b7e605 KK |
2068 | /** |
2069 | * pci_pcie_cap - get the saved PCIe capability offset | |
2070 | * @dev: PCI device | |
2071 | * | |
2072 | * PCIe capability offset is calculated at PCI device initialization | |
2073 | * time and saved in the data structure. This function returns saved | |
2074 | * PCIe capability offset. Using this instead of pci_find_capability() | |
2075 | * reduces unnecessary search in the PCI configuration space. If you | |
2076 | * need to calculate PCIe capability offset from raw device for some | |
2077 | * reasons, please use pci_find_capability() instead. | |
2078 | */ | |
2079 | static inline int pci_pcie_cap(struct pci_dev *dev) | |
2080 | { | |
2081 | return dev->pcie_cap; | |
2082 | } | |
2083 | ||
7eb776c4 KK |
2084 | /** |
2085 | * pci_is_pcie - check if the PCI device is PCI Express capable | |
2086 | * @dev: PCI device | |
2087 | * | |
a895c28a | 2088 | * Returns: true if the PCI device is PCI Express capable, false otherwise. |
7eb776c4 KK |
2089 | */ |
2090 | static inline bool pci_is_pcie(struct pci_dev *dev) | |
2091 | { | |
a895c28a | 2092 | return pci_pcie_cap(dev); |
7eb776c4 KK |
2093 | } |
2094 | ||
7c9c003c MS |
2095 | /** |
2096 | * pcie_caps_reg - get the PCIe Capabilities Register | |
2097 | * @dev: PCI device | |
2098 | */ | |
2099 | static inline u16 pcie_caps_reg(const struct pci_dev *dev) | |
2100 | { | |
2101 | return dev->pcie_flags_reg; | |
2102 | } | |
2103 | ||
786e2288 YW |
2104 | /** |
2105 | * pci_pcie_type - get the PCIe device/port type | |
2106 | * @dev: PCI device | |
2107 | */ | |
2108 | static inline int pci_pcie_type(const struct pci_dev *dev) | |
2109 | { | |
1c531d82 | 2110 | return (pcie_caps_reg(dev) & PCI_EXP_FLAGS_TYPE) >> 4; |
786e2288 YW |
2111 | } |
2112 | ||
e784930b JT |
2113 | static inline struct pci_dev *pcie_find_root_port(struct pci_dev *dev) |
2114 | { | |
2115 | while (1) { | |
2116 | if (!pci_is_pcie(dev)) | |
2117 | break; | |
2118 | if (pci_pcie_type(dev) == PCI_EXP_TYPE_ROOT_PORT) | |
2119 | return dev; | |
2120 | if (!dev->bus->self) | |
2121 | break; | |
2122 | dev = dev->bus->self; | |
2123 | } | |
2124 | return NULL; | |
2125 | } | |
2126 | ||
5d990b62 | 2127 | void pci_request_acs(void); |
ad805758 AW |
2128 | bool pci_acs_enabled(struct pci_dev *pdev, u16 acs_flags); |
2129 | bool pci_acs_path_enabled(struct pci_dev *start, | |
2130 | struct pci_dev *end, u16 acs_flags); | |
430a2368 | 2131 | int pci_enable_atomic_ops_to_root(struct pci_dev *dev, u32 cap_mask); |
a2ce7662 | 2132 | |
7ad506fa | 2133 | #define PCI_VPD_LRDT 0x80 /* Large Resource Data Type */ |
63ddc0b8 | 2134 | #define PCI_VPD_LRDT_ID(x) ((x) | PCI_VPD_LRDT) |
7ad506fa MC |
2135 | |
2136 | /* Large Resource Data Type Tag Item Names */ | |
2137 | #define PCI_VPD_LTIN_ID_STRING 0x02 /* Identifier String */ | |
2138 | #define PCI_VPD_LTIN_RO_DATA 0x10 /* Read-Only Data */ | |
2139 | #define PCI_VPD_LTIN_RW_DATA 0x11 /* Read-Write Data */ | |
2140 | ||
2141 | #define PCI_VPD_LRDT_ID_STRING PCI_VPD_LRDT_ID(PCI_VPD_LTIN_ID_STRING) | |
2142 | #define PCI_VPD_LRDT_RO_DATA PCI_VPD_LRDT_ID(PCI_VPD_LTIN_RO_DATA) | |
2143 | #define PCI_VPD_LRDT_RW_DATA PCI_VPD_LRDT_ID(PCI_VPD_LTIN_RW_DATA) | |
2144 | ||
2145 | /* Small Resource Data Type Tag Item Names */ | |
9eb45d5c | 2146 | #define PCI_VPD_STIN_END 0x0f /* End */ |
7ad506fa | 2147 | |
9eb45d5c | 2148 | #define PCI_VPD_SRDT_END (PCI_VPD_STIN_END << 3) |
7ad506fa MC |
2149 | |
2150 | #define PCI_VPD_SRDT_TIN_MASK 0x78 | |
2151 | #define PCI_VPD_SRDT_LEN_MASK 0x07 | |
9eb45d5c | 2152 | #define PCI_VPD_LRDT_TIN_MASK 0x7f |
7ad506fa MC |
2153 | |
2154 | #define PCI_VPD_LRDT_TAG_SIZE 3 | |
2155 | #define PCI_VPD_SRDT_TAG_SIZE 1 | |
a2ce7662 | 2156 | |
e1d5bdab MC |
2157 | #define PCI_VPD_INFO_FLD_HDR_SIZE 3 |
2158 | ||
4067a854 MC |
2159 | #define PCI_VPD_RO_KEYWORD_PARTNO "PN" |
2160 | #define PCI_VPD_RO_KEYWORD_MFR_ID "MN" | |
2161 | #define PCI_VPD_RO_KEYWORD_VENDOR0 "V0" | |
d4894f3e | 2162 | #define PCI_VPD_RO_KEYWORD_CHKSUM "RV" |
4067a854 | 2163 | |
a2ce7662 MC |
2164 | /** |
2165 | * pci_vpd_lrdt_size - Extracts the Large Resource Data Type length | |
2166 | * @lrdt: Pointer to the beginning of the Large Resource Data Type tag | |
2167 | * | |
2168 | * Returns the extracted Large Resource Data Type length. | |
2169 | */ | |
2170 | static inline u16 pci_vpd_lrdt_size(const u8 *lrdt) | |
2171 | { | |
2172 | return (u16)lrdt[1] + ((u16)lrdt[2] << 8); | |
2173 | } | |
2174 | ||
9eb45d5c HR |
2175 | /** |
2176 | * pci_vpd_lrdt_tag - Extracts the Large Resource Data Type Tag Item | |
2177 | * @lrdt: Pointer to the beginning of the Large Resource Data Type tag | |
2178 | * | |
2179 | * Returns the extracted Large Resource Data Type Tag item. | |
2180 | */ | |
2181 | static inline u16 pci_vpd_lrdt_tag(const u8 *lrdt) | |
2182 | { | |
0aa0f5d1 | 2183 | return (u16)(lrdt[0] & PCI_VPD_LRDT_TIN_MASK); |
9eb45d5c HR |
2184 | } |
2185 | ||
7ad506fa MC |
2186 | /** |
2187 | * pci_vpd_srdt_size - Extracts the Small Resource Data Type length | |
0142626d | 2188 | * @srdt: Pointer to the beginning of the Small Resource Data Type tag |
7ad506fa MC |
2189 | * |
2190 | * Returns the extracted Small Resource Data Type length. | |
2191 | */ | |
2192 | static inline u8 pci_vpd_srdt_size(const u8 *srdt) | |
2193 | { | |
2194 | return (*srdt) & PCI_VPD_SRDT_LEN_MASK; | |
2195 | } | |
2196 | ||
9eb45d5c HR |
2197 | /** |
2198 | * pci_vpd_srdt_tag - Extracts the Small Resource Data Type Tag Item | |
0142626d | 2199 | * @srdt: Pointer to the beginning of the Small Resource Data Type tag |
9eb45d5c HR |
2200 | * |
2201 | * Returns the extracted Small Resource Data Type Tag Item. | |
2202 | */ | |
2203 | static inline u8 pci_vpd_srdt_tag(const u8 *srdt) | |
2204 | { | |
2205 | return ((*srdt) & PCI_VPD_SRDT_TIN_MASK) >> 3; | |
2206 | } | |
2207 | ||
e1d5bdab MC |
2208 | /** |
2209 | * pci_vpd_info_field_size - Extracts the information field length | |
2210 | * @lrdt: Pointer to the beginning of an information field header | |
2211 | * | |
2212 | * Returns the extracted information field length. | |
2213 | */ | |
2214 | static inline u8 pci_vpd_info_field_size(const u8 *info_field) | |
2215 | { | |
2216 | return info_field[2]; | |
2217 | } | |
2218 | ||
b55ac1b2 MC |
2219 | /** |
2220 | * pci_vpd_find_tag - Locates the Resource Data Type tag provided | |
2221 | * @buf: Pointer to buffered vpd data | |
2222 | * @off: The offset into the buffer at which to begin the search | |
2223 | * @len: The length of the vpd buffer | |
2224 | * @rdt: The Resource Data Type to search for | |
2225 | * | |
2226 | * Returns the index where the Resource Data Type was found or | |
2227 | * -ENOENT otherwise. | |
2228 | */ | |
2229 | int pci_vpd_find_tag(const u8 *buf, unsigned int off, unsigned int len, u8 rdt); | |
2230 | ||
4067a854 MC |
2231 | /** |
2232 | * pci_vpd_find_info_keyword - Locates an information field keyword in the VPD | |
2233 | * @buf: Pointer to buffered vpd data | |
2234 | * @off: The offset into the buffer at which to begin the search | |
2235 | * @len: The length of the buffer area, relative to off, in which to search | |
2236 | * @kw: The keyword to search for | |
2237 | * | |
2238 | * Returns the index where the information field keyword was found or | |
2239 | * -ENOENT otherwise. | |
2240 | */ | |
2241 | int pci_vpd_find_info_keyword(const u8 *buf, unsigned int off, | |
2242 | unsigned int len, const char *kw); | |
2243 | ||
98d9f30c BH |
2244 | /* PCI <-> OF binding helpers */ |
2245 | #ifdef CONFIG_OF | |
2246 | struct device_node; | |
b165e2b6 | 2247 | struct irq_domain; |
f39d5b72 BH |
2248 | void pci_set_of_node(struct pci_dev *dev); |
2249 | void pci_release_of_node(struct pci_dev *dev); | |
2250 | void pci_set_bus_of_node(struct pci_bus *bus); | |
2251 | void pci_release_bus_of_node(struct pci_bus *bus); | |
b165e2b6 | 2252 | struct irq_domain *pci_host_bridge_of_msi_domain(struct pci_bus *bus); |
3a8f77e4 CP |
2253 | int pci_parse_request_of_pci_ranges(struct device *dev, |
2254 | struct list_head *resources, | |
2255 | struct resource **bus_range); | |
98d9f30c BH |
2256 | |
2257 | /* Arch may override this (weak) */ | |
723ec4d0 | 2258 | struct device_node *pcibios_get_phb_of_node(struct pci_bus *bus); |
98d9f30c | 2259 | |
0aa0f5d1 | 2260 | #else /* CONFIG_OF */ |
98d9f30c BH |
2261 | static inline void pci_set_of_node(struct pci_dev *dev) { } |
2262 | static inline void pci_release_of_node(struct pci_dev *dev) { } | |
2263 | static inline void pci_set_bus_of_node(struct pci_bus *bus) { } | |
2264 | static inline void pci_release_bus_of_node(struct pci_bus *bus) { } | |
b165e2b6 MZ |
2265 | static inline struct irq_domain * |
2266 | pci_host_bridge_of_msi_domain(struct pci_bus *bus) { return NULL; } | |
3a8f77e4 CP |
2267 | static inline int pci_parse_request_of_pci_ranges(struct device *dev, |
2268 | struct list_head *resources, | |
2269 | struct resource **bus_range) | |
2270 | { | |
2271 | return -EINVAL; | |
2272 | } | |
98d9f30c BH |
2273 | #endif /* CONFIG_OF */ |
2274 | ||
ad32eb2d BM |
2275 | static inline struct device_node * |
2276 | pci_device_to_OF_node(const struct pci_dev *pdev) | |
2277 | { | |
2278 | return pdev ? pdev->dev.of_node : NULL; | |
2279 | } | |
2280 | ||
2281 | static inline struct device_node *pci_bus_to_OF_node(struct pci_bus *bus) | |
2282 | { | |
2283 | return bus ? bus->dev.of_node : NULL; | |
2284 | } | |
2285 | ||
471036b2 SS |
2286 | #ifdef CONFIG_ACPI |
2287 | struct irq_domain *pci_host_bridge_acpi_msi_domain(struct pci_bus *bus); | |
2288 | ||
2289 | void | |
2290 | pci_msi_register_fwnode_provider(struct fwnode_handle *(*fn)(struct device *)); | |
2291 | #else | |
2292 | static inline struct irq_domain * | |
2293 | pci_host_bridge_acpi_msi_domain(struct pci_bus *bus) { return NULL; } | |
2294 | #endif | |
2295 | ||
eb740b5f GS |
2296 | #ifdef CONFIG_EEH |
2297 | static inline struct eeh_dev *pci_dev_to_eeh_dev(struct pci_dev *pdev) | |
2298 | { | |
2299 | return pdev->dev.archdata.edev; | |
2300 | } | |
2301 | #endif | |
2302 | ||
f0af9593 | 2303 | void pci_add_dma_alias(struct pci_dev *dev, u8 devfn); |
338c3149 | 2304 | bool pci_devs_are_dma_aliases(struct pci_dev *dev1, struct pci_dev *dev2); |
c25dc828 AW |
2305 | int pci_for_each_dma_alias(struct pci_dev *pdev, |
2306 | int (*fn)(struct pci_dev *pdev, | |
2307 | u16 alias, void *data), void *data); | |
2308 | ||
0aa0f5d1 | 2309 | /* Helper functions for operation of device flag */ |
ce052984 EZ |
2310 | static inline void pci_set_dev_assigned(struct pci_dev *pdev) |
2311 | { | |
2312 | pdev->dev_flags |= PCI_DEV_FLAGS_ASSIGNED; | |
2313 | } | |
2314 | static inline void pci_clear_dev_assigned(struct pci_dev *pdev) | |
2315 | { | |
2316 | pdev->dev_flags &= ~PCI_DEV_FLAGS_ASSIGNED; | |
2317 | } | |
2318 | static inline bool pci_is_dev_assigned(struct pci_dev *pdev) | |
2319 | { | |
2320 | return (pdev->dev_flags & PCI_DEV_FLAGS_ASSIGNED) == PCI_DEV_FLAGS_ASSIGNED; | |
2321 | } | |
19bdb6e4 AW |
2322 | |
2323 | /** | |
2324 | * pci_ari_enabled - query ARI forwarding status | |
2325 | * @bus: the PCI bus | |
2326 | * | |
2327 | * Returns true if ARI forwarding is enabled. | |
2328 | */ | |
2329 | static inline bool pci_ari_enabled(struct pci_bus *bus) | |
2330 | { | |
2331 | return bus->self && bus->self->ari_enabled; | |
2332 | } | |
bc4b024a | 2333 | |
8531e283 LW |
2334 | /** |
2335 | * pci_is_thunderbolt_attached - whether device is on a Thunderbolt daisy chain | |
2336 | * @pdev: PCI device to check | |
2337 | * | |
2338 | * Walk upwards from @pdev and check for each encountered bridge if it's part | |
2339 | * of a Thunderbolt controller. Reaching the host bridge means @pdev is not | |
2340 | * Thunderbolt-attached. (But rather soldered to the mainboard usually.) | |
2341 | */ | |
2342 | static inline bool pci_is_thunderbolt_attached(struct pci_dev *pdev) | |
2343 | { | |
2344 | struct pci_dev *parent = pdev; | |
2345 | ||
2346 | if (pdev->is_thunderbolt) | |
2347 | return true; | |
2348 | ||
2349 | while ((parent = pci_upstream_bridge(parent))) | |
2350 | if (parent->is_thunderbolt) | |
2351 | return true; | |
2352 | ||
2353 | return false; | |
2354 | } | |
2355 | ||
2e28bc84 | 2356 | #if defined(CONFIG_PCIEPORTBUS) || defined(CONFIG_EEH) |
3ecac020 ME |
2357 | void pci_uevent_ers(struct pci_dev *pdev, enum pci_ers_result err_type); |
2358 | #endif | |
856e1eb9 | 2359 | |
0aa0f5d1 | 2360 | /* Provide the legacy pci_dma_* API */ |
bc4b024a CH |
2361 | #include <linux/pci-dma-compat.h> |
2362 | ||
7506dc79 FL |
2363 | #define pci_printk(level, pdev, fmt, arg...) \ |
2364 | dev_printk(level, &(pdev)->dev, fmt, ##arg) | |
2365 | ||
2366 | #define pci_emerg(pdev, fmt, arg...) dev_emerg(&(pdev)->dev, fmt, ##arg) | |
2367 | #define pci_alert(pdev, fmt, arg...) dev_alert(&(pdev)->dev, fmt, ##arg) | |
2368 | #define pci_crit(pdev, fmt, arg...) dev_crit(&(pdev)->dev, fmt, ##arg) | |
2369 | #define pci_err(pdev, fmt, arg...) dev_err(&(pdev)->dev, fmt, ##arg) | |
2370 | #define pci_warn(pdev, fmt, arg...) dev_warn(&(pdev)->dev, fmt, ##arg) | |
2371 | #define pci_notice(pdev, fmt, arg...) dev_notice(&(pdev)->dev, fmt, ##arg) | |
2372 | #define pci_info(pdev, fmt, arg...) dev_info(&(pdev)->dev, fmt, ##arg) | |
2373 | #define pci_dbg(pdev, fmt, arg...) dev_dbg(&(pdev)->dev, fmt, ##arg) | |
2374 | ||
a88a7b3e BH |
2375 | #define pci_notice_ratelimited(pdev, fmt, arg...) \ |
2376 | dev_notice_ratelimited(&(pdev)->dev, fmt, ##arg) | |
2377 | ||
1da177e4 | 2378 | #endif /* LINUX_PCI_H */ |