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PCI: Factor out pcie_retrain_link() function
[mirror_ubuntu-bionic-kernel.git] / include / linux / pci.h
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b2441318 1/* SPDX-License-Identifier: GPL-2.0 */
1da177e4
LT		 2/*
3 * pci.h
4 *
5 * PCI defines and function prototypes
6 * Copyright 1994, Drew Eckhardt
7 * Copyright 1997--1999 Martin Mares <mj@ucw.cz>
8 *
9 * For more information, please consult the following manuals (look at
10 * http://www.pcisig.com/ for how to get them):
11 *
12 * PCI BIOS Specification
13 * PCI Local Bus Specification
14 * PCI to PCI Bridge Specification
15 * PCI System Design Guide
16 */
1da177e4
LT		 17#ifndef LINUX_PCI_H
18#define LINUX_PCI_H
19
1da177e4 20
778382e0
DW		 21#include <linux/mod_devicetable.h>
22
1da177e4 23#include <linux/types.h>
98db6f19 24#include <linux/init.h>
1da177e4
LT		 25#include <linux/ioport.h>
26#include <linux/list.h>
4a7fb636 27#include <linux/compiler.h>
1da177e4 28#include <linux/errno.h>
f46753c5 29#include <linux/kobject.h>
60063497 30#include <linux/atomic.h>
1da177e4 31#include <linux/device.h>
704e8953 32#include <linux/interrupt.h>
1388cc96 33#include <linux/io.h>
14d76b68 34#include <linux/resource_ext.h>
607ca46e 35#include <uapi/linux/pci.h>
1da177e4 36
7e7a43c3
AB		 37#include <linux/pci_ids.h>
38
85467136
SK		 39/*
40 * The PCI interface treats multi-function devices as independent
41 * devices. The slot/function address of each device is encoded
42 * in a single byte as follows:
43 *
44 * 7:3 = slot
45 * 2:0 = function
f7625980
BH		 46 *
47 * PCI_DEVFN(), PCI_SLOT(), and PCI_FUNC() are defined in uapi/linux/pci.h.
85467136 48 * In the interest of not exposing interfaces to user-space unnecessarily,
f7625980 49 * the following kernel-only defines are being added here.
85467136 50 */
63ddc0b8 51#define PCI_DEVID(bus, devfn) ((((u16)(bus)) << 8) | (devfn))
85467136
SK		 52/* return bus from PCI devid = ((u16)bus_number) << 8) | devfn */
53#define PCI_BUS_NUM(x) (((x) >> 8) & 0xff)
54
f46753c5
AC		 55/* pci_slot represents a physical slot */
56struct pci_slot {
57 struct pci_bus *bus; /* The bus this slot is on */
58 struct list_head list; /* node in list of slots on this bus */
59 struct hotplug_slot *hotplug; /* Hotplug info (migrate over time) */
60 unsigned char number; /* PCI_SLOT(pci_dev->devfn) */
61 struct kobject kobj;
62};
63
0ad772ec
AC		 64static inline const char *pci_slot_name(const struct pci_slot *slot)
65{
66 return kobject_name(&slot->kobj);
67}
68
1da177e4
LT		 69/* File state for mmap()s on /proc/bus/pci/X/Y */
70enum pci_mmap_state {
71 pci_mmap_io,
72 pci_mmap_mem
73};
74
fde09c6d
YZ		 75/*
76 * For PCI devices, the region numbers are assigned this way:
77 */
78enum {
79 /* #0-5: standard PCI resources */
80 PCI_STD_RESOURCES,
81 PCI_STD_RESOURCE_END = 5,
82
83 /* #6: expansion ROM resource */
84 PCI_ROM_RESOURCE,
85
d1b054da
YZ		 86 /* device specific resources */
87#ifdef CONFIG_PCI_IOV
88 PCI_IOV_RESOURCES,
89 PCI_IOV_RESOURCE_END = PCI_IOV_RESOURCES + PCI_SRIOV_NUM_BARS - 1,
90#endif
91
fde09c6d
YZ		 92 /* resources assigned to buses behind the bridge */
93#define PCI_BRIDGE_RESOURCE_NUM 4
94
95 PCI_BRIDGE_RESOURCES,
96 PCI_BRIDGE_RESOURCE_END = PCI_BRIDGE_RESOURCES +
97 PCI_BRIDGE_RESOURCE_NUM - 1,
98
99 /* total resources associated with a PCI device */
100 PCI_NUM_RESOURCES,
101
102 /* preserve this for compatibility */
cda57bf9 103 DEVICE_COUNT_RESOURCE = PCI_NUM_RESOURCES,
fde09c6d 104};
1da177e4 105
b352baf1
PB		 106/**
107 * enum pci_interrupt_pin - PCI INTx interrupt values
108 * @PCI_INTERRUPT_UNKNOWN: Unknown or unassigned interrupt
109 * @PCI_INTERRUPT_INTA: PCI INTA pin
110 * @PCI_INTERRUPT_INTB: PCI INTB pin
111 * @PCI_INTERRUPT_INTC: PCI INTC pin
112 * @PCI_INTERRUPT_INTD: PCI INTD pin
113 *
114 * Corresponds to values for legacy PCI INTx interrupts, as can be found in the
115 * PCI_INTERRUPT_PIN register.
116 */
117enum pci_interrupt_pin {
118 PCI_INTERRUPT_UNKNOWN,
119 PCI_INTERRUPT_INTA,
120 PCI_INTERRUPT_INTB,
121 PCI_INTERRUPT_INTC,
122 PCI_INTERRUPT_INTD,
123};
124
125/* The number of legacy PCI INTx interrupts */
126#define PCI_NUM_INTX 4
127
224abb67
BH		 128/*
129 * pci_power_t values must match the bits in the Capabilities PME_Support
130 * and Control/Status PowerState fields in the Power Management capability.
131 */
1da177e4
LT		 132typedef int __bitwise pci_power_t;
133
4352dfd5
GKH		 134#define PCI_D0 ((pci_power_t __force) 0)
135#define PCI_D1 ((pci_power_t __force) 1)
136#define PCI_D2 ((pci_power_t __force) 2)
1da177e4
LT		 137#define PCI_D3hot ((pci_power_t __force) 3)
138#define PCI_D3cold ((pci_power_t __force) 4)
3fe9d19f 139#define PCI_UNKNOWN ((pci_power_t __force) 5)
438510f6 140#define PCI_POWER_ERROR ((pci_power_t __force) -1)
1da177e4 141
00240c38
AS		 142/* Remember to update this when the list above changes! */
143extern const char *pci_power_names[];
144
145static inline const char *pci_power_name(pci_power_t state)
146{
9661e783 147 return pci_power_names[1 + (__force int) state];
00240c38
AS		 148}
149
448bd857
HY		 150#define PCI_PM_D2_DELAY 200
151#define PCI_PM_D3_WAIT 10
152#define PCI_PM_D3COLD_WAIT 100
153#define PCI_PM_BUS_WAIT 50
aa8c6c93 154
392a1ce7
LV		 155/** The pci_channel state describes connectivity between the CPU and
156 * the pci device. If some PCI bus between here and the pci device
157 * has crashed or locked up, this info is reflected here.
158 */
159typedef unsigned int __bitwise pci_channel_state_t;
160
161enum pci_channel_state {
162 /* I/O channel is in normal state */
163 pci_channel_io_normal = (__force pci_channel_state_t) 1,
164
165 /* I/O to channel is blocked */
166 pci_channel_io_frozen = (__force pci_channel_state_t) 2,
167
168 /* PCI card is dead */
169 pci_channel_io_perm_failure = (__force pci_channel_state_t) 3,
170};
171
f7bdd12d
BK		 172typedef unsigned int __bitwise pcie_reset_state_t;
173
174enum pcie_reset_state {
175 /* Reset is NOT asserted (Use to deassert reset) */
176 pcie_deassert_reset = (__force pcie_reset_state_t) 1,
177
f7625980 178 /* Use #PERST to reset PCIe device */
f7bdd12d
BK		 179 pcie_warm_reset = (__force pcie_reset_state_t) 2,
180
f7625980 181 /* Use PCIe Hot Reset to reset device */
f7bdd12d
BK		 182 pcie_hot_reset = (__force pcie_reset_state_t) 3
183};
184
ba698ad4
DM		 185typedef unsigned short __bitwise pci_dev_flags_t;
186enum pci_dev_flags {
187 /* INTX_DISABLE in PCI_COMMAND register disables MSI
188 * generation too.
189 */
6b121592 190 PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG = (__force pci_dev_flags_t) (1 << 0),
979b1791 191 /* Device configuration is irrevocably lost if disabled into D3 */
6b121592 192 PCI_DEV_FLAGS_NO_D3 = (__force pci_dev_flags_t) (1 << 1),
6777829c 193 /* Provide indication device is assigned by a Virtual Machine Manager */
6b121592 194 PCI_DEV_FLAGS_ASSIGNED = (__force pci_dev_flags_t) (1 << 2),
5757a769 195 /* Flag for quirk use to store if quirk-specific ACS is enabled */
6b121592 196 PCI_DEV_FLAGS_ACS_ENABLED_QUIRK = (__force pci_dev_flags_t) (1 << 3),
c8fe16e3
AW		 197 /* Use a PCIe-to-PCI bridge alias even if !pci_is_pcie */
198 PCI_DEV_FLAG_PCIE_BRIDGE_ALIAS = (__force pci_dev_flags_t) (1 << 5),
f331a859
AW		 199 /* Do not use bus resets for device */
200 PCI_DEV_FLAGS_NO_BUS_RESET = (__force pci_dev_flags_t) (1 << 6),
51e53738
AW		 201 /* Do not use PM reset even if device advertises NoSoftRst- */
202 PCI_DEV_FLAGS_NO_PM_RESET = (__force pci_dev_flags_t) (1 << 7),
932c435c
MR		 203 /* Get VPD from function 0 VPD */
204 PCI_DEV_FLAGS_VPD_REF_F0 = (__force pci_dev_flags_t) (1 << 8),
ffff8858
J		 205 /* a non-root bridge where translation occurs, stop alias search here */
206 PCI_DEV_FLAGS_BRIDGE_XLATE_ROOT = (__force pci_dev_flags_t) (1 << 9),
f65fd1aa
SN		 207 /* Do not use FLR even if device advertises PCI_AF_CAP */
208 PCI_DEV_FLAGS_NO_FLR_RESET = (__force pci_dev_flags_t) (1 << 10),
a99b646a 209 /* Don't use Relaxed Ordering for TLPs directed at this device */
c2eac4d3 210 PCI_DEV_FLAGS_NO_RELAXED_ORDERING = (__force pci_dev_flags_t) (1 << 11),
ba698ad4
DM		 211};
212
e1d3a908
SA		 213enum pci_irq_reroute_variant {
214 INTEL_IRQ_REROUTE_VARIANT = 1,
215 MAX_IRQ_REROUTE_VARIANTS = 3
216};
217
6e325a62
MT		 218typedef unsigned short __bitwise pci_bus_flags_t;
219enum pci_bus_flags {
032c3d86
JD		 220 PCI_BUS_FLAGS_NO_MSI = (__force pci_bus_flags_t) 1,
221 PCI_BUS_FLAGS_NO_MMRBC = (__force pci_bus_flags_t) 2,
222 PCI_BUS_FLAGS_NO_AERSID = (__force pci_bus_flags_t) 4,
6e325a62
MT		 223};
224
59da381e
JK		 225/* These values come from the PCI Express Spec */
226enum pcie_link_width {
227 PCIE_LNK_WIDTH_RESRV = 0x00,
228 PCIE_LNK_X1 = 0x01,
229 PCIE_LNK_X2 = 0x02,
230 PCIE_LNK_X4 = 0x04,
231 PCIE_LNK_X8 = 0x08,
232 PCIE_LNK_X12 = 0x0C,
233 PCIE_LNK_X16 = 0x10,
234 PCIE_LNK_X32 = 0x20,
235 PCIE_LNK_WIDTH_UNKNOWN = 0xFF,
236};
237
536c8cb4
MW		 238/* Based on the PCI Hotplug Spec, but some values are made up by us */
239enum pci_bus_speed {
240 PCI_SPEED_33MHz = 0x00,
241 PCI_SPEED_66MHz = 0x01,
242 PCI_SPEED_66MHz_PCIX = 0x02,
243 PCI_SPEED_100MHz_PCIX = 0x03,
244 PCI_SPEED_133MHz_PCIX = 0x04,
245 PCI_SPEED_66MHz_PCIX_ECC = 0x05,
246 PCI_SPEED_100MHz_PCIX_ECC = 0x06,
247 PCI_SPEED_133MHz_PCIX_ECC = 0x07,
248 PCI_SPEED_66MHz_PCIX_266 = 0x09,
249 PCI_SPEED_100MHz_PCIX_266 = 0x0a,
250 PCI_SPEED_133MHz_PCIX_266 = 0x0b,
45b4cdd5
MW		 251 AGP_UNKNOWN = 0x0c,
252 AGP_1X = 0x0d,
253 AGP_2X = 0x0e,
254 AGP_4X = 0x0f,
255 AGP_8X = 0x10,
536c8cb4
MW		 256 PCI_SPEED_66MHz_PCIX_533 = 0x11,
257 PCI_SPEED_100MHz_PCIX_533 = 0x12,
258 PCI_SPEED_133MHz_PCIX_533 = 0x13,
259 PCIE_SPEED_2_5GT = 0x14,
260 PCIE_SPEED_5_0GT = 0x15,
9dfd97fe 261 PCIE_SPEED_8_0GT = 0x16,
ac924662 262 PCIE_SPEED_16_0GT = 0x17,
536c8cb4
MW		 263 PCI_SPEED_UNKNOWN = 0xff,
264};
265
24a4742f 266struct pci_cap_saved_data {
fd0f7f73
AW		 267 u16 cap_nr;
268 bool cap_extended;
24a4742f 269 unsigned int size;
41017f0c
SL		 270 u32 data[0];
271};
272
24a4742f
AW		 273struct pci_cap_saved_state {
274 struct hlist_node next;
275 struct pci_cap_saved_data cap;
276};
277
402723ad 278struct irq_affinity;
7d715a6c 279struct pcie_link_state;
ee69439c 280struct pci_vpd;
d1b054da 281struct pci_sriov;
302b4215 282struct pci_ats;
ee69439c 283
1da177e4
LT		 284/*
285 * The pci_dev structure is used to describe PCI devices.
286 */
287struct pci_dev {
1da177e4
LT		 288 struct list_head bus_list; /* node in per-bus list */
289 struct pci_bus *bus; /* bus this device is on */
290 struct pci_bus *subordinate; /* bus this device bridges to */
291
292 void *sysdata; /* hook for sys-specific extension */
293 struct proc_dir_entry *procent; /* device entry in /proc/bus/pci */
f46753c5 294 struct pci_slot *slot; /* Physical slot this device is in */
1da177e4
LT		 295
296 unsigned int devfn; /* encoded device & function index */
297 unsigned short vendor;
298 unsigned short device;
299 unsigned short subsystem_vendor;
300 unsigned short subsystem_device;
301 unsigned int class; /* 3 bytes: (base,sub,prog-if) */
b8a3a521 302 u8 revision; /* PCI revision, low byte of class word */
1da177e4 303 u8 hdr_type; /* PCI header type (`multi' flag masked out) */
66b80809
KB		 304#ifdef CONFIG_PCIEAER
305 u16 aer_cap; /* AER capability offset */
306#endif
f7625980 307 u8 pcie_cap; /* PCIe capability offset */
e375b561
GS		 308 u8 msi_cap; /* MSI capability offset */
309 u8 msix_cap; /* MSI-X capability offset */
f7625980 310 u8 pcie_mpss:3; /* PCIe Max Payload Size Supported */
1da177e4 311 u8 rom_base_reg; /* which config register controls the ROM */
f7625980
BH		 312 u8 pin; /* which interrupt pin this device uses */
313 u16 pcie_flags_reg; /* cached PCIe Capabilities Register */
338c3149 314 unsigned long *dma_alias_mask;/* mask of enabled devfn aliases */
1da177e4
LT		 315
316 struct pci_driver *driver; /* which driver has allocated this device */
317 u64 dma_mask; /* Mask of the bits of bus address this
318 device implements. Normally this is
319 0xffffffff. You only need to change
320 this if your device has broken DMA
321 or supports 64-bit transfers. */
322
4d57cdfa
FT		 323 struct device_dma_parameters dma_parms;
324
1da177e4
LT		 325 pci_power_t current_state; /* Current operating state. In ACPI-speak,
326 this is D0-D3, D0 being fully functional,
327 and D3 being off. */
703860ed 328 u8 pm_cap; /* PM capability offset */
337001b6
RW		 329 unsigned int pme_support:5; /* Bitmask of states from which PME#
330 can be generated */
379021d5 331 unsigned int pme_poll:1; /* Poll device's PME status bit */
337001b6
RW		 332 unsigned int d1_support:1; /* Low power state D1 is supported */
333 unsigned int d2_support:1; /* Low power state D2 is supported */
448bd857
HY		 334 unsigned int no_d1d2:1; /* D1 and D2 are forbidden */
335 unsigned int no_d3cold:1; /* D3cold is forbidden */
9d26d3a8 336 unsigned int bridge_d3:1; /* Allow D3 for bridge */
448bd857 337 unsigned int d3cold_allowed:1; /* D3cold is allowed by user */
253d2e54
JP		 338 unsigned int mmio_always_on:1; /* disallow turning off io/mem
339 decoding during bar sizing */
e80bb09d 340 unsigned int wakeup_prepared:1;
448bd857
HY		 341 unsigned int runtime_d3cold:1; /* whether go through runtime
342 D3cold, not set for devices
343 powered on/off by the
344 corresponding bridge */
81f98d30 345 unsigned int skip_bus_pm:1; /* Internal: Skip bus-level PM */
b440bde7 346 unsigned int ignore_hotplug:1; /* Ignore hotplug events */
576243b3
KB		 347 unsigned int hotplug_user_indicators:1; /* SlotCtl indicators
348 controlled exclusively by
349 user sysfs */
1ae861e6 350 unsigned int d3_delay; /* D3->D0 transition time in ms */
448bd857 351 unsigned int d3cold_delay; /* D3cold->D0 transition time in ms */
1da177e4 352
7d715a6c 353#ifdef CONFIG_PCIEASPM
f7625980 354 struct pcie_link_state *link_state; /* ASPM link state */
2b78239e
BH		 355 unsigned int ltr_path:1; /* Latency Tolerance Reporting
356 supported from root to here */
7d715a6c
SL		 357#endif
358
392a1ce7 359 pci_channel_state_t error_state; /* current connectivity state */
1da177e4
LT		 360 struct device dev; /* Generic device interface */
361
1da177e4
LT		 362 int cfg_size; /* Size of configuration space */
363
364 /*
365 * Instead of touching interrupt line and base address registers
366 * directly, use the values stored here. They might be different!
367 */
368 unsigned int irq;
369 struct resource resource[DEVICE_COUNT_RESOURCE]; /* I/O and memory regions + expansion ROMs */
370
58d9a38f 371 bool match_driver; /* Skip attaching driver */
1da177e4 372 /* These fields are used by common fixups */
f7625980 373 unsigned int transparent:1; /* Subtractive decode PCI bridge */
1da177e4
LT		 374 unsigned int multifunction:1;/* Part of multi-function device */
375 /* keep track of device state */
8a1bc901 376 unsigned int is_added:1;
1da177e4 377 unsigned int is_busmaster:1; /* device is busmaster */
4602b88d 378 unsigned int no_msi:1; /* device may not use msi */
f144d149 379 unsigned int no_64bit_msi:1; /* device may only use 32-bit MSIs */
fb51ccbf 380 unsigned int block_cfg_access:1; /* config space access is blocked */
bd8481e1 381 unsigned int broken_parity_status:1; /* Device generates false positive parity */
e1d3a908 382 unsigned int irq_reroute_variant:2; /* device needs IRQ rerouting variant */
f7625980 383 unsigned int msi_enabled:1;
99dc804d 384 unsigned int msix_enabled:1;
58c3a727 385 unsigned int ari_enabled:1; /* ARI forwarding */
d544d75a 386 unsigned int ats_enabled:1; /* Address Translation Service */
a4f4fa68
JPB		 387 unsigned int pasid_enabled:1; /* Process Address Space ID */
388 unsigned int pri_enabled:1; /* Page Request Interface */
9ac7849e 389 unsigned int is_managed:1;
260d703a 390 unsigned int needs_freset:1; /* Dev requires fundamental reset */
aa8c6c93 391 unsigned int state_saved:1;
d1b054da 392 unsigned int is_physfn:1;
dd7cc44d 393 unsigned int is_virtfn:1;
711d5779 394 unsigned int reset_fn:1;
28760489 395 unsigned int is_hotplug_bridge:1;
8531e283 396 unsigned int is_thunderbolt:1; /* Thunderbolt controller */
4fcbcb08
MW		 397 /*
398 * Devices marked being untrusted are the ones that can potentially
399 * execute DMA attacks and similar. They are typically connected
400 * through external ports such as Thunderbolt but not limited to
401 * that. When an IOMMU is enabled they should be getting full
402 * mappings to make sure they cannot access arbitrary memory.
403 */
404 unsigned int untrusted:1;
affb72c3
HY		 405 unsigned int __aer_firmware_first_valid:1;
406 unsigned int __aer_firmware_first:1;
99b3c58f 407 unsigned int broken_intx_masking:1; /* INTx masking can't be used */
2b28ae19 408 unsigned int io_window_1k:1; /* Intel P2P bridge 1K I/O windows */
cffe0a2b 409 unsigned int irq_managed:1;
d0751b98 410 unsigned int has_secondary_link:1;
b84106b4 411 unsigned int non_compliant_bars:1; /* broken BARs; ignore them */
0b2c2a71 412 unsigned int is_probed:1; /* device probing in progress */
ba698ad4 413 pci_dev_flags_t dev_flags;
bae94d02 414 atomic_t enable_cnt; /* pci_enable_device has been called */
4602b88d 415
1da177e4 416 u32 saved_config_space[16]; /* config space saved at suspend time */
41017f0c 417 struct hlist_head saved_cap_space;
1da177e4
LT		 418 struct bin_attribute *rom_attr; /* attribute descriptor for sysfs ROM entry */
419 int rom_attr_enabled; /* has display of the rom attribute been enabled? */
420 struct bin_attribute *res_attr[DEVICE_COUNT_RESOURCE]; /* sysfs file for resources */
45aec1ae 421 struct bin_attribute *res_attr_wc[DEVICE_COUNT_RESOURCE]; /* sysfs file for WC mapping of resources */
9bb04a0c
JY		 422
423#ifdef CONFIG_PCIE_PTM
424 unsigned int ptm_root:1;
425 unsigned int ptm_enabled:1;
8b2ec318 426 u8 ptm_granularity;
9bb04a0c 427#endif
ded86d8d 428#ifdef CONFIG_PCI_MSI
1c51b50c 429 const struct attribute_group **msi_irq_groups;
ded86d8d 430#endif
94e61088 431 struct pci_vpd *vpd;
466b3ddf 432#ifdef CONFIG_PCI_ATS
dd7cc44d
YZ		 433 union {
434 struct pci_sriov *sriov; /* SR-IOV capability related */
435 struct pci_dev *physfn; /* the PF this VF is associated with */
436 };
67930995
BH		 437 u16 ats_cap; /* ATS Capability offset */
438 u8 ats_stu; /* ATS Smallest Translation Unit */
d544d75a 439 atomic_t ats_ref_cnt; /* number of VFs with ATS enabled */
4ebeb1ec
CT		 440#endif
441#ifdef CONFIG_PCI_PRI
442 u32 pri_reqs_alloc; /* Number of PRI requests allocated */
443#endif
444#ifdef CONFIG_PCI_PASID
445 u16 pasid_features;
d1b054da 446#endif
dbd3fc33 447 phys_addr_t rom; /* Physical address of ROM if it's not from the BAR */
84c1b80e 448 size_t romlen; /* Length of ROM if it's not from the BAR */
782a985d 449 char *driver_override; /* Driver name to force a match */
89ee9f76
KB		 450
451 unsigned long priv_flags; /* Private flags for the pci driver */
1da177e4
LT		 452};
453
dda56549
Y		 454static inline struct pci_dev *pci_physfn(struct pci_dev *dev)
455{
456#ifdef CONFIG_PCI_IOV
457 if (dev->is_virtfn)
458 dev = dev->physfn;
459#endif
dda56549
Y		 460 return dev;
461}
462
3c6e6ae7 463struct pci_dev *pci_alloc_dev(struct pci_bus *bus);
65891215 464
1da177e4
LT		 465#define to_pci_dev(n) container_of(n, struct pci_dev, dev)
466#define for_each_pci_dev(d) while ((d = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, d)) != NULL)
467
a7369f1f
LV		 468static inline int pci_channel_offline(struct pci_dev *pdev)
469{
470 return (pdev->error_state != pci_channel_io_normal);
471}
472
5a21d70d 473struct pci_host_bridge {
7b543663 474 struct device dev;
5a21d70d 475 struct pci_bus *bus; /* root bus */
37d6a0a6
AB		 476 struct pci_ops *ops;
477 void *sysdata;
478 int busnr;
14d76b68 479 struct list_head windows; /* resource_entry */
3aa8a41e
MM		 480 u8 (*swizzle_irq)(struct pci_dev *, u8 *); /* platform IRQ swizzler */
481 int (*map_irq)(const struct pci_dev *, u8, u8);
4fa2649a
YL		 482 void (*release_fn)(struct pci_host_bridge *);
483 void *release_data;
37d6a0a6 484 struct msi_controller *msi;
e33caa82 485 unsigned int ignore_reset_delay:1; /* for entire hierarchy */
62ce94a7 486 unsigned int no_ext_tags:1; /* no Extended Tags */
7c7a0e94
GP		 487 /* Resource alignment requirements */
488 resource_size_t (*align_resource)(struct pci_dev *dev,
489 const struct resource *res,
490 resource_size_t start,
491 resource_size_t size,
492 resource_size_t align);
59094065 493 unsigned long private[0] ____cacheline_aligned;
5a21d70d 494};
41017f0c 495
7b543663 496#define to_pci_host_bridge(n) container_of(n, struct pci_host_bridge, dev)
7c7a0e94 497
59094065
TR		 498static inline void *pci_host_bridge_priv(struct pci_host_bridge *bridge)
499{
500 return (void *)bridge->private;
501}
502
503static inline struct pci_host_bridge *pci_host_bridge_from_priv(void *priv)
504{
505 return container_of(priv, struct pci_host_bridge, private);
506}
507
a52d1443 508struct pci_host_bridge *pci_alloc_host_bridge(size_t priv);
5c3f18cc
LP		 509struct pci_host_bridge *devm_pci_alloc_host_bridge(struct device *dev,
510 size_t priv);
dff79b91 511void pci_free_host_bridge(struct pci_host_bridge *bridge);
7c7a0e94
GP		 512struct pci_host_bridge *pci_find_host_bridge(struct pci_bus *bus);
513
4fa2649a
YL		 514void pci_set_host_bridge_release(struct pci_host_bridge *bridge,
515 void (*release_fn)(struct pci_host_bridge *),
516 void *release_data);
7b543663 517
6c0cc950
RW		 518int pcibios_root_bridge_prepare(struct pci_host_bridge *bridge);
519
2fe2abf8
BH		 520/*
521 * The first PCI_BRIDGE_RESOURCE_NUM PCI bus resources (those that correspond
522 * to P2P or CardBus bridge windows) go in a table. Additional ones (for
523 * buses below host bridges or subtractive decode bridges) go in the list.
524 * Use pci_bus_for_each_resource() to iterate through all the resources.
525 */
526
527/*
528 * PCI_SUBTRACTIVE_DECODE means the bridge forwards the window implicitly
529 * and there's no way to program the bridge with the details of the window.
530 * This does not apply to ACPI _CRS windows, even with the _DEC subtractive-
531 * decode bit set, because they are explicit and can be programmed with _SRS.
532 */
533#define PCI_SUBTRACTIVE_DECODE 0x1
534
535struct pci_bus_resource {
536 struct list_head list;
537 struct resource *res;
538 unsigned int flags;
539};
4352dfd5
GKH		 540
541#define PCI_REGION_FLAG_MASK 0x0fU /* These bits of resource flags tell us the PCI region flags */
1da177e4
LT		 542
543struct pci_bus {
544 struct list_head node; /* node in list of buses */
545 struct pci_bus *parent; /* parent bus this bridge is on */
546 struct list_head children; /* list of child buses */
547 struct list_head devices; /* list of devices on this bus */
548 struct pci_dev *self; /* bridge device as seen by parent */
67546762
YW		 549 struct list_head slots; /* list of slots on this bus;
550 protected by pci_slot_mutex */
2fe2abf8
BH		 551 struct resource *resource[PCI_BRIDGE_RESOURCE_NUM];
552 struct list_head resources; /* address space routed to this bus */
92f02430 553 struct resource busn_res; /* bus numbers routed to this bus */
1da177e4
LT		 554
555 struct pci_ops *ops; /* configuration access functions */
c2791b80 556 struct msi_controller *msi; /* MSI controller */
1da177e4
LT		 557 void *sysdata; /* hook for sys-specific extension */
558 struct proc_dir_entry *procdir; /* directory entry in /proc/bus/pci */
559
560 unsigned char number; /* bus number */
561 unsigned char primary; /* number of primary bridge */
3749c51a
MW		 562 unsigned char max_bus_speed; /* enum pci_bus_speed */
563 unsigned char cur_bus_speed; /* enum pci_bus_speed */
670ba0c8
CM		 564#ifdef CONFIG_PCI_DOMAINS_GENERIC
565 int domain_nr;
566#endif
1da177e4
LT		 567
568 char name[48];
569
570 unsigned short bridge_ctl; /* manage NO_ISA/FBB/et al behaviors */
f7625980 571 pci_bus_flags_t bus_flags; /* inherited by child buses */
1da177e4 572 struct device *bridge;
fd7d1ced 573 struct device dev;
1da177e4
LT		 574 struct bin_attribute *legacy_io; /* legacy I/O for this bus */
575 struct bin_attribute *legacy_mem; /* legacy mem */
cc74d96f 576 unsigned int is_added:1;
1da177e4
LT		 577};
578
fd7d1ced 579#define to_pci_bus(n) container_of(n, struct pci_bus, dev)
1da177e4 580
79af72d7 581/*
f7625980 582 * Returns true if the PCI bus is root (behind host-PCI bridge),
79af72d7 583 * false otherwise
77a0dfcd
BH		 584 *
585 * Some code assumes that "bus->self == NULL" means that bus is a root bus.
586 * This is incorrect because "virtual" buses added for SR-IOV (via
587 * virtfn_add_bus()) have "bus->self == NULL" but are not root buses.
79af72d7
KK		 588 */
589static inline bool pci_is_root_bus(struct pci_bus *pbus)
590{
591 return !(pbus->parent);
592}
593
1c86438c
YW		 594/**
595 * pci_is_bridge - check if the PCI device is a bridge
596 * @dev: PCI device
597 *
598 * Return true if the PCI device is bridge whether it has subordinate
599 * or not.
600 */
601static inline bool pci_is_bridge(struct pci_dev *dev)
602{
603 return dev->hdr_type == PCI_HEADER_TYPE_BRIDGE ||
604 dev->hdr_type == PCI_HEADER_TYPE_CARDBUS;
605}
606
24a0c654
AS		 607#define for_each_pci_bridge(dev, bus) \
608 list_for_each_entry(dev, &bus->devices, bus_list) \
609 if (!pci_is_bridge(dev)) {} else
610
c6bde215
BH		 611static inline struct pci_dev *pci_upstream_bridge(struct pci_dev *dev)
612{
613 dev = pci_physfn(dev);
614 if (pci_is_root_bus(dev->bus))
615 return NULL;
616
617 return dev->bus->self;
618}
619
6675a601
MK		 620struct device *pci_get_host_bridge_device(struct pci_dev *dev);
621void pci_put_host_bridge_device(struct device *dev);
622
16cf0ebc
RW		 623#ifdef CONFIG_PCI_MSI
624static inline bool pci_dev_msi_enabled(struct pci_dev *pci_dev)
625{
626 return pci_dev->msi_enabled || pci_dev->msix_enabled;
627}
628#else
629static inline bool pci_dev_msi_enabled(struct pci_dev *pci_dev) { return false; }
630#endif
631
1da177e4
LT		 632/*
633 * Error values that may be returned by PCI functions.
634 */
635#define PCIBIOS_SUCCESSFUL 0x00
636#define PCIBIOS_FUNC_NOT_SUPPORTED 0x81
637#define PCIBIOS_BAD_VENDOR_ID 0x83
638#define PCIBIOS_DEVICE_NOT_FOUND 0x86
639#define PCIBIOS_BAD_REGISTER_NUMBER 0x87
640#define PCIBIOS_SET_FAILED 0x88
641#define PCIBIOS_BUFFER_TOO_SMALL 0x89
642
a6961651 643/*
f7625980 644 * Translate above to generic errno for passing back through non-PCI code.
a6961651
AW		 645 */
646static inline int pcibios_err_to_errno(int err)
647{
648 if (err <= PCIBIOS_SUCCESSFUL)
649 return err; /* Assume already errno */
650
651 switch (err) {
652 case PCIBIOS_FUNC_NOT_SUPPORTED:
653 return -ENOENT;
654 case PCIBIOS_BAD_VENDOR_ID:
d97ffe23 655 return -ENOTTY;
a6961651
AW		 656 case PCIBIOS_DEVICE_NOT_FOUND:
657 return -ENODEV;
658 case PCIBIOS_BAD_REGISTER_NUMBER:
659 return -EFAULT;
660 case PCIBIOS_SET_FAILED:
661 return -EIO;
662 case PCIBIOS_BUFFER_TOO_SMALL:
663 return -ENOSPC;
664 }
665
d97ffe23 666 return -ERANGE;
a6961651
AW		 667}
668
1da177e4
LT		 669/* Low-level architecture-dependent routines */
670
671struct pci_ops {
057bd2e0
TR		 672 int (*add_bus)(struct pci_bus *bus);
673 void (*remove_bus)(struct pci_bus *bus);
1f94a94f 674 void __iomem *(*map_bus)(struct pci_bus *bus, unsigned int devfn, int where);
1da177e4
LT		 675 int (*read)(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 *val);
676 int (*write)(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 val);
677};
678
b6ce068a
MW		 679/*
680 * ACPI needs to be able to access PCI config space before we've done a
681 * PCI bus scan and created pci_bus structures.
682 */
f39d5b72
BH		 683int raw_pci_read(unsigned int domain, unsigned int bus, unsigned int devfn,
684 int reg, int len, u32 *val);
685int raw_pci_write(unsigned int domain, unsigned int bus, unsigned int devfn,
686 int reg, int len, u32 val);
1da177e4 687
3a9ad0b4
YL		 688#ifdef CONFIG_PCI_BUS_ADDR_T_64BIT
689typedef u64 pci_bus_addr_t;
690#else
691typedef u32 pci_bus_addr_t;
692#endif
693
1da177e4 694struct pci_bus_region {
3a9ad0b4
YL		 695 pci_bus_addr_t start;
696 pci_bus_addr_t end;
1da177e4
LT		 697};
698
699struct pci_dynids {
700 spinlock_t lock; /* protects list, index */
701 struct list_head list; /* for IDs added at runtime */
1da177e4
LT		 702};
703
f7625980
BH		 704
705/*
706 * PCI Error Recovery System (PCI-ERS). If a PCI device driver provides
707 * a set of callbacks in struct pci_error_handlers, that device driver
708 * will be notified of PCI bus errors, and will be driven to recovery
709 * when an error occurs.
392a1ce7
LV		 710 */
711
712typedef unsigned int __bitwise pci_ers_result_t;
713
714enum pci_ers_result {
715 /* no result/none/not supported in device driver */
716 PCI_ERS_RESULT_NONE = (__force pci_ers_result_t) 1,
717
718 /* Device driver can recover without slot reset */
719 PCI_ERS_RESULT_CAN_RECOVER = (__force pci_ers_result_t) 2,
720
721 /* Device driver wants slot to be reset. */
722 PCI_ERS_RESULT_NEED_RESET = (__force pci_ers_result_t) 3,
723
724 /* Device has completely failed, is unrecoverable */
725 PCI_ERS_RESULT_DISCONNECT = (__force pci_ers_result_t) 4,
726
727 /* Device driver is fully recovered and operational */
728 PCI_ERS_RESULT_RECOVERED = (__force pci_ers_result_t) 5,
918b4053
VMP		 729
730 /* No AER capabilities registered for the driver */
731 PCI_ERS_RESULT_NO_AER_DRIVER = (__force pci_ers_result_t) 6,
392a1ce7
LV		 732};
733
734/* PCI bus error event callbacks */
05cca6e5 735struct pci_error_handlers {
392a1ce7
LV		 736 /* PCI bus error detected on this device */
737 pci_ers_result_t (*error_detected)(struct pci_dev *dev,
05cca6e5 738 enum pci_channel_state error);
392a1ce7
LV		 739
740 /* MMIO has been re-enabled, but not DMA */
741 pci_ers_result_t (*mmio_enabled)(struct pci_dev *dev);
742
392a1ce7
LV		 743 /* PCI slot has been reset */
744 pci_ers_result_t (*slot_reset)(struct pci_dev *dev);
745
3ebe7f9f 746 /* PCI function reset prepare or completed */
775755ed
CH		 747 void (*reset_prepare)(struct pci_dev *dev);
748 void (*reset_done)(struct pci_dev *dev);
3ebe7f9f 749
392a1ce7
LV		 750 /* Device driver may resume normal operations */
751 void (*resume)(struct pci_dev *dev);
752};
753
392a1ce7 754
1da177e4
LT		 755struct module;
756struct pci_driver {
757 struct list_head node;
42b21932 758 const char *name;
1da177e4
LT		 759 const struct pci_device_id *id_table; /* must be non-NULL for probe to be called */
760 int (*probe) (struct pci_dev *dev, const struct pci_device_id *id); /* New device inserted */
761 void (*remove) (struct pci_dev *dev); /* Device removed (NULL if not a hot-plug capable driver) */
762 int (*suspend) (struct pci_dev *dev, pm_message_t state); /* Device suspended */
cbd69dbb
LT		 763 int (*suspend_late) (struct pci_dev *dev, pm_message_t state);
764 int (*resume_early) (struct pci_dev *dev);
1da177e4 765 int (*resume) (struct pci_dev *dev); /* Device woken up */
c8958177 766 void (*shutdown) (struct pci_dev *dev);
1789382a 767 int (*sriov_configure) (struct pci_dev *dev, int num_vfs); /* PF pdev */
49453028 768 const struct pci_error_handlers *err_handler;
92d50fc1 769 const struct attribute_group **groups;
1da177e4
LT		 770 struct device_driver driver;
771 struct pci_dynids dynids;
772};
773
05cca6e5 774#define to_pci_driver(drv) container_of(drv, struct pci_driver, driver)
1da177e4
LT		 775
776/**
777 * PCI_DEVICE - macro used to describe a specific pci device
778 * @vend: the 16 bit PCI Vendor ID
779 * @dev: the 16 bit PCI Device ID
780 *
781 * This macro is used to create a struct pci_device_id that matches a
782 * specific device. The subvendor and subdevice fields will be set to
783 * PCI_ANY_ID.
784 */
785#define PCI_DEVICE(vend,dev) \
786 .vendor = (vend), .device = (dev), \
787 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID
788
3d567e0e
NNS		 789/**
790 * PCI_DEVICE_SUB - macro used to describe a specific pci device with subsystem
791 * @vend: the 16 bit PCI Vendor ID
792 * @dev: the 16 bit PCI Device ID
793 * @subvend: the 16 bit PCI Subvendor ID
794 * @subdev: the 16 bit PCI Subdevice ID
795 *
796 * This macro is used to create a struct pci_device_id that matches a
797 * specific device with subsystem information.
798 */
799#define PCI_DEVICE_SUB(vend, dev, subvend, subdev) \
800 .vendor = (vend), .device = (dev), \
801 .subvendor = (subvend), .subdevice = (subdev)
802
1da177e4
LT		 803/**
804 * PCI_DEVICE_CLASS - macro used to describe a specific pci device class
805 * @dev_class: the class, subclass, prog-if triple for this device
806 * @dev_class_mask: the class mask for this device
807 *
808 * This macro is used to create a struct pci_device_id that matches a
4352dfd5 809 * specific PCI class. The vendor, device, subvendor, and subdevice
1da177e4
LT		 810 * fields will be set to PCI_ANY_ID.
811 */
812#define PCI_DEVICE_CLASS(dev_class,dev_class_mask) \
813 .class = (dev_class), .class_mask = (dev_class_mask), \
814 .vendor = PCI_ANY_ID, .device = PCI_ANY_ID, \
815 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID
816
1597cacb
AC		 817/**
818 * PCI_VDEVICE - macro used to describe a specific pci device in short form
c1309040
MR		 819 * @vend: the vendor name
820 * @dev: the 16 bit PCI Device ID
1597cacb
AC		 821 *
822 * This macro is used to create a struct pci_device_id that matches a
823 * specific PCI device. The subvendor, and subdevice fields will be set
824 * to PCI_ANY_ID. The macro allows the next field to follow as the device
825 * private data.
826 */
827
c1309040
MR		 828#define PCI_VDEVICE(vend, dev) \
829 .vendor = PCI_VENDOR_ID_##vend, .device = (dev), \
830 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID, 0, 0
1597cacb 831
5bbe029f
BH		 832enum {
833 PCI_REASSIGN_ALL_RSRC = 0x00000001, /* ignore firmware setup */
834 PCI_REASSIGN_ALL_BUS = 0x00000002, /* reassign all bus numbers */
835 PCI_PROBE_ONLY = 0x00000004, /* use existing setup */
836 PCI_CAN_SKIP_ISA_ALIGN = 0x00000008, /* don't do ISA alignment */
837 PCI_ENABLE_PROC_DOMAINS = 0x00000010, /* enable domains in /proc */
838 PCI_COMPAT_DOMAIN_0 = 0x00000020, /* ... except domain 0 */
839 PCI_SCAN_ALL_PCIE_DEVS = 0x00000040, /* scan all, not just dev 0 */
840};
841
1da177e4
LT		 842/* these external functions are only available when PCI support is enabled */
843#ifdef CONFIG_PCI
844
5bbe029f
BH		 845extern unsigned int pci_flags;
846
847static inline void pci_set_flags(int flags) { pci_flags = flags; }
848static inline void pci_add_flags(int flags) { pci_flags |= flags; }
849static inline void pci_clear_flags(int flags) { pci_flags &= ~flags; }
850static inline int pci_has_flag(int flag) { return pci_flags & flag; }
851
a58674ff 852void pcie_bus_configure_settings(struct pci_bus *bus);
b03e7495
JM		 853
854enum pcie_bus_config_types {
27d868b5
KB		 855 PCIE_BUS_TUNE_OFF, /* don't touch MPS at all */
856 PCIE_BUS_DEFAULT, /* ensure MPS matches upstream bridge */
857 PCIE_BUS_SAFE, /* use largest MPS boot-time devices support */
858 PCIE_BUS_PERFORMANCE, /* use MPS and MRRS for best performance */
859 PCIE_BUS_PEER2PEER, /* set MPS = 128 for all devices */
b03e7495
JM		 860};
861
862extern enum pcie_bus_config_types pcie_bus_config;
863
1da177e4
LT		 864extern struct bus_type pci_bus_type;
865
f7625980
BH		 866/* Do NOT directly access these two variables, unless you are arch-specific PCI
867 * code, or PCI core code. */
1da177e4 868extern struct list_head pci_root_buses; /* list of all known PCI buses */
f7625980 869/* Some device drivers need know if PCI is initiated */
f39d5b72 870int no_pci_devices(void);
1da177e4 871
3c449ed0 872void pcibios_resource_survey_bus(struct pci_bus *bus);
7b77061f 873void pcibios_bus_add_device(struct pci_dev *pdev);
10a95747
JL		 874void pcibios_add_bus(struct pci_bus *bus);
875void pcibios_remove_bus(struct pci_bus *bus);
1da177e4 876void pcibios_fixup_bus(struct pci_bus *);
4a7fb636 877int __must_check pcibios_enable_device(struct pci_dev *, int mask);
f7625980 878/* Architecture-specific versions may override this (weak) */
05cca6e5 879char *pcibios_setup(char *str);
1da177e4
LT		 880
881/* Used only when drivers/pci/setup.c is used */
3b7a17fc 882resource_size_t pcibios_align_resource(void *, const struct resource *,
b26b2d49 883 resource_size_t,
e31dd6e4 884 resource_size_t);
1da177e4 885
2d1c8618
BH		 886/* Weak but can be overriden by arch */
887void pci_fixup_cardbus(struct pci_bus *);
888
1da177e4
LT		 889/* Generic PCI functions used internally */
890
fc279850 891void pcibios_resource_to_bus(struct pci_bus *bus, struct pci_bus_region *region,
36a66cd6 892 struct resource *res);
fc279850 893void pcibios_bus_to_resource(struct pci_bus *bus, struct resource *res,
36a66cd6 894 struct pci_bus_region *region);
d1fd4fb6 895void pcibios_scan_specific_bus(int busn);
f39d5b72 896struct pci_bus *pci_find_bus(int domain, int busnr);
c48f1670 897void pci_bus_add_devices(const struct pci_bus *bus);
de4b2f76 898struct pci_bus *pci_scan_bus(int bus, struct pci_ops *ops, void *sysdata);
166c6370
BH		 899struct pci_bus *pci_create_root_bus(struct device *parent, int bus,
900 struct pci_ops *ops, void *sysdata,
901 struct list_head *resources);
98a35831
YL		 902int pci_bus_insert_busn_res(struct pci_bus *b, int bus, int busmax);
903int pci_bus_update_busn_res_end(struct pci_bus *b, int busmax);
904void pci_bus_release_busn_res(struct pci_bus *b);
15856ad5 905struct pci_bus *pci_scan_root_bus(struct device *parent, int bus,
a2ebb827
BH		 906 struct pci_ops *ops, void *sysdata,
907 struct list_head *resources);
1228c4b6 908int pci_scan_root_bus_bridge(struct pci_host_bridge *bridge);
05cca6e5
GKH		 909struct pci_bus *pci_add_new_bus(struct pci_bus *parent, struct pci_dev *dev,
910 int busnr);
3749c51a 911void pcie_update_link_speed(struct pci_bus *bus, u16 link_status);
f46753c5 912struct pci_slot *pci_create_slot(struct pci_bus *parent, int slot_nr,
828f3768
AC		 913 const char *name,
914 struct hotplug_slot *hotplug);
f46753c5 915void pci_destroy_slot(struct pci_slot *slot);
017ffe64
YW		 916#ifdef CONFIG_SYSFS
917void pci_dev_assign_slot(struct pci_dev *dev);
918#else
919static inline void pci_dev_assign_slot(struct pci_dev *dev) { }
920#endif
1da177e4 921int pci_scan_slot(struct pci_bus *bus, int devfn);
05cca6e5 922struct pci_dev *pci_scan_single_device(struct pci_bus *bus, int devfn);
cdb9b9f7 923void pci_device_add(struct pci_dev *dev, struct pci_bus *bus);
1da177e4 924unsigned int pci_scan_child_bus(struct pci_bus *bus);
c893d133 925void pci_bus_add_device(struct pci_dev *dev);
1da177e4 926void pci_read_bridge_bases(struct pci_bus *child);
05cca6e5
GKH		 927struct resource *pci_find_parent_resource(const struct pci_dev *dev,
928 struct resource *res);
c56d4450 929struct pci_dev *pci_find_pcie_root_port(struct pci_dev *dev);
3df425f3 930u8 pci_swizzle_interrupt_pin(const struct pci_dev *dev, u8 pin);
1da177e4 931int pci_get_interrupt_pin(struct pci_dev *dev, struct pci_dev **bridge);
68feac87 932u8 pci_common_swizzle(struct pci_dev *dev, u8 *pinp);
f39d5b72
BH		 933struct pci_dev *pci_dev_get(struct pci_dev *dev);
934void pci_dev_put(struct pci_dev *dev);
935void pci_remove_bus(struct pci_bus *b);
936void pci_stop_and_remove_bus_device(struct pci_dev *dev);
9d16947b 937void pci_stop_and_remove_bus_device_locked(struct pci_dev *dev);
cdfcc572
YL		 938void pci_stop_root_bus(struct pci_bus *bus);
939void pci_remove_root_bus(struct pci_bus *bus);
b3743fa4 940void pci_setup_cardbus(struct pci_bus *bus);
d366d28c 941void pcibios_setup_bridge(struct pci_bus *bus, unsigned long type);
f39d5b72 942void pci_sort_breadthfirst(void);
fb8a0d9d
WM		 943#define dev_is_pci(d) ((d)->bus == &pci_bus_type)
944#define dev_is_pf(d) ((dev_is_pci(d) ? to_pci_dev(d)->is_physfn : false))
1da177e4
LT		 945
946/* Generic PCI functions exported to card drivers */
947
388c8c16
JB		 948enum pci_lost_interrupt_reason {
949 PCI_LOST_IRQ_NO_INFORMATION = 0,
950 PCI_LOST_IRQ_DISABLE_MSI,
951 PCI_LOST_IRQ_DISABLE_MSIX,
952 PCI_LOST_IRQ_DISABLE_ACPI,
953};
954enum pci_lost_interrupt_reason pci_lost_interrupt(struct pci_dev *dev);
05cca6e5
GKH		 955int pci_find_capability(struct pci_dev *dev, int cap);
956int pci_find_next_capability(struct pci_dev *dev, u8 pos, int cap);
957int pci_find_ext_capability(struct pci_dev *dev, int cap);
44a9a36f 958int pci_find_next_ext_capability(struct pci_dev *dev, int pos, int cap);
05cca6e5
GKH		 959int pci_find_ht_capability(struct pci_dev *dev, int ht_cap);
960int pci_find_next_ht_capability(struct pci_dev *dev, int pos, int ht_cap);
29f3eb64 961struct pci_bus *pci_find_next_bus(const struct pci_bus *from);
1da177e4 962
d42552c3
AM		 963struct pci_dev *pci_get_device(unsigned int vendor, unsigned int device,
964 struct pci_dev *from);
05cca6e5 965struct pci_dev *pci_get_subsys(unsigned int vendor, unsigned int device,
1da177e4 966 unsigned int ss_vendor, unsigned int ss_device,
b08508c4 967 struct pci_dev *from);
05cca6e5 968struct pci_dev *pci_get_slot(struct pci_bus *bus, unsigned int devfn);
3c299dc2
AP		 969struct pci_dev *pci_get_domain_bus_and_slot(int domain, unsigned int bus,
970 unsigned int devfn);
971static inline struct pci_dev *pci_get_bus_and_slot(unsigned int bus,
972 unsigned int devfn)
973{
974 return pci_get_domain_bus_and_slot(0, bus, devfn);
975}
05cca6e5 976struct pci_dev *pci_get_class(unsigned int class, struct pci_dev *from);
1da177e4
LT		 977int pci_dev_present(const struct pci_device_id *ids);
978
05cca6e5
GKH		 979int pci_bus_read_config_byte(struct pci_bus *bus, unsigned int devfn,
980 int where, u8 *val);
981int pci_bus_read_config_word(struct pci_bus *bus, unsigned int devfn,
982 int where, u16 *val);
983int pci_bus_read_config_dword(struct pci_bus *bus, unsigned int devfn,
984 int where, u32 *val);
985int pci_bus_write_config_byte(struct pci_bus *bus, unsigned int devfn,
986 int where, u8 val);
987int pci_bus_write_config_word(struct pci_bus *bus, unsigned int devfn,
988 int where, u16 val);
989int pci_bus_write_config_dword(struct pci_bus *bus, unsigned int devfn,
990 int where, u32 val);
1f94a94f
RH		 991
992int pci_generic_config_read(struct pci_bus *bus, unsigned int devfn,
993 int where, int size, u32 *val);
994int pci_generic_config_write(struct pci_bus *bus, unsigned int devfn,
995 int where, int size, u32 val);
996int pci_generic_config_read32(struct pci_bus *bus, unsigned int devfn,
997 int where, int size, u32 *val);
998int pci_generic_config_write32(struct pci_bus *bus, unsigned int devfn,
999 int where, int size, u32 val);
1000
a72b46c3 1001struct pci_ops *pci_bus_set_ops(struct pci_bus *bus, struct pci_ops *ops);
1da177e4 1002
d3881e50
KB		 1003int pci_read_config_byte(const struct pci_dev *dev, int where, u8 *val);
1004int pci_read_config_word(const struct pci_dev *dev, int where, u16 *val);
1005int pci_read_config_dword(const struct pci_dev *dev, int where, u32 *val);
1006int pci_write_config_byte(const struct pci_dev *dev, int where, u8 val);
1007int pci_write_config_word(const struct pci_dev *dev, int where, u16 val);
1008int pci_write_config_dword(const struct pci_dev *dev, int where, u32 val);
1da177e4 1009
8c0d3a02
JL		 1010int pcie_capability_read_word(struct pci_dev *dev, int pos, u16 *val);
1011int pcie_capability_read_dword(struct pci_dev *dev, int pos, u32 *val);
1012int pcie_capability_write_word(struct pci_dev *dev, int pos, u16 val);
1013int pcie_capability_write_dword(struct pci_dev *dev, int pos, u32 val);
1014int pcie_capability_clear_and_set_word(struct pci_dev *dev, int pos,
1015 u16 clear, u16 set);
1016int pcie_capability_clear_and_set_dword(struct pci_dev *dev, int pos,
1017 u32 clear, u32 set);
1018
1019static inline int pcie_capability_set_word(struct pci_dev *dev, int pos,
1020 u16 set)
1021{
1022 return pcie_capability_clear_and_set_word(dev, pos, 0, set);
1023}
1024
1025static inline int pcie_capability_set_dword(struct pci_dev *dev, int pos,
1026 u32 set)
1027{
1028 return pcie_capability_clear_and_set_dword(dev, pos, 0, set);
1029}
1030
1031static inline int pcie_capability_clear_word(struct pci_dev *dev, int pos,
1032 u16 clear)
1033{
1034 return pcie_capability_clear_and_set_word(dev, pos, clear, 0);
1035}
1036
1037static inline int pcie_capability_clear_dword(struct pci_dev *dev, int pos,
1038 u32 clear)
1039{
1040 return pcie_capability_clear_and_set_dword(dev, pos, clear, 0);
1041}
1042
c63587d7
AW		 1043/* user-space driven config access */
1044int pci_user_read_config_byte(struct pci_dev *dev, int where, u8 *val);
1045int pci_user_read_config_word(struct pci_dev *dev, int where, u16 *val);
1046int pci_user_read_config_dword(struct pci_dev *dev, int where, u32 *val);
1047int pci_user_write_config_byte(struct pci_dev *dev, int where, u8 val);
1048int pci_user_write_config_word(struct pci_dev *dev, int where, u16 val);
1049int pci_user_write_config_dword(struct pci_dev *dev, int where, u32 val);
1050
4a7fb636 1051int __must_check pci_enable_device(struct pci_dev *dev);
b718989d
BH		 1052int __must_check pci_enable_device_io(struct pci_dev *dev);
1053int __must_check pci_enable_device_mem(struct pci_dev *dev);
0b62e13b 1054int __must_check pci_reenable_device(struct pci_dev *);
9ac7849e
TH		 1055int __must_check pcim_enable_device(struct pci_dev *pdev);
1056void pcim_pin_device(struct pci_dev *pdev);
1057
99b3c58f
PG		 1058static inline bool pci_intx_mask_supported(struct pci_dev *pdev)
1059{
1060 /*
1061 * INTx masking is supported if PCI_COMMAND_INTX_DISABLE is
1062 * writable and no quirk has marked the feature broken.
1063 */
1064 return !pdev->broken_intx_masking;
1065}
1066
296ccb08
YS		 1067static inline int pci_is_enabled(struct pci_dev *pdev)
1068{
1069 return (atomic_read(&pdev->enable_cnt) > 0);
1070}
1071
9ac7849e
TH		 1072static inline int pci_is_managed(struct pci_dev *pdev)
1073{
1074 return pdev->is_managed;
1075}
1076
1da177e4 1077void pci_disable_device(struct pci_dev *dev);
96c55900
MS		 1078
1079extern unsigned int pcibios_max_latency;
1da177e4 1080void pci_set_master(struct pci_dev *dev);
6a479079 1081void pci_clear_master(struct pci_dev *dev);
96c55900 1082
f7bdd12d 1083int pci_set_pcie_reset_state(struct pci_dev *dev, enum pcie_reset_state state);
15ea76d4 1084int pci_set_cacheline_size(struct pci_dev *dev);
1da177e4 1085#define HAVE_PCI_SET_MWI
4a7fb636 1086int __must_check pci_set_mwi(struct pci_dev *dev);
70aa92f2 1087int __must_check pcim_set_mwi(struct pci_dev *dev);
694625c0 1088int pci_try_set_mwi(struct pci_dev *dev);
1da177e4 1089void pci_clear_mwi(struct pci_dev *dev);
a04ce0ff 1090void pci_intx(struct pci_dev *dev, int enable);
a2e27787
JK		 1091bool pci_check_and_mask_intx(struct pci_dev *dev);
1092bool pci_check_and_unmask_intx(struct pci_dev *dev);
157e876f 1093int pci_wait_for_pending(struct pci_dev *dev, int pos, u16 mask);
3775a209 1094int pci_wait_for_pending_transaction(struct pci_dev *dev);
d556ad4b
PO		 1095int pcix_get_max_mmrbc(struct pci_dev *dev);
1096int pcix_get_mmrbc(struct pci_dev *dev);
1097int pcix_set_mmrbc(struct pci_dev *dev, int mmrbc);
2637e5b5 1098int pcie_get_readrq(struct pci_dev *dev);
d556ad4b 1099int pcie_set_readrq(struct pci_dev *dev, int rq);
b03e7495
JM		 1100int pcie_get_mps(struct pci_dev *dev);
1101int pcie_set_mps(struct pci_dev *dev, int mps);
81377c8d
JK		 1102int pcie_get_minimum_link(struct pci_dev *dev, enum pci_bus_speed *speed,
1103 enum pcie_link_width *width);
a60a2b73 1104void pcie_flr(struct pci_dev *dev);
a96d627a 1105int __pci_reset_function_locked(struct pci_dev *dev);
8dd7f803 1106int pci_reset_function(struct pci_dev *dev);
a477b9cd 1107int pci_reset_function_locked(struct pci_dev *dev);
61cf16d8 1108int pci_try_reset_function(struct pci_dev *dev);
9a3d2b9b 1109int pci_probe_reset_slot(struct pci_slot *slot);
090a3c53 1110int pci_reset_slot(struct pci_slot *slot);
61cf16d8 1111int pci_try_reset_slot(struct pci_slot *slot);
9a3d2b9b 1112int pci_probe_reset_bus(struct pci_bus *bus);
090a3c53 1113int pci_reset_bus(struct pci_bus *bus);
61cf16d8 1114int pci_try_reset_bus(struct pci_bus *bus);
9e33002f
GS		 1115void pci_reset_secondary_bus(struct pci_dev *dev);
1116void pcibios_reset_secondary_bus(struct pci_dev *dev);
64e8674f 1117void pci_reset_bridge_secondary_bus(struct pci_dev *dev);
14add80b 1118void pci_update_resource(struct pci_dev *dev, int resno);
4a7fb636 1119int __must_check pci_assign_resource(struct pci_dev *dev, int i);
2bbc6942 1120int __must_check pci_reassign_resource(struct pci_dev *dev, int i, resource_size_t add_size, resource_size_t align);
8bb705e3
CK		 1121void pci_release_resource(struct pci_dev *dev, int resno);
1122int __must_check pci_resize_resource(struct pci_dev *dev, int i, int size);
c87deff7 1123int pci_select_bars(struct pci_dev *dev, unsigned long flags);
8496e85c 1124bool pci_device_is_present(struct pci_dev *pdev);
08249651 1125void pci_ignore_hotplug(struct pci_dev *dev);
1da177e4 1126
704e8953
CH		 1127int __printf(6, 7) pci_request_irq(struct pci_dev *dev, unsigned int nr,
1128 irq_handler_t handler, irq_handler_t thread_fn, void *dev_id,
1129 const char *fmt, ...);
1130void pci_free_irq(struct pci_dev *dev, unsigned int nr, void *dev_id);
1131
1da177e4 1132/* ROM control related routines */
e416de5e
AC		 1133int pci_enable_rom(struct pci_dev *pdev);
1134void pci_disable_rom(struct pci_dev *pdev);
144a50ea 1135void __iomem __must_check *pci_map_rom(struct pci_dev *pdev, size_t *size);
1da177e4 1136void pci_unmap_rom(struct pci_dev *pdev, void __iomem *rom);
97c44836 1137size_t pci_get_rom_size(struct pci_dev *pdev, void __iomem *rom, size_t size);
fffe01f7 1138void __iomem __must_check *pci_platform_rom(struct pci_dev *pdev, size_t *size);
1da177e4
LT		 1139
1140/* Power management related routines */
1141int pci_save_state(struct pci_dev *dev);
1d3c16a8 1142void pci_restore_state(struct pci_dev *dev);
ffbdd3f7 1143struct pci_saved_state *pci_store_saved_state(struct pci_dev *dev);
98d9b271
KRW		 1144int pci_load_saved_state(struct pci_dev *dev,
1145 struct pci_saved_state *state);
ffbdd3f7
AW		 1146int pci_load_and_free_saved_state(struct pci_dev *dev,
1147 struct pci_saved_state **state);
fd0f7f73
AW		 1148struct pci_cap_saved_state *pci_find_saved_cap(struct pci_dev *dev, char cap);
1149struct pci_cap_saved_state *pci_find_saved_ext_cap(struct pci_dev *dev,
1150 u16 cap);
1151int pci_add_cap_save_buffer(struct pci_dev *dev, char cap, unsigned int size);
1152int pci_add_ext_cap_save_buffer(struct pci_dev *dev,
1153 u16 cap, unsigned int size);
0e5dd46b 1154int __pci_complete_power_transition(struct pci_dev *dev, pci_power_t state);
9c8550ee
LT		 1155int pci_set_power_state(struct pci_dev *dev, pci_power_t state);
1156pci_power_t pci_choose_state(struct pci_dev *dev, pm_message_t state);
e5899e1b 1157bool pci_pme_capable(struct pci_dev *dev, pci_power_t state);
5a6c9b60 1158void pci_pme_active(struct pci_dev *dev, bool enable);
0847684c 1159int pci_enable_wake(struct pci_dev *dev, pci_power_t state, bool enable);
0235c4fc 1160int pci_wake_from_d3(struct pci_dev *dev, bool enable);
404cc2d8
RW		 1161int pci_prepare_to_sleep(struct pci_dev *dev);
1162int pci_back_from_sleep(struct pci_dev *dev);
b67ea761 1163bool pci_dev_run_wake(struct pci_dev *dev);
bf4d2908 1164bool pci_check_pme_status(struct pci_dev *dev);
bf4d2908 1165void pci_pme_wakeup_bus(struct pci_bus *bus);
9d26d3a8
MW		 1166void pci_d3cold_enable(struct pci_dev *dev);
1167void pci_d3cold_disable(struct pci_dev *dev);
a99b646a 1168bool pcie_relaxed_ordering_enabled(struct pci_dev *dev);
1da177e4 1169
425c1b22
AW		 1170/* PCI Virtual Channel */
1171int pci_save_vc_state(struct pci_dev *dev);
1172void pci_restore_vc_state(struct pci_dev *dev);
1173void pci_allocate_vc_save_buffers(struct pci_dev *dev);
51c2e0a7 1174
bb209c82
BH		 1175/* For use by arch with custom probe code */
1176void set_pcie_port_type(struct pci_dev *pdev);
1177void set_pcie_hotplug_bridge(struct pci_dev *pdev);
1178
ce5ccdef 1179/* Functions for PCI Hotplug drivers to use */
05cca6e5 1180int pci_bus_find_capability(struct pci_bus *bus, unsigned int devfn, int cap);
2f320521 1181unsigned int pci_rescan_bus_bridge_resize(struct pci_dev *bridge);
3ed4fd96 1182unsigned int pci_rescan_bus(struct pci_bus *bus);
9d16947b
RW		 1183void pci_lock_rescan_remove(void);
1184void pci_unlock_rescan_remove(void);
ce5ccdef 1185
287d19ce
SH		 1186/* Vital product data routines */
1187ssize_t pci_read_vpd(struct pci_dev *dev, loff_t pos, size_t count, void *buf);
1188ssize_t pci_write_vpd(struct pci_dev *dev, loff_t pos, size_t count, const void *buf);
cb92148b 1189int pci_set_vpd_size(struct pci_dev *dev, size_t len);
287d19ce 1190
1da177e4 1191/* Helper functions for low-level code (drivers/pci/setup-[bus,res].c) */
925845bd 1192resource_size_t pcibios_retrieve_fw_addr(struct pci_dev *dev, int idx);
ea741551 1193void pci_bus_assign_resources(const struct pci_bus *bus);
765bf9b7 1194void pci_bus_claim_resources(struct pci_bus *bus);
1da177e4
LT		 1195void pci_bus_size_bridges(struct pci_bus *bus);
1196int pci_claim_resource(struct pci_dev *, int);
8505e729 1197int pci_claim_bridge_resource(struct pci_dev *bridge, int i);
1da177e4 1198void pci_assign_unassigned_resources(void);
6841ec68 1199void pci_assign_unassigned_bridge_resources(struct pci_dev *bridge);
17787940 1200void pci_assign_unassigned_bus_resources(struct pci_bus *bus);
39772038 1201void pci_assign_unassigned_root_bus_resources(struct pci_bus *bus);
8bb705e3 1202int pci_reassign_bridge_resources(struct pci_dev *bridge, unsigned long type);
1da177e4 1203void pdev_enable_device(struct pci_dev *);
842de40d 1204int pci_enable_resources(struct pci_dev *, int mask);
47a650f2 1205void pci_assign_irq(struct pci_dev *dev);
afd29f90 1206struct resource *pci_find_resource(struct pci_dev *dev, struct resource *res);
1da177e4 1207#define HAVE_PCI_REQ_REGIONS 2
4a7fb636 1208int __must_check pci_request_regions(struct pci_dev *, const char *);
e8de1481 1209int __must_check pci_request_regions_exclusive(struct pci_dev *, const char *);
1da177e4 1210void pci_release_regions(struct pci_dev *);
4a7fb636 1211int __must_check pci_request_region(struct pci_dev *, int, const char *);
e8de1481 1212int __must_check pci_request_region_exclusive(struct pci_dev *, int, const char *);
1da177e4 1213void pci_release_region(struct pci_dev *, int);
c87deff7 1214int pci_request_selected_regions(struct pci_dev *, int, const char *);
e8de1481 1215int pci_request_selected_regions_exclusive(struct pci_dev *, int, const char *);
c87deff7 1216void pci_release_selected_regions(struct pci_dev *, int);
1da177e4
LT		 1217
1218/* drivers/pci/bus.c */
fe830ef6
JL		 1219struct pci_bus *pci_bus_get(struct pci_bus *bus);
1220void pci_bus_put(struct pci_bus *bus);
45ca9e97 1221void pci_add_resource(struct list_head *resources, struct resource *res);
0efd5aab
BH		 1222void pci_add_resource_offset(struct list_head *resources, struct resource *res,
1223 resource_size_t offset);
45ca9e97 1224void pci_free_resource_list(struct list_head *resources);
950334bc
BH		 1225void pci_bus_add_resource(struct pci_bus *bus, struct resource *res,
1226 unsigned int flags);
2fe2abf8
BH		 1227struct resource *pci_bus_resource_n(const struct pci_bus *bus, int n);
1228void pci_bus_remove_resources(struct pci_bus *bus);
950334bc
BH		 1229int devm_request_pci_bus_resources(struct device *dev,
1230 struct list_head *resources);
2fe2abf8 1231
89a74ecc 1232#define pci_bus_for_each_resource(bus, res, i) \
2fe2abf8
BH		 1233 for (i = 0; \
1234 (res = pci_bus_resource_n(bus, i)) || i < PCI_BRIDGE_RESOURCE_NUM; \
1235 i++)
89a74ecc 1236
4a7fb636
AM		 1237int __must_check pci_bus_alloc_resource(struct pci_bus *bus,
1238 struct resource *res, resource_size_t size,
1239 resource_size_t align, resource_size_t min,
664c2848 1240 unsigned long type_mask,
3b7a17fc
DB		 1241 resource_size_t (*alignf)(void *,
1242 const struct resource *,
b26b2d49
DB		 1243 resource_size_t,
1244 resource_size_t),
4a7fb636 1245 void *alignf_data);
1da177e4 1246
8b921acf 1247
36e6f3d4
GP		 1248int pci_register_io_range(struct fwnode_handle *fwnode, phys_addr_t addr,
1249 resource_size_t size);
c5076cfe
TN		 1250unsigned long pci_address_to_pio(phys_addr_t addr);
1251phys_addr_t pci_pio_to_address(unsigned long pio);
8b921acf 1252int pci_remap_iospace(const struct resource *res, phys_addr_t phys_addr);
7799ae5d
SS		 1253int devm_pci_remap_iospace(struct device *dev, const struct resource *res,
1254 phys_addr_t phys_addr);
4d3f1384 1255void pci_unmap_iospace(struct resource *res);
490cb6dd
LP		 1256void __iomem *devm_pci_remap_cfgspace(struct device *dev,
1257 resource_size_t offset,
1258 resource_size_t size);
1259void __iomem *devm_pci_remap_cfg_resource(struct device *dev,
1260 struct resource *res);
8b921acf 1261
3a9ad0b4 1262static inline pci_bus_addr_t pci_bus_address(struct pci_dev *pdev, int bar)
06cf56e4
BH		 1263{
1264 struct pci_bus_region region;
1265
1266 pcibios_resource_to_bus(pdev->bus, &region, &pdev->resource[bar]);
1267 return region.start;
1268}
1269
863b18f4 1270/* Proper probing supporting hot-pluggable devices */
725522b5
GKH		 1271int __must_check __pci_register_driver(struct pci_driver *, struct module *,
1272 const char *mod_name);
bba81165
AM		 1273
1274/*
1275 * pci_register_driver must be a macro so that KBUILD_MODNAME can be expanded
1276 */
1277#define pci_register_driver(driver) \
1278 __pci_register_driver(driver, THIS_MODULE, KBUILD_MODNAME)
863b18f4 1279
05cca6e5 1280void pci_unregister_driver(struct pci_driver *dev);
aad4f400
GKH		 1281
1282/**
1283 * module_pci_driver() - Helper macro for registering a PCI driver
1284 * @__pci_driver: pci_driver struct
1285 *
1286 * Helper macro for PCI drivers which do not do anything special in module
1287 * init/exit. This eliminates a lot of boilerplate. Each module may only
1288 * use this macro once, and calling it replaces module_init() and module_exit()
1289 */
1290#define module_pci_driver(__pci_driver) \
1291 module_driver(__pci_driver, pci_register_driver, \
1292 pci_unregister_driver)
1293
b4eb6cdb
PG		 1294/**
1295 * builtin_pci_driver() - Helper macro for registering a PCI driver
1296 * @__pci_driver: pci_driver struct
1297 *
1298 * Helper macro for PCI drivers which do not do anything special in their
1299 * init code. This eliminates a lot of boilerplate. Each driver may only
1300 * use this macro once, and calling it replaces device_initcall(...)
1301 */
1302#define builtin_pci_driver(__pci_driver) \
1303 builtin_driver(__pci_driver, pci_register_driver)
1304
05cca6e5 1305struct pci_driver *pci_dev_driver(const struct pci_dev *dev);
9dba910e
TH		 1306int pci_add_dynid(struct pci_driver *drv,
1307 unsigned int vendor, unsigned int device,
1308 unsigned int subvendor, unsigned int subdevice,
1309 unsigned int class, unsigned int class_mask,
1310 unsigned long driver_data);
05cca6e5
GKH		 1311const struct pci_device_id *pci_match_id(const struct pci_device_id *ids,
1312 struct pci_dev *dev);
1313int pci_scan_bridge(struct pci_bus *bus, struct pci_dev *dev, int max,
1314 int pass);
1da177e4 1315
70298c6e 1316void pci_walk_bus(struct pci_bus *top, int (*cb)(struct pci_dev *, void *),
cecf4864 1317 void *userdata);
ac7dc65a 1318int pci_cfg_space_size(struct pci_dev *dev);
05cca6e5 1319unsigned char pci_bus_max_busnr(struct pci_bus *bus);
e2444273 1320void pci_setup_bridge(struct pci_bus *bus);
ac5ad93e
GS		 1321resource_size_t pcibios_window_alignment(struct pci_bus *bus,
1322 unsigned long type);
978d2d68 1323resource_size_t pcibios_iov_resource_alignment(struct pci_dev *dev, int resno);
cecf4864 1324
3448a19d
DA		 1325#define PCI_VGA_STATE_CHANGE_BRIDGE (1 << 0)
1326#define PCI_VGA_STATE_CHANGE_DECODES (1 << 1)
1327
deb2d2ec 1328int pci_set_vga_state(struct pci_dev *pdev, bool decode,
3448a19d 1329 unsigned int command_bits, u32 flags);
fe537670 1330
4fe0d154
CH		 1331#define PCI_IRQ_LEGACY (1 << 0) /* allow legacy interrupts */
1332#define PCI_IRQ_MSI (1 << 1) /* allow MSI interrupts */
1333#define PCI_IRQ_MSIX (1 << 2) /* allow MSI-X interrupts */
1334#define PCI_IRQ_AFFINITY (1 << 3) /* auto-assign affinity */
1335#define PCI_IRQ_ALL_TYPES \
1336 (PCI_IRQ_LEGACY | PCI_IRQ_MSI | PCI_IRQ_MSIX)
aff17164 1337
1da177e4
LT		 1338/* kmem_cache style wrapper around pci_alloc_consistent() */
1339
f41b1771 1340#include <linux/pci-dma.h>
1da177e4
LT		 1341#include <linux/dmapool.h>
1342
1343#define pci_pool dma_pool
1344#define pci_pool_create(name, pdev, size, align, allocation) \
1345 dma_pool_create(name, &pdev->dev, size, align, allocation)
1346#define pci_pool_destroy(pool) dma_pool_destroy(pool)
1347#define pci_pool_alloc(pool, flags, handle) dma_pool_alloc(pool, flags, handle)
01a7fd33
SS		 1348#define pci_pool_zalloc(pool, flags, handle) \
1349 dma_pool_zalloc(pool, flags, handle)
1da177e4
LT		 1350#define pci_pool_free(pool, vaddr, addr) dma_pool_free(pool, vaddr, addr)
1351
1da177e4 1352struct msix_entry {
16dbef4a 1353 u32 vector; /* kernel uses to write allocated vector */
1da177e4
LT		 1354 u16 entry; /* driver uses to specify entry, OS writes */
1355};
1356
4c859804
BH		 1357#ifdef CONFIG_PCI_MSI
1358int pci_msi_vec_count(struct pci_dev *dev);
f39d5b72 1359void pci_disable_msi(struct pci_dev *dev);
4c859804 1360int pci_msix_vec_count(struct pci_dev *dev);
f39d5b72 1361void pci_disable_msix(struct pci_dev *dev);
f39d5b72
BH		 1362void pci_restore_msi_state(struct pci_dev *dev);
1363int pci_msi_enabled(void);
4fe03955 1364int pci_enable_msi(struct pci_dev *dev);
4c859804
BH		 1365int pci_enable_msix_range(struct pci_dev *dev, struct msix_entry *entries,
1366 int minvec, int maxvec);
f7fc32cb
AG		 1367static inline int pci_enable_msix_exact(struct pci_dev *dev,
1368 struct msix_entry *entries, int nvec)
1369{
1370 int rc = pci_enable_msix_range(dev, entries, nvec, nvec);
1371 if (rc < 0)
1372 return rc;
1373 return 0;
1374}
402723ad
CH		 1375int pci_alloc_irq_vectors_affinity(struct pci_dev *dev, unsigned int min_vecs,
1376 unsigned int max_vecs, unsigned int flags,
1377 const struct irq_affinity *affd);
1378
aff17164
CH		 1379void pci_free_irq_vectors(struct pci_dev *dev);
1380int pci_irq_vector(struct pci_dev *dev, unsigned int nr);
ee8d41e5 1381const struct cpumask *pci_irq_get_affinity(struct pci_dev *pdev, int vec);
27ddb689 1382int pci_irq_get_node(struct pci_dev *pdev, int vec);
aff17164 1383
4c859804 1384#else
2ee546c4 1385static inline int pci_msi_vec_count(struct pci_dev *dev) { return -ENOSYS; }
2ee546c4
BH		 1386static inline void pci_disable_msi(struct pci_dev *dev) { }
1387static inline int pci_msix_vec_count(struct pci_dev *dev) { return -ENOSYS; }
2ee546c4 1388static inline void pci_disable_msix(struct pci_dev *dev) { }
2ee546c4
BH		 1389static inline void pci_restore_msi_state(struct pci_dev *dev) { }
1390static inline int pci_msi_enabled(void) { return 0; }
4fe03955 1391static inline int pci_enable_msi(struct pci_dev *dev)
f7fc32cb 1392{ return -ENOSYS; }
302a2523
AG		 1393static inline int pci_enable_msix_range(struct pci_dev *dev,
1394 struct msix_entry *entries, int minvec, int maxvec)
2ee546c4 1395{ return -ENOSYS; }
f7fc32cb
AG		 1396static inline int pci_enable_msix_exact(struct pci_dev *dev,
1397 struct msix_entry *entries, int nvec)
1398{ return -ENOSYS; }
402723ad
CH		 1399
1400static inline int
1401pci_alloc_irq_vectors_affinity(struct pci_dev *dev, unsigned int min_vecs,
1402 unsigned int max_vecs, unsigned int flags,
1403 const struct irq_affinity *aff_desc)
aff17164 1404{
83b4605b
CH		 1405 if ((flags & PCI_IRQ_LEGACY) && min_vecs == 1 && dev->irq)
1406 return 1;
1407 return -ENOSPC;
aff17164 1408}
402723ad 1409
aff17164
CH		 1410static inline void pci_free_irq_vectors(struct pci_dev *dev)
1411{
1412}
1413
1414static inline int pci_irq_vector(struct pci_dev *dev, unsigned int nr)
1415{
1416 if (WARN_ON_ONCE(nr > 0))
1417 return -EINVAL;
1418 return dev->irq;
1419}
ee8d41e5
TG		 1420static inline const struct cpumask *pci_irq_get_affinity(struct pci_dev *pdev,
1421 int vec)
1422{
1423 return cpu_possible_mask;
1424}
27ddb689
SL		 1425
1426static inline int pci_irq_get_node(struct pci_dev *pdev, int vec)
1427{
1428 return first_online_node;
1429}
1da177e4
LT		 1430#endif
1431
402723ad
CH		 1432static inline int
1433pci_alloc_irq_vectors(struct pci_dev *dev, unsigned int min_vecs,
1434 unsigned int max_vecs, unsigned int flags)
1435{
1436 return pci_alloc_irq_vectors_affinity(dev, min_vecs, max_vecs, flags,
1437 NULL);
1438}
1439
0d58e6c1
PB		 1440/**
1441 * pci_irqd_intx_xlate() - Translate PCI INTx value to an IRQ domain hwirq
1442 * @d: the INTx IRQ domain
1443 * @node: the DT node for the device whose interrupt we're translating
1444 * @intspec: the interrupt specifier data from the DT
1445 * @intsize: the number of entries in @intspec
1446 * @out_hwirq: pointer at which to write the hwirq number
1447 * @out_type: pointer at which to write the interrupt type
1448 *
1449 * Translate a PCI INTx interrupt number from device tree in the range 1-4, as
1450 * stored in the standard PCI_INTERRUPT_PIN register, to a value in the range
1451 * 0-3 suitable for use in a 4 entry IRQ domain. That is, subtract one from the
1452 * INTx value to obtain the hwirq number.
1453 *
1454 * Returns 0 on success, or -EINVAL if the interrupt specifier is out of range.
1455 */
1456static inline int pci_irqd_intx_xlate(struct irq_domain *d,
1457 struct device_node *node,
1458 const u32 *intspec,
1459 unsigned int intsize,
1460 unsigned long *out_hwirq,
1461 unsigned int *out_type)
1462{
1463 const u32 intx = intspec[0];
1464
1465 if (intx < PCI_INTERRUPT_INTA || intx > PCI_INTERRUPT_INTD)
1466 return -EINVAL;
1467
1468 *out_hwirq = intx - PCI_INTERRUPT_INTA;
1469 return 0;
1470}
1471
ab0724ff 1472#ifdef CONFIG_PCIEPORTBUS
415e12b2
RW		 1473extern bool pcie_ports_disabled;
1474extern bool pcie_ports_auto;
ab0724ff
MT		 1475#else
1476#define pcie_ports_disabled true
1477#define pcie_ports_auto false
1478#endif
415e12b2 1479
4c859804 1480#ifdef CONFIG_PCIEASPM
f39d5b72 1481bool pcie_aspm_support_enabled(void);
4c859804
BH		 1482#else
1483static inline bool pcie_aspm_support_enabled(void) { return false; }
3e1b1600
AP		 1484#endif
1485
415e12b2
RW		 1486#ifdef CONFIG_PCIEAER
1487void pci_no_aer(void);
1488bool pci_aer_available(void);
66b80809 1489int pci_aer_init(struct pci_dev *dev);
415e12b2
RW		 1490#else
1491static inline void pci_no_aer(void) { }
1492static inline bool pci_aer_available(void) { return false; }
66b80809 1493static inline int pci_aer_init(struct pci_dev *d) { return -ENODEV; }
415e12b2
RW		 1494#endif
1495
4c859804 1496#ifdef CONFIG_PCIE_ECRC
f39d5b72
BH		 1497void pcie_set_ecrc_checking(struct pci_dev *dev);
1498void pcie_ecrc_get_policy(char *str);
4c859804 1499#else
2ee546c4
BH		 1500static inline void pcie_set_ecrc_checking(struct pci_dev *dev) { }
1501static inline void pcie_ecrc_get_policy(char *str) { }
43c16408
AP		 1502#endif
1503
edc90fee
BH		 1504#ifdef CONFIG_PCI_ATS
1505/* Address Translation Service */
1506void pci_ats_init(struct pci_dev *dev);
ff9bee89
BH		 1507int pci_enable_ats(struct pci_dev *dev, int ps);
1508void pci_disable_ats(struct pci_dev *dev);
1509int pci_ats_queue_depth(struct pci_dev *dev);
edc90fee 1510#else
ff9bee89
BH		 1511static inline void pci_ats_init(struct pci_dev *d) { }
1512static inline int pci_enable_ats(struct pci_dev *d, int ps) { return -ENODEV; }
1513static inline void pci_disable_ats(struct pci_dev *d) { }
1514static inline int pci_ats_queue_depth(struct pci_dev *d) { return -ENODEV; }
edc90fee
BH		 1515#endif
1516
eec097d4
BH		 1517#ifdef CONFIG_PCIE_PTM
1518int pci_enable_ptm(struct pci_dev *dev, u8 *granularity);
1519#else
1520static inline int pci_enable_ptm(struct pci_dev *dev, u8 *granularity)
1521{ return -EINVAL; }
1522#endif
1523
f39d5b72
BH		 1524void pci_cfg_access_lock(struct pci_dev *dev);
1525bool pci_cfg_access_trylock(struct pci_dev *dev);
1526void pci_cfg_access_unlock(struct pci_dev *dev);
e04b0ea2 1527
4352dfd5
GKH		 1528/*
1529 * PCI domain support. Sometimes called PCI segment (eg by ACPI),
f7625980 1530 * a PCI domain is defined to be a set of PCI buses which share
4352dfd5
GKH		 1531 * configuration space.
1532 */
32a2eea7
JG		 1533#ifdef CONFIG_PCI_DOMAINS
1534extern int pci_domains_supported;
41e5c0f8 1535int pci_get_new_domain_nr(void);
32a2eea7
JG		 1536#else
1537enum { pci_domains_supported = 0 };
2ee546c4
BH		 1538static inline int pci_domain_nr(struct pci_bus *bus) { return 0; }
1539static inline int pci_proc_domain(struct pci_bus *bus) { return 0; }
41e5c0f8 1540static inline int pci_get_new_domain_nr(void) { return -ENOSYS; }
32a2eea7 1541#endif /* CONFIG_PCI_DOMAINS */
1da177e4 1542
670ba0c8
CM		 1543/*
1544 * Generic implementation for PCI domain support. If your
1545 * architecture does not need custom management of PCI
1546 * domains then this implementation will be used
1547 */
1548#ifdef CONFIG_PCI_DOMAINS_GENERIC
1549static inline int pci_domain_nr(struct pci_bus *bus)
1550{
1551 return bus->domain_nr;
1552}
2ab51dde
TN		 1553#ifdef CONFIG_ACPI
1554int acpi_pci_bus_find_domain_nr(struct pci_bus *bus);
670ba0c8 1555#else
2ab51dde
TN		 1556static inline int acpi_pci_bus_find_domain_nr(struct pci_bus *bus)
1557{ return 0; }
1558#endif
9c7cb891 1559int pci_bus_find_domain_nr(struct pci_bus *bus, struct device *parent);
670ba0c8
CM		 1560#endif
1561
95a8b6ef
MT		 1562/* some architectures require additional setup to direct VGA traffic */
1563typedef int (*arch_set_vga_state_t)(struct pci_dev *pdev, bool decode,
3448a19d 1564 unsigned int command_bits, u32 flags);
f39d5b72 1565void pci_register_set_vga_state(arch_set_vga_state_t func);
95a8b6ef 1566
be9d2e89
JT		 1567static inline int
1568pci_request_io_regions(struct pci_dev *pdev, const char *name)
1569{
1570 return pci_request_selected_regions(pdev,
1571 pci_select_bars(pdev, IORESOURCE_IO), name);
1572}
1573
1574static inline void
1575pci_release_io_regions(struct pci_dev *pdev)
1576{
1577 return pci_release_selected_regions(pdev,
1578 pci_select_bars(pdev, IORESOURCE_IO));
1579}
1580
1581static inline int
1582pci_request_mem_regions(struct pci_dev *pdev, const char *name)
1583{
1584 return pci_request_selected_regions(pdev,
1585 pci_select_bars(pdev, IORESOURCE_MEM), name);
1586}
1587
1588static inline void
1589pci_release_mem_regions(struct pci_dev *pdev)
1590{
1591 return pci_release_selected_regions(pdev,
1592 pci_select_bars(pdev, IORESOURCE_MEM));
1593}
1594
4352dfd5 1595#else /* CONFIG_PCI is not enabled */
1da177e4 1596
5bbe029f
BH		 1597static inline void pci_set_flags(int flags) { }
1598static inline void pci_add_flags(int flags) { }
1599static inline void pci_clear_flags(int flags) { }
1600static inline int pci_has_flag(int flag) { return 0; }
1601
1da177e4
LT		 1602/*
1603 * If the system does not have PCI, clearly these return errors. Define
1604 * these as simple inline functions to avoid hair in drivers.
1605 */
1606
05cca6e5
GKH		 1607#define _PCI_NOP(o, s, t) \
1608 static inline int pci_##o##_config_##s(struct pci_dev *dev, \
1609 int where, t val) \
1da177e4 1610 { return PCIBIOS_FUNC_NOT_SUPPORTED; }
05cca6e5
GKH		 1611
1612#define _PCI_NOP_ALL(o, x) _PCI_NOP(o, byte, u8 x) \
1613 _PCI_NOP(o, word, u16 x) \
1614 _PCI_NOP(o, dword, u32 x)
1da177e4
LT		 1615_PCI_NOP_ALL(read, *)
1616_PCI_NOP_ALL(write,)
1617
d42552c3 1618static inline struct pci_dev *pci_get_device(unsigned int vendor,
05cca6e5
GKH		 1619 unsigned int device,
1620 struct pci_dev *from)
2ee546c4 1621{ return NULL; }
d42552c3 1622
05cca6e5
GKH		 1623static inline struct pci_dev *pci_get_subsys(unsigned int vendor,
1624 unsigned int device,
1625 unsigned int ss_vendor,
1626 unsigned int ss_device,
b08508c4 1627 struct pci_dev *from)
2ee546c4 1628{ return NULL; }
1da177e4 1629
05cca6e5
GKH		 1630static inline struct pci_dev *pci_get_class(unsigned int class,
1631 struct pci_dev *from)
2ee546c4 1632{ return NULL; }
1da177e4
LT		 1633
1634#define pci_dev_present(ids) (0)
ed4aaadb 1635#define no_pci_devices() (1)
1da177e4
LT		 1636#define pci_dev_put(dev) do { } while (0)
1637
2ee546c4
BH		 1638static inline void pci_set_master(struct pci_dev *dev) { }
1639static inline int pci_enable_device(struct pci_dev *dev) { return -EIO; }
1640static inline void pci_disable_device(struct pci_dev *dev) { }
05cca6e5 1641static inline int pci_assign_resource(struct pci_dev *dev, int i)
2ee546c4 1642{ return -EBUSY; }
05cca6e5
GKH		 1643static inline int __pci_register_driver(struct pci_driver *drv,
1644 struct module *owner)
2ee546c4 1645{ return 0; }
05cca6e5 1646static inline int pci_register_driver(struct pci_driver *drv)
2ee546c4
BH		 1647{ return 0; }
1648static inline void pci_unregister_driver(struct pci_driver *drv) { }
05cca6e5 1649static inline int pci_find_capability(struct pci_dev *dev, int cap)
2ee546c4 1650{ return 0; }
05cca6e5
GKH		 1651static inline int pci_find_next_capability(struct pci_dev *dev, u8 post,
1652 int cap)
2ee546c4 1653{ return 0; }
05cca6e5 1654static inline int pci_find_ext_capability(struct pci_dev *dev, int cap)
2ee546c4 1655{ return 0; }
05cca6e5 1656
1da177e4 1657/* Power management related routines */
2ee546c4
BH		 1658static inline int pci_save_state(struct pci_dev *dev) { return 0; }
1659static inline void pci_restore_state(struct pci_dev *dev) { }
05cca6e5 1660static inline int pci_set_power_state(struct pci_dev *dev, pci_power_t state)
2ee546c4 1661{ return 0; }
3449248c 1662static inline int pci_wake_from_d3(struct pci_dev *dev, bool enable)
2ee546c4 1663{ return 0; }
05cca6e5
GKH		 1664static inline pci_power_t pci_choose_state(struct pci_dev *dev,
1665 pm_message_t state)
2ee546c4 1666{ return PCI_D0; }
05cca6e5
GKH		 1667static inline int pci_enable_wake(struct pci_dev *dev, pci_power_t state,
1668 int enable)
2ee546c4 1669{ return 0; }
48a92a81 1670
afd29f90
MW		 1671static inline struct resource *pci_find_resource(struct pci_dev *dev,
1672 struct resource *res)
1673{ return NULL; }
05cca6e5 1674static inline int pci_request_regions(struct pci_dev *dev, const char *res_name)
2ee546c4
BH		 1675{ return -EIO; }
1676static inline void pci_release_regions(struct pci_dev *dev) { }
0da0ead9 1677
c5076cfe
TN		 1678static inline unsigned long pci_address_to_pio(phys_addr_t addr) { return -1; }
1679
2ee546c4 1680static inline void pci_block_cfg_access(struct pci_dev *dev) { }
fb51ccbf
JK		 1681static inline int pci_block_cfg_access_in_atomic(struct pci_dev *dev)
1682{ return 0; }
2ee546c4 1683static inline void pci_unblock_cfg_access(struct pci_dev *dev) { }
e04b0ea2 1684
d80d0217
RD		 1685static inline struct pci_bus *pci_find_next_bus(const struct pci_bus *from)
1686{ return NULL; }
d80d0217
RD		 1687static inline struct pci_dev *pci_get_slot(struct pci_bus *bus,
1688 unsigned int devfn)
1689{ return NULL; }
d80d0217
RD		 1690static inline struct pci_dev *pci_get_bus_and_slot(unsigned int bus,
1691 unsigned int devfn)
1692{ return NULL; }
7912af5c
RD		 1693static inline struct pci_dev *pci_get_domain_bus_and_slot(int domain,
1694 unsigned int bus, unsigned int devfn)
1695{ return NULL; }
d80d0217 1696
2ee546c4
BH		 1697static inline int pci_domain_nr(struct pci_bus *bus) { return 0; }
1698static inline struct pci_dev *pci_dev_get(struct pci_dev *dev) { return NULL; }
41e5c0f8 1699static inline int pci_get_new_domain_nr(void) { return -ENOSYS; }
12ea6cad 1700
fb8a0d9d
WM		 1701#define dev_is_pci(d) (false)
1702#define dev_is_pf(d) (false)
fe594932
GU		 1703static inline bool pci_acs_enabled(struct pci_dev *pdev, u16 acs_flags)
1704{ return false; }
1de08652
NC		 1705static inline int pci_irqd_intx_xlate(struct irq_domain *d,
1706 struct device_node *node,
1707 const u32 *intspec,
1708 unsigned int intsize,
1709 unsigned long *out_hwirq,
1710 unsigned int *out_type)
1711{ return -EINVAL; }
4352dfd5 1712#endif /* CONFIG_PCI */
1da177e4 1713
4352dfd5
GKH		 1714/* Include architecture-dependent settings and functions */
1715
1716#include <asm/pci.h>
1da177e4 1717
f7195824
DW		 1718/* These two functions provide almost identical functionality. Depennding
1719 * on the architecture, one will be implemented as a wrapper around the
1720 * other (in drivers/pci/mmap.c).
1721 *
1722 * pci_mmap_resource_range() maps a specific BAR, and vm->vm_pgoff
1723 * is expected to be an offset within that region.
1724 *
1725 * pci_mmap_page_range() is the legacy architecture-specific interface,
1726 * which accepts a "user visible" resource address converted by
1727 * pci_resource_to_user(), as used in the legacy mmap() interface in
1728 * /proc/bus/pci/.
1729 */
1730int pci_mmap_resource_range(struct pci_dev *dev, int bar,
1731 struct vm_area_struct *vma,
1732 enum pci_mmap_state mmap_state, int write_combine);
f66e2258
DW		 1733int pci_mmap_page_range(struct pci_dev *pdev, int bar,
1734 struct vm_area_struct *vma,
11df1954
DW		 1735 enum pci_mmap_state mmap_state, int write_combine);
1736
ae749c7a
DW		 1737#ifndef arch_can_pci_mmap_wc
1738#define arch_can_pci_mmap_wc() 0
1739#endif
2bea36fd 1740
e854d8b2
DW		 1741#ifndef arch_can_pci_mmap_io
1742#define arch_can_pci_mmap_io() 0
2bea36fd
DW		 1743#define pci_iobar_pfn(pdev, bar, vma) (-EINVAL)
1744#else
1745int pci_iobar_pfn(struct pci_dev *pdev, int bar, struct vm_area_struct *vma);
e854d8b2 1746#endif
ae749c7a 1747
92016ba5
JO		 1748#ifndef pci_root_bus_fwnode
1749#define pci_root_bus_fwnode(bus) NULL
1750#endif
1751
1da177e4
LT		 1752/* these helpers provide future and backwards compatibility
1753 * for accessing popular PCI BAR info */
05cca6e5
GKH		 1754#define pci_resource_start(dev, bar) ((dev)->resource[(bar)].start)
1755#define pci_resource_end(dev, bar) ((dev)->resource[(bar)].end)
1756#define pci_resource_flags(dev, bar) ((dev)->resource[(bar)].flags)
1da177e4 1757#define pci_resource_len(dev,bar) \
05cca6e5
GKH		 1758 ((pci_resource_start((dev), (bar)) == 0 && \
1759 pci_resource_end((dev), (bar)) == \
1760 pci_resource_start((dev), (bar))) ? 0 : \
1761 \
1762 (pci_resource_end((dev), (bar)) - \
1763 pci_resource_start((dev), (bar)) + 1))
1da177e4
LT		 1764
1765/* Similar to the helpers above, these manipulate per-pci_dev
1766 * driver-specific data. They are really just a wrapper around
1767 * the generic device structure functions of these calls.
1768 */
05cca6e5 1769static inline void *pci_get_drvdata(struct pci_dev *pdev)
1da177e4
LT		 1770{
1771 return dev_get_drvdata(&pdev->dev);
1772}
1773
05cca6e5 1774static inline void pci_set_drvdata(struct pci_dev *pdev, void *data)
1da177e4
LT		 1775{
1776 dev_set_drvdata(&pdev->dev, data);
1777}
1778
1779/* If you want to know what to call your pci_dev, ask this function.
1780 * Again, it's a wrapper around the generic device.
1781 */
2fc90f61 1782static inline const char *pci_name(const struct pci_dev *pdev)
1da177e4 1783{
c6c4f070 1784 return dev_name(&pdev->dev);
1da177e4
LT		 1785}
1786
2311b1f2
ME		 1787
1788/* Some archs don't want to expose struct resource to userland as-is
1789 * in sysfs and /proc
1790 */
8221a013
BH		 1791#ifdef HAVE_ARCH_PCI_RESOURCE_TO_USER
1792void pci_resource_to_user(const struct pci_dev *dev, int bar,
1793 const struct resource *rsrc,
1794 resource_size_t *start, resource_size_t *end);
1795#else
2311b1f2 1796static inline void pci_resource_to_user(const struct pci_dev *dev, int bar,
05cca6e5 1797 const struct resource *rsrc, resource_size_t *start,
e31dd6e4 1798 resource_size_t *end)
2311b1f2
ME		 1799{
1800 *start = rsrc->start;
1801 *end = rsrc->end;
1802}
1803#endif /* HAVE_ARCH_PCI_RESOURCE_TO_USER */
1804
1805
1da177e4
LT		 1806/*
1807 * The world is not perfect and supplies us with broken PCI devices.
1808 * For at least a part of these bugs we need a work-around, so both
1809 * generic (drivers/pci/quirks.c) and per-architecture code can define
1810 * fixup hooks to be called for particular buggy devices.
1811 */
1812
1813struct pci_fixup {
f4ca5c6a
YL		 1814 u16 vendor; /* You can use PCI_ANY_ID here of course */
1815 u16 device; /* You can use PCI_ANY_ID here of course */
1816 u32 class; /* You can use PCI_ANY_ID here too */
1817 unsigned int class_shift; /* should be 0, 8, 16 */
1da177e4
LT		 1818 void (*hook)(struct pci_dev *dev);
1819};
1820
1821enum pci_fixup_pass {
1822 pci_fixup_early, /* Before probing BARs */
1823 pci_fixup_header, /* After reading configuration header */
1824 pci_fixup_final, /* Final phase of device fixups */
1825 pci_fixup_enable, /* pci_enable_device() time */
e1a2a51e 1826 pci_fixup_resume, /* pci_device_resume() */
7d2a01b8 1827 pci_fixup_suspend, /* pci_device_suspend() */
e1a2a51e 1828 pci_fixup_resume_early, /* pci_device_resume_early() */
7d2a01b8 1829 pci_fixup_suspend_late, /* pci_device_suspend_late() */
1da177e4
LT		 1830};
1831
1832/* Anonymous variables would be nice... */
f4ca5c6a
YL		 1833#define DECLARE_PCI_FIXUP_SECTION(section, name, vendor, device, class, \
1834 class_shift, hook) \
ecf61c78 1835 static const struct pci_fixup __PASTE(__pci_fixup_##name,__LINE__) __used \
f4ca5c6a
YL		 1836 __attribute__((__section__(#section), aligned((sizeof(void *))))) \
1837 = { vendor, device, class, class_shift, hook };
1838
1839#define DECLARE_PCI_FIXUP_CLASS_EARLY(vendor, device, class, \
1840 class_shift, hook) \
1841 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_early, \
ecf61c78 1842 hook, vendor, device, class, class_shift, hook)
f4ca5c6a
YL		 1843#define DECLARE_PCI_FIXUP_CLASS_HEADER(vendor, device, class, \
1844 class_shift, hook) \
1845 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_header, \
ecf61c78 1846 hook, vendor, device, class, class_shift, hook)
f4ca5c6a
YL		 1847#define DECLARE_PCI_FIXUP_CLASS_FINAL(vendor, device, class, \
1848 class_shift, hook) \
1849 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_final, \
ecf61c78 1850 hook, vendor, device, class, class_shift, hook)
f4ca5c6a
YL		 1851#define DECLARE_PCI_FIXUP_CLASS_ENABLE(vendor, device, class, \
1852 class_shift, hook) \
1853 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_enable, \
ecf61c78 1854 hook, vendor, device, class, class_shift, hook)
f4ca5c6a
YL		 1855#define DECLARE_PCI_FIXUP_CLASS_RESUME(vendor, device, class, \
1856 class_shift, hook) \
1857 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume, \
ecf61c78 1858 resume##hook, vendor, device, class, \
f4ca5c6a
YL		 1859 class_shift, hook)
1860#define DECLARE_PCI_FIXUP_CLASS_RESUME_EARLY(vendor, device, class, \
1861 class_shift, hook) \
1862 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume_early, \
ecf61c78 1863 resume_early##hook, vendor, device, \
f4ca5c6a
YL		 1864 class, class_shift, hook)
1865#define DECLARE_PCI_FIXUP_CLASS_SUSPEND(vendor, device, class, \
1866 class_shift, hook) \
1867 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend, \
ecf61c78 1868 suspend##hook, vendor, device, class, \
f4ca5c6a 1869 class_shift, hook)
7d2a01b8
AN		 1870#define DECLARE_PCI_FIXUP_CLASS_SUSPEND_LATE(vendor, device, class, \
1871 class_shift, hook) \
1872 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend_late, \
1873 suspend_late##hook, vendor, device, \
1874 class, class_shift, hook)
f4ca5c6a 1875
1da177e4
LT		 1876#define DECLARE_PCI_FIXUP_EARLY(vendor, device, hook) \
1877 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_early, \
ecf61c78 1878 hook, vendor, device, PCI_ANY_ID, 0, hook)
1da177e4
LT		 1879#define DECLARE_PCI_FIXUP_HEADER(vendor, device, hook) \
1880 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_header, \
ecf61c78 1881 hook, vendor, device, PCI_ANY_ID, 0, hook)
1da177e4
LT		 1882#define DECLARE_PCI_FIXUP_FINAL(vendor, device, hook) \
1883 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_final, \
ecf61c78 1884 hook, vendor, device, PCI_ANY_ID, 0, hook)
1da177e4
LT		 1885#define DECLARE_PCI_FIXUP_ENABLE(vendor, device, hook) \
1886 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_enable, \
ecf61c78 1887 hook, vendor, device, PCI_ANY_ID, 0, hook)
1597cacb
AC		 1888#define DECLARE_PCI_FIXUP_RESUME(vendor, device, hook) \
1889 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume, \
ecf61c78 1890 resume##hook, vendor, device, \
f4ca5c6a 1891 PCI_ANY_ID, 0, hook)
e1a2a51e
RW		 1892#define DECLARE_PCI_FIXUP_RESUME_EARLY(vendor, device, hook) \
1893 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume_early, \
ecf61c78 1894 resume_early##hook, vendor, device, \
f4ca5c6a 1895 PCI_ANY_ID, 0, hook)
e1a2a51e
RW		 1896#define DECLARE_PCI_FIXUP_SUSPEND(vendor, device, hook) \
1897 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend, \
ecf61c78 1898 suspend##hook, vendor, device, \
f4ca5c6a 1899 PCI_ANY_ID, 0, hook)
7d2a01b8
AN		 1900#define DECLARE_PCI_FIXUP_SUSPEND_LATE(vendor, device, hook) \
1901 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend_late, \
1902 suspend_late##hook, vendor, device, \
1903 PCI_ANY_ID, 0, hook)
1da177e4 1904
93177a74 1905#ifdef CONFIG_PCI_QUIRKS
1da177e4 1906void pci_fixup_device(enum pci_fixup_pass pass, struct pci_dev *dev);
ad805758 1907int pci_dev_specific_acs_enabled(struct pci_dev *dev, u16 acs_flags);
c1d61c9b 1908int pci_dev_specific_enable_acs(struct pci_dev *dev);
93177a74
RW		 1909#else
1910static inline void pci_fixup_device(enum pci_fixup_pass pass,
2ee546c4 1911 struct pci_dev *dev) { }
ad805758
AW		 1912static inline int pci_dev_specific_acs_enabled(struct pci_dev *dev,
1913 u16 acs_flags)
1914{
1915 return -ENOTTY;
1916}
c1d61c9b
AW		 1917static inline int pci_dev_specific_enable_acs(struct pci_dev *dev)
1918{
1919 return -ENOTTY;
1920}
93177a74 1921#endif
1da177e4 1922
05cca6e5 1923void __iomem *pcim_iomap(struct pci_dev *pdev, int bar, unsigned long maxlen);
5ea81769 1924void pcim_iounmap(struct pci_dev *pdev, void __iomem *addr);
05cca6e5 1925void __iomem * const *pcim_iomap_table(struct pci_dev *pdev);
fb7ebfe4
YL		 1926int pcim_iomap_regions(struct pci_dev *pdev, int mask, const char *name);
1927int pcim_iomap_regions_request_all(struct pci_dev *pdev, int mask,
916fbfb7 1928 const char *name);
fb7ebfe4 1929void pcim_iounmap_regions(struct pci_dev *pdev, int mask);
5ea81769 1930
1da177e4 1931extern int pci_pci_problems;
236561e5 1932#define PCIPCI_FAIL 1 /* No PCI PCI DMA */
1da177e4
LT		 1933#define PCIPCI_TRITON 2
1934#define PCIPCI_NATOMA 4
1935#define PCIPCI_VIAETBF 8
1936#define PCIPCI_VSFX 16
236561e5
AC		 1937#define PCIPCI_ALIMAGIK 32 /* Need low latency setting */
1938#define PCIAGP_FAIL 64 /* No PCI to AGP DMA */
1da177e4 1939
4516a618
AN		 1940extern unsigned long pci_cardbus_io_size;
1941extern unsigned long pci_cardbus_mem_size;
15856ad5 1942extern u8 pci_dfl_cache_line_size;
ac1aa47b 1943extern u8 pci_cache_line_size;
4516a618 1944
28760489
EB		 1945extern unsigned long pci_hotplug_io_size;
1946extern unsigned long pci_hotplug_mem_size;
e16b4660 1947extern unsigned long pci_hotplug_bus_size;
28760489 1948
f7625980 1949/* Architecture-specific versions may override these (weak) */
19792a08 1950void pcibios_disable_device(struct pci_dev *dev);
cfce9fb8 1951void pcibios_set_master(struct pci_dev *dev);
19792a08
AB		 1952int pcibios_set_pcie_reset_state(struct pci_dev *dev,
1953 enum pcie_reset_state state);
eca0d467 1954int pcibios_add_device(struct pci_dev *dev);
6ae32c53 1955void pcibios_release_device(struct pci_dev *dev);
a43ae58c 1956void pcibios_penalize_isa_irq(int irq, int active);
890e4847
JL		 1957int pcibios_alloc_irq(struct pci_dev *dev);
1958void pcibios_free_irq(struct pci_dev *dev);
575e3348 1959
699c1985
SO		 1960#ifdef CONFIG_HIBERNATE_CALLBACKS
1961extern struct dev_pm_ops pcibios_pm_ops;
1962#endif
1963
935c760e 1964#if defined(CONFIG_PCI_MMCONFIG) || defined(CONFIG_ACPI_MCFG)
f39d5b72
BH		 1965void __init pci_mmcfg_early_init(void);
1966void __init pci_mmcfg_late_init(void);
7752d5cf 1967#else
bb63b421 1968static inline void pci_mmcfg_early_init(void) { }
7752d5cf
RH		 1969static inline void pci_mmcfg_late_init(void) { }
1970#endif
1971
642c92da 1972int pci_ext_cfg_avail(void);
0ef5f8f6 1973
1684f5dd 1974void __iomem *pci_ioremap_bar(struct pci_dev *pdev, int bar);
c43996f4 1975void __iomem *pci_ioremap_wc_bar(struct pci_dev *pdev, int bar);
aa42d7c6 1976
dd7cc44d 1977#ifdef CONFIG_PCI_IOV
b07579c0
WY		 1978int pci_iov_virtfn_bus(struct pci_dev *dev, int id);
1979int pci_iov_virtfn_devfn(struct pci_dev *dev, int id);
1980
f39d5b72
BH		 1981int pci_enable_sriov(struct pci_dev *dev, int nr_virtfn);
1982void pci_disable_sriov(struct pci_dev *dev);
753f6124
JS		 1983int pci_iov_add_virtfn(struct pci_dev *dev, int id);
1984void pci_iov_remove_virtfn(struct pci_dev *dev, int id);
f39d5b72 1985int pci_num_vf(struct pci_dev *dev);
5a8eb242 1986int pci_vfs_assigned(struct pci_dev *dev);
f39d5b72
BH		 1987int pci_sriov_set_totalvfs(struct pci_dev *dev, u16 numvfs);
1988int pci_sriov_get_totalvfs(struct pci_dev *dev);
0e6c9122 1989resource_size_t pci_iov_resource_size(struct pci_dev *dev, int resno);
dd7cc44d 1990#else
b07579c0
WY		 1991static inline int pci_iov_virtfn_bus(struct pci_dev *dev, int id)
1992{
1993 return -ENOSYS;
1994}
1995static inline int pci_iov_virtfn_devfn(struct pci_dev *dev, int id)
1996{
1997 return -ENOSYS;
1998}
dd7cc44d 1999static inline int pci_enable_sriov(struct pci_dev *dev, int nr_virtfn)
2ee546c4 2000{ return -ENODEV; }
753f6124 2001static inline int pci_iov_add_virtfn(struct pci_dev *dev, int id)
c194f7ea
WY		 2002{
2003 return -ENOSYS;
2004}
2005static inline void pci_iov_remove_virtfn(struct pci_dev *dev,
753f6124 2006 int id) { }
2ee546c4 2007static inline void pci_disable_sriov(struct pci_dev *dev) { }
2ee546c4 2008static inline int pci_num_vf(struct pci_dev *dev) { return 0; }
5a8eb242 2009static inline int pci_vfs_assigned(struct pci_dev *dev)
2ee546c4 2010{ return 0; }
bff73156 2011static inline int pci_sriov_set_totalvfs(struct pci_dev *dev, u16 numvfs)
2ee546c4 2012{ return 0; }
bff73156 2013static inline int pci_sriov_get_totalvfs(struct pci_dev *dev)
2ee546c4 2014{ return 0; }
0e6c9122
WY		 2015static inline resource_size_t pci_iov_resource_size(struct pci_dev *dev, int resno)
2016{ return 0; }
dd7cc44d
YZ		 2017#endif
2018
c825bc94 2019#if defined(CONFIG_HOTPLUG_PCI) || defined(CONFIG_HOTPLUG_PCI_MODULE)
f39d5b72
BH		 2020void pci_hp_create_module_link(struct pci_slot *pci_slot);
2021void pci_hp_remove_module_link(struct pci_slot *pci_slot);
c825bc94
KK		 2022#endif
2023
d7b7e605
KK		 2024/**
2025 * pci_pcie_cap - get the saved PCIe capability offset
2026 * @dev: PCI device
2027 *
2028 * PCIe capability offset is calculated at PCI device initialization
2029 * time and saved in the data structure. This function returns saved
2030 * PCIe capability offset. Using this instead of pci_find_capability()
2031 * reduces unnecessary search in the PCI configuration space. If you
2032 * need to calculate PCIe capability offset from raw device for some
2033 * reasons, please use pci_find_capability() instead.
2034 */
2035static inline int pci_pcie_cap(struct pci_dev *dev)
2036{
2037 return dev->pcie_cap;
2038}
2039
7eb776c4
KK		 2040/**
2041 * pci_is_pcie - check if the PCI device is PCI Express capable
2042 * @dev: PCI device
2043 *
a895c28a 2044 * Returns: true if the PCI device is PCI Express capable, false otherwise.
7eb776c4
KK		 2045 */
2046static inline bool pci_is_pcie(struct pci_dev *dev)
2047{
a895c28a 2048 return pci_pcie_cap(dev);
7eb776c4
KK		 2049}
2050
7c9c003c
MS		 2051/**
2052 * pcie_caps_reg - get the PCIe Capabilities Register
2053 * @dev: PCI device
2054 */
2055static inline u16 pcie_caps_reg(const struct pci_dev *dev)
2056{
2057 return dev->pcie_flags_reg;
2058}
2059
786e2288
YW		 2060/**
2061 * pci_pcie_type - get the PCIe device/port type
2062 * @dev: PCI device
2063 */
2064static inline int pci_pcie_type(const struct pci_dev *dev)
2065{
1c531d82 2066 return (pcie_caps_reg(dev) & PCI_EXP_FLAGS_TYPE) >> 4;
786e2288
YW		 2067}
2068
e784930b
JT		 2069static inline struct pci_dev *pcie_find_root_port(struct pci_dev *dev)
2070{
2071 while (1) {
2072 if (!pci_is_pcie(dev))
2073 break;
2074 if (pci_pcie_type(dev) == PCI_EXP_TYPE_ROOT_PORT)
2075 return dev;
2076 if (!dev->bus->self)
2077 break;
2078 dev = dev->bus->self;
2079 }
2080 return NULL;
2081}
2082
5d990b62 2083void pci_request_acs(void);
ad805758
AW		 2084bool pci_acs_enabled(struct pci_dev *pdev, u16 acs_flags);
2085bool pci_acs_path_enabled(struct pci_dev *start,
2086 struct pci_dev *end, u16 acs_flags);
a2ce7662 2087
7ad506fa 2088#define PCI_VPD_LRDT 0x80 /* Large Resource Data Type */
63ddc0b8 2089#define PCI_VPD_LRDT_ID(x) ((x) | PCI_VPD_LRDT)
7ad506fa
MC		 2090
2091/* Large Resource Data Type Tag Item Names */
2092#define PCI_VPD_LTIN_ID_STRING 0x02 /* Identifier String */
2093#define PCI_VPD_LTIN_RO_DATA 0x10 /* Read-Only Data */
2094#define PCI_VPD_LTIN_RW_DATA 0x11 /* Read-Write Data */
2095
2096#define PCI_VPD_LRDT_ID_STRING PCI_VPD_LRDT_ID(PCI_VPD_LTIN_ID_STRING)
2097#define PCI_VPD_LRDT_RO_DATA PCI_VPD_LRDT_ID(PCI_VPD_LTIN_RO_DATA)
2098#define PCI_VPD_LRDT_RW_DATA PCI_VPD_LRDT_ID(PCI_VPD_LTIN_RW_DATA)
2099
2100/* Small Resource Data Type Tag Item Names */
9eb45d5c 2101#define PCI_VPD_STIN_END 0x0f /* End */
7ad506fa 2102
9eb45d5c 2103#define PCI_VPD_SRDT_END (PCI_VPD_STIN_END << 3)
7ad506fa
MC		 2104
2105#define PCI_VPD_SRDT_TIN_MASK 0x78
2106#define PCI_VPD_SRDT_LEN_MASK 0x07
9eb45d5c 2107#define PCI_VPD_LRDT_TIN_MASK 0x7f
7ad506fa
MC		 2108
2109#define PCI_VPD_LRDT_TAG_SIZE 3
2110#define PCI_VPD_SRDT_TAG_SIZE 1
a2ce7662 2111
e1d5bdab
MC		 2112#define PCI_VPD_INFO_FLD_HDR_SIZE 3
2113
4067a854
MC		 2114#define PCI_VPD_RO_KEYWORD_PARTNO "PN"
2115#define PCI_VPD_RO_KEYWORD_MFR_ID "MN"
2116#define PCI_VPD_RO_KEYWORD_VENDOR0 "V0"
d4894f3e 2117#define PCI_VPD_RO_KEYWORD_CHKSUM "RV"
4067a854 2118
a2ce7662
MC		 2119/**
2120 * pci_vpd_lrdt_size - Extracts the Large Resource Data Type length
2121 * @lrdt: Pointer to the beginning of the Large Resource Data Type tag
2122 *
2123 * Returns the extracted Large Resource Data Type length.
2124 */
2125static inline u16 pci_vpd_lrdt_size(const u8 *lrdt)
2126{
2127 return (u16)lrdt[1] + ((u16)lrdt[2] << 8);
2128}
2129
9eb45d5c
HR		 2130/**
2131 * pci_vpd_lrdt_tag - Extracts the Large Resource Data Type Tag Item
2132 * @lrdt: Pointer to the beginning of the Large Resource Data Type tag
2133 *
2134 * Returns the extracted Large Resource Data Type Tag item.
2135 */
2136static inline u16 pci_vpd_lrdt_tag(const u8 *lrdt)
2137{
2138 return (u16)(lrdt[0] & PCI_VPD_LRDT_TIN_MASK);
2139}
2140
7ad506fa
MC		 2141/**
2142 * pci_vpd_srdt_size - Extracts the Small Resource Data Type length
0142626d 2143 * @srdt: Pointer to the beginning of the Small Resource Data Type tag
7ad506fa
MC		 2144 *
2145 * Returns the extracted Small Resource Data Type length.
2146 */
2147static inline u8 pci_vpd_srdt_size(const u8 *srdt)
2148{
2149 return (*srdt) & PCI_VPD_SRDT_LEN_MASK;
2150}
2151
9eb45d5c
HR		 2152/**
2153 * pci_vpd_srdt_tag - Extracts the Small Resource Data Type Tag Item
0142626d 2154 * @srdt: Pointer to the beginning of the Small Resource Data Type tag
9eb45d5c
HR		 2155 *
2156 * Returns the extracted Small Resource Data Type Tag Item.
2157 */
2158static inline u8 pci_vpd_srdt_tag(const u8 *srdt)
2159{
2160 return ((*srdt) & PCI_VPD_SRDT_TIN_MASK) >> 3;
2161}
2162
e1d5bdab
MC		 2163/**
2164 * pci_vpd_info_field_size - Extracts the information field length
2165 * @lrdt: Pointer to the beginning of an information field header
2166 *
2167 * Returns the extracted information field length.
2168 */
2169static inline u8 pci_vpd_info_field_size(const u8 *info_field)
2170{
2171 return info_field[2];
2172}
2173
b55ac1b2
MC		 2174/**
2175 * pci_vpd_find_tag - Locates the Resource Data Type tag provided
2176 * @buf: Pointer to buffered vpd data
2177 * @off: The offset into the buffer at which to begin the search
2178 * @len: The length of the vpd buffer
2179 * @rdt: The Resource Data Type to search for
2180 *
2181 * Returns the index where the Resource Data Type was found or
2182 * -ENOENT otherwise.
2183 */
2184int pci_vpd_find_tag(const u8 *buf, unsigned int off, unsigned int len, u8 rdt);
2185
4067a854
MC		 2186/**
2187 * pci_vpd_find_info_keyword - Locates an information field keyword in the VPD
2188 * @buf: Pointer to buffered vpd data
2189 * @off: The offset into the buffer at which to begin the search
2190 * @len: The length of the buffer area, relative to off, in which to search
2191 * @kw: The keyword to search for
2192 *
2193 * Returns the index where the information field keyword was found or
2194 * -ENOENT otherwise.
2195 */
2196int pci_vpd_find_info_keyword(const u8 *buf, unsigned int off,
2197 unsigned int len, const char *kw);
2198
98d9f30c
BH		 2199/* PCI <-> OF binding helpers */
2200#ifdef CONFIG_OF
2201struct device_node;
b165e2b6 2202struct irq_domain;
f39d5b72
BH		 2203void pci_set_of_node(struct pci_dev *dev);
2204void pci_release_of_node(struct pci_dev *dev);
2205void pci_set_bus_of_node(struct pci_bus *bus);
2206void pci_release_bus_of_node(struct pci_bus *bus);
b165e2b6 2207struct irq_domain *pci_host_bridge_of_msi_domain(struct pci_bus *bus);
98d9f30c
BH		 2208
2209/* Arch may override this (weak) */
723ec4d0 2210struct device_node *pcibios_get_phb_of_node(struct pci_bus *bus);
98d9f30c 2211
3df425f3
JC		 2212static inline struct device_node *
2213pci_device_to_OF_node(const struct pci_dev *pdev)
64099d98
BH		 2214{
2215 return pdev ? pdev->dev.of_node : NULL;
2216}
2217
ef3b4f8c
BH		 2218static inline struct device_node *pci_bus_to_OF_node(struct pci_bus *bus)
2219{
2220 return bus ? bus->dev.of_node : NULL;
2221}
2222
98d9f30c
BH		 2223#else /* CONFIG_OF */
2224static inline void pci_set_of_node(struct pci_dev *dev) { }
2225static inline void pci_release_of_node(struct pci_dev *dev) { }
2226static inline void pci_set_bus_of_node(struct pci_bus *bus) { }
2227static inline void pci_release_bus_of_node(struct pci_bus *bus) { }
f0b66a2c
KH		 2228static inline struct device_node *
2229pci_device_to_OF_node(const struct pci_dev *pdev) { return NULL; }
b165e2b6
MZ		 2230static inline struct irq_domain *
2231pci_host_bridge_of_msi_domain(struct pci_bus *bus) { return NULL; }
98d9f30c
BH		 2232#endif /* CONFIG_OF */
2233
471036b2
SS		 2234#ifdef CONFIG_ACPI
2235struct irq_domain *pci_host_bridge_acpi_msi_domain(struct pci_bus *bus);
2236
2237void
2238pci_msi_register_fwnode_provider(struct fwnode_handle *(*fn)(struct device *));
2239#else
2240static inline struct irq_domain *
2241pci_host_bridge_acpi_msi_domain(struct pci_bus *bus) { return NULL; }
2242#endif
2243
eb740b5f
GS		 2244#ifdef CONFIG_EEH
2245static inline struct eeh_dev *pci_dev_to_eeh_dev(struct pci_dev *pdev)
2246{
2247 return pdev->dev.archdata.edev;
2248}
2249#endif
2250
f0af9593 2251void pci_add_dma_alias(struct pci_dev *dev, u8 devfn);
338c3149 2252bool pci_devs_are_dma_aliases(struct pci_dev *dev1, struct pci_dev *dev2);
c25dc828
AW		 2253int pci_for_each_dma_alias(struct pci_dev *pdev,
2254 int (*fn)(struct pci_dev *pdev,
2255 u16 alias, void *data), void *data);
2256
ce052984
EZ		 2257/* helper functions for operation of device flag */
2258static inline void pci_set_dev_assigned(struct pci_dev *pdev)
2259{
2260 pdev->dev_flags |= PCI_DEV_FLAGS_ASSIGNED;
2261}
2262static inline void pci_clear_dev_assigned(struct pci_dev *pdev)
2263{
2264 pdev->dev_flags &= ~PCI_DEV_FLAGS_ASSIGNED;
2265}
2266static inline bool pci_is_dev_assigned(struct pci_dev *pdev)
2267{
2268 return (pdev->dev_flags & PCI_DEV_FLAGS_ASSIGNED) == PCI_DEV_FLAGS_ASSIGNED;
2269}
19bdb6e4
AW		 2270
2271/**
2272 * pci_ari_enabled - query ARI forwarding status
2273 * @bus: the PCI bus
2274 *
2275 * Returns true if ARI forwarding is enabled.
2276 */
2277static inline bool pci_ari_enabled(struct pci_bus *bus)
2278{
2279 return bus->self && bus->self->ari_enabled;
2280}
bc4b024a 2281
8531e283
LW		 2282/**
2283 * pci_is_thunderbolt_attached - whether device is on a Thunderbolt daisy chain
2284 * @pdev: PCI device to check
2285 *
2286 * Walk upwards from @pdev and check for each encountered bridge if it's part
2287 * of a Thunderbolt controller. Reaching the host bridge means @pdev is not
2288 * Thunderbolt-attached. (But rather soldered to the mainboard usually.)
2289 */
2290static inline bool pci_is_thunderbolt_attached(struct pci_dev *pdev)
2291{
2292 struct pci_dev *parent = pdev;
2293
2294 if (pdev->is_thunderbolt)
2295 return true;
2296
2297 while ((parent = pci_upstream_bridge(parent)))
2298 if (parent->is_thunderbolt)
2299 return true;
2300
2301 return false;
2302}
2303
bc4b024a
CH		 2304/* provide the legacy pci_dma_* API */
2305#include <linux/pci-dma-compat.h>
2306
f667c779
FL		 2307#define pci_printk(level, pdev, fmt, arg...) \
2308 dev_printk(level, &(pdev)->dev, fmt, ##arg)
2309
2310#define pci_emerg(pdev, fmt, arg...) dev_emerg(&(pdev)->dev, fmt, ##arg)
2311#define pci_alert(pdev, fmt, arg...) dev_alert(&(pdev)->dev, fmt, ##arg)
2312#define pci_crit(pdev, fmt, arg...) dev_crit(&(pdev)->dev, fmt, ##arg)
2313#define pci_err(pdev, fmt, arg...) dev_err(&(pdev)->dev, fmt, ##arg)
2314#define pci_warn(pdev, fmt, arg...) dev_warn(&(pdev)->dev, fmt, ##arg)
2315#define pci_notice(pdev, fmt, arg...) dev_notice(&(pdev)->dev, fmt, ##arg)
2316#define pci_info(pdev, fmt, arg...) dev_info(&(pdev)->dev, fmt, ##arg)
2317#define pci_dbg(pdev, fmt, arg...) dev_dbg(&(pdev)->dev, fmt, ##arg)
2318
1da177e4 2319#endif /* LINUX_PCI_H */
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