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Merge remote-tracking branch 'regulator/fix/max77802' into regulator-linus
[mirror_ubuntu-artful-kernel.git] / include / linux / pci.h
CommitLineData
1da177e4
LT		 1/*
2 * pci.h
3 *
4 * PCI defines and function prototypes
5 * Copyright 1994, Drew Eckhardt
6 * Copyright 1997--1999 Martin Mares <mj@ucw.cz>
7 *
8 * For more information, please consult the following manuals (look at
9 * http://www.pcisig.com/ for how to get them):
10 *
11 * PCI BIOS Specification
12 * PCI Local Bus Specification
13 * PCI to PCI Bridge Specification
14 * PCI System Design Guide
15 */
1da177e4
LT		 16#ifndef LINUX_PCI_H
17#define LINUX_PCI_H
18
1da177e4 19
778382e0
DW		 20#include <linux/mod_devicetable.h>
21
1da177e4 22#include <linux/types.h>
98db6f19 23#include <linux/init.h>
1da177e4
LT		 24#include <linux/ioport.h>
25#include <linux/list.h>
4a7fb636 26#include <linux/compiler.h>
1da177e4 27#include <linux/errno.h>
f46753c5 28#include <linux/kobject.h>
60063497 29#include <linux/atomic.h>
1da177e4 30#include <linux/device.h>
704e8953 31#include <linux/interrupt.h>
1388cc96 32#include <linux/io.h>
14d76b68 33#include <linux/resource_ext.h>
607ca46e 34#include <uapi/linux/pci.h>
1da177e4 35
7e7a43c3
AB		 36#include <linux/pci_ids.h>
37
85467136
SK		 38/*
39 * The PCI interface treats multi-function devices as independent
40 * devices. The slot/function address of each device is encoded
41 * in a single byte as follows:
42 *
43 * 7:3 = slot
44 * 2:0 = function
f7625980
BH		 45 *
46 * PCI_DEVFN(), PCI_SLOT(), and PCI_FUNC() are defined in uapi/linux/pci.h.
85467136 47 * In the interest of not exposing interfaces to user-space unnecessarily,
f7625980 48 * the following kernel-only defines are being added here.
85467136 49 */
63ddc0b8 50#define PCI_DEVID(bus, devfn) ((((u16)(bus)) << 8) | (devfn))
85467136
SK		 51/* return bus from PCI devid = ((u16)bus_number) << 8) | devfn */
52#define PCI_BUS_NUM(x) (((x) >> 8) & 0xff)
53
f46753c5
AC		 54/* pci_slot represents a physical slot */
55struct pci_slot {
56 struct pci_bus *bus; /* The bus this slot is on */
57 struct list_head list; /* node in list of slots on this bus */
58 struct hotplug_slot *hotplug; /* Hotplug info (migrate over time) */
59 unsigned char number; /* PCI_SLOT(pci_dev->devfn) */
60 struct kobject kobj;
61};
62
0ad772ec
AC		 63static inline const char *pci_slot_name(const struct pci_slot *slot)
64{
65 return kobject_name(&slot->kobj);
66}
67
1da177e4
LT		 68/* File state for mmap()s on /proc/bus/pci/X/Y */
69enum pci_mmap_state {
70 pci_mmap_io,
71 pci_mmap_mem
72};
73
fde09c6d
YZ		 74/*
75 * For PCI devices, the region numbers are assigned this way:
76 */
77enum {
78 /* #0-5: standard PCI resources */
79 PCI_STD_RESOURCES,
80 PCI_STD_RESOURCE_END = 5,
81
82 /* #6: expansion ROM resource */
83 PCI_ROM_RESOURCE,
84
d1b054da
YZ		 85 /* device specific resources */
86#ifdef CONFIG_PCI_IOV
87 PCI_IOV_RESOURCES,
88 PCI_IOV_RESOURCE_END = PCI_IOV_RESOURCES + PCI_SRIOV_NUM_BARS - 1,
89#endif
90
fde09c6d
YZ		 91 /* resources assigned to buses behind the bridge */
92#define PCI_BRIDGE_RESOURCE_NUM 4
93
94 PCI_BRIDGE_RESOURCES,
95 PCI_BRIDGE_RESOURCE_END = PCI_BRIDGE_RESOURCES +
96 PCI_BRIDGE_RESOURCE_NUM - 1,
97
98 /* total resources associated with a PCI device */
99 PCI_NUM_RESOURCES,
100
101 /* preserve this for compatibility */
cda57bf9 102 DEVICE_COUNT_RESOURCE = PCI_NUM_RESOURCES,
fde09c6d 103};
1da177e4 104
224abb67
BH		 105/*
106 * pci_power_t values must match the bits in the Capabilities PME_Support
107 * and Control/Status PowerState fields in the Power Management capability.
108 */
1da177e4
LT		 109typedef int __bitwise pci_power_t;
110
4352dfd5
GKH		 111#define PCI_D0 ((pci_power_t __force) 0)
112#define PCI_D1 ((pci_power_t __force) 1)
113#define PCI_D2 ((pci_power_t __force) 2)
1da177e4
LT		 114#define PCI_D3hot ((pci_power_t __force) 3)
115#define PCI_D3cold ((pci_power_t __force) 4)
3fe9d19f 116#define PCI_UNKNOWN ((pci_power_t __force) 5)
438510f6 117#define PCI_POWER_ERROR ((pci_power_t __force) -1)
1da177e4 118
00240c38
AS		 119/* Remember to update this when the list above changes! */
120extern const char *pci_power_names[];
121
122static inline const char *pci_power_name(pci_power_t state)
123{
9661e783 124 return pci_power_names[1 + (__force int) state];
00240c38
AS		 125}
126
448bd857
HY		 127#define PCI_PM_D2_DELAY 200
128#define PCI_PM_D3_WAIT 10
129#define PCI_PM_D3COLD_WAIT 100
130#define PCI_PM_BUS_WAIT 50
aa8c6c93 131
392a1ce7
LV		 132/** The pci_channel state describes connectivity between the CPU and
133 * the pci device. If some PCI bus between here and the pci device
134 * has crashed or locked up, this info is reflected here.
135 */
136typedef unsigned int __bitwise pci_channel_state_t;
137
138enum pci_channel_state {
139 /* I/O channel is in normal state */
140 pci_channel_io_normal = (__force pci_channel_state_t) 1,
141
142 /* I/O to channel is blocked */
143 pci_channel_io_frozen = (__force pci_channel_state_t) 2,
144
145 /* PCI card is dead */
146 pci_channel_io_perm_failure = (__force pci_channel_state_t) 3,
147};
148
f7bdd12d
BK		 149typedef unsigned int __bitwise pcie_reset_state_t;
150
151enum pcie_reset_state {
152 /* Reset is NOT asserted (Use to deassert reset) */
153 pcie_deassert_reset = (__force pcie_reset_state_t) 1,
154
f7625980 155 /* Use #PERST to reset PCIe device */
f7bdd12d
BK		 156 pcie_warm_reset = (__force pcie_reset_state_t) 2,
157
f7625980 158 /* Use PCIe Hot Reset to reset device */
f7bdd12d
BK		 159 pcie_hot_reset = (__force pcie_reset_state_t) 3
160};
161
ba698ad4
DM		 162typedef unsigned short __bitwise pci_dev_flags_t;
163enum pci_dev_flags {
164 /* INTX_DISABLE in PCI_COMMAND register disables MSI
165 * generation too.
166 */
6b121592 167 PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG = (__force pci_dev_flags_t) (1 << 0),
979b1791 168 /* Device configuration is irrevocably lost if disabled into D3 */
6b121592 169 PCI_DEV_FLAGS_NO_D3 = (__force pci_dev_flags_t) (1 << 1),
6777829c 170 /* Provide indication device is assigned by a Virtual Machine Manager */
6b121592 171 PCI_DEV_FLAGS_ASSIGNED = (__force pci_dev_flags_t) (1 << 2),
5757a769 172 /* Flag for quirk use to store if quirk-specific ACS is enabled */
6b121592 173 PCI_DEV_FLAGS_ACS_ENABLED_QUIRK = (__force pci_dev_flags_t) (1 << 3),
c8fe16e3
AW		 174 /* Use a PCIe-to-PCI bridge alias even if !pci_is_pcie */
175 PCI_DEV_FLAG_PCIE_BRIDGE_ALIAS = (__force pci_dev_flags_t) (1 << 5),
f331a859
AW		 176 /* Do not use bus resets for device */
177 PCI_DEV_FLAGS_NO_BUS_RESET = (__force pci_dev_flags_t) (1 << 6),
51e53738
AW		 178 /* Do not use PM reset even if device advertises NoSoftRst- */
179 PCI_DEV_FLAGS_NO_PM_RESET = (__force pci_dev_flags_t) (1 << 7),
932c435c
MR		 180 /* Get VPD from function 0 VPD */
181 PCI_DEV_FLAGS_VPD_REF_F0 = (__force pci_dev_flags_t) (1 << 8),
ffff8858
J		 182 /* a non-root bridge where translation occurs, stop alias search here */
183 PCI_DEV_FLAGS_BRIDGE_XLATE_ROOT = (__force pci_dev_flags_t) (1 << 9),
f65fd1aa
SN		 184 /* Do not use FLR even if device advertises PCI_AF_CAP */
185 PCI_DEV_FLAGS_NO_FLR_RESET = (__force pci_dev_flags_t) (1 << 10),
4d071c32
ID		 186 /*
187 * Resume before calling the driver's system suspend hooks, disabling
188 * the direct_complete optimization.
189 */
190 PCI_DEV_FLAGS_NEEDS_RESUME = (__force pci_dev_flags_t) (1 << 11),
ba698ad4
DM		 191};
192
e1d3a908
SA		 193enum pci_irq_reroute_variant {
194 INTEL_IRQ_REROUTE_VARIANT = 1,
195 MAX_IRQ_REROUTE_VARIANTS = 3
196};
197
6e325a62
MT		 198typedef unsigned short __bitwise pci_bus_flags_t;
199enum pci_bus_flags {
032c3d86
JD		 200 PCI_BUS_FLAGS_NO_MSI = (__force pci_bus_flags_t) 1,
201 PCI_BUS_FLAGS_NO_MMRBC = (__force pci_bus_flags_t) 2,
202 PCI_BUS_FLAGS_NO_AERSID = (__force pci_bus_flags_t) 4,
6e325a62
MT		 203};
204
59da381e
JK		 205/* These values come from the PCI Express Spec */
206enum pcie_link_width {
207 PCIE_LNK_WIDTH_RESRV = 0x00,
208 PCIE_LNK_X1 = 0x01,
209 PCIE_LNK_X2 = 0x02,
210 PCIE_LNK_X4 = 0x04,
211 PCIE_LNK_X8 = 0x08,
212 PCIE_LNK_X12 = 0x0C,
213 PCIE_LNK_X16 = 0x10,
214 PCIE_LNK_X32 = 0x20,
215 PCIE_LNK_WIDTH_UNKNOWN = 0xFF,
216};
217
536c8cb4
MW		 218/* Based on the PCI Hotplug Spec, but some values are made up by us */
219enum pci_bus_speed {
220 PCI_SPEED_33MHz = 0x00,
221 PCI_SPEED_66MHz = 0x01,
222 PCI_SPEED_66MHz_PCIX = 0x02,
223 PCI_SPEED_100MHz_PCIX = 0x03,
224 PCI_SPEED_133MHz_PCIX = 0x04,
225 PCI_SPEED_66MHz_PCIX_ECC = 0x05,
226 PCI_SPEED_100MHz_PCIX_ECC = 0x06,
227 PCI_SPEED_133MHz_PCIX_ECC = 0x07,
228 PCI_SPEED_66MHz_PCIX_266 = 0x09,
229 PCI_SPEED_100MHz_PCIX_266 = 0x0a,
230 PCI_SPEED_133MHz_PCIX_266 = 0x0b,
45b4cdd5
MW		 231 AGP_UNKNOWN = 0x0c,
232 AGP_1X = 0x0d,
233 AGP_2X = 0x0e,
234 AGP_4X = 0x0f,
235 AGP_8X = 0x10,
536c8cb4
MW		 236 PCI_SPEED_66MHz_PCIX_533 = 0x11,
237 PCI_SPEED_100MHz_PCIX_533 = 0x12,
238 PCI_SPEED_133MHz_PCIX_533 = 0x13,
239 PCIE_SPEED_2_5GT = 0x14,
240 PCIE_SPEED_5_0GT = 0x15,
9dfd97fe 241 PCIE_SPEED_8_0GT = 0x16,
536c8cb4
MW		 242 PCI_SPEED_UNKNOWN = 0xff,
243};
244
24a4742f 245struct pci_cap_saved_data {
fd0f7f73
AW		 246 u16 cap_nr;
247 bool cap_extended;
24a4742f 248 unsigned int size;
41017f0c
SL		 249 u32 data[0];
250};
251
24a4742f
AW		 252struct pci_cap_saved_state {
253 struct hlist_node next;
254 struct pci_cap_saved_data cap;
255};
256
402723ad 257struct irq_affinity;
7d715a6c 258struct pcie_link_state;
ee69439c 259struct pci_vpd;
d1b054da 260struct pci_sriov;
302b4215 261struct pci_ats;
ee69439c 262
1da177e4
LT		 263/*
264 * The pci_dev structure is used to describe PCI devices.
265 */
266struct pci_dev {
1da177e4
LT		 267 struct list_head bus_list; /* node in per-bus list */
268 struct pci_bus *bus; /* bus this device is on */
269 struct pci_bus *subordinate; /* bus this device bridges to */
270
271 void *sysdata; /* hook for sys-specific extension */
272 struct proc_dir_entry *procent; /* device entry in /proc/bus/pci */
f46753c5 273 struct pci_slot *slot; /* Physical slot this device is in */
1da177e4
LT		 274
275 unsigned int devfn; /* encoded device & function index */
276 unsigned short vendor;
277 unsigned short device;
278 unsigned short subsystem_vendor;
279 unsigned short subsystem_device;
280 unsigned int class; /* 3 bytes: (base,sub,prog-if) */
b8a3a521 281 u8 revision; /* PCI revision, low byte of class word */
1da177e4 282 u8 hdr_type; /* PCI header type (`multi' flag masked out) */
66b80809
KB		 283#ifdef CONFIG_PCIEAER
284 u16 aer_cap; /* AER capability offset */
285#endif
f7625980 286 u8 pcie_cap; /* PCIe capability offset */
e375b561
GS		 287 u8 msi_cap; /* MSI capability offset */
288 u8 msix_cap; /* MSI-X capability offset */
f7625980 289 u8 pcie_mpss:3; /* PCIe Max Payload Size Supported */
1da177e4 290 u8 rom_base_reg; /* which config register controls the ROM */
f7625980
BH		 291 u8 pin; /* which interrupt pin this device uses */
292 u16 pcie_flags_reg; /* cached PCIe Capabilities Register */
338c3149 293 unsigned long *dma_alias_mask;/* mask of enabled devfn aliases */
1da177e4
LT		 294
295 struct pci_driver *driver; /* which driver has allocated this device */
296 u64 dma_mask; /* Mask of the bits of bus address this
297 device implements. Normally this is
298 0xffffffff. You only need to change
299 this if your device has broken DMA
300 or supports 64-bit transfers. */
301
4d57cdfa
FT		 302 struct device_dma_parameters dma_parms;
303
1da177e4
LT		 304 pci_power_t current_state; /* Current operating state. In ACPI-speak,
305 this is D0-D3, D0 being fully functional,
306 and D3 being off. */
703860ed 307 u8 pm_cap; /* PM capability offset */
337001b6
RW		 308 unsigned int pme_support:5; /* Bitmask of states from which PME#
309 can be generated */
c7f48656 310 unsigned int pme_interrupt:1;
379021d5 311 unsigned int pme_poll:1; /* Poll device's PME status bit */
337001b6
RW		 312 unsigned int d1_support:1; /* Low power state D1 is supported */
313 unsigned int d2_support:1; /* Low power state D2 is supported */
448bd857
HY		 314 unsigned int no_d1d2:1; /* D1 and D2 are forbidden */
315 unsigned int no_d3cold:1; /* D3cold is forbidden */
9d26d3a8 316 unsigned int bridge_d3:1; /* Allow D3 for bridge */
448bd857 317 unsigned int d3cold_allowed:1; /* D3cold is allowed by user */
253d2e54
JP		 318 unsigned int mmio_always_on:1; /* disallow turning off io/mem
319 decoding during bar sizing */
e80bb09d 320 unsigned int wakeup_prepared:1;
448bd857
HY		 321 unsigned int runtime_d3cold:1; /* whether go through runtime
322 D3cold, not set for devices
323 powered on/off by the
324 corresponding bridge */
b440bde7 325 unsigned int ignore_hotplug:1; /* Ignore hotplug events */
576243b3
KB		 326 unsigned int hotplug_user_indicators:1; /* SlotCtl indicators
327 controlled exclusively by
328 user sysfs */
1ae861e6 329 unsigned int d3_delay; /* D3->D0 transition time in ms */
448bd857 330 unsigned int d3cold_delay; /* D3cold->D0 transition time in ms */
1da177e4 331
7d715a6c 332#ifdef CONFIG_PCIEASPM
f7625980 333 struct pcie_link_state *link_state; /* ASPM link state */
7d715a6c
SL		 334#endif
335
392a1ce7 336 pci_channel_state_t error_state; /* current connectivity state */
1da177e4
LT		 337 struct device dev; /* Generic device interface */
338
1da177e4
LT		 339 int cfg_size; /* Size of configuration space */
340
341 /*
342 * Instead of touching interrupt line and base address registers
343 * directly, use the values stored here. They might be different!
344 */
345 unsigned int irq;
346 struct resource resource[DEVICE_COUNT_RESOURCE]; /* I/O and memory regions + expansion ROMs */
347
58d9a38f 348 bool match_driver; /* Skip attaching driver */
1da177e4 349 /* These fields are used by common fixups */
f7625980 350 unsigned int transparent:1; /* Subtractive decode PCI bridge */
1da177e4
LT		 351 unsigned int multifunction:1;/* Part of multi-function device */
352 /* keep track of device state */
8a1bc901 353 unsigned int is_added:1;
1da177e4 354 unsigned int is_busmaster:1; /* device is busmaster */
4602b88d 355 unsigned int no_msi:1; /* device may not use msi */
f144d149 356 unsigned int no_64bit_msi:1; /* device may only use 32-bit MSIs */
fb51ccbf 357 unsigned int block_cfg_access:1; /* config space access is blocked */
bd8481e1 358 unsigned int broken_parity_status:1; /* Device generates false positive parity */
e1d3a908 359 unsigned int irq_reroute_variant:2; /* device needs IRQ rerouting variant */
f7625980 360 unsigned int msi_enabled:1;
99dc804d 361 unsigned int msix_enabled:1;
58c3a727 362 unsigned int ari_enabled:1; /* ARI forwarding */
d544d75a 363 unsigned int ats_enabled:1; /* Address Translation Service */
9ac7849e 364 unsigned int is_managed:1;
260d703a 365 unsigned int needs_freset:1; /* Dev requires fundamental reset */
aa8c6c93 366 unsigned int state_saved:1;
d1b054da 367 unsigned int is_physfn:1;
dd7cc44d 368 unsigned int is_virtfn:1;
711d5779 369 unsigned int reset_fn:1;
28760489 370 unsigned int is_hotplug_bridge:1;
8531e283 371 unsigned int is_thunderbolt:1; /* Thunderbolt controller */
affb72c3
HY		 372 unsigned int __aer_firmware_first_valid:1;
373 unsigned int __aer_firmware_first:1;
fbebb9fd 374 unsigned int broken_intx_masking:1;
2b28ae19 375 unsigned int io_window_1k:1; /* Intel P2P bridge 1K I/O windows */
cffe0a2b 376 unsigned int irq_managed:1;
d0751b98 377 unsigned int has_secondary_link:1;
b84106b4 378 unsigned int non_compliant_bars:1; /* broken BARs; ignore them */
ba698ad4 379 pci_dev_flags_t dev_flags;
bae94d02 380 atomic_t enable_cnt; /* pci_enable_device has been called */
4602b88d 381
1da177e4 382 u32 saved_config_space[16]; /* config space saved at suspend time */
41017f0c 383 struct hlist_head saved_cap_space;
1da177e4
LT		 384 struct bin_attribute *rom_attr; /* attribute descriptor for sysfs ROM entry */
385 int rom_attr_enabled; /* has display of the rom attribute been enabled? */
386 struct bin_attribute *res_attr[DEVICE_COUNT_RESOURCE]; /* sysfs file for resources */
45aec1ae 387 struct bin_attribute *res_attr_wc[DEVICE_COUNT_RESOURCE]; /* sysfs file for WC mapping of resources */
9bb04a0c
JY		 388
389#ifdef CONFIG_PCIE_PTM
390 unsigned int ptm_root:1;
391 unsigned int ptm_enabled:1;
8b2ec318 392 u8 ptm_granularity;
9bb04a0c 393#endif
ded86d8d 394#ifdef CONFIG_PCI_MSI
1c51b50c 395 const struct attribute_group **msi_irq_groups;
ded86d8d 396#endif
94e61088 397 struct pci_vpd *vpd;
466b3ddf 398#ifdef CONFIG_PCI_ATS
dd7cc44d
YZ		 399 union {
400 struct pci_sriov *sriov; /* SR-IOV capability related */
401 struct pci_dev *physfn; /* the PF this VF is associated with */
402 };
67930995
BH		 403 u16 ats_cap; /* ATS Capability offset */
404 u8 ats_stu; /* ATS Smallest Translation Unit */
d544d75a 405 atomic_t ats_ref_cnt; /* number of VFs with ATS enabled */
d1b054da 406#endif
dbd3fc33 407 phys_addr_t rom; /* Physical address of ROM if it's not from the BAR */
84c1b80e 408 size_t romlen; /* Length of ROM if it's not from the BAR */
782a985d 409 char *driver_override; /* Driver name to force a match */
89ee9f76
KB		 410
411 unsigned long priv_flags; /* Private flags for the pci driver */
1da177e4
LT		 412};
413
dda56549
Y		 414static inline struct pci_dev *pci_physfn(struct pci_dev *dev)
415{
416#ifdef CONFIG_PCI_IOV
417 if (dev->is_virtfn)
418 dev = dev->physfn;
419#endif
dda56549
Y		 420 return dev;
421}
422
3c6e6ae7 423struct pci_dev *pci_alloc_dev(struct pci_bus *bus);
65891215 424
1da177e4
LT		 425#define to_pci_dev(n) container_of(n, struct pci_dev, dev)
426#define for_each_pci_dev(d) while ((d = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, d)) != NULL)
427
a7369f1f
LV		 428static inline int pci_channel_offline(struct pci_dev *pdev)
429{
430 return (pdev->error_state != pci_channel_io_normal);
431}
432
5a21d70d 433struct pci_host_bridge {
7b543663 434 struct device dev;
5a21d70d 435 struct pci_bus *bus; /* root bus */
37d6a0a6
AB		 436 struct pci_ops *ops;
437 void *sysdata;
438 int busnr;
14d76b68 439 struct list_head windows; /* resource_entry */
4fa2649a
YL		 440 void (*release_fn)(struct pci_host_bridge *);
441 void *release_data;
37d6a0a6 442 struct msi_controller *msi;
e33caa82 443 unsigned int ignore_reset_delay:1; /* for entire hierarchy */
7c7a0e94
GP		 444 /* Resource alignment requirements */
445 resource_size_t (*align_resource)(struct pci_dev *dev,
446 const struct resource *res,
447 resource_size_t start,
448 resource_size_t size,
449 resource_size_t align);
59094065 450 unsigned long private[0] ____cacheline_aligned;
5a21d70d 451};
41017f0c 452
7b543663 453#define to_pci_host_bridge(n) container_of(n, struct pci_host_bridge, dev)
7c7a0e94 454
59094065
TR		 455static inline void *pci_host_bridge_priv(struct pci_host_bridge *bridge)
456{
457 return (void *)bridge->private;
458}
459
460static inline struct pci_host_bridge *pci_host_bridge_from_priv(void *priv)
461{
462 return container_of(priv, struct pci_host_bridge, private);
463}
464
a52d1443
TR		 465struct pci_host_bridge *pci_alloc_host_bridge(size_t priv);
466int pci_register_host_bridge(struct pci_host_bridge *bridge);
7c7a0e94
GP		 467struct pci_host_bridge *pci_find_host_bridge(struct pci_bus *bus);
468
4fa2649a
YL		 469void pci_set_host_bridge_release(struct pci_host_bridge *bridge,
470 void (*release_fn)(struct pci_host_bridge *),
471 void *release_data);
7b543663 472
6c0cc950
RW		 473int pcibios_root_bridge_prepare(struct pci_host_bridge *bridge);
474
2fe2abf8
BH		 475/*
476 * The first PCI_BRIDGE_RESOURCE_NUM PCI bus resources (those that correspond
477 * to P2P or CardBus bridge windows) go in a table. Additional ones (for
478 * buses below host bridges or subtractive decode bridges) go in the list.
479 * Use pci_bus_for_each_resource() to iterate through all the resources.
480 */
481
482/*
483 * PCI_SUBTRACTIVE_DECODE means the bridge forwards the window implicitly
484 * and there's no way to program the bridge with the details of the window.
485 * This does not apply to ACPI _CRS windows, even with the _DEC subtractive-
486 * decode bit set, because they are explicit and can be programmed with _SRS.
487 */
488#define PCI_SUBTRACTIVE_DECODE 0x1
489
490struct pci_bus_resource {
491 struct list_head list;
492 struct resource *res;
493 unsigned int flags;
494};
4352dfd5
GKH		 495
496#define PCI_REGION_FLAG_MASK 0x0fU /* These bits of resource flags tell us the PCI region flags */
1da177e4
LT		 497
498struct pci_bus {
499 struct list_head node; /* node in list of buses */
500 struct pci_bus *parent; /* parent bus this bridge is on */
501 struct list_head children; /* list of child buses */
502 struct list_head devices; /* list of devices on this bus */
503 struct pci_dev *self; /* bridge device as seen by parent */
67546762
YW		 504 struct list_head slots; /* list of slots on this bus;
505 protected by pci_slot_mutex */
2fe2abf8
BH		 506 struct resource *resource[PCI_BRIDGE_RESOURCE_NUM];
507 struct list_head resources; /* address space routed to this bus */
92f02430 508 struct resource busn_res; /* bus numbers routed to this bus */
1da177e4
LT		 509
510 struct pci_ops *ops; /* configuration access functions */
c2791b80 511 struct msi_controller *msi; /* MSI controller */
1da177e4
LT		 512 void *sysdata; /* hook for sys-specific extension */
513 struct proc_dir_entry *procdir; /* directory entry in /proc/bus/pci */
514
515 unsigned char number; /* bus number */
516 unsigned char primary; /* number of primary bridge */
3749c51a
MW		 517 unsigned char max_bus_speed; /* enum pci_bus_speed */
518 unsigned char cur_bus_speed; /* enum pci_bus_speed */
670ba0c8
CM		 519#ifdef CONFIG_PCI_DOMAINS_GENERIC
520 int domain_nr;
521#endif
1da177e4
LT		 522
523 char name[48];
524
525 unsigned short bridge_ctl; /* manage NO_ISA/FBB/et al behaviors */
f7625980 526 pci_bus_flags_t bus_flags; /* inherited by child buses */
1da177e4 527 struct device *bridge;
fd7d1ced 528 struct device dev;
1da177e4
LT		 529 struct bin_attribute *legacy_io; /* legacy I/O for this bus */
530 struct bin_attribute *legacy_mem; /* legacy mem */
cc74d96f 531 unsigned int is_added:1;
1da177e4
LT		 532};
533
fd7d1ced 534#define to_pci_bus(n) container_of(n, struct pci_bus, dev)
1da177e4 535
79af72d7 536/*
f7625980 537 * Returns true if the PCI bus is root (behind host-PCI bridge),
79af72d7 538 * false otherwise
77a0dfcd
BH		 539 *
540 * Some code assumes that "bus->self == NULL" means that bus is a root bus.
541 * This is incorrect because "virtual" buses added for SR-IOV (via
542 * virtfn_add_bus()) have "bus->self == NULL" but are not root buses.
79af72d7
KK		 543 */
544static inline bool pci_is_root_bus(struct pci_bus *pbus)
545{
546 return !(pbus->parent);
547}
548
1c86438c
YW		 549/**
550 * pci_is_bridge - check if the PCI device is a bridge
551 * @dev: PCI device
552 *
553 * Return true if the PCI device is bridge whether it has subordinate
554 * or not.
555 */
556static inline bool pci_is_bridge(struct pci_dev *dev)
557{
558 return dev->hdr_type == PCI_HEADER_TYPE_BRIDGE ||
559 dev->hdr_type == PCI_HEADER_TYPE_CARDBUS;
560}
561
c6bde215
BH		 562static inline struct pci_dev *pci_upstream_bridge(struct pci_dev *dev)
563{
564 dev = pci_physfn(dev);
565 if (pci_is_root_bus(dev->bus))
566 return NULL;
567
568 return dev->bus->self;
569}
570
6675a601
MK		 571struct device *pci_get_host_bridge_device(struct pci_dev *dev);
572void pci_put_host_bridge_device(struct device *dev);
573
16cf0ebc
RW		 574#ifdef CONFIG_PCI_MSI
575static inline bool pci_dev_msi_enabled(struct pci_dev *pci_dev)
576{
577 return pci_dev->msi_enabled || pci_dev->msix_enabled;
578}
579#else
580static inline bool pci_dev_msi_enabled(struct pci_dev *pci_dev) { return false; }
581#endif
582
1da177e4
LT		 583/*
584 * Error values that may be returned by PCI functions.
585 */
586#define PCIBIOS_SUCCESSFUL 0x00
587#define PCIBIOS_FUNC_NOT_SUPPORTED 0x81
588#define PCIBIOS_BAD_VENDOR_ID 0x83
589#define PCIBIOS_DEVICE_NOT_FOUND 0x86
590#define PCIBIOS_BAD_REGISTER_NUMBER 0x87
591#define PCIBIOS_SET_FAILED 0x88
592#define PCIBIOS_BUFFER_TOO_SMALL 0x89
593
a6961651 594/*
f7625980 595 * Translate above to generic errno for passing back through non-PCI code.
a6961651
AW		 596 */
597static inline int pcibios_err_to_errno(int err)
598{
599 if (err <= PCIBIOS_SUCCESSFUL)
600 return err; /* Assume already errno */
601
602 switch (err) {
603 case PCIBIOS_FUNC_NOT_SUPPORTED:
604 return -ENOENT;
605 case PCIBIOS_BAD_VENDOR_ID:
d97ffe23 606 return -ENOTTY;
a6961651
AW		 607 case PCIBIOS_DEVICE_NOT_FOUND:
608 return -ENODEV;
609 case PCIBIOS_BAD_REGISTER_NUMBER:
610 return -EFAULT;
611 case PCIBIOS_SET_FAILED:
612 return -EIO;
613 case PCIBIOS_BUFFER_TOO_SMALL:
614 return -ENOSPC;
615 }
616
d97ffe23 617 return -ERANGE;
a6961651
AW		 618}
619
1da177e4
LT		 620/* Low-level architecture-dependent routines */
621
622struct pci_ops {
057bd2e0
TR		 623 int (*add_bus)(struct pci_bus *bus);
624 void (*remove_bus)(struct pci_bus *bus);
1f94a94f 625 void __iomem *(*map_bus)(struct pci_bus *bus, unsigned int devfn, int where);
1da177e4
LT		 626 int (*read)(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 *val);
627 int (*write)(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 val);
628};
629
b6ce068a
MW		 630/*
631 * ACPI needs to be able to access PCI config space before we've done a
632 * PCI bus scan and created pci_bus structures.
633 */
f39d5b72
BH		 634int raw_pci_read(unsigned int domain, unsigned int bus, unsigned int devfn,
635 int reg, int len, u32 *val);
636int raw_pci_write(unsigned int domain, unsigned int bus, unsigned int devfn,
637 int reg, int len, u32 val);
1da177e4 638
3a9ad0b4
YL		 639#ifdef CONFIG_PCI_BUS_ADDR_T_64BIT
640typedef u64 pci_bus_addr_t;
641#else
642typedef u32 pci_bus_addr_t;
643#endif
644
1da177e4 645struct pci_bus_region {
3a9ad0b4
YL		 646 pci_bus_addr_t start;
647 pci_bus_addr_t end;
1da177e4
LT		 648};
649
650struct pci_dynids {
651 spinlock_t lock; /* protects list, index */
652 struct list_head list; /* for IDs added at runtime */
1da177e4
LT		 653};
654
f7625980
BH		 655
656/*
657 * PCI Error Recovery System (PCI-ERS). If a PCI device driver provides
658 * a set of callbacks in struct pci_error_handlers, that device driver
659 * will be notified of PCI bus errors, and will be driven to recovery
660 * when an error occurs.
392a1ce7
LV		 661 */
662
663typedef unsigned int __bitwise pci_ers_result_t;
664
665enum pci_ers_result {
666 /* no result/none/not supported in device driver */
667 PCI_ERS_RESULT_NONE = (__force pci_ers_result_t) 1,
668
669 /* Device driver can recover without slot reset */
670 PCI_ERS_RESULT_CAN_RECOVER = (__force pci_ers_result_t) 2,
671
672 /* Device driver wants slot to be reset. */
673 PCI_ERS_RESULT_NEED_RESET = (__force pci_ers_result_t) 3,
674
675 /* Device has completely failed, is unrecoverable */
676 PCI_ERS_RESULT_DISCONNECT = (__force pci_ers_result_t) 4,
677
678 /* Device driver is fully recovered and operational */
679 PCI_ERS_RESULT_RECOVERED = (__force pci_ers_result_t) 5,
918b4053
VMP		 680
681 /* No AER capabilities registered for the driver */
682 PCI_ERS_RESULT_NO_AER_DRIVER = (__force pci_ers_result_t) 6,
392a1ce7
LV		 683};
684
685/* PCI bus error event callbacks */
05cca6e5 686struct pci_error_handlers {
392a1ce7
LV		 687 /* PCI bus error detected on this device */
688 pci_ers_result_t (*error_detected)(struct pci_dev *dev,
05cca6e5 689 enum pci_channel_state error);
392a1ce7
LV		 690
691 /* MMIO has been re-enabled, but not DMA */
692 pci_ers_result_t (*mmio_enabled)(struct pci_dev *dev);
693
392a1ce7
LV		 694 /* PCI slot has been reset */
695 pci_ers_result_t (*slot_reset)(struct pci_dev *dev);
696
3ebe7f9f
KB		 697 /* PCI function reset prepare or completed */
698 void (*reset_notify)(struct pci_dev *dev, bool prepare);
699
392a1ce7
LV		 700 /* Device driver may resume normal operations */
701 void (*resume)(struct pci_dev *dev);
702};
703
392a1ce7 704
1da177e4
LT		 705struct module;
706struct pci_driver {
707 struct list_head node;
42b21932 708 const char *name;
1da177e4
LT		 709 const struct pci_device_id *id_table; /* must be non-NULL for probe to be called */
710 int (*probe) (struct pci_dev *dev, const struct pci_device_id *id); /* New device inserted */
711 void (*remove) (struct pci_dev *dev); /* Device removed (NULL if not a hot-plug capable driver) */
712 int (*suspend) (struct pci_dev *dev, pm_message_t state); /* Device suspended */
cbd69dbb
LT		 713 int (*suspend_late) (struct pci_dev *dev, pm_message_t state);
714 int (*resume_early) (struct pci_dev *dev);
1da177e4 715 int (*resume) (struct pci_dev *dev); /* Device woken up */
c8958177 716 void (*shutdown) (struct pci_dev *dev);
1789382a 717 int (*sriov_configure) (struct pci_dev *dev, int num_vfs); /* PF pdev */
49453028 718 const struct pci_error_handlers *err_handler;
1da177e4
LT		 719 struct device_driver driver;
720 struct pci_dynids dynids;
721};
722
05cca6e5 723#define to_pci_driver(drv) container_of(drv, struct pci_driver, driver)
1da177e4
LT		 724
725/**
726 * PCI_DEVICE - macro used to describe a specific pci device
727 * @vend: the 16 bit PCI Vendor ID
728 * @dev: the 16 bit PCI Device ID
729 *
730 * This macro is used to create a struct pci_device_id that matches a
731 * specific device. The subvendor and subdevice fields will be set to
732 * PCI_ANY_ID.
733 */
734#define PCI_DEVICE(vend,dev) \
735 .vendor = (vend), .device = (dev), \
736 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID
737
3d567e0e
NNS		 738/**
739 * PCI_DEVICE_SUB - macro used to describe a specific pci device with subsystem
740 * @vend: the 16 bit PCI Vendor ID
741 * @dev: the 16 bit PCI Device ID
742 * @subvend: the 16 bit PCI Subvendor ID
743 * @subdev: the 16 bit PCI Subdevice ID
744 *
745 * This macro is used to create a struct pci_device_id that matches a
746 * specific device with subsystem information.
747 */
748#define PCI_DEVICE_SUB(vend, dev, subvend, subdev) \
749 .vendor = (vend), .device = (dev), \
750 .subvendor = (subvend), .subdevice = (subdev)
751
1da177e4
LT		 752/**
753 * PCI_DEVICE_CLASS - macro used to describe a specific pci device class
754 * @dev_class: the class, subclass, prog-if triple for this device
755 * @dev_class_mask: the class mask for this device
756 *
757 * This macro is used to create a struct pci_device_id that matches a
4352dfd5 758 * specific PCI class. The vendor, device, subvendor, and subdevice
1da177e4
LT		 759 * fields will be set to PCI_ANY_ID.
760 */
761#define PCI_DEVICE_CLASS(dev_class,dev_class_mask) \
762 .class = (dev_class), .class_mask = (dev_class_mask), \
763 .vendor = PCI_ANY_ID, .device = PCI_ANY_ID, \
764 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID
765
1597cacb
AC		 766/**
767 * PCI_VDEVICE - macro used to describe a specific pci device in short form
c1309040
MR		 768 * @vend: the vendor name
769 * @dev: the 16 bit PCI Device ID
1597cacb
AC		 770 *
771 * This macro is used to create a struct pci_device_id that matches a
772 * specific PCI device. The subvendor, and subdevice fields will be set
773 * to PCI_ANY_ID. The macro allows the next field to follow as the device
774 * private data.
775 */
776
c1309040
MR		 777#define PCI_VDEVICE(vend, dev) \
778 .vendor = PCI_VENDOR_ID_##vend, .device = (dev), \
779 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID, 0, 0
1597cacb 780
5bbe029f
BH		 781enum {
782 PCI_REASSIGN_ALL_RSRC = 0x00000001, /* ignore firmware setup */
783 PCI_REASSIGN_ALL_BUS = 0x00000002, /* reassign all bus numbers */
784 PCI_PROBE_ONLY = 0x00000004, /* use existing setup */
785 PCI_CAN_SKIP_ISA_ALIGN = 0x00000008, /* don't do ISA alignment */
786 PCI_ENABLE_PROC_DOMAINS = 0x00000010, /* enable domains in /proc */
787 PCI_COMPAT_DOMAIN_0 = 0x00000020, /* ... except domain 0 */
788 PCI_SCAN_ALL_PCIE_DEVS = 0x00000040, /* scan all, not just dev 0 */
789};
790
1da177e4
LT		 791/* these external functions are only available when PCI support is enabled */
792#ifdef CONFIG_PCI
793
5bbe029f
BH		 794extern unsigned int pci_flags;
795
796static inline void pci_set_flags(int flags) { pci_flags = flags; }
797static inline void pci_add_flags(int flags) { pci_flags |= flags; }
798static inline void pci_clear_flags(int flags) { pci_flags &= ~flags; }
799static inline int pci_has_flag(int flag) { return pci_flags & flag; }
800
a58674ff 801void pcie_bus_configure_settings(struct pci_bus *bus);
b03e7495
JM		 802
803enum pcie_bus_config_types {
27d868b5
KB		 804 PCIE_BUS_TUNE_OFF, /* don't touch MPS at all */
805 PCIE_BUS_DEFAULT, /* ensure MPS matches upstream bridge */
806 PCIE_BUS_SAFE, /* use largest MPS boot-time devices support */
807 PCIE_BUS_PERFORMANCE, /* use MPS and MRRS for best performance */
808 PCIE_BUS_PEER2PEER, /* set MPS = 128 for all devices */
b03e7495
JM		 809};
810
811extern enum pcie_bus_config_types pcie_bus_config;
812
1da177e4
LT		 813extern struct bus_type pci_bus_type;
814
f7625980
BH		 815/* Do NOT directly access these two variables, unless you are arch-specific PCI
816 * code, or PCI core code. */
1da177e4 817extern struct list_head pci_root_buses; /* list of all known PCI buses */
f7625980 818/* Some device drivers need know if PCI is initiated */
f39d5b72 819int no_pci_devices(void);
1da177e4 820
3c449ed0 821void pcibios_resource_survey_bus(struct pci_bus *bus);
7b77061f 822void pcibios_bus_add_device(struct pci_dev *pdev);
10a95747
JL		 823void pcibios_add_bus(struct pci_bus *bus);
824void pcibios_remove_bus(struct pci_bus *bus);
1da177e4 825void pcibios_fixup_bus(struct pci_bus *);
4a7fb636 826int __must_check pcibios_enable_device(struct pci_dev *, int mask);
f7625980 827/* Architecture-specific versions may override this (weak) */
05cca6e5 828char *pcibios_setup(char *str);
1da177e4
LT		 829
830/* Used only when drivers/pci/setup.c is used */
3b7a17fc 831resource_size_t pcibios_align_resource(void *, const struct resource *,
b26b2d49 832 resource_size_t,
e31dd6e4 833 resource_size_t);
1da177e4
LT		 834void pcibios_update_irq(struct pci_dev *, int irq);
835
2d1c8618
BH		 836/* Weak but can be overriden by arch */
837void pci_fixup_cardbus(struct pci_bus *);
838
1da177e4
LT		 839/* Generic PCI functions used internally */
840
fc279850 841void pcibios_resource_to_bus(struct pci_bus *bus, struct pci_bus_region *region,
36a66cd6 842 struct resource *res);
fc279850 843void pcibios_bus_to_resource(struct pci_bus *bus, struct resource *res,
36a66cd6 844 struct pci_bus_region *region);
d1fd4fb6 845void pcibios_scan_specific_bus(int busn);
f39d5b72 846struct pci_bus *pci_find_bus(int domain, int busnr);
c48f1670 847void pci_bus_add_devices(const struct pci_bus *bus);
de4b2f76 848struct pci_bus *pci_scan_bus(int bus, struct pci_ops *ops, void *sysdata);
166c6370
BH		 849struct pci_bus *pci_create_root_bus(struct device *parent, int bus,
850 struct pci_ops *ops, void *sysdata,
851 struct list_head *resources);
98a35831
YL		 852int pci_bus_insert_busn_res(struct pci_bus *b, int bus, int busmax);
853int pci_bus_update_busn_res_end(struct pci_bus *b, int busmax);
854void pci_bus_release_busn_res(struct pci_bus *b);
d2a7926d
LP		 855struct pci_bus *pci_scan_root_bus_msi(struct device *parent, int bus,
856 struct pci_ops *ops, void *sysdata,
857 struct list_head *resources,
858 struct msi_controller *msi);
15856ad5 859struct pci_bus *pci_scan_root_bus(struct device *parent, int bus,
a2ebb827
BH		 860 struct pci_ops *ops, void *sysdata,
861 struct list_head *resources);
05cca6e5
GKH		 862struct pci_bus *pci_add_new_bus(struct pci_bus *parent, struct pci_dev *dev,
863 int busnr);
3749c51a 864void pcie_update_link_speed(struct pci_bus *bus, u16 link_status);
f46753c5 865struct pci_slot *pci_create_slot(struct pci_bus *parent, int slot_nr,
828f3768
AC		 866 const char *name,
867 struct hotplug_slot *hotplug);
f46753c5 868void pci_destroy_slot(struct pci_slot *slot);
017ffe64
YW		 869#ifdef CONFIG_SYSFS
870void pci_dev_assign_slot(struct pci_dev *dev);
871#else
872static inline void pci_dev_assign_slot(struct pci_dev *dev) { }
873#endif
1da177e4 874int pci_scan_slot(struct pci_bus *bus, int devfn);
05cca6e5 875struct pci_dev *pci_scan_single_device(struct pci_bus *bus, int devfn);
cdb9b9f7 876void pci_device_add(struct pci_dev *dev, struct pci_bus *bus);
1da177e4 877unsigned int pci_scan_child_bus(struct pci_bus *bus);
c893d133 878void pci_bus_add_device(struct pci_dev *dev);
1da177e4 879void pci_read_bridge_bases(struct pci_bus *child);
05cca6e5
GKH		 880struct resource *pci_find_parent_resource(const struct pci_dev *dev,
881 struct resource *res);
c56d4450 882struct pci_dev *pci_find_pcie_root_port(struct pci_dev *dev);
3df425f3 883u8 pci_swizzle_interrupt_pin(const struct pci_dev *dev, u8 pin);
1da177e4 884int pci_get_interrupt_pin(struct pci_dev *dev, struct pci_dev **bridge);
68feac87 885u8 pci_common_swizzle(struct pci_dev *dev, u8 *pinp);
f39d5b72
BH		 886struct pci_dev *pci_dev_get(struct pci_dev *dev);
887void pci_dev_put(struct pci_dev *dev);
888void pci_remove_bus(struct pci_bus *b);
889void pci_stop_and_remove_bus_device(struct pci_dev *dev);
9d16947b 890void pci_stop_and_remove_bus_device_locked(struct pci_dev *dev);
cdfcc572
YL		 891void pci_stop_root_bus(struct pci_bus *bus);
892void pci_remove_root_bus(struct pci_bus *bus);
b3743fa4 893void pci_setup_cardbus(struct pci_bus *bus);
d366d28c 894void pcibios_setup_bridge(struct pci_bus *bus, unsigned long type);
f39d5b72 895void pci_sort_breadthfirst(void);
fb8a0d9d
WM		 896#define dev_is_pci(d) ((d)->bus == &pci_bus_type)
897#define dev_is_pf(d) ((dev_is_pci(d) ? to_pci_dev(d)->is_physfn : false))
1da177e4
LT		 898
899/* Generic PCI functions exported to card drivers */
900
388c8c16
JB		 901enum pci_lost_interrupt_reason {
902 PCI_LOST_IRQ_NO_INFORMATION = 0,
903 PCI_LOST_IRQ_DISABLE_MSI,
904 PCI_LOST_IRQ_DISABLE_MSIX,
905 PCI_LOST_IRQ_DISABLE_ACPI,
906};
907enum pci_lost_interrupt_reason pci_lost_interrupt(struct pci_dev *dev);
05cca6e5
GKH		 908int pci_find_capability(struct pci_dev *dev, int cap);
909int pci_find_next_capability(struct pci_dev *dev, u8 pos, int cap);
910int pci_find_ext_capability(struct pci_dev *dev, int cap);
44a9a36f 911int pci_find_next_ext_capability(struct pci_dev *dev, int pos, int cap);
05cca6e5
GKH		 912int pci_find_ht_capability(struct pci_dev *dev, int ht_cap);
913int pci_find_next_ht_capability(struct pci_dev *dev, int pos, int ht_cap);
29f3eb64 914struct pci_bus *pci_find_next_bus(const struct pci_bus *from);
1da177e4 915
d42552c3
AM		 916struct pci_dev *pci_get_device(unsigned int vendor, unsigned int device,
917 struct pci_dev *from);
05cca6e5 918struct pci_dev *pci_get_subsys(unsigned int vendor, unsigned int device,
1da177e4 919 unsigned int ss_vendor, unsigned int ss_device,
b08508c4 920 struct pci_dev *from);
05cca6e5 921struct pci_dev *pci_get_slot(struct pci_bus *bus, unsigned int devfn);
3c299dc2
AP		 922struct pci_dev *pci_get_domain_bus_and_slot(int domain, unsigned int bus,
923 unsigned int devfn);
924static inline struct pci_dev *pci_get_bus_and_slot(unsigned int bus,
925 unsigned int devfn)
926{
927 return pci_get_domain_bus_and_slot(0, bus, devfn);
928}
05cca6e5 929struct pci_dev *pci_get_class(unsigned int class, struct pci_dev *from);
1da177e4
LT		 930int pci_dev_present(const struct pci_device_id *ids);
931
05cca6e5
GKH		 932int pci_bus_read_config_byte(struct pci_bus *bus, unsigned int devfn,
933 int where, u8 *val);
934int pci_bus_read_config_word(struct pci_bus *bus, unsigned int devfn,
935 int where, u16 *val);
936int pci_bus_read_config_dword(struct pci_bus *bus, unsigned int devfn,
937 int where, u32 *val);
938int pci_bus_write_config_byte(struct pci_bus *bus, unsigned int devfn,
939 int where, u8 val);
940int pci_bus_write_config_word(struct pci_bus *bus, unsigned int devfn,
941 int where, u16 val);
942int pci_bus_write_config_dword(struct pci_bus *bus, unsigned int devfn,
943 int where, u32 val);
1f94a94f
RH		 944
945int pci_generic_config_read(struct pci_bus *bus, unsigned int devfn,
946 int where, int size, u32 *val);
947int pci_generic_config_write(struct pci_bus *bus, unsigned int devfn,
948 int where, int size, u32 val);
949int pci_generic_config_read32(struct pci_bus *bus, unsigned int devfn,
950 int where, int size, u32 *val);
951int pci_generic_config_write32(struct pci_bus *bus, unsigned int devfn,
952 int where, int size, u32 val);
953
a72b46c3 954struct pci_ops *pci_bus_set_ops(struct pci_bus *bus, struct pci_ops *ops);
1da177e4 955
d3881e50
KB		 956int pci_read_config_byte(const struct pci_dev *dev, int where, u8 *val);
957int pci_read_config_word(const struct pci_dev *dev, int where, u16 *val);
958int pci_read_config_dword(const struct pci_dev *dev, int where, u32 *val);
959int pci_write_config_byte(const struct pci_dev *dev, int where, u8 val);
960int pci_write_config_word(const struct pci_dev *dev, int where, u16 val);
961int pci_write_config_dword(const struct pci_dev *dev, int where, u32 val);
1da177e4 962
8c0d3a02
JL		 963int pcie_capability_read_word(struct pci_dev *dev, int pos, u16 *val);
964int pcie_capability_read_dword(struct pci_dev *dev, int pos, u32 *val);
965int pcie_capability_write_word(struct pci_dev *dev, int pos, u16 val);
966int pcie_capability_write_dword(struct pci_dev *dev, int pos, u32 val);
967int pcie_capability_clear_and_set_word(struct pci_dev *dev, int pos,
968 u16 clear, u16 set);
969int pcie_capability_clear_and_set_dword(struct pci_dev *dev, int pos,
970 u32 clear, u32 set);
971
972static inline int pcie_capability_set_word(struct pci_dev *dev, int pos,
973 u16 set)
974{
975 return pcie_capability_clear_and_set_word(dev, pos, 0, set);
976}
977
978static inline int pcie_capability_set_dword(struct pci_dev *dev, int pos,
979 u32 set)
980{
981 return pcie_capability_clear_and_set_dword(dev, pos, 0, set);
982}
983
984static inline int pcie_capability_clear_word(struct pci_dev *dev, int pos,
985 u16 clear)
986{
987 return pcie_capability_clear_and_set_word(dev, pos, clear, 0);
988}
989
990static inline int pcie_capability_clear_dword(struct pci_dev *dev, int pos,
991 u32 clear)
992{
993 return pcie_capability_clear_and_set_dword(dev, pos, clear, 0);
994}
995
c63587d7
AW		 996/* user-space driven config access */
997int pci_user_read_config_byte(struct pci_dev *dev, int where, u8 *val);
998int pci_user_read_config_word(struct pci_dev *dev, int where, u16 *val);
999int pci_user_read_config_dword(struct pci_dev *dev, int where, u32 *val);
1000int pci_user_write_config_byte(struct pci_dev *dev, int where, u8 val);
1001int pci_user_write_config_word(struct pci_dev *dev, int where, u16 val);
1002int pci_user_write_config_dword(struct pci_dev *dev, int where, u32 val);
1003
4a7fb636 1004int __must_check pci_enable_device(struct pci_dev *dev);
b718989d
BH		 1005int __must_check pci_enable_device_io(struct pci_dev *dev);
1006int __must_check pci_enable_device_mem(struct pci_dev *dev);
0b62e13b 1007int __must_check pci_reenable_device(struct pci_dev *);
9ac7849e
TH		 1008int __must_check pcim_enable_device(struct pci_dev *pdev);
1009void pcim_pin_device(struct pci_dev *pdev);
1010
296ccb08
YS		 1011static inline int pci_is_enabled(struct pci_dev *pdev)
1012{
1013 return (atomic_read(&pdev->enable_cnt) > 0);
1014}
1015
9ac7849e
TH		 1016static inline int pci_is_managed(struct pci_dev *pdev)
1017{
1018 return pdev->is_managed;
1019}
1020
1da177e4 1021void pci_disable_device(struct pci_dev *dev);
96c55900
MS		 1022
1023extern unsigned int pcibios_max_latency;
1da177e4 1024void pci_set_master(struct pci_dev *dev);
6a479079 1025void pci_clear_master(struct pci_dev *dev);
96c55900 1026
f7bdd12d 1027int pci_set_pcie_reset_state(struct pci_dev *dev, enum pcie_reset_state state);
15ea76d4 1028int pci_set_cacheline_size(struct pci_dev *dev);
1da177e4 1029#define HAVE_PCI_SET_MWI
4a7fb636 1030int __must_check pci_set_mwi(struct pci_dev *dev);
694625c0 1031int pci_try_set_mwi(struct pci_dev *dev);
1da177e4 1032void pci_clear_mwi(struct pci_dev *dev);
a04ce0ff 1033void pci_intx(struct pci_dev *dev, int enable);
a2e27787
JK		 1034bool pci_intx_mask_supported(struct pci_dev *dev);
1035bool pci_check_and_mask_intx(struct pci_dev *dev);
1036bool pci_check_and_unmask_intx(struct pci_dev *dev);
157e876f 1037int pci_wait_for_pending(struct pci_dev *dev, int pos, u16 mask);
3775a209 1038int pci_wait_for_pending_transaction(struct pci_dev *dev);
d556ad4b
PO		 1039int pcix_get_max_mmrbc(struct pci_dev *dev);
1040int pcix_get_mmrbc(struct pci_dev *dev);
1041int pcix_set_mmrbc(struct pci_dev *dev, int mmrbc);
2637e5b5 1042int pcie_get_readrq(struct pci_dev *dev);
d556ad4b 1043int pcie_set_readrq(struct pci_dev *dev, int rq);
b03e7495
JM		 1044int pcie_get_mps(struct pci_dev *dev);
1045int pcie_set_mps(struct pci_dev *dev, int mps);
81377c8d
JK		 1046int pcie_get_minimum_link(struct pci_dev *dev, enum pci_bus_speed *speed,
1047 enum pcie_link_width *width);
a60a2b73 1048void pcie_flr(struct pci_dev *dev);
8c1c699f 1049int __pci_reset_function(struct pci_dev *dev);
a96d627a 1050int __pci_reset_function_locked(struct pci_dev *dev);
8dd7f803 1051int pci_reset_function(struct pci_dev *dev);
61cf16d8 1052int pci_try_reset_function(struct pci_dev *dev);
9a3d2b9b 1053int pci_probe_reset_slot(struct pci_slot *slot);
090a3c53 1054int pci_reset_slot(struct pci_slot *slot);
61cf16d8 1055int pci_try_reset_slot(struct pci_slot *slot);
9a3d2b9b 1056int pci_probe_reset_bus(struct pci_bus *bus);
090a3c53 1057int pci_reset_bus(struct pci_bus *bus);
61cf16d8 1058int pci_try_reset_bus(struct pci_bus *bus);
9e33002f
GS		 1059void pci_reset_secondary_bus(struct pci_dev *dev);
1060void pcibios_reset_secondary_bus(struct pci_dev *dev);
64e8674f 1061void pci_reset_bridge_secondary_bus(struct pci_dev *dev);
14add80b 1062void pci_update_resource(struct pci_dev *dev, int resno);
4a7fb636 1063int __must_check pci_assign_resource(struct pci_dev *dev, int i);
2bbc6942 1064int __must_check pci_reassign_resource(struct pci_dev *dev, int i, resource_size_t add_size, resource_size_t align);
c87deff7 1065int pci_select_bars(struct pci_dev *dev, unsigned long flags);
8496e85c 1066bool pci_device_is_present(struct pci_dev *pdev);
08249651 1067void pci_ignore_hotplug(struct pci_dev *dev);
1da177e4 1068
704e8953
CH		 1069int __printf(6, 7) pci_request_irq(struct pci_dev *dev, unsigned int nr,
1070 irq_handler_t handler, irq_handler_t thread_fn, void *dev_id,
1071 const char *fmt, ...);
1072void pci_free_irq(struct pci_dev *dev, unsigned int nr, void *dev_id);
1073
1da177e4 1074/* ROM control related routines */
e416de5e
AC		 1075int pci_enable_rom(struct pci_dev *pdev);
1076void pci_disable_rom(struct pci_dev *pdev);
144a50ea 1077void __iomem __must_check *pci_map_rom(struct pci_dev *pdev, size_t *size);
1da177e4 1078void pci_unmap_rom(struct pci_dev *pdev, void __iomem *rom);
97c44836 1079size_t pci_get_rom_size(struct pci_dev *pdev, void __iomem *rom, size_t size);
fffe01f7 1080void __iomem __must_check *pci_platform_rom(struct pci_dev *pdev, size_t *size);
1da177e4
LT		 1081
1082/* Power management related routines */
1083int pci_save_state(struct pci_dev *dev);
1d3c16a8 1084void pci_restore_state(struct pci_dev *dev);
ffbdd3f7 1085struct pci_saved_state *pci_store_saved_state(struct pci_dev *dev);
98d9b271
KRW		 1086int pci_load_saved_state(struct pci_dev *dev,
1087 struct pci_saved_state *state);
ffbdd3f7
AW		 1088int pci_load_and_free_saved_state(struct pci_dev *dev,
1089 struct pci_saved_state **state);
fd0f7f73
AW		 1090struct pci_cap_saved_state *pci_find_saved_cap(struct pci_dev *dev, char cap);
1091struct pci_cap_saved_state *pci_find_saved_ext_cap(struct pci_dev *dev,
1092 u16 cap);
1093int pci_add_cap_save_buffer(struct pci_dev *dev, char cap, unsigned int size);
1094int pci_add_ext_cap_save_buffer(struct pci_dev *dev,
1095 u16 cap, unsigned int size);
0e5dd46b 1096int __pci_complete_power_transition(struct pci_dev *dev, pci_power_t state);
9c8550ee
LT		 1097int pci_set_power_state(struct pci_dev *dev, pci_power_t state);
1098pci_power_t pci_choose_state(struct pci_dev *dev, pm_message_t state);
e5899e1b 1099bool pci_pme_capable(struct pci_dev *dev, pci_power_t state);
5a6c9b60 1100void pci_pme_active(struct pci_dev *dev, bool enable);
6cbf8214
RW		 1101int __pci_enable_wake(struct pci_dev *dev, pci_power_t state,
1102 bool runtime, bool enable);
0235c4fc 1103int pci_wake_from_d3(struct pci_dev *dev, bool enable);
404cc2d8
RW		 1104int pci_prepare_to_sleep(struct pci_dev *dev);
1105int pci_back_from_sleep(struct pci_dev *dev);
b67ea761 1106bool pci_dev_run_wake(struct pci_dev *dev);
bf4d2908 1107bool pci_check_pme_status(struct pci_dev *dev);
bf4d2908 1108void pci_pme_wakeup_bus(struct pci_bus *bus);
9d26d3a8
MW		 1109void pci_d3cold_enable(struct pci_dev *dev);
1110void pci_d3cold_disable(struct pci_dev *dev);
1da177e4 1111
6cbf8214
RW		 1112static inline int pci_enable_wake(struct pci_dev *dev, pci_power_t state,
1113 bool enable)
1114{
1115 return __pci_enable_wake(dev, state, false, enable);
1116}
1da177e4 1117
425c1b22
AW		 1118/* PCI Virtual Channel */
1119int pci_save_vc_state(struct pci_dev *dev);
1120void pci_restore_vc_state(struct pci_dev *dev);
1121void pci_allocate_vc_save_buffers(struct pci_dev *dev);
51c2e0a7 1122
bb209c82
BH		 1123/* For use by arch with custom probe code */
1124void set_pcie_port_type(struct pci_dev *pdev);
1125void set_pcie_hotplug_bridge(struct pci_dev *pdev);
1126
ce5ccdef 1127/* Functions for PCI Hotplug drivers to use */
05cca6e5 1128int pci_bus_find_capability(struct pci_bus *bus, unsigned int devfn, int cap);
2f320521 1129unsigned int pci_rescan_bus_bridge_resize(struct pci_dev *bridge);
3ed4fd96 1130unsigned int pci_rescan_bus(struct pci_bus *bus);
9d16947b
RW		 1131void pci_lock_rescan_remove(void);
1132void pci_unlock_rescan_remove(void);
ce5ccdef 1133
287d19ce
SH		 1134/* Vital product data routines */
1135ssize_t pci_read_vpd(struct pci_dev *dev, loff_t pos, size_t count, void *buf);
1136ssize_t pci_write_vpd(struct pci_dev *dev, loff_t pos, size_t count, const void *buf);
cb92148b 1137int pci_set_vpd_size(struct pci_dev *dev, size_t len);
287d19ce 1138
1da177e4 1139/* Helper functions for low-level code (drivers/pci/setup-[bus,res].c) */
925845bd 1140resource_size_t pcibios_retrieve_fw_addr(struct pci_dev *dev, int idx);
ea741551 1141void pci_bus_assign_resources(const struct pci_bus *bus);
765bf9b7 1142void pci_bus_claim_resources(struct pci_bus *bus);
1da177e4
LT		 1143void pci_bus_size_bridges(struct pci_bus *bus);
1144int pci_claim_resource(struct pci_dev *, int);
8505e729 1145int pci_claim_bridge_resource(struct pci_dev *bridge, int i);
1da177e4 1146void pci_assign_unassigned_resources(void);
6841ec68 1147void pci_assign_unassigned_bridge_resources(struct pci_dev *bridge);
17787940 1148void pci_assign_unassigned_bus_resources(struct pci_bus *bus);
39772038 1149void pci_assign_unassigned_root_bus_resources(struct pci_bus *bus);
1da177e4 1150void pdev_enable_device(struct pci_dev *);
842de40d 1151int pci_enable_resources(struct pci_dev *, int mask);
1da177e4 1152void pci_fixup_irqs(u8 (*)(struct pci_dev *, u8 *),
d5341942 1153 int (*)(const struct pci_dev *, u8, u8));
afd29f90 1154struct resource *pci_find_resource(struct pci_dev *dev, struct resource *res);
1da177e4 1155#define HAVE_PCI_REQ_REGIONS 2
4a7fb636 1156int __must_check pci_request_regions(struct pci_dev *, const char *);
e8de1481 1157int __must_check pci_request_regions_exclusive(struct pci_dev *, const char *);
1da177e4 1158void pci_release_regions(struct pci_dev *);
4a7fb636 1159int __must_check pci_request_region(struct pci_dev *, int, const char *);
e8de1481 1160int __must_check pci_request_region_exclusive(struct pci_dev *, int, const char *);
1da177e4 1161void pci_release_region(struct pci_dev *, int);
c87deff7 1162int pci_request_selected_regions(struct pci_dev *, int, const char *);
e8de1481 1163int pci_request_selected_regions_exclusive(struct pci_dev *, int, const char *);
c87deff7 1164void pci_release_selected_regions(struct pci_dev *, int);
1da177e4
LT		 1165
1166/* drivers/pci/bus.c */
fe830ef6
JL		 1167struct pci_bus *pci_bus_get(struct pci_bus *bus);
1168void pci_bus_put(struct pci_bus *bus);
45ca9e97 1169void pci_add_resource(struct list_head *resources, struct resource *res);
0efd5aab
BH		 1170void pci_add_resource_offset(struct list_head *resources, struct resource *res,
1171 resource_size_t offset);
45ca9e97 1172void pci_free_resource_list(struct list_head *resources);
950334bc
BH		 1173void pci_bus_add_resource(struct pci_bus *bus, struct resource *res,
1174 unsigned int flags);
2fe2abf8
BH		 1175struct resource *pci_bus_resource_n(const struct pci_bus *bus, int n);
1176void pci_bus_remove_resources(struct pci_bus *bus);
950334bc
BH		 1177int devm_request_pci_bus_resources(struct device *dev,
1178 struct list_head *resources);
2fe2abf8 1179
89a74ecc 1180#define pci_bus_for_each_resource(bus, res, i) \
2fe2abf8
BH		 1181 for (i = 0; \
1182 (res = pci_bus_resource_n(bus, i)) || i < PCI_BRIDGE_RESOURCE_NUM; \
1183 i++)
89a74ecc 1184
4a7fb636
AM		 1185int __must_check pci_bus_alloc_resource(struct pci_bus *bus,
1186 struct resource *res, resource_size_t size,
1187 resource_size_t align, resource_size_t min,
664c2848 1188 unsigned long type_mask,
3b7a17fc
DB		 1189 resource_size_t (*alignf)(void *,
1190 const struct resource *,
b26b2d49
DB		 1191 resource_size_t,
1192 resource_size_t),
4a7fb636 1193 void *alignf_data);
1da177e4 1194
8b921acf 1195
c5076cfe
TN		 1196int pci_register_io_range(phys_addr_t addr, resource_size_t size);
1197unsigned long pci_address_to_pio(phys_addr_t addr);
1198phys_addr_t pci_pio_to_address(unsigned long pio);
8b921acf 1199int pci_remap_iospace(const struct resource *res, phys_addr_t phys_addr);
4d3f1384 1200void pci_unmap_iospace(struct resource *res);
490cb6dd
LP		 1201void __iomem *devm_pci_remap_cfgspace(struct device *dev,
1202 resource_size_t offset,
1203 resource_size_t size);
1204void __iomem *devm_pci_remap_cfg_resource(struct device *dev,
1205 struct resource *res);
8b921acf 1206
3a9ad0b4 1207static inline pci_bus_addr_t pci_bus_address(struct pci_dev *pdev, int bar)
06cf56e4
BH		 1208{
1209 struct pci_bus_region region;
1210
1211 pcibios_resource_to_bus(pdev->bus, &region, &pdev->resource[bar]);
1212 return region.start;
1213}
1214
863b18f4 1215/* Proper probing supporting hot-pluggable devices */
725522b5
GKH		 1216int __must_check __pci_register_driver(struct pci_driver *, struct module *,
1217 const char *mod_name);
bba81165
AM		 1218
1219/*
1220 * pci_register_driver must be a macro so that KBUILD_MODNAME can be expanded
1221 */
1222#define pci_register_driver(driver) \
1223 __pci_register_driver(driver, THIS_MODULE, KBUILD_MODNAME)
863b18f4 1224
05cca6e5 1225void pci_unregister_driver(struct pci_driver *dev);
aad4f400
GKH		 1226
1227/**
1228 * module_pci_driver() - Helper macro for registering a PCI driver
1229 * @__pci_driver: pci_driver struct
1230 *
1231 * Helper macro for PCI drivers which do not do anything special in module
1232 * init/exit. This eliminates a lot of boilerplate. Each module may only
1233 * use this macro once, and calling it replaces module_init() and module_exit()
1234 */
1235#define module_pci_driver(__pci_driver) \
1236 module_driver(__pci_driver, pci_register_driver, \
1237 pci_unregister_driver)
1238
b4eb6cdb
PG		 1239/**
1240 * builtin_pci_driver() - Helper macro for registering a PCI driver
1241 * @__pci_driver: pci_driver struct
1242 *
1243 * Helper macro for PCI drivers which do not do anything special in their
1244 * init code. This eliminates a lot of boilerplate. Each driver may only
1245 * use this macro once, and calling it replaces device_initcall(...)
1246 */
1247#define builtin_pci_driver(__pci_driver) \
1248 builtin_driver(__pci_driver, pci_register_driver)
1249
05cca6e5 1250struct pci_driver *pci_dev_driver(const struct pci_dev *dev);
9dba910e
TH		 1251int pci_add_dynid(struct pci_driver *drv,
1252 unsigned int vendor, unsigned int device,
1253 unsigned int subvendor, unsigned int subdevice,
1254 unsigned int class, unsigned int class_mask,
1255 unsigned long driver_data);
05cca6e5
GKH		 1256const struct pci_device_id *pci_match_id(const struct pci_device_id *ids,
1257 struct pci_dev *dev);
1258int pci_scan_bridge(struct pci_bus *bus, struct pci_dev *dev, int max,
1259 int pass);
1da177e4 1260
70298c6e 1261void pci_walk_bus(struct pci_bus *top, int (*cb)(struct pci_dev *, void *),
cecf4864 1262 void *userdata);
ac7dc65a 1263int pci_cfg_space_size(struct pci_dev *dev);
05cca6e5 1264unsigned char pci_bus_max_busnr(struct pci_bus *bus);
e2444273 1265void pci_setup_bridge(struct pci_bus *bus);
ac5ad93e
GS		 1266resource_size_t pcibios_window_alignment(struct pci_bus *bus,
1267 unsigned long type);
978d2d68 1268resource_size_t pcibios_iov_resource_alignment(struct pci_dev *dev, int resno);
cecf4864 1269
3448a19d
DA		 1270#define PCI_VGA_STATE_CHANGE_BRIDGE (1 << 0)
1271#define PCI_VGA_STATE_CHANGE_DECODES (1 << 1)
1272
deb2d2ec 1273int pci_set_vga_state(struct pci_dev *pdev, bool decode,
3448a19d 1274 unsigned int command_bits, u32 flags);
fe537670 1275
4fe0d154
CH		 1276#define PCI_IRQ_LEGACY (1 << 0) /* allow legacy interrupts */
1277#define PCI_IRQ_MSI (1 << 1) /* allow MSI interrupts */
1278#define PCI_IRQ_MSIX (1 << 2) /* allow MSI-X interrupts */
1279#define PCI_IRQ_AFFINITY (1 << 3) /* auto-assign affinity */
1280#define PCI_IRQ_ALL_TYPES \
1281 (PCI_IRQ_LEGACY | PCI_IRQ_MSI | PCI_IRQ_MSIX)
aff17164 1282
1da177e4
LT		 1283/* kmem_cache style wrapper around pci_alloc_consistent() */
1284
f41b1771 1285#include <linux/pci-dma.h>
1da177e4
LT		 1286#include <linux/dmapool.h>
1287
1288#define pci_pool dma_pool
1289#define pci_pool_create(name, pdev, size, align, allocation) \
1290 dma_pool_create(name, &pdev->dev, size, align, allocation)
1291#define pci_pool_destroy(pool) dma_pool_destroy(pool)
1292#define pci_pool_alloc(pool, flags, handle) dma_pool_alloc(pool, flags, handle)
01a7fd33
SS		 1293#define pci_pool_zalloc(pool, flags, handle) \
1294 dma_pool_zalloc(pool, flags, handle)
1da177e4
LT		 1295#define pci_pool_free(pool, vaddr, addr) dma_pool_free(pool, vaddr, addr)
1296
1da177e4 1297struct msix_entry {
16dbef4a 1298 u32 vector; /* kernel uses to write allocated vector */
1da177e4
LT		 1299 u16 entry; /* driver uses to specify entry, OS writes */
1300};
1301
4c859804
BH		 1302#ifdef CONFIG_PCI_MSI
1303int pci_msi_vec_count(struct pci_dev *dev);
f39d5b72 1304void pci_disable_msi(struct pci_dev *dev);
4c859804 1305int pci_msix_vec_count(struct pci_dev *dev);
f39d5b72 1306void pci_disable_msix(struct pci_dev *dev);
f39d5b72
BH		 1307void pci_restore_msi_state(struct pci_dev *dev);
1308int pci_msi_enabled(void);
4fe03955 1309int pci_enable_msi(struct pci_dev *dev);
4c859804
BH		 1310int pci_enable_msix_range(struct pci_dev *dev, struct msix_entry *entries,
1311 int minvec, int maxvec);
f7fc32cb
AG		 1312static inline int pci_enable_msix_exact(struct pci_dev *dev,
1313 struct msix_entry *entries, int nvec)
1314{
1315 int rc = pci_enable_msix_range(dev, entries, nvec, nvec);
1316 if (rc < 0)
1317 return rc;
1318 return 0;
1319}
402723ad
CH		 1320int pci_alloc_irq_vectors_affinity(struct pci_dev *dev, unsigned int min_vecs,
1321 unsigned int max_vecs, unsigned int flags,
1322 const struct irq_affinity *affd);
1323
aff17164
CH		 1324void pci_free_irq_vectors(struct pci_dev *dev);
1325int pci_irq_vector(struct pci_dev *dev, unsigned int nr);
ee8d41e5 1326const struct cpumask *pci_irq_get_affinity(struct pci_dev *pdev, int vec);
27ddb689 1327int pci_irq_get_node(struct pci_dev *pdev, int vec);
aff17164 1328
4c859804 1329#else
2ee546c4 1330static inline int pci_msi_vec_count(struct pci_dev *dev) { return -ENOSYS; }
2ee546c4
BH		 1331static inline void pci_disable_msi(struct pci_dev *dev) { }
1332static inline int pci_msix_vec_count(struct pci_dev *dev) { return -ENOSYS; }
2ee546c4 1333static inline void pci_disable_msix(struct pci_dev *dev) { }
2ee546c4
BH		 1334static inline void pci_restore_msi_state(struct pci_dev *dev) { }
1335static inline int pci_msi_enabled(void) { return 0; }
4fe03955 1336static inline int pci_enable_msi(struct pci_dev *dev)
f7fc32cb 1337{ return -ENOSYS; }
302a2523
AG		 1338static inline int pci_enable_msix_range(struct pci_dev *dev,
1339 struct msix_entry *entries, int minvec, int maxvec)
2ee546c4 1340{ return -ENOSYS; }
f7fc32cb
AG		 1341static inline int pci_enable_msix_exact(struct pci_dev *dev,
1342 struct msix_entry *entries, int nvec)
1343{ return -ENOSYS; }
402723ad
CH		 1344
1345static inline int
1346pci_alloc_irq_vectors_affinity(struct pci_dev *dev, unsigned int min_vecs,
1347 unsigned int max_vecs, unsigned int flags,
1348 const struct irq_affinity *aff_desc)
aff17164 1349{
83b4605b
CH		 1350 if ((flags & PCI_IRQ_LEGACY) && min_vecs == 1 && dev->irq)
1351 return 1;
1352 return -ENOSPC;
aff17164 1353}
402723ad 1354
aff17164
CH		 1355static inline void pci_free_irq_vectors(struct pci_dev *dev)
1356{
1357}
1358
1359static inline int pci_irq_vector(struct pci_dev *dev, unsigned int nr)
1360{
1361 if (WARN_ON_ONCE(nr > 0))
1362 return -EINVAL;
1363 return dev->irq;
1364}
ee8d41e5
TG		 1365static inline const struct cpumask *pci_irq_get_affinity(struct pci_dev *pdev,
1366 int vec)
1367{
1368 return cpu_possible_mask;
1369}
27ddb689
SL		 1370
1371static inline int pci_irq_get_node(struct pci_dev *pdev, int vec)
1372{
1373 return first_online_node;
1374}
1da177e4
LT		 1375#endif
1376
402723ad
CH		 1377static inline int
1378pci_alloc_irq_vectors(struct pci_dev *dev, unsigned int min_vecs,
1379 unsigned int max_vecs, unsigned int flags)
1380{
1381 return pci_alloc_irq_vectors_affinity(dev, min_vecs, max_vecs, flags,
1382 NULL);
1383}
1384
ab0724ff 1385#ifdef CONFIG_PCIEPORTBUS
415e12b2
RW		 1386extern bool pcie_ports_disabled;
1387extern bool pcie_ports_auto;
ab0724ff
MT		 1388#else
1389#define pcie_ports_disabled true
1390#define pcie_ports_auto false
1391#endif
415e12b2 1392
4c859804 1393#ifdef CONFIG_PCIEASPM
f39d5b72 1394bool pcie_aspm_support_enabled(void);
4c859804
BH		 1395#else
1396static inline bool pcie_aspm_support_enabled(void) { return false; }
3e1b1600
AP		 1397#endif
1398
415e12b2
RW		 1399#ifdef CONFIG_PCIEAER
1400void pci_no_aer(void);
1401bool pci_aer_available(void);
66b80809 1402int pci_aer_init(struct pci_dev *dev);
415e12b2
RW		 1403#else
1404static inline void pci_no_aer(void) { }
1405static inline bool pci_aer_available(void) { return false; }
66b80809 1406static inline int pci_aer_init(struct pci_dev *d) { return -ENODEV; }
415e12b2
RW		 1407#endif
1408
4c859804 1409#ifdef CONFIG_PCIE_ECRC
f39d5b72
BH		 1410void pcie_set_ecrc_checking(struct pci_dev *dev);
1411void pcie_ecrc_get_policy(char *str);
4c859804 1412#else
2ee546c4
BH		 1413static inline void pcie_set_ecrc_checking(struct pci_dev *dev) { }
1414static inline void pcie_ecrc_get_policy(char *str) { }
43c16408
AP		 1415#endif
1416
8b955b0d 1417#ifdef CONFIG_HT_IRQ
8b955b0d
EB		 1418/* The functions a driver should call */
1419int ht_create_irq(struct pci_dev *dev, int idx);
1420void ht_destroy_irq(unsigned int irq);
8b955b0d
EB		 1421#endif /* CONFIG_HT_IRQ */
1422
edc90fee
BH		 1423#ifdef CONFIG_PCI_ATS
1424/* Address Translation Service */
1425void pci_ats_init(struct pci_dev *dev);
ff9bee89
BH		 1426int pci_enable_ats(struct pci_dev *dev, int ps);
1427void pci_disable_ats(struct pci_dev *dev);
1428int pci_ats_queue_depth(struct pci_dev *dev);
edc90fee 1429#else
ff9bee89
BH		 1430static inline void pci_ats_init(struct pci_dev *d) { }
1431static inline int pci_enable_ats(struct pci_dev *d, int ps) { return -ENODEV; }
1432static inline void pci_disable_ats(struct pci_dev *d) { }
1433static inline int pci_ats_queue_depth(struct pci_dev *d) { return -ENODEV; }
edc90fee
BH		 1434#endif
1435
eec097d4
BH		 1436#ifdef CONFIG_PCIE_PTM
1437int pci_enable_ptm(struct pci_dev *dev, u8 *granularity);
1438#else
1439static inline int pci_enable_ptm(struct pci_dev *dev, u8 *granularity)
1440{ return -EINVAL; }
1441#endif
1442
f39d5b72
BH		 1443void pci_cfg_access_lock(struct pci_dev *dev);
1444bool pci_cfg_access_trylock(struct pci_dev *dev);
1445void pci_cfg_access_unlock(struct pci_dev *dev);
e04b0ea2 1446
4352dfd5
GKH		 1447/*
1448 * PCI domain support. Sometimes called PCI segment (eg by ACPI),
f7625980 1449 * a PCI domain is defined to be a set of PCI buses which share
4352dfd5
GKH		 1450 * configuration space.
1451 */
32a2eea7
JG		 1452#ifdef CONFIG_PCI_DOMAINS
1453extern int pci_domains_supported;
41e5c0f8 1454int pci_get_new_domain_nr(void);
32a2eea7
JG		 1455#else
1456enum { pci_domains_supported = 0 };
2ee546c4
BH		 1457static inline int pci_domain_nr(struct pci_bus *bus) { return 0; }
1458static inline int pci_proc_domain(struct pci_bus *bus) { return 0; }
41e5c0f8 1459static inline int pci_get_new_domain_nr(void) { return -ENOSYS; }
32a2eea7 1460#endif /* CONFIG_PCI_DOMAINS */
1da177e4 1461
670ba0c8
CM		 1462/*
1463 * Generic implementation for PCI domain support. If your
1464 * architecture does not need custom management of PCI
1465 * domains then this implementation will be used
1466 */
1467#ifdef CONFIG_PCI_DOMAINS_GENERIC
1468static inline int pci_domain_nr(struct pci_bus *bus)
1469{
1470 return bus->domain_nr;
1471}
2ab51dde
TN		 1472#ifdef CONFIG_ACPI
1473int acpi_pci_bus_find_domain_nr(struct pci_bus *bus);
670ba0c8 1474#else
2ab51dde
TN		 1475static inline int acpi_pci_bus_find_domain_nr(struct pci_bus *bus)
1476{ return 0; }
1477#endif
9c7cb891 1478int pci_bus_find_domain_nr(struct pci_bus *bus, struct device *parent);
670ba0c8
CM		 1479#endif
1480
95a8b6ef
MT		 1481/* some architectures require additional setup to direct VGA traffic */
1482typedef int (*arch_set_vga_state_t)(struct pci_dev *pdev, bool decode,
3448a19d 1483 unsigned int command_bits, u32 flags);
f39d5b72 1484void pci_register_set_vga_state(arch_set_vga_state_t func);
95a8b6ef 1485
be9d2e89
JT		 1486static inline int
1487pci_request_io_regions(struct pci_dev *pdev, const char *name)
1488{
1489 return pci_request_selected_regions(pdev,
1490 pci_select_bars(pdev, IORESOURCE_IO), name);
1491}
1492
1493static inline void
1494pci_release_io_regions(struct pci_dev *pdev)
1495{
1496 return pci_release_selected_regions(pdev,
1497 pci_select_bars(pdev, IORESOURCE_IO));
1498}
1499
1500static inline int
1501pci_request_mem_regions(struct pci_dev *pdev, const char *name)
1502{
1503 return pci_request_selected_regions(pdev,
1504 pci_select_bars(pdev, IORESOURCE_MEM), name);
1505}
1506
1507static inline void
1508pci_release_mem_regions(struct pci_dev *pdev)
1509{
1510 return pci_release_selected_regions(pdev,
1511 pci_select_bars(pdev, IORESOURCE_MEM));
1512}
1513
4352dfd5 1514#else /* CONFIG_PCI is not enabled */
1da177e4 1515
5bbe029f
BH		 1516static inline void pci_set_flags(int flags) { }
1517static inline void pci_add_flags(int flags) { }
1518static inline void pci_clear_flags(int flags) { }
1519static inline int pci_has_flag(int flag) { return 0; }
1520
1da177e4
LT		 1521/*
1522 * If the system does not have PCI, clearly these return errors. Define
1523 * these as simple inline functions to avoid hair in drivers.
1524 */
1525
05cca6e5
GKH		 1526#define _PCI_NOP(o, s, t) \
1527 static inline int pci_##o##_config_##s(struct pci_dev *dev, \
1528 int where, t val) \
1da177e4 1529 { return PCIBIOS_FUNC_NOT_SUPPORTED; }
05cca6e5
GKH		 1530
1531#define _PCI_NOP_ALL(o, x) _PCI_NOP(o, byte, u8 x) \
1532 _PCI_NOP(o, word, u16 x) \
1533 _PCI_NOP(o, dword, u32 x)
1da177e4
LT		 1534_PCI_NOP_ALL(read, *)
1535_PCI_NOP_ALL(write,)
1536
d42552c3 1537static inline struct pci_dev *pci_get_device(unsigned int vendor,
05cca6e5
GKH		 1538 unsigned int device,
1539 struct pci_dev *from)
2ee546c4 1540{ return NULL; }
d42552c3 1541
05cca6e5
GKH		 1542static inline struct pci_dev *pci_get_subsys(unsigned int vendor,
1543 unsigned int device,
1544 unsigned int ss_vendor,
1545 unsigned int ss_device,
b08508c4 1546 struct pci_dev *from)
2ee546c4 1547{ return NULL; }
1da177e4 1548
05cca6e5
GKH		 1549static inline struct pci_dev *pci_get_class(unsigned int class,
1550 struct pci_dev *from)
2ee546c4 1551{ return NULL; }
1da177e4
LT		 1552
1553#define pci_dev_present(ids) (0)
ed4aaadb 1554#define no_pci_devices() (1)
1da177e4
LT		 1555#define pci_dev_put(dev) do { } while (0)
1556
2ee546c4
BH		 1557static inline void pci_set_master(struct pci_dev *dev) { }
1558static inline int pci_enable_device(struct pci_dev *dev) { return -EIO; }
1559static inline void pci_disable_device(struct pci_dev *dev) { }
05cca6e5 1560static inline int pci_assign_resource(struct pci_dev *dev, int i)
2ee546c4 1561{ return -EBUSY; }
05cca6e5
GKH		 1562static inline int __pci_register_driver(struct pci_driver *drv,
1563 struct module *owner)
2ee546c4 1564{ return 0; }
05cca6e5 1565static inline int pci_register_driver(struct pci_driver *drv)
2ee546c4
BH		 1566{ return 0; }
1567static inline void pci_unregister_driver(struct pci_driver *drv) { }
05cca6e5 1568static inline int pci_find_capability(struct pci_dev *dev, int cap)
2ee546c4 1569{ return 0; }
05cca6e5
GKH		 1570static inline int pci_find_next_capability(struct pci_dev *dev, u8 post,
1571 int cap)
2ee546c4 1572{ return 0; }
05cca6e5 1573static inline int pci_find_ext_capability(struct pci_dev *dev, int cap)
2ee546c4 1574{ return 0; }
05cca6e5 1575
1da177e4 1576/* Power management related routines */
2ee546c4
BH		 1577static inline int pci_save_state(struct pci_dev *dev) { return 0; }
1578static inline void pci_restore_state(struct pci_dev *dev) { }
05cca6e5 1579static inline int pci_set_power_state(struct pci_dev *dev, pci_power_t state)
2ee546c4 1580{ return 0; }
3449248c 1581static inline int pci_wake_from_d3(struct pci_dev *dev, bool enable)
2ee546c4 1582{ return 0; }
05cca6e5
GKH		 1583static inline pci_power_t pci_choose_state(struct pci_dev *dev,
1584 pm_message_t state)
2ee546c4 1585{ return PCI_D0; }
05cca6e5
GKH		 1586static inline int pci_enable_wake(struct pci_dev *dev, pci_power_t state,
1587 int enable)
2ee546c4 1588{ return 0; }
48a92a81 1589
afd29f90
MW		 1590static inline struct resource *pci_find_resource(struct pci_dev *dev,
1591 struct resource *res)
1592{ return NULL; }
05cca6e5 1593static inline int pci_request_regions(struct pci_dev *dev, const char *res_name)
2ee546c4
BH		 1594{ return -EIO; }
1595static inline void pci_release_regions(struct pci_dev *dev) { }
0da0ead9 1596
c5076cfe
TN		 1597static inline unsigned long pci_address_to_pio(phys_addr_t addr) { return -1; }
1598
2ee546c4 1599static inline void pci_block_cfg_access(struct pci_dev *dev) { }
fb51ccbf
JK		 1600static inline int pci_block_cfg_access_in_atomic(struct pci_dev *dev)
1601{ return 0; }
2ee546c4 1602static inline void pci_unblock_cfg_access(struct pci_dev *dev) { }
e04b0ea2 1603
d80d0217
RD		 1604static inline struct pci_bus *pci_find_next_bus(const struct pci_bus *from)
1605{ return NULL; }
d80d0217
RD		 1606static inline struct pci_dev *pci_get_slot(struct pci_bus *bus,
1607 unsigned int devfn)
1608{ return NULL; }
d80d0217
RD		 1609static inline struct pci_dev *pci_get_bus_and_slot(unsigned int bus,
1610 unsigned int devfn)
1611{ return NULL; }
1612
2ee546c4
BH		 1613static inline int pci_domain_nr(struct pci_bus *bus) { return 0; }
1614static inline struct pci_dev *pci_dev_get(struct pci_dev *dev) { return NULL; }
41e5c0f8 1615static inline int pci_get_new_domain_nr(void) { return -ENOSYS; }
12ea6cad 1616
fb8a0d9d
WM		 1617#define dev_is_pci(d) (false)
1618#define dev_is_pf(d) (false)
4352dfd5 1619#endif /* CONFIG_PCI */
1da177e4 1620
4352dfd5
GKH		 1621/* Include architecture-dependent settings and functions */
1622
1623#include <asm/pci.h>
1da177e4 1624
f7195824
DW		 1625/* These two functions provide almost identical functionality. Depennding
1626 * on the architecture, one will be implemented as a wrapper around the
1627 * other (in drivers/pci/mmap.c).
1628 *
1629 * pci_mmap_resource_range() maps a specific BAR, and vm->vm_pgoff
1630 * is expected to be an offset within that region.
1631 *
1632 * pci_mmap_page_range() is the legacy architecture-specific interface,
1633 * which accepts a "user visible" resource address converted by
1634 * pci_resource_to_user(), as used in the legacy mmap() interface in
1635 * /proc/bus/pci/.
1636 */
1637int pci_mmap_resource_range(struct pci_dev *dev, int bar,
1638 struct vm_area_struct *vma,
1639 enum pci_mmap_state mmap_state, int write_combine);
f66e2258
DW		 1640int pci_mmap_page_range(struct pci_dev *pdev, int bar,
1641 struct vm_area_struct *vma,
11df1954
DW		 1642 enum pci_mmap_state mmap_state, int write_combine);
1643
ae749c7a
DW		 1644#ifndef arch_can_pci_mmap_wc
1645#define arch_can_pci_mmap_wc() 0
1646#endif
2bea36fd 1647
e854d8b2
DW		 1648#ifndef arch_can_pci_mmap_io
1649#define arch_can_pci_mmap_io() 0
2bea36fd
DW		 1650#define pci_iobar_pfn(pdev, bar, vma) (-EINVAL)
1651#else
1652int pci_iobar_pfn(struct pci_dev *pdev, int bar, struct vm_area_struct *vma);
e854d8b2 1653#endif
ae749c7a 1654
92016ba5
JO		 1655#ifndef pci_root_bus_fwnode
1656#define pci_root_bus_fwnode(bus) NULL
1657#endif
1658
1da177e4
LT		 1659/* these helpers provide future and backwards compatibility
1660 * for accessing popular PCI BAR info */
05cca6e5
GKH		 1661#define pci_resource_start(dev, bar) ((dev)->resource[(bar)].start)
1662#define pci_resource_end(dev, bar) ((dev)->resource[(bar)].end)
1663#define pci_resource_flags(dev, bar) ((dev)->resource[(bar)].flags)
1da177e4 1664#define pci_resource_len(dev,bar) \
05cca6e5
GKH		 1665 ((pci_resource_start((dev), (bar)) == 0 && \
1666 pci_resource_end((dev), (bar)) == \
1667 pci_resource_start((dev), (bar))) ? 0 : \
1668 \
1669 (pci_resource_end((dev), (bar)) - \
1670 pci_resource_start((dev), (bar)) + 1))
1da177e4
LT		 1671
1672/* Similar to the helpers above, these manipulate per-pci_dev
1673 * driver-specific data. They are really just a wrapper around
1674 * the generic device structure functions of these calls.
1675 */
05cca6e5 1676static inline void *pci_get_drvdata(struct pci_dev *pdev)
1da177e4
LT		 1677{
1678 return dev_get_drvdata(&pdev->dev);
1679}
1680
05cca6e5 1681static inline void pci_set_drvdata(struct pci_dev *pdev, void *data)
1da177e4
LT		 1682{
1683 dev_set_drvdata(&pdev->dev, data);
1684}
1685
1686/* If you want to know what to call your pci_dev, ask this function.
1687 * Again, it's a wrapper around the generic device.
1688 */
2fc90f61 1689static inline const char *pci_name(const struct pci_dev *pdev)
1da177e4 1690{
c6c4f070 1691 return dev_name(&pdev->dev);
1da177e4
LT		 1692}
1693
2311b1f2
ME		 1694
1695/* Some archs don't want to expose struct resource to userland as-is
1696 * in sysfs and /proc
1697 */
8221a013
BH		 1698#ifdef HAVE_ARCH_PCI_RESOURCE_TO_USER
1699void pci_resource_to_user(const struct pci_dev *dev, int bar,
1700 const struct resource *rsrc,
1701 resource_size_t *start, resource_size_t *end);
1702#else
2311b1f2 1703static inline void pci_resource_to_user(const struct pci_dev *dev, int bar,
05cca6e5 1704 const struct resource *rsrc, resource_size_t *start,
e31dd6e4 1705 resource_size_t *end)
2311b1f2
ME		 1706{
1707 *start = rsrc->start;
1708 *end = rsrc->end;
1709}
1710#endif /* HAVE_ARCH_PCI_RESOURCE_TO_USER */
1711
1712
1da177e4
LT		 1713/*
1714 * The world is not perfect and supplies us with broken PCI devices.
1715 * For at least a part of these bugs we need a work-around, so both
1716 * generic (drivers/pci/quirks.c) and per-architecture code can define
1717 * fixup hooks to be called for particular buggy devices.
1718 */
1719
1720struct pci_fixup {
f4ca5c6a
YL		 1721 u16 vendor; /* You can use PCI_ANY_ID here of course */
1722 u16 device; /* You can use PCI_ANY_ID here of course */
1723 u32 class; /* You can use PCI_ANY_ID here too */
1724 unsigned int class_shift; /* should be 0, 8, 16 */
1da177e4
LT		 1725 void (*hook)(struct pci_dev *dev);
1726};
1727
1728enum pci_fixup_pass {
1729 pci_fixup_early, /* Before probing BARs */
1730 pci_fixup_header, /* After reading configuration header */
1731 pci_fixup_final, /* Final phase of device fixups */
1732 pci_fixup_enable, /* pci_enable_device() time */
e1a2a51e 1733 pci_fixup_resume, /* pci_device_resume() */
7d2a01b8 1734 pci_fixup_suspend, /* pci_device_suspend() */
e1a2a51e 1735 pci_fixup_resume_early, /* pci_device_resume_early() */
7d2a01b8 1736 pci_fixup_suspend_late, /* pci_device_suspend_late() */
1da177e4
LT		 1737};
1738
1739/* Anonymous variables would be nice... */
f4ca5c6a
YL		 1740#define DECLARE_PCI_FIXUP_SECTION(section, name, vendor, device, class, \
1741 class_shift, hook) \
ecf61c78 1742 static const struct pci_fixup __PASTE(__pci_fixup_##name,__LINE__) __used \
f4ca5c6a
YL		 1743 __attribute__((__section__(#section), aligned((sizeof(void *))))) \
1744 = { vendor, device, class, class_shift, hook };
1745
1746#define DECLARE_PCI_FIXUP_CLASS_EARLY(vendor, device, class, \
1747 class_shift, hook) \
1748 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_early, \
ecf61c78 1749 hook, vendor, device, class, class_shift, hook)
f4ca5c6a
YL		 1750#define DECLARE_PCI_FIXUP_CLASS_HEADER(vendor, device, class, \
1751 class_shift, hook) \
1752 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_header, \
ecf61c78 1753 hook, vendor, device, class, class_shift, hook)
f4ca5c6a
YL		 1754#define DECLARE_PCI_FIXUP_CLASS_FINAL(vendor, device, class, \
1755 class_shift, hook) \
1756 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_final, \
ecf61c78 1757 hook, vendor, device, class, class_shift, hook)
f4ca5c6a
YL		 1758#define DECLARE_PCI_FIXUP_CLASS_ENABLE(vendor, device, class, \
1759 class_shift, hook) \
1760 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_enable, \
ecf61c78 1761 hook, vendor, device, class, class_shift, hook)
f4ca5c6a
YL		 1762#define DECLARE_PCI_FIXUP_CLASS_RESUME(vendor, device, class, \
1763 class_shift, hook) \
1764 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume, \
ecf61c78 1765 resume##hook, vendor, device, class, \
f4ca5c6a
YL		 1766 class_shift, hook)
1767#define DECLARE_PCI_FIXUP_CLASS_RESUME_EARLY(vendor, device, class, \
1768 class_shift, hook) \
1769 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume_early, \
ecf61c78 1770 resume_early##hook, vendor, device, \
f4ca5c6a
YL		 1771 class, class_shift, hook)
1772#define DECLARE_PCI_FIXUP_CLASS_SUSPEND(vendor, device, class, \
1773 class_shift, hook) \
1774 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend, \
ecf61c78 1775 suspend##hook, vendor, device, class, \
f4ca5c6a 1776 class_shift, hook)
7d2a01b8
AN		 1777#define DECLARE_PCI_FIXUP_CLASS_SUSPEND_LATE(vendor, device, class, \
1778 class_shift, hook) \
1779 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend_late, \
1780 suspend_late##hook, vendor, device, \
1781 class, class_shift, hook)
f4ca5c6a 1782
1da177e4
LT		 1783#define DECLARE_PCI_FIXUP_EARLY(vendor, device, hook) \
1784 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_early, \
ecf61c78 1785 hook, vendor, device, PCI_ANY_ID, 0, hook)
1da177e4
LT		 1786#define DECLARE_PCI_FIXUP_HEADER(vendor, device, hook) \
1787 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_header, \
ecf61c78 1788 hook, vendor, device, PCI_ANY_ID, 0, hook)
1da177e4
LT		 1789#define DECLARE_PCI_FIXUP_FINAL(vendor, device, hook) \
1790 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_final, \
ecf61c78 1791 hook, vendor, device, PCI_ANY_ID, 0, hook)
1da177e4
LT		 1792#define DECLARE_PCI_FIXUP_ENABLE(vendor, device, hook) \
1793 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_enable, \
ecf61c78 1794 hook, vendor, device, PCI_ANY_ID, 0, hook)
1597cacb
AC		 1795#define DECLARE_PCI_FIXUP_RESUME(vendor, device, hook) \
1796 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume, \
ecf61c78 1797 resume##hook, vendor, device, \
f4ca5c6a 1798 PCI_ANY_ID, 0, hook)
e1a2a51e
RW		 1799#define DECLARE_PCI_FIXUP_RESUME_EARLY(vendor, device, hook) \
1800 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume_early, \
ecf61c78 1801 resume_early##hook, vendor, device, \
f4ca5c6a 1802 PCI_ANY_ID, 0, hook)
e1a2a51e
RW		 1803#define DECLARE_PCI_FIXUP_SUSPEND(vendor, device, hook) \
1804 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend, \
ecf61c78 1805 suspend##hook, vendor, device, \
f4ca5c6a 1806 PCI_ANY_ID, 0, hook)
7d2a01b8
AN		 1807#define DECLARE_PCI_FIXUP_SUSPEND_LATE(vendor, device, hook) \
1808 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend_late, \
1809 suspend_late##hook, vendor, device, \
1810 PCI_ANY_ID, 0, hook)
1da177e4 1811
93177a74 1812#ifdef CONFIG_PCI_QUIRKS
1da177e4 1813void pci_fixup_device(enum pci_fixup_pass pass, struct pci_dev *dev);
ad805758 1814int pci_dev_specific_acs_enabled(struct pci_dev *dev, u16 acs_flags);
c1d61c9b 1815int pci_dev_specific_enable_acs(struct pci_dev *dev);
93177a74
RW		 1816#else
1817static inline void pci_fixup_device(enum pci_fixup_pass pass,
2ee546c4 1818 struct pci_dev *dev) { }
ad805758
AW		 1819static inline int pci_dev_specific_acs_enabled(struct pci_dev *dev,
1820 u16 acs_flags)
1821{
1822 return -ENOTTY;
1823}
c1d61c9b
AW		 1824static inline int pci_dev_specific_enable_acs(struct pci_dev *dev)
1825{
1826 return -ENOTTY;
1827}
93177a74 1828#endif
1da177e4 1829
05cca6e5 1830void __iomem *pcim_iomap(struct pci_dev *pdev, int bar, unsigned long maxlen);
5ea81769 1831void pcim_iounmap(struct pci_dev *pdev, void __iomem *addr);
05cca6e5 1832void __iomem * const *pcim_iomap_table(struct pci_dev *pdev);
fb7ebfe4
YL		 1833int pcim_iomap_regions(struct pci_dev *pdev, int mask, const char *name);
1834int pcim_iomap_regions_request_all(struct pci_dev *pdev, int mask,
916fbfb7 1835 const char *name);
fb7ebfe4 1836void pcim_iounmap_regions(struct pci_dev *pdev, int mask);
5ea81769 1837
1da177e4 1838extern int pci_pci_problems;
236561e5 1839#define PCIPCI_FAIL 1 /* No PCI PCI DMA */
1da177e4
LT		 1840#define PCIPCI_TRITON 2
1841#define PCIPCI_NATOMA 4
1842#define PCIPCI_VIAETBF 8
1843#define PCIPCI_VSFX 16
236561e5
AC		 1844#define PCIPCI_ALIMAGIK 32 /* Need low latency setting */
1845#define PCIAGP_FAIL 64 /* No PCI to AGP DMA */
1da177e4 1846
4516a618
AN		 1847extern unsigned long pci_cardbus_io_size;
1848extern unsigned long pci_cardbus_mem_size;
15856ad5 1849extern u8 pci_dfl_cache_line_size;
ac1aa47b 1850extern u8 pci_cache_line_size;
4516a618 1851
28760489
EB		 1852extern unsigned long pci_hotplug_io_size;
1853extern unsigned long pci_hotplug_mem_size;
e16b4660 1854extern unsigned long pci_hotplug_bus_size;
28760489 1855
f7625980 1856/* Architecture-specific versions may override these (weak) */
19792a08 1857void pcibios_disable_device(struct pci_dev *dev);
cfce9fb8 1858void pcibios_set_master(struct pci_dev *dev);
19792a08
AB		 1859int pcibios_set_pcie_reset_state(struct pci_dev *dev,
1860 enum pcie_reset_state state);
eca0d467 1861int pcibios_add_device(struct pci_dev *dev);
6ae32c53 1862void pcibios_release_device(struct pci_dev *dev);
a43ae58c 1863void pcibios_penalize_isa_irq(int irq, int active);
890e4847
JL		 1864int pcibios_alloc_irq(struct pci_dev *dev);
1865void pcibios_free_irq(struct pci_dev *dev);
575e3348 1866
699c1985
SO		 1867#ifdef CONFIG_HIBERNATE_CALLBACKS
1868extern struct dev_pm_ops pcibios_pm_ops;
1869#endif
1870
935c760e 1871#if defined(CONFIG_PCI_MMCONFIG) || defined(CONFIG_ACPI_MCFG)
f39d5b72
BH		 1872void __init pci_mmcfg_early_init(void);
1873void __init pci_mmcfg_late_init(void);
7752d5cf 1874#else
bb63b421 1875static inline void pci_mmcfg_early_init(void) { }
7752d5cf
RH		 1876static inline void pci_mmcfg_late_init(void) { }
1877#endif
1878
642c92da 1879int pci_ext_cfg_avail(void);
0ef5f8f6 1880
1684f5dd 1881void __iomem *pci_ioremap_bar(struct pci_dev *pdev, int bar);
c43996f4 1882void __iomem *pci_ioremap_wc_bar(struct pci_dev *pdev, int bar);
aa42d7c6 1883
dd7cc44d 1884#ifdef CONFIG_PCI_IOV
b07579c0
WY		 1885int pci_iov_virtfn_bus(struct pci_dev *dev, int id);
1886int pci_iov_virtfn_devfn(struct pci_dev *dev, int id);
1887
f39d5b72
BH		 1888int pci_enable_sriov(struct pci_dev *dev, int nr_virtfn);
1889void pci_disable_sriov(struct pci_dev *dev);
c194f7ea
WY		 1890int pci_iov_add_virtfn(struct pci_dev *dev, int id, int reset);
1891void pci_iov_remove_virtfn(struct pci_dev *dev, int id, int reset);
f39d5b72 1892int pci_num_vf(struct pci_dev *dev);
5a8eb242 1893int pci_vfs_assigned(struct pci_dev *dev);
f39d5b72
BH		 1894int pci_sriov_set_totalvfs(struct pci_dev *dev, u16 numvfs);
1895int pci_sriov_get_totalvfs(struct pci_dev *dev);
0e6c9122 1896resource_size_t pci_iov_resource_size(struct pci_dev *dev, int resno);
dd7cc44d 1897#else
b07579c0
WY		 1898static inline int pci_iov_virtfn_bus(struct pci_dev *dev, int id)
1899{
1900 return -ENOSYS;
1901}
1902static inline int pci_iov_virtfn_devfn(struct pci_dev *dev, int id)
1903{
1904 return -ENOSYS;
1905}
dd7cc44d 1906static inline int pci_enable_sriov(struct pci_dev *dev, int nr_virtfn)
2ee546c4 1907{ return -ENODEV; }
c194f7ea
WY		 1908static inline int pci_iov_add_virtfn(struct pci_dev *dev, int id, int reset)
1909{
1910 return -ENOSYS;
1911}
1912static inline void pci_iov_remove_virtfn(struct pci_dev *dev,
1913 int id, int reset) { }
2ee546c4 1914static inline void pci_disable_sriov(struct pci_dev *dev) { }
2ee546c4 1915static inline int pci_num_vf(struct pci_dev *dev) { return 0; }
5a8eb242 1916static inline int pci_vfs_assigned(struct pci_dev *dev)
2ee546c4 1917{ return 0; }
bff73156 1918static inline int pci_sriov_set_totalvfs(struct pci_dev *dev, u16 numvfs)
2ee546c4 1919{ return 0; }
bff73156 1920static inline int pci_sriov_get_totalvfs(struct pci_dev *dev)
2ee546c4 1921{ return 0; }
0e6c9122
WY		 1922static inline resource_size_t pci_iov_resource_size(struct pci_dev *dev, int resno)
1923{ return 0; }
dd7cc44d
YZ		 1924#endif
1925
c825bc94 1926#if defined(CONFIG_HOTPLUG_PCI) || defined(CONFIG_HOTPLUG_PCI_MODULE)
f39d5b72
BH		 1927void pci_hp_create_module_link(struct pci_slot *pci_slot);
1928void pci_hp_remove_module_link(struct pci_slot *pci_slot);
c825bc94
KK		 1929#endif
1930
d7b7e605
KK		 1931/**
1932 * pci_pcie_cap - get the saved PCIe capability offset
1933 * @dev: PCI device
1934 *
1935 * PCIe capability offset is calculated at PCI device initialization
1936 * time and saved in the data structure. This function returns saved
1937 * PCIe capability offset. Using this instead of pci_find_capability()
1938 * reduces unnecessary search in the PCI configuration space. If you
1939 * need to calculate PCIe capability offset from raw device for some
1940 * reasons, please use pci_find_capability() instead.
1941 */
1942static inline int pci_pcie_cap(struct pci_dev *dev)
1943{
1944 return dev->pcie_cap;
1945}
1946
7eb776c4
KK		 1947/**
1948 * pci_is_pcie - check if the PCI device is PCI Express capable
1949 * @dev: PCI device
1950 *
a895c28a 1951 * Returns: true if the PCI device is PCI Express capable, false otherwise.
7eb776c4
KK		 1952 */
1953static inline bool pci_is_pcie(struct pci_dev *dev)
1954{
a895c28a 1955 return pci_pcie_cap(dev);
7eb776c4
KK		 1956}
1957
7c9c003c
MS		 1958/**
1959 * pcie_caps_reg - get the PCIe Capabilities Register
1960 * @dev: PCI device
1961 */
1962static inline u16 pcie_caps_reg(const struct pci_dev *dev)
1963{
1964 return dev->pcie_flags_reg;
1965}
1966
786e2288
YW		 1967/**
1968 * pci_pcie_type - get the PCIe device/port type
1969 * @dev: PCI device
1970 */
1971static inline int pci_pcie_type(const struct pci_dev *dev)
1972{
1c531d82 1973 return (pcie_caps_reg(dev) & PCI_EXP_FLAGS_TYPE) >> 4;
786e2288
YW		 1974}
1975
e784930b
JT		 1976static inline struct pci_dev *pcie_find_root_port(struct pci_dev *dev)
1977{
1978 while (1) {
1979 if (!pci_is_pcie(dev))
1980 break;
1981 if (pci_pcie_type(dev) == PCI_EXP_TYPE_ROOT_PORT)
1982 return dev;
1983 if (!dev->bus->self)
1984 break;
1985 dev = dev->bus->self;
1986 }
1987 return NULL;
1988}
1989
5d990b62 1990void pci_request_acs(void);
ad805758
AW		 1991bool pci_acs_enabled(struct pci_dev *pdev, u16 acs_flags);
1992bool pci_acs_path_enabled(struct pci_dev *start,
1993 struct pci_dev *end, u16 acs_flags);
a2ce7662 1994
7ad506fa 1995#define PCI_VPD_LRDT 0x80 /* Large Resource Data Type */
63ddc0b8 1996#define PCI_VPD_LRDT_ID(x) ((x) | PCI_VPD_LRDT)
7ad506fa
MC		 1997
1998/* Large Resource Data Type Tag Item Names */
1999#define PCI_VPD_LTIN_ID_STRING 0x02 /* Identifier String */
2000#define PCI_VPD_LTIN_RO_DATA 0x10 /* Read-Only Data */
2001#define PCI_VPD_LTIN_RW_DATA 0x11 /* Read-Write Data */
2002
2003#define PCI_VPD_LRDT_ID_STRING PCI_VPD_LRDT_ID(PCI_VPD_LTIN_ID_STRING)
2004#define PCI_VPD_LRDT_RO_DATA PCI_VPD_LRDT_ID(PCI_VPD_LTIN_RO_DATA)
2005#define PCI_VPD_LRDT_RW_DATA PCI_VPD_LRDT_ID(PCI_VPD_LTIN_RW_DATA)
2006
2007/* Small Resource Data Type Tag Item Names */
9eb45d5c 2008#define PCI_VPD_STIN_END 0x0f /* End */
7ad506fa 2009
9eb45d5c 2010#define PCI_VPD_SRDT_END (PCI_VPD_STIN_END << 3)
7ad506fa
MC		 2011
2012#define PCI_VPD_SRDT_TIN_MASK 0x78
2013#define PCI_VPD_SRDT_LEN_MASK 0x07
9eb45d5c 2014#define PCI_VPD_LRDT_TIN_MASK 0x7f
7ad506fa
MC		 2015
2016#define PCI_VPD_LRDT_TAG_SIZE 3
2017#define PCI_VPD_SRDT_TAG_SIZE 1
a2ce7662 2018
e1d5bdab
MC		 2019#define PCI_VPD_INFO_FLD_HDR_SIZE 3
2020
4067a854
MC		 2021#define PCI_VPD_RO_KEYWORD_PARTNO "PN"
2022#define PCI_VPD_RO_KEYWORD_MFR_ID "MN"
2023#define PCI_VPD_RO_KEYWORD_VENDOR0 "V0"
d4894f3e 2024#define PCI_VPD_RO_KEYWORD_CHKSUM "RV"
4067a854 2025
a2ce7662
MC		 2026/**
2027 * pci_vpd_lrdt_size - Extracts the Large Resource Data Type length
2028 * @lrdt: Pointer to the beginning of the Large Resource Data Type tag
2029 *
2030 * Returns the extracted Large Resource Data Type length.
2031 */
2032static inline u16 pci_vpd_lrdt_size(const u8 *lrdt)
2033{
2034 return (u16)lrdt[1] + ((u16)lrdt[2] << 8);
2035}
2036
9eb45d5c
HR		 2037/**
2038 * pci_vpd_lrdt_tag - Extracts the Large Resource Data Type Tag Item
2039 * @lrdt: Pointer to the beginning of the Large Resource Data Type tag
2040 *
2041 * Returns the extracted Large Resource Data Type Tag item.
2042 */
2043static inline u16 pci_vpd_lrdt_tag(const u8 *lrdt)
2044{
2045 return (u16)(lrdt[0] & PCI_VPD_LRDT_TIN_MASK);
2046}
2047
7ad506fa
MC		 2048/**
2049 * pci_vpd_srdt_size - Extracts the Small Resource Data Type length
2050 * @lrdt: Pointer to the beginning of the Small Resource Data Type tag
2051 *
2052 * Returns the extracted Small Resource Data Type length.
2053 */
2054static inline u8 pci_vpd_srdt_size(const u8 *srdt)
2055{
2056 return (*srdt) & PCI_VPD_SRDT_LEN_MASK;
2057}
2058
9eb45d5c
HR		 2059/**
2060 * pci_vpd_srdt_tag - Extracts the Small Resource Data Type Tag Item
2061 * @lrdt: Pointer to the beginning of the Small Resource Data Type tag
2062 *
2063 * Returns the extracted Small Resource Data Type Tag Item.
2064 */
2065static inline u8 pci_vpd_srdt_tag(const u8 *srdt)
2066{
2067 return ((*srdt) & PCI_VPD_SRDT_TIN_MASK) >> 3;
2068}
2069
e1d5bdab
MC		 2070/**
2071 * pci_vpd_info_field_size - Extracts the information field length
2072 * @lrdt: Pointer to the beginning of an information field header
2073 *
2074 * Returns the extracted information field length.
2075 */
2076static inline u8 pci_vpd_info_field_size(const u8 *info_field)
2077{
2078 return info_field[2];
2079}
2080
b55ac1b2
MC		 2081/**
2082 * pci_vpd_find_tag - Locates the Resource Data Type tag provided
2083 * @buf: Pointer to buffered vpd data
2084 * @off: The offset into the buffer at which to begin the search
2085 * @len: The length of the vpd buffer
2086 * @rdt: The Resource Data Type to search for
2087 *
2088 * Returns the index where the Resource Data Type was found or
2089 * -ENOENT otherwise.
2090 */
2091int pci_vpd_find_tag(const u8 *buf, unsigned int off, unsigned int len, u8 rdt);
2092
4067a854
MC		 2093/**
2094 * pci_vpd_find_info_keyword - Locates an information field keyword in the VPD
2095 * @buf: Pointer to buffered vpd data
2096 * @off: The offset into the buffer at which to begin the search
2097 * @len: The length of the buffer area, relative to off, in which to search
2098 * @kw: The keyword to search for
2099 *
2100 * Returns the index where the information field keyword was found or
2101 * -ENOENT otherwise.
2102 */
2103int pci_vpd_find_info_keyword(const u8 *buf, unsigned int off,
2104 unsigned int len, const char *kw);
2105
98d9f30c
BH		 2106/* PCI <-> OF binding helpers */
2107#ifdef CONFIG_OF
2108struct device_node;
b165e2b6 2109struct irq_domain;
f39d5b72
BH		 2110void pci_set_of_node(struct pci_dev *dev);
2111void pci_release_of_node(struct pci_dev *dev);
2112void pci_set_bus_of_node(struct pci_bus *bus);
2113void pci_release_bus_of_node(struct pci_bus *bus);
b165e2b6 2114struct irq_domain *pci_host_bridge_of_msi_domain(struct pci_bus *bus);
98d9f30c
BH		 2115
2116/* Arch may override this (weak) */
723ec4d0 2117struct device_node *pcibios_get_phb_of_node(struct pci_bus *bus);
98d9f30c 2118
3df425f3
JC		 2119static inline struct device_node *
2120pci_device_to_OF_node(const struct pci_dev *pdev)
64099d98
BH		 2121{
2122 return pdev ? pdev->dev.of_node : NULL;
2123}
2124
ef3b4f8c
BH		 2125static inline struct device_node *pci_bus_to_OF_node(struct pci_bus *bus)
2126{
2127 return bus ? bus->dev.of_node : NULL;
2128}
2129
98d9f30c
BH		 2130#else /* CONFIG_OF */
2131static inline void pci_set_of_node(struct pci_dev *dev) { }
2132static inline void pci_release_of_node(struct pci_dev *dev) { }
2133static inline void pci_set_bus_of_node(struct pci_bus *bus) { }
2134static inline void pci_release_bus_of_node(struct pci_bus *bus) { }
f0b66a2c
KH		 2135static inline struct device_node *
2136pci_device_to_OF_node(const struct pci_dev *pdev) { return NULL; }
b165e2b6
MZ		 2137static inline struct irq_domain *
2138pci_host_bridge_of_msi_domain(struct pci_bus *bus) { return NULL; }
98d9f30c
BH		 2139#endif /* CONFIG_OF */
2140
471036b2
SS		 2141#ifdef CONFIG_ACPI
2142struct irq_domain *pci_host_bridge_acpi_msi_domain(struct pci_bus *bus);
2143
2144void
2145pci_msi_register_fwnode_provider(struct fwnode_handle *(*fn)(struct device *));
2146#else
2147static inline struct irq_domain *
2148pci_host_bridge_acpi_msi_domain(struct pci_bus *bus) { return NULL; }
2149#endif
2150
eb740b5f
GS		 2151#ifdef CONFIG_EEH
2152static inline struct eeh_dev *pci_dev_to_eeh_dev(struct pci_dev *pdev)
2153{
2154 return pdev->dev.archdata.edev;
2155}
2156#endif
2157
f0af9593 2158void pci_add_dma_alias(struct pci_dev *dev, u8 devfn);
338c3149 2159bool pci_devs_are_dma_aliases(struct pci_dev *dev1, struct pci_dev *dev2);
c25dc828
AW		 2160int pci_for_each_dma_alias(struct pci_dev *pdev,
2161 int (*fn)(struct pci_dev *pdev,
2162 u16 alias, void *data), void *data);
2163
ce052984
EZ		 2164/* helper functions for operation of device flag */
2165static inline void pci_set_dev_assigned(struct pci_dev *pdev)
2166{
2167 pdev->dev_flags |= PCI_DEV_FLAGS_ASSIGNED;
2168}
2169static inline void pci_clear_dev_assigned(struct pci_dev *pdev)
2170{
2171 pdev->dev_flags &= ~PCI_DEV_FLAGS_ASSIGNED;
2172}
2173static inline bool pci_is_dev_assigned(struct pci_dev *pdev)
2174{
2175 return (pdev->dev_flags & PCI_DEV_FLAGS_ASSIGNED) == PCI_DEV_FLAGS_ASSIGNED;
2176}
19bdb6e4
AW		 2177
2178/**
2179 * pci_ari_enabled - query ARI forwarding status
2180 * @bus: the PCI bus
2181 *
2182 * Returns true if ARI forwarding is enabled.
2183 */
2184static inline bool pci_ari_enabled(struct pci_bus *bus)
2185{
2186 return bus->self && bus->self->ari_enabled;
2187}
bc4b024a 2188
8531e283
LW		 2189/**
2190 * pci_is_thunderbolt_attached - whether device is on a Thunderbolt daisy chain
2191 * @pdev: PCI device to check
2192 *
2193 * Walk upwards from @pdev and check for each encountered bridge if it's part
2194 * of a Thunderbolt controller. Reaching the host bridge means @pdev is not
2195 * Thunderbolt-attached. (But rather soldered to the mainboard usually.)
2196 */
2197static inline bool pci_is_thunderbolt_attached(struct pci_dev *pdev)
2198{
2199 struct pci_dev *parent = pdev;
2200
2201 if (pdev->is_thunderbolt)
2202 return true;
2203
2204 while ((parent = pci_upstream_bridge(parent)))
2205 if (parent->is_thunderbolt)
2206 return true;
2207
2208 return false;
2209}
2210
bc4b024a
CH		 2211/* provide the legacy pci_dma_* API */
2212#include <linux/pci-dma-compat.h>
2213
1da177e4 2214#endif /* LINUX_PCI_H */
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