]>
Commit | Line | Data |
---|---|---|
1da177e4 LT |
1 | /* |
2 | * pci.h | |
3 | * | |
4 | * PCI defines and function prototypes | |
5 | * Copyright 1994, Drew Eckhardt | |
6 | * Copyright 1997--1999 Martin Mares <mj@ucw.cz> | |
7 | * | |
8 | * For more information, please consult the following manuals (look at | |
9 | * http://www.pcisig.com/ for how to get them): | |
10 | * | |
11 | * PCI BIOS Specification | |
12 | * PCI Local Bus Specification | |
13 | * PCI to PCI Bridge Specification | |
14 | * PCI System Design Guide | |
15 | */ | |
16 | ||
17 | #ifndef LINUX_PCI_H | |
18 | #define LINUX_PCI_H | |
19 | ||
4352dfd5 GKH |
20 | /* Include the pci register defines */ |
21 | #include <linux/pci_regs.h> | |
1da177e4 | 22 | |
1da177e4 LT |
23 | /* |
24 | * The PCI interface treats multi-function devices as independent | |
25 | * devices. The slot/function address of each device is encoded | |
26 | * in a single byte as follows: | |
27 | * | |
28 | * 7:3 = slot | |
29 | * 2:0 = function | |
30 | */ | |
05cca6e5 | 31 | #define PCI_DEVFN(slot, func) ((((slot) & 0x1f) << 3) | ((func) & 0x07)) |
1da177e4 LT |
32 | #define PCI_SLOT(devfn) (((devfn) >> 3) & 0x1f) |
33 | #define PCI_FUNC(devfn) ((devfn) & 0x07) | |
34 | ||
35 | /* Ioctls for /proc/bus/pci/X/Y nodes. */ | |
36 | #define PCIIOC_BASE ('P' << 24 | 'C' << 16 | 'I' << 8) | |
37 | #define PCIIOC_CONTROLLER (PCIIOC_BASE | 0x00) /* Get controller for PCI device. */ | |
38 | #define PCIIOC_MMAP_IS_IO (PCIIOC_BASE | 0x01) /* Set mmap state to I/O space. */ | |
39 | #define PCIIOC_MMAP_IS_MEM (PCIIOC_BASE | 0x02) /* Set mmap state to MEM space. */ | |
40 | #define PCIIOC_WRITE_COMBINE (PCIIOC_BASE | 0x03) /* Enable/disable write-combining. */ | |
41 | ||
42 | #ifdef __KERNEL__ | |
43 | ||
778382e0 DW |
44 | #include <linux/mod_devicetable.h> |
45 | ||
1da177e4 | 46 | #include <linux/types.h> |
98db6f19 | 47 | #include <linux/init.h> |
1da177e4 LT |
48 | #include <linux/ioport.h> |
49 | #include <linux/list.h> | |
4a7fb636 | 50 | #include <linux/compiler.h> |
1da177e4 | 51 | #include <linux/errno.h> |
bae94d02 | 52 | #include <asm/atomic.h> |
1da177e4 LT |
53 | #include <linux/device.h> |
54 | ||
7e7a43c3 AB |
55 | /* Include the ID list */ |
56 | #include <linux/pci_ids.h> | |
57 | ||
1da177e4 LT |
58 | /* File state for mmap()s on /proc/bus/pci/X/Y */ |
59 | enum pci_mmap_state { | |
60 | pci_mmap_io, | |
61 | pci_mmap_mem | |
62 | }; | |
63 | ||
64 | /* This defines the direction arg to the DMA mapping routines. */ | |
65 | #define PCI_DMA_BIDIRECTIONAL 0 | |
66 | #define PCI_DMA_TODEVICE 1 | |
67 | #define PCI_DMA_FROMDEVICE 2 | |
68 | #define PCI_DMA_NONE 3 | |
69 | ||
1da177e4 LT |
70 | #define DEVICE_COUNT_RESOURCE 12 |
71 | ||
72 | typedef int __bitwise pci_power_t; | |
73 | ||
4352dfd5 GKH |
74 | #define PCI_D0 ((pci_power_t __force) 0) |
75 | #define PCI_D1 ((pci_power_t __force) 1) | |
76 | #define PCI_D2 ((pci_power_t __force) 2) | |
1da177e4 LT |
77 | #define PCI_D3hot ((pci_power_t __force) 3) |
78 | #define PCI_D3cold ((pci_power_t __force) 4) | |
3fe9d19f | 79 | #define PCI_UNKNOWN ((pci_power_t __force) 5) |
438510f6 | 80 | #define PCI_POWER_ERROR ((pci_power_t __force) -1) |
1da177e4 | 81 | |
392a1ce7 LV |
82 | /** The pci_channel state describes connectivity between the CPU and |
83 | * the pci device. If some PCI bus between here and the pci device | |
84 | * has crashed or locked up, this info is reflected here. | |
85 | */ | |
86 | typedef unsigned int __bitwise pci_channel_state_t; | |
87 | ||
88 | enum pci_channel_state { | |
89 | /* I/O channel is in normal state */ | |
90 | pci_channel_io_normal = (__force pci_channel_state_t) 1, | |
91 | ||
92 | /* I/O to channel is blocked */ | |
93 | pci_channel_io_frozen = (__force pci_channel_state_t) 2, | |
94 | ||
95 | /* PCI card is dead */ | |
96 | pci_channel_io_perm_failure = (__force pci_channel_state_t) 3, | |
97 | }; | |
98 | ||
f7bdd12d BK |
99 | typedef unsigned int __bitwise pcie_reset_state_t; |
100 | ||
101 | enum pcie_reset_state { | |
102 | /* Reset is NOT asserted (Use to deassert reset) */ | |
103 | pcie_deassert_reset = (__force pcie_reset_state_t) 1, | |
104 | ||
105 | /* Use #PERST to reset PCI-E device */ | |
106 | pcie_warm_reset = (__force pcie_reset_state_t) 2, | |
107 | ||
108 | /* Use PCI-E Hot Reset to reset device */ | |
109 | pcie_hot_reset = (__force pcie_reset_state_t) 3 | |
110 | }; | |
111 | ||
ba698ad4 DM |
112 | typedef unsigned short __bitwise pci_dev_flags_t; |
113 | enum pci_dev_flags { | |
114 | /* INTX_DISABLE in PCI_COMMAND register disables MSI | |
115 | * generation too. | |
116 | */ | |
117 | PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG = (__force pci_dev_flags_t) 1, | |
118 | }; | |
119 | ||
6e325a62 MT |
120 | typedef unsigned short __bitwise pci_bus_flags_t; |
121 | enum pci_bus_flags { | |
d556ad4b PO |
122 | PCI_BUS_FLAGS_NO_MSI = (__force pci_bus_flags_t) 1, |
123 | PCI_BUS_FLAGS_NO_MMRBC = (__force pci_bus_flags_t) 2, | |
6e325a62 MT |
124 | }; |
125 | ||
41017f0c SL |
126 | struct pci_cap_saved_state { |
127 | struct hlist_node next; | |
128 | char cap_nr; | |
129 | u32 data[0]; | |
130 | }; | |
131 | ||
7d715a6c | 132 | struct pcie_link_state; |
ee69439c JB |
133 | struct pci_vpd; |
134 | ||
1da177e4 LT |
135 | /* |
136 | * The pci_dev structure is used to describe PCI devices. | |
137 | */ | |
138 | struct pci_dev { | |
1da177e4 LT |
139 | struct list_head bus_list; /* node in per-bus list */ |
140 | struct pci_bus *bus; /* bus this device is on */ | |
141 | struct pci_bus *subordinate; /* bus this device bridges to */ | |
142 | ||
143 | void *sysdata; /* hook for sys-specific extension */ | |
144 | struct proc_dir_entry *procent; /* device entry in /proc/bus/pci */ | |
145 | ||
146 | unsigned int devfn; /* encoded device & function index */ | |
147 | unsigned short vendor; | |
148 | unsigned short device; | |
149 | unsigned short subsystem_vendor; | |
150 | unsigned short subsystem_device; | |
151 | unsigned int class; /* 3 bytes: (base,sub,prog-if) */ | |
b8a3a521 | 152 | u8 revision; /* PCI revision, low byte of class word */ |
1da177e4 | 153 | u8 hdr_type; /* PCI header type (`multi' flag masked out) */ |
994a65e2 | 154 | u8 pcie_type; /* PCI-E device/port type */ |
1da177e4 | 155 | u8 rom_base_reg; /* which config register controls the ROM */ |
ffeff788 | 156 | u8 pin; /* which interrupt pin this device uses */ |
1da177e4 LT |
157 | |
158 | struct pci_driver *driver; /* which driver has allocated this device */ | |
159 | u64 dma_mask; /* Mask of the bits of bus address this | |
160 | device implements. Normally this is | |
161 | 0xffffffff. You only need to change | |
162 | this if your device has broken DMA | |
163 | or supports 64-bit transfers. */ | |
164 | ||
4d57cdfa FT |
165 | struct device_dma_parameters dma_parms; |
166 | ||
1da177e4 LT |
167 | pci_power_t current_state; /* Current operating state. In ACPI-speak, |
168 | this is D0-D3, D0 being fully functional, | |
169 | and D3 being off. */ | |
170 | ||
7d715a6c SL |
171 | #ifdef CONFIG_PCIEASPM |
172 | struct pcie_link_state *link_state; /* ASPM link state. */ | |
173 | #endif | |
174 | ||
392a1ce7 | 175 | pci_channel_state_t error_state; /* current connectivity state */ |
1da177e4 LT |
176 | struct device dev; /* Generic device interface */ |
177 | ||
1da177e4 LT |
178 | int cfg_size; /* Size of configuration space */ |
179 | ||
180 | /* | |
181 | * Instead of touching interrupt line and base address registers | |
182 | * directly, use the values stored here. They might be different! | |
183 | */ | |
184 | unsigned int irq; | |
185 | struct resource resource[DEVICE_COUNT_RESOURCE]; /* I/O and memory regions + expansion ROMs */ | |
186 | ||
187 | /* These fields are used by common fixups */ | |
188 | unsigned int transparent:1; /* Transparent PCI bridge */ | |
189 | unsigned int multifunction:1;/* Part of multi-function device */ | |
190 | /* keep track of device state */ | |
8a1bc901 | 191 | unsigned int is_added:1; |
1da177e4 | 192 | unsigned int is_busmaster:1; /* device is busmaster */ |
4602b88d | 193 | unsigned int no_msi:1; /* device may not use msi */ |
ffadcc2f | 194 | unsigned int no_d1d2:1; /* only allow d0 or d3 */ |
e04b0ea2 | 195 | unsigned int block_ucfg_access:1; /* userspace config space access is blocked */ |
bd8481e1 | 196 | unsigned int broken_parity_status:1; /* Device generates false positive parity */ |
99dc804d SL |
197 | unsigned int msi_enabled:1; |
198 | unsigned int msix_enabled:1; | |
9ac7849e | 199 | unsigned int is_managed:1; |
994a65e2 | 200 | unsigned int is_pcie:1; |
ba698ad4 | 201 | pci_dev_flags_t dev_flags; |
bae94d02 | 202 | atomic_t enable_cnt; /* pci_enable_device has been called */ |
4602b88d | 203 | |
1da177e4 | 204 | u32 saved_config_space[16]; /* config space saved at suspend time */ |
41017f0c | 205 | struct hlist_head saved_cap_space; |
1da177e4 LT |
206 | struct bin_attribute *rom_attr; /* attribute descriptor for sysfs ROM entry */ |
207 | int rom_attr_enabled; /* has display of the rom attribute been enabled? */ | |
208 | struct bin_attribute *res_attr[DEVICE_COUNT_RESOURCE]; /* sysfs file for resources */ | |
ded86d8d | 209 | #ifdef CONFIG_PCI_MSI |
4aa9bc95 | 210 | struct list_head msi_list; |
ded86d8d | 211 | #endif |
94e61088 | 212 | struct pci_vpd *vpd; |
1da177e4 LT |
213 | }; |
214 | ||
65891215 ME |
215 | extern struct pci_dev *alloc_pci_dev(void); |
216 | ||
1da177e4 LT |
217 | #define pci_dev_b(n) list_entry(n, struct pci_dev, bus_list) |
218 | #define to_pci_dev(n) container_of(n, struct pci_dev, dev) | |
219 | #define for_each_pci_dev(d) while ((d = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, d)) != NULL) | |
220 | ||
a7369f1f LV |
221 | static inline int pci_channel_offline(struct pci_dev *pdev) |
222 | { | |
223 | return (pdev->error_state != pci_channel_io_normal); | |
224 | } | |
225 | ||
41017f0c | 226 | static inline struct pci_cap_saved_state *pci_find_saved_cap( |
05cca6e5 | 227 | struct pci_dev *pci_dev, char cap) |
41017f0c SL |
228 | { |
229 | struct pci_cap_saved_state *tmp; | |
230 | struct hlist_node *pos; | |
231 | ||
232 | hlist_for_each_entry(tmp, pos, &pci_dev->saved_cap_space, next) { | |
233 | if (tmp->cap_nr == cap) | |
234 | return tmp; | |
235 | } | |
236 | return NULL; | |
237 | } | |
238 | ||
239 | static inline void pci_add_saved_cap(struct pci_dev *pci_dev, | |
240 | struct pci_cap_saved_state *new_cap) | |
241 | { | |
242 | hlist_add_head(&new_cap->next, &pci_dev->saved_cap_space); | |
243 | } | |
244 | ||
1da177e4 LT |
245 | /* |
246 | * For PCI devices, the region numbers are assigned this way: | |
247 | * | |
248 | * 0-5 standard PCI regions | |
249 | * 6 expansion ROM | |
250 | * 7-10 bridges: address space assigned to buses behind the bridge | |
251 | */ | |
252 | ||
4352dfd5 GKH |
253 | #define PCI_ROM_RESOURCE 6 |
254 | #define PCI_BRIDGE_RESOURCES 7 | |
255 | #define PCI_NUM_RESOURCES 11 | |
1da177e4 LT |
256 | |
257 | #ifndef PCI_BUS_NUM_RESOURCES | |
30a18d6c | 258 | #define PCI_BUS_NUM_RESOURCES 16 |
1da177e4 | 259 | #endif |
4352dfd5 GKH |
260 | |
261 | #define PCI_REGION_FLAG_MASK 0x0fU /* These bits of resource flags tell us the PCI region flags */ | |
1da177e4 LT |
262 | |
263 | struct pci_bus { | |
264 | struct list_head node; /* node in list of buses */ | |
265 | struct pci_bus *parent; /* parent bus this bridge is on */ | |
266 | struct list_head children; /* list of child buses */ | |
267 | struct list_head devices; /* list of devices on this bus */ | |
268 | struct pci_dev *self; /* bridge device as seen by parent */ | |
269 | struct resource *resource[PCI_BUS_NUM_RESOURCES]; | |
270 | /* address space routed to this bus */ | |
271 | ||
272 | struct pci_ops *ops; /* configuration access functions */ | |
273 | void *sysdata; /* hook for sys-specific extension */ | |
274 | struct proc_dir_entry *procdir; /* directory entry in /proc/bus/pci */ | |
275 | ||
276 | unsigned char number; /* bus number */ | |
277 | unsigned char primary; /* number of primary bridge */ | |
278 | unsigned char secondary; /* number of secondary bridge */ | |
279 | unsigned char subordinate; /* max number of subordinate buses */ | |
280 | ||
281 | char name[48]; | |
282 | ||
283 | unsigned short bridge_ctl; /* manage NO_ISA/FBB/et al behaviors */ | |
6e325a62 | 284 | pci_bus_flags_t bus_flags; /* Inherited by child busses */ |
1da177e4 | 285 | struct device *bridge; |
fd7d1ced | 286 | struct device dev; |
1da177e4 LT |
287 | struct bin_attribute *legacy_io; /* legacy I/O for this bus */ |
288 | struct bin_attribute *legacy_mem; /* legacy mem */ | |
cc74d96f | 289 | unsigned int is_added:1; |
1da177e4 LT |
290 | }; |
291 | ||
292 | #define pci_bus_b(n) list_entry(n, struct pci_bus, node) | |
fd7d1ced | 293 | #define to_pci_bus(n) container_of(n, struct pci_bus, dev) |
1da177e4 LT |
294 | |
295 | /* | |
296 | * Error values that may be returned by PCI functions. | |
297 | */ | |
298 | #define PCIBIOS_SUCCESSFUL 0x00 | |
299 | #define PCIBIOS_FUNC_NOT_SUPPORTED 0x81 | |
300 | #define PCIBIOS_BAD_VENDOR_ID 0x83 | |
301 | #define PCIBIOS_DEVICE_NOT_FOUND 0x86 | |
302 | #define PCIBIOS_BAD_REGISTER_NUMBER 0x87 | |
303 | #define PCIBIOS_SET_FAILED 0x88 | |
304 | #define PCIBIOS_BUFFER_TOO_SMALL 0x89 | |
305 | ||
306 | /* Low-level architecture-dependent routines */ | |
307 | ||
308 | struct pci_ops { | |
309 | int (*read)(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 *val); | |
310 | int (*write)(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 val); | |
311 | }; | |
312 | ||
b6ce068a MW |
313 | /* |
314 | * ACPI needs to be able to access PCI config space before we've done a | |
315 | * PCI bus scan and created pci_bus structures. | |
316 | */ | |
317 | extern int raw_pci_read(unsigned int domain, unsigned int bus, | |
318 | unsigned int devfn, int reg, int len, u32 *val); | |
319 | extern int raw_pci_write(unsigned int domain, unsigned int bus, | |
320 | unsigned int devfn, int reg, int len, u32 val); | |
1da177e4 LT |
321 | |
322 | struct pci_bus_region { | |
c40a22e0 BH |
323 | resource_size_t start; |
324 | resource_size_t end; | |
1da177e4 LT |
325 | }; |
326 | ||
327 | struct pci_dynids { | |
328 | spinlock_t lock; /* protects list, index */ | |
329 | struct list_head list; /* for IDs added at runtime */ | |
330 | unsigned int use_driver_data:1; /* pci_driver->driver_data is used */ | |
331 | }; | |
332 | ||
392a1ce7 LV |
333 | /* ---------------------------------------------------------------- */ |
334 | /** PCI Error Recovery System (PCI-ERS). If a PCI device driver provides | |
579082df | 335 | * a set of callbacks in struct pci_error_handlers, then that device driver |
392a1ce7 LV |
336 | * will be notified of PCI bus errors, and will be driven to recovery |
337 | * when an error occurs. | |
338 | */ | |
339 | ||
340 | typedef unsigned int __bitwise pci_ers_result_t; | |
341 | ||
342 | enum pci_ers_result { | |
343 | /* no result/none/not supported in device driver */ | |
344 | PCI_ERS_RESULT_NONE = (__force pci_ers_result_t) 1, | |
345 | ||
346 | /* Device driver can recover without slot reset */ | |
347 | PCI_ERS_RESULT_CAN_RECOVER = (__force pci_ers_result_t) 2, | |
348 | ||
349 | /* Device driver wants slot to be reset. */ | |
350 | PCI_ERS_RESULT_NEED_RESET = (__force pci_ers_result_t) 3, | |
351 | ||
352 | /* Device has completely failed, is unrecoverable */ | |
353 | PCI_ERS_RESULT_DISCONNECT = (__force pci_ers_result_t) 4, | |
354 | ||
355 | /* Device driver is fully recovered and operational */ | |
356 | PCI_ERS_RESULT_RECOVERED = (__force pci_ers_result_t) 5, | |
357 | }; | |
358 | ||
359 | /* PCI bus error event callbacks */ | |
05cca6e5 | 360 | struct pci_error_handlers { |
392a1ce7 LV |
361 | /* PCI bus error detected on this device */ |
362 | pci_ers_result_t (*error_detected)(struct pci_dev *dev, | |
05cca6e5 | 363 | enum pci_channel_state error); |
392a1ce7 LV |
364 | |
365 | /* MMIO has been re-enabled, but not DMA */ | |
366 | pci_ers_result_t (*mmio_enabled)(struct pci_dev *dev); | |
367 | ||
368 | /* PCI Express link has been reset */ | |
369 | pci_ers_result_t (*link_reset)(struct pci_dev *dev); | |
370 | ||
371 | /* PCI slot has been reset */ | |
372 | pci_ers_result_t (*slot_reset)(struct pci_dev *dev); | |
373 | ||
374 | /* Device driver may resume normal operations */ | |
375 | void (*resume)(struct pci_dev *dev); | |
376 | }; | |
377 | ||
378 | /* ---------------------------------------------------------------- */ | |
379 | ||
1da177e4 LT |
380 | struct module; |
381 | struct pci_driver { | |
382 | struct list_head node; | |
383 | char *name; | |
1da177e4 LT |
384 | const struct pci_device_id *id_table; /* must be non-NULL for probe to be called */ |
385 | int (*probe) (struct pci_dev *dev, const struct pci_device_id *id); /* New device inserted */ | |
386 | void (*remove) (struct pci_dev *dev); /* Device removed (NULL if not a hot-plug capable driver) */ | |
387 | int (*suspend) (struct pci_dev *dev, pm_message_t state); /* Device suspended */ | |
cbd69dbb LT |
388 | int (*suspend_late) (struct pci_dev *dev, pm_message_t state); |
389 | int (*resume_early) (struct pci_dev *dev); | |
1da177e4 | 390 | int (*resume) (struct pci_dev *dev); /* Device woken up */ |
c8958177 | 391 | void (*shutdown) (struct pci_dev *dev); |
bbb44d9f | 392 | struct pm_ext_ops *pm; |
392a1ce7 | 393 | struct pci_error_handlers *err_handler; |
1da177e4 LT |
394 | struct device_driver driver; |
395 | struct pci_dynids dynids; | |
396 | }; | |
397 | ||
05cca6e5 | 398 | #define to_pci_driver(drv) container_of(drv, struct pci_driver, driver) |
1da177e4 | 399 | |
90a1ba0c | 400 | /** |
9f9351bb | 401 | * DEFINE_PCI_DEVICE_TABLE - macro used to describe a pci device table |
90a1ba0c JB |
402 | * @_table: device table name |
403 | * | |
404 | * This macro is used to create a struct pci_device_id array (a device table) | |
405 | * in a generic manner. | |
406 | */ | |
9f9351bb | 407 | #define DEFINE_PCI_DEVICE_TABLE(_table) \ |
90a1ba0c JB |
408 | const struct pci_device_id _table[] __devinitconst |
409 | ||
1da177e4 LT |
410 | /** |
411 | * PCI_DEVICE - macro used to describe a specific pci device | |
412 | * @vend: the 16 bit PCI Vendor ID | |
413 | * @dev: the 16 bit PCI Device ID | |
414 | * | |
415 | * This macro is used to create a struct pci_device_id that matches a | |
416 | * specific device. The subvendor and subdevice fields will be set to | |
417 | * PCI_ANY_ID. | |
418 | */ | |
419 | #define PCI_DEVICE(vend,dev) \ | |
420 | .vendor = (vend), .device = (dev), \ | |
421 | .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID | |
422 | ||
423 | /** | |
424 | * PCI_DEVICE_CLASS - macro used to describe a specific pci device class | |
425 | * @dev_class: the class, subclass, prog-if triple for this device | |
426 | * @dev_class_mask: the class mask for this device | |
427 | * | |
428 | * This macro is used to create a struct pci_device_id that matches a | |
4352dfd5 | 429 | * specific PCI class. The vendor, device, subvendor, and subdevice |
1da177e4 LT |
430 | * fields will be set to PCI_ANY_ID. |
431 | */ | |
432 | #define PCI_DEVICE_CLASS(dev_class,dev_class_mask) \ | |
433 | .class = (dev_class), .class_mask = (dev_class_mask), \ | |
434 | .vendor = PCI_ANY_ID, .device = PCI_ANY_ID, \ | |
435 | .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID | |
436 | ||
1597cacb AC |
437 | /** |
438 | * PCI_VDEVICE - macro used to describe a specific pci device in short form | |
439 | * @vend: the vendor name | |
440 | * @dev: the 16 bit PCI Device ID | |
441 | * | |
442 | * This macro is used to create a struct pci_device_id that matches a | |
443 | * specific PCI device. The subvendor, and subdevice fields will be set | |
444 | * to PCI_ANY_ID. The macro allows the next field to follow as the device | |
445 | * private data. | |
446 | */ | |
447 | ||
448 | #define PCI_VDEVICE(vendor, device) \ | |
449 | PCI_VENDOR_ID_##vendor, (device), \ | |
450 | PCI_ANY_ID, PCI_ANY_ID, 0, 0 | |
451 | ||
1da177e4 LT |
452 | /* these external functions are only available when PCI support is enabled */ |
453 | #ifdef CONFIG_PCI | |
454 | ||
455 | extern struct bus_type pci_bus_type; | |
456 | ||
457 | /* Do NOT directly access these two variables, unless you are arch specific pci | |
458 | * code, or pci core code. */ | |
459 | extern struct list_head pci_root_buses; /* list of all known PCI buses */ | |
ed4aaadb ZY |
460 | /* Some device drivers need know if pci is initiated */ |
461 | extern int no_pci_devices(void); | |
1da177e4 LT |
462 | |
463 | void pcibios_fixup_bus(struct pci_bus *); | |
4a7fb636 | 464 | int __must_check pcibios_enable_device(struct pci_dev *, int mask); |
05cca6e5 | 465 | char *pcibios_setup(char *str); |
1da177e4 LT |
466 | |
467 | /* Used only when drivers/pci/setup.c is used */ | |
e31dd6e4 GKH |
468 | void pcibios_align_resource(void *, struct resource *, resource_size_t, |
469 | resource_size_t); | |
1da177e4 LT |
470 | void pcibios_update_irq(struct pci_dev *, int irq); |
471 | ||
472 | /* Generic PCI functions used internally */ | |
473 | ||
474 | extern struct pci_bus *pci_find_bus(int domain, int busnr); | |
c431ada4 | 475 | void pci_bus_add_devices(struct pci_bus *bus); |
05cca6e5 GKH |
476 | struct pci_bus *pci_scan_bus_parented(struct device *parent, int bus, |
477 | struct pci_ops *ops, void *sysdata); | |
98db6f19 | 478 | static inline struct pci_bus * __devinit pci_scan_bus(int bus, struct pci_ops *ops, |
05cca6e5 | 479 | void *sysdata) |
1da177e4 | 480 | { |
c431ada4 RS |
481 | struct pci_bus *root_bus; |
482 | root_bus = pci_scan_bus_parented(NULL, bus, ops, sysdata); | |
483 | if (root_bus) | |
484 | pci_bus_add_devices(root_bus); | |
485 | return root_bus; | |
1da177e4 | 486 | } |
05cca6e5 GKH |
487 | struct pci_bus *pci_create_bus(struct device *parent, int bus, |
488 | struct pci_ops *ops, void *sysdata); | |
489 | struct pci_bus *pci_add_new_bus(struct pci_bus *parent, struct pci_dev *dev, | |
490 | int busnr); | |
1da177e4 | 491 | int pci_scan_slot(struct pci_bus *bus, int devfn); |
05cca6e5 | 492 | struct pci_dev *pci_scan_single_device(struct pci_bus *bus, int devfn); |
cdb9b9f7 | 493 | void pci_device_add(struct pci_dev *dev, struct pci_bus *bus); |
1da177e4 | 494 | unsigned int pci_scan_child_bus(struct pci_bus *bus); |
b19441af | 495 | int __must_check pci_bus_add_device(struct pci_dev *dev); |
1da177e4 | 496 | void pci_read_bridge_bases(struct pci_bus *child); |
05cca6e5 GKH |
497 | struct resource *pci_find_parent_resource(const struct pci_dev *dev, |
498 | struct resource *res); | |
1da177e4 LT |
499 | int pci_get_interrupt_pin(struct pci_dev *dev, struct pci_dev **bridge); |
500 | extern struct pci_dev *pci_dev_get(struct pci_dev *dev); | |
501 | extern void pci_dev_put(struct pci_dev *dev); | |
502 | extern void pci_remove_bus(struct pci_bus *b); | |
503 | extern void pci_remove_bus_device(struct pci_dev *dev); | |
24f8aa9b | 504 | extern void pci_stop_bus_device(struct pci_dev *dev); |
b3743fa4 | 505 | void pci_setup_cardbus(struct pci_bus *bus); |
6b4b78fe | 506 | extern void pci_sort_breadthfirst(void); |
1da177e4 LT |
507 | |
508 | /* Generic PCI functions exported to card drivers */ | |
509 | ||
bd3989e0 | 510 | #ifdef CONFIG_PCI_LEGACY |
05cca6e5 GKH |
511 | struct pci_dev __deprecated *pci_find_device(unsigned int vendor, |
512 | unsigned int device, | |
513 | const struct pci_dev *from); | |
514 | struct pci_dev __deprecated *pci_find_slot(unsigned int bus, | |
515 | unsigned int devfn); | |
bd3989e0 JG |
516 | #endif /* CONFIG_PCI_LEGACY */ |
517 | ||
05cca6e5 GKH |
518 | int pci_find_capability(struct pci_dev *dev, int cap); |
519 | int pci_find_next_capability(struct pci_dev *dev, u8 pos, int cap); | |
520 | int pci_find_ext_capability(struct pci_dev *dev, int cap); | |
521 | int pci_find_ht_capability(struct pci_dev *dev, int ht_cap); | |
522 | int pci_find_next_ht_capability(struct pci_dev *dev, int pos, int ht_cap); | |
29f3eb64 | 523 | struct pci_bus *pci_find_next_bus(const struct pci_bus *from); |
1da177e4 | 524 | |
d42552c3 AM |
525 | struct pci_dev *pci_get_device(unsigned int vendor, unsigned int device, |
526 | struct pci_dev *from); | |
05cca6e5 | 527 | struct pci_dev *pci_get_subsys(unsigned int vendor, unsigned int device, |
1da177e4 | 528 | unsigned int ss_vendor, unsigned int ss_device, |
95247b57 | 529 | const struct pci_dev *from); |
05cca6e5 GKH |
530 | struct pci_dev *pci_get_slot(struct pci_bus *bus, unsigned int devfn); |
531 | struct pci_dev *pci_get_bus_and_slot(unsigned int bus, unsigned int devfn); | |
532 | struct pci_dev *pci_get_class(unsigned int class, struct pci_dev *from); | |
1da177e4 LT |
533 | int pci_dev_present(const struct pci_device_id *ids); |
534 | ||
05cca6e5 GKH |
535 | int pci_bus_read_config_byte(struct pci_bus *bus, unsigned int devfn, |
536 | int where, u8 *val); | |
537 | int pci_bus_read_config_word(struct pci_bus *bus, unsigned int devfn, | |
538 | int where, u16 *val); | |
539 | int pci_bus_read_config_dword(struct pci_bus *bus, unsigned int devfn, | |
540 | int where, u32 *val); | |
541 | int pci_bus_write_config_byte(struct pci_bus *bus, unsigned int devfn, | |
542 | int where, u8 val); | |
543 | int pci_bus_write_config_word(struct pci_bus *bus, unsigned int devfn, | |
544 | int where, u16 val); | |
545 | int pci_bus_write_config_dword(struct pci_bus *bus, unsigned int devfn, | |
546 | int where, u32 val); | |
1da177e4 LT |
547 | |
548 | static inline int pci_read_config_byte(struct pci_dev *dev, int where, u8 *val) | |
549 | { | |
05cca6e5 | 550 | return pci_bus_read_config_byte(dev->bus, dev->devfn, where, val); |
1da177e4 LT |
551 | } |
552 | static inline int pci_read_config_word(struct pci_dev *dev, int where, u16 *val) | |
553 | { | |
05cca6e5 | 554 | return pci_bus_read_config_word(dev->bus, dev->devfn, where, val); |
1da177e4 | 555 | } |
05cca6e5 GKH |
556 | static inline int pci_read_config_dword(struct pci_dev *dev, int where, |
557 | u32 *val) | |
1da177e4 | 558 | { |
05cca6e5 | 559 | return pci_bus_read_config_dword(dev->bus, dev->devfn, where, val); |
1da177e4 LT |
560 | } |
561 | static inline int pci_write_config_byte(struct pci_dev *dev, int where, u8 val) | |
562 | { | |
05cca6e5 | 563 | return pci_bus_write_config_byte(dev->bus, dev->devfn, where, val); |
1da177e4 LT |
564 | } |
565 | static inline int pci_write_config_word(struct pci_dev *dev, int where, u16 val) | |
566 | { | |
05cca6e5 | 567 | return pci_bus_write_config_word(dev->bus, dev->devfn, where, val); |
1da177e4 | 568 | } |
05cca6e5 GKH |
569 | static inline int pci_write_config_dword(struct pci_dev *dev, int where, |
570 | u32 val) | |
1da177e4 | 571 | { |
05cca6e5 | 572 | return pci_bus_write_config_dword(dev->bus, dev->devfn, where, val); |
1da177e4 LT |
573 | } |
574 | ||
4a7fb636 | 575 | int __must_check pci_enable_device(struct pci_dev *dev); |
b718989d BH |
576 | int __must_check pci_enable_device_io(struct pci_dev *dev); |
577 | int __must_check pci_enable_device_mem(struct pci_dev *dev); | |
0b62e13b | 578 | int __must_check pci_reenable_device(struct pci_dev *); |
9ac7849e TH |
579 | int __must_check pcim_enable_device(struct pci_dev *pdev); |
580 | void pcim_pin_device(struct pci_dev *pdev); | |
581 | ||
582 | static inline int pci_is_managed(struct pci_dev *pdev) | |
583 | { | |
584 | return pdev->is_managed; | |
585 | } | |
586 | ||
1da177e4 LT |
587 | void pci_disable_device(struct pci_dev *dev); |
588 | void pci_set_master(struct pci_dev *dev); | |
f7bdd12d | 589 | int pci_set_pcie_reset_state(struct pci_dev *dev, enum pcie_reset_state state); |
1da177e4 | 590 | #define HAVE_PCI_SET_MWI |
4a7fb636 | 591 | int __must_check pci_set_mwi(struct pci_dev *dev); |
694625c0 | 592 | int pci_try_set_mwi(struct pci_dev *dev); |
1da177e4 | 593 | void pci_clear_mwi(struct pci_dev *dev); |
a04ce0ff | 594 | void pci_intx(struct pci_dev *dev, int enable); |
f5f2b131 | 595 | void pci_msi_off(struct pci_dev *dev); |
9c8550ee LT |
596 | int pci_set_dma_mask(struct pci_dev *dev, u64 mask); |
597 | int pci_set_consistent_dma_mask(struct pci_dev *dev, u64 mask); | |
4d57cdfa | 598 | int pci_set_dma_max_seg_size(struct pci_dev *dev, unsigned int size); |
59fc67de | 599 | int pci_set_dma_seg_boundary(struct pci_dev *dev, unsigned long mask); |
d556ad4b PO |
600 | int pcix_get_max_mmrbc(struct pci_dev *dev); |
601 | int pcix_get_mmrbc(struct pci_dev *dev); | |
602 | int pcix_set_mmrbc(struct pci_dev *dev, int mmrbc); | |
2637e5b5 | 603 | int pcie_get_readrq(struct pci_dev *dev); |
d556ad4b | 604 | int pcie_set_readrq(struct pci_dev *dev, int rq); |
064b53db | 605 | void pci_update_resource(struct pci_dev *dev, struct resource *res, int resno); |
4a7fb636 | 606 | int __must_check pci_assign_resource(struct pci_dev *dev, int i); |
c87deff7 | 607 | int pci_select_bars(struct pci_dev *dev, unsigned long flags); |
1da177e4 LT |
608 | |
609 | /* ROM control related routines */ | |
144a50ea | 610 | void __iomem __must_check *pci_map_rom(struct pci_dev *pdev, size_t *size); |
1da177e4 | 611 | void pci_unmap_rom(struct pci_dev *pdev, void __iomem *rom); |
d7ad2254 | 612 | size_t pci_get_rom_size(void __iomem *rom, size_t size); |
1da177e4 LT |
613 | |
614 | /* Power management related routines */ | |
615 | int pci_save_state(struct pci_dev *dev); | |
616 | int pci_restore_state(struct pci_dev *dev); | |
9c8550ee LT |
617 | int pci_set_power_state(struct pci_dev *dev, pci_power_t state); |
618 | pci_power_t pci_choose_state(struct pci_dev *dev, pm_message_t state); | |
619 | int pci_enable_wake(struct pci_dev *dev, pci_power_t state, int enable); | |
1da177e4 | 620 | |
ce5ccdef | 621 | /* Functions for PCI Hotplug drivers to use */ |
05cca6e5 | 622 | int pci_bus_find_capability(struct pci_bus *bus, unsigned int devfn, int cap); |
ce5ccdef | 623 | |
1da177e4 LT |
624 | /* Helper functions for low-level code (drivers/pci/setup-[bus,res].c) */ |
625 | void pci_bus_assign_resources(struct pci_bus *bus); | |
626 | void pci_bus_size_bridges(struct pci_bus *bus); | |
627 | int pci_claim_resource(struct pci_dev *, int); | |
628 | void pci_assign_unassigned_resources(void); | |
629 | void pdev_enable_device(struct pci_dev *); | |
630 | void pdev_sort_resources(struct pci_dev *, struct resource_list *); | |
842de40d | 631 | int pci_enable_resources(struct pci_dev *, int mask); |
1da177e4 LT |
632 | void pci_fixup_irqs(u8 (*)(struct pci_dev *, u8 *), |
633 | int (*)(struct pci_dev *, u8, u8)); | |
634 | #define HAVE_PCI_REQ_REGIONS 2 | |
4a7fb636 | 635 | int __must_check pci_request_regions(struct pci_dev *, const char *); |
1da177e4 | 636 | void pci_release_regions(struct pci_dev *); |
4a7fb636 | 637 | int __must_check pci_request_region(struct pci_dev *, int, const char *); |
1da177e4 | 638 | void pci_release_region(struct pci_dev *, int); |
c87deff7 HS |
639 | int pci_request_selected_regions(struct pci_dev *, int, const char *); |
640 | void pci_release_selected_regions(struct pci_dev *, int); | |
1da177e4 LT |
641 | |
642 | /* drivers/pci/bus.c */ | |
4a7fb636 AM |
643 | int __must_check pci_bus_alloc_resource(struct pci_bus *bus, |
644 | struct resource *res, resource_size_t size, | |
645 | resource_size_t align, resource_size_t min, | |
646 | unsigned int type_mask, | |
647 | void (*alignf)(void *, struct resource *, | |
648 | resource_size_t, resource_size_t), | |
649 | void *alignf_data); | |
1da177e4 LT |
650 | void pci_enable_bridges(struct pci_bus *bus); |
651 | ||
863b18f4 | 652 | /* Proper probing supporting hot-pluggable devices */ |
725522b5 GKH |
653 | int __must_check __pci_register_driver(struct pci_driver *, struct module *, |
654 | const char *mod_name); | |
4a7fb636 | 655 | static inline int __must_check pci_register_driver(struct pci_driver *driver) |
863b18f4 | 656 | { |
725522b5 | 657 | return __pci_register_driver(driver, THIS_MODULE, KBUILD_MODNAME); |
863b18f4 L |
658 | } |
659 | ||
05cca6e5 GKH |
660 | void pci_unregister_driver(struct pci_driver *dev); |
661 | void pci_remove_behind_bridge(struct pci_dev *dev); | |
662 | struct pci_driver *pci_dev_driver(const struct pci_dev *dev); | |
663 | const struct pci_device_id *pci_match_id(const struct pci_device_id *ids, | |
664 | struct pci_dev *dev); | |
665 | int pci_scan_bridge(struct pci_bus *bus, struct pci_dev *dev, int max, | |
666 | int pass); | |
1da177e4 | 667 | |
cecf4864 PM |
668 | void pci_walk_bus(struct pci_bus *top, void (*cb)(struct pci_dev *, void *), |
669 | void *userdata); | |
70b9f7dc | 670 | int pci_cfg_space_size_ext(struct pci_dev *dev); |
ac7dc65a | 671 | int pci_cfg_space_size(struct pci_dev *dev); |
05cca6e5 | 672 | unsigned char pci_bus_max_busnr(struct pci_bus *bus); |
cecf4864 | 673 | |
1da177e4 LT |
674 | /* kmem_cache style wrapper around pci_alloc_consistent() */ |
675 | ||
676 | #include <linux/dmapool.h> | |
677 | ||
678 | #define pci_pool dma_pool | |
679 | #define pci_pool_create(name, pdev, size, align, allocation) \ | |
680 | dma_pool_create(name, &pdev->dev, size, align, allocation) | |
681 | #define pci_pool_destroy(pool) dma_pool_destroy(pool) | |
682 | #define pci_pool_alloc(pool, flags, handle) dma_pool_alloc(pool, flags, handle) | |
683 | #define pci_pool_free(pool, vaddr, addr) dma_pool_free(pool, vaddr, addr) | |
684 | ||
e24c2d96 DM |
685 | enum pci_dma_burst_strategy { |
686 | PCI_DMA_BURST_INFINITY, /* make bursts as large as possible, | |
687 | strategy_parameter is N/A */ | |
688 | PCI_DMA_BURST_BOUNDARY, /* disconnect at every strategy_parameter | |
689 | byte boundaries */ | |
690 | PCI_DMA_BURST_MULTIPLE, /* disconnect at some multiple of | |
691 | strategy_parameter byte boundaries */ | |
692 | }; | |
693 | ||
1da177e4 LT |
694 | struct msix_entry { |
695 | u16 vector; /* kernel uses to write allocated vector */ | |
696 | u16 entry; /* driver uses to specify entry, OS writes */ | |
697 | }; | |
698 | ||
0366f8f7 | 699 | |
1da177e4 | 700 | #ifndef CONFIG_PCI_MSI |
05cca6e5 GKH |
701 | static inline int pci_enable_msi(struct pci_dev *dev) |
702 | { | |
703 | return -1; | |
704 | } | |
705 | ||
d52877c7 YL |
706 | static inline void pci_msi_shutdown(struct pci_dev *dev) |
707 | { } | |
05cca6e5 GKH |
708 | static inline void pci_disable_msi(struct pci_dev *dev) |
709 | { } | |
710 | ||
711 | static inline int pci_enable_msix(struct pci_dev *dev, | |
712 | struct msix_entry *entries, int nvec) | |
713 | { | |
714 | return -1; | |
715 | } | |
716 | ||
d52877c7 YL |
717 | static inline void pci_msix_shutdown(struct pci_dev *dev) |
718 | { } | |
05cca6e5 GKH |
719 | static inline void pci_disable_msix(struct pci_dev *dev) |
720 | { } | |
721 | ||
722 | static inline void msi_remove_pci_irq_vectors(struct pci_dev *dev) | |
723 | { } | |
724 | ||
725 | static inline void pci_restore_msi_state(struct pci_dev *dev) | |
726 | { } | |
1da177e4 | 727 | #else |
1da177e4 | 728 | extern int pci_enable_msi(struct pci_dev *dev); |
d52877c7 | 729 | extern void pci_msi_shutdown(struct pci_dev *dev); |
1da177e4 | 730 | extern void pci_disable_msi(struct pci_dev *dev); |
05cca6e5 | 731 | extern int pci_enable_msix(struct pci_dev *dev, |
1da177e4 | 732 | struct msix_entry *entries, int nvec); |
d52877c7 | 733 | extern void pci_msix_shutdown(struct pci_dev *dev); |
1da177e4 LT |
734 | extern void pci_disable_msix(struct pci_dev *dev); |
735 | extern void msi_remove_pci_irq_vectors(struct pci_dev *dev); | |
94688cf2 | 736 | extern void pci_restore_msi_state(struct pci_dev *dev); |
1da177e4 LT |
737 | #endif |
738 | ||
8b955b0d | 739 | #ifdef CONFIG_HT_IRQ |
8b955b0d EB |
740 | /* The functions a driver should call */ |
741 | int ht_create_irq(struct pci_dev *dev, int idx); | |
742 | void ht_destroy_irq(unsigned int irq); | |
8b955b0d EB |
743 | #endif /* CONFIG_HT_IRQ */ |
744 | ||
e04b0ea2 BK |
745 | extern void pci_block_user_cfg_access(struct pci_dev *dev); |
746 | extern void pci_unblock_user_cfg_access(struct pci_dev *dev); | |
747 | ||
4352dfd5 GKH |
748 | /* |
749 | * PCI domain support. Sometimes called PCI segment (eg by ACPI), | |
750 | * a PCI domain is defined to be a set of PCI busses which share | |
751 | * configuration space. | |
752 | */ | |
32a2eea7 JG |
753 | #ifdef CONFIG_PCI_DOMAINS |
754 | extern int pci_domains_supported; | |
755 | #else | |
756 | enum { pci_domains_supported = 0 }; | |
05cca6e5 GKH |
757 | static inline int pci_domain_nr(struct pci_bus *bus) |
758 | { | |
759 | return 0; | |
760 | } | |
761 | ||
4352dfd5 GKH |
762 | static inline int pci_proc_domain(struct pci_bus *bus) |
763 | { | |
764 | return 0; | |
765 | } | |
32a2eea7 | 766 | #endif /* CONFIG_PCI_DOMAINS */ |
1da177e4 | 767 | |
4352dfd5 | 768 | #else /* CONFIG_PCI is not enabled */ |
1da177e4 LT |
769 | |
770 | /* | |
771 | * If the system does not have PCI, clearly these return errors. Define | |
772 | * these as simple inline functions to avoid hair in drivers. | |
773 | */ | |
774 | ||
05cca6e5 GKH |
775 | #define _PCI_NOP(o, s, t) \ |
776 | static inline int pci_##o##_config_##s(struct pci_dev *dev, \ | |
777 | int where, t val) \ | |
1da177e4 | 778 | { return PCIBIOS_FUNC_NOT_SUPPORTED; } |
05cca6e5 GKH |
779 | |
780 | #define _PCI_NOP_ALL(o, x) _PCI_NOP(o, byte, u8 x) \ | |
781 | _PCI_NOP(o, word, u16 x) \ | |
782 | _PCI_NOP(o, dword, u32 x) | |
1da177e4 LT |
783 | _PCI_NOP_ALL(read, *) |
784 | _PCI_NOP_ALL(write,) | |
785 | ||
05cca6e5 GKH |
786 | static inline struct pci_dev *pci_find_device(unsigned int vendor, |
787 | unsigned int device, | |
788 | const struct pci_dev *from) | |
789 | { | |
790 | return NULL; | |
791 | } | |
1da177e4 | 792 | |
05cca6e5 GKH |
793 | static inline struct pci_dev *pci_find_slot(unsigned int bus, |
794 | unsigned int devfn) | |
795 | { | |
796 | return NULL; | |
797 | } | |
1da177e4 | 798 | |
d42552c3 | 799 | static inline struct pci_dev *pci_get_device(unsigned int vendor, |
05cca6e5 GKH |
800 | unsigned int device, |
801 | struct pci_dev *from) | |
802 | { | |
803 | return NULL; | |
804 | } | |
d42552c3 | 805 | |
05cca6e5 GKH |
806 | static inline struct pci_dev *pci_get_subsys(unsigned int vendor, |
807 | unsigned int device, | |
808 | unsigned int ss_vendor, | |
809 | unsigned int ss_device, | |
95247b57 | 810 | const struct pci_dev *from) |
05cca6e5 GKH |
811 | { |
812 | return NULL; | |
813 | } | |
1da177e4 | 814 | |
05cca6e5 GKH |
815 | static inline struct pci_dev *pci_get_class(unsigned int class, |
816 | struct pci_dev *from) | |
817 | { | |
818 | return NULL; | |
819 | } | |
1da177e4 LT |
820 | |
821 | #define pci_dev_present(ids) (0) | |
ed4aaadb | 822 | #define no_pci_devices() (1) |
1da177e4 LT |
823 | #define pci_dev_put(dev) do { } while (0) |
824 | ||
05cca6e5 GKH |
825 | static inline void pci_set_master(struct pci_dev *dev) |
826 | { } | |
827 | ||
828 | static inline int pci_enable_device(struct pci_dev *dev) | |
829 | { | |
830 | return -EIO; | |
831 | } | |
832 | ||
833 | static inline void pci_disable_device(struct pci_dev *dev) | |
834 | { } | |
835 | ||
836 | static inline int pci_set_dma_mask(struct pci_dev *dev, u64 mask) | |
837 | { | |
838 | return -EIO; | |
839 | } | |
840 | ||
4d57cdfa FT |
841 | static inline int pci_set_dma_max_seg_size(struct pci_dev *dev, |
842 | unsigned int size) | |
843 | { | |
844 | return -EIO; | |
845 | } | |
846 | ||
59fc67de FT |
847 | static inline int pci_set_dma_seg_boundary(struct pci_dev *dev, |
848 | unsigned long mask) | |
849 | { | |
850 | return -EIO; | |
851 | } | |
852 | ||
05cca6e5 GKH |
853 | static inline int pci_assign_resource(struct pci_dev *dev, int i) |
854 | { | |
855 | return -EBUSY; | |
856 | } | |
857 | ||
858 | static inline int __pci_register_driver(struct pci_driver *drv, | |
859 | struct module *owner) | |
860 | { | |
861 | return 0; | |
862 | } | |
863 | ||
864 | static inline int pci_register_driver(struct pci_driver *drv) | |
865 | { | |
866 | return 0; | |
867 | } | |
868 | ||
869 | static inline void pci_unregister_driver(struct pci_driver *drv) | |
870 | { } | |
871 | ||
872 | static inline int pci_find_capability(struct pci_dev *dev, int cap) | |
873 | { | |
874 | return 0; | |
875 | } | |
876 | ||
877 | static inline int pci_find_next_capability(struct pci_dev *dev, u8 post, | |
878 | int cap) | |
879 | { | |
880 | return 0; | |
881 | } | |
882 | ||
883 | static inline int pci_find_ext_capability(struct pci_dev *dev, int cap) | |
884 | { | |
885 | return 0; | |
886 | } | |
887 | ||
1da177e4 | 888 | /* Power management related routines */ |
05cca6e5 GKH |
889 | static inline int pci_save_state(struct pci_dev *dev) |
890 | { | |
891 | return 0; | |
892 | } | |
893 | ||
894 | static inline int pci_restore_state(struct pci_dev *dev) | |
895 | { | |
896 | return 0; | |
897 | } | |
1da177e4 | 898 | |
05cca6e5 GKH |
899 | static inline int pci_set_power_state(struct pci_dev *dev, pci_power_t state) |
900 | { | |
901 | return 0; | |
902 | } | |
903 | ||
904 | static inline pci_power_t pci_choose_state(struct pci_dev *dev, | |
905 | pm_message_t state) | |
906 | { | |
907 | return PCI_D0; | |
908 | } | |
909 | ||
910 | static inline int pci_enable_wake(struct pci_dev *dev, pci_power_t state, | |
911 | int enable) | |
912 | { | |
913 | return 0; | |
914 | } | |
915 | ||
916 | static inline int pci_request_regions(struct pci_dev *dev, const char *res_name) | |
917 | { | |
918 | return -EIO; | |
919 | } | |
920 | ||
921 | static inline void pci_release_regions(struct pci_dev *dev) | |
922 | { } | |
0da0ead9 | 923 | |
a46e8126 KG |
924 | #define pci_dma_burst_advice(pdev, strat, strategy_parameter) do { } while (0) |
925 | ||
05cca6e5 GKH |
926 | static inline void pci_block_user_cfg_access(struct pci_dev *dev) |
927 | { } | |
928 | ||
929 | static inline void pci_unblock_user_cfg_access(struct pci_dev *dev) | |
930 | { } | |
e04b0ea2 | 931 | |
d80d0217 RD |
932 | static inline struct pci_bus *pci_find_next_bus(const struct pci_bus *from) |
933 | { return NULL; } | |
934 | ||
935 | static inline struct pci_dev *pci_get_slot(struct pci_bus *bus, | |
936 | unsigned int devfn) | |
937 | { return NULL; } | |
938 | ||
939 | static inline struct pci_dev *pci_get_bus_and_slot(unsigned int bus, | |
940 | unsigned int devfn) | |
941 | { return NULL; } | |
942 | ||
4352dfd5 | 943 | #endif /* CONFIG_PCI */ |
1da177e4 | 944 | |
4352dfd5 GKH |
945 | /* Include architecture-dependent settings and functions */ |
946 | ||
947 | #include <asm/pci.h> | |
1da177e4 LT |
948 | |
949 | /* these helpers provide future and backwards compatibility | |
950 | * for accessing popular PCI BAR info */ | |
05cca6e5 GKH |
951 | #define pci_resource_start(dev, bar) ((dev)->resource[(bar)].start) |
952 | #define pci_resource_end(dev, bar) ((dev)->resource[(bar)].end) | |
953 | #define pci_resource_flags(dev, bar) ((dev)->resource[(bar)].flags) | |
1da177e4 | 954 | #define pci_resource_len(dev,bar) \ |
05cca6e5 GKH |
955 | ((pci_resource_start((dev), (bar)) == 0 && \ |
956 | pci_resource_end((dev), (bar)) == \ | |
957 | pci_resource_start((dev), (bar))) ? 0 : \ | |
958 | \ | |
959 | (pci_resource_end((dev), (bar)) - \ | |
960 | pci_resource_start((dev), (bar)) + 1)) | |
1da177e4 LT |
961 | |
962 | /* Similar to the helpers above, these manipulate per-pci_dev | |
963 | * driver-specific data. They are really just a wrapper around | |
964 | * the generic device structure functions of these calls. | |
965 | */ | |
05cca6e5 | 966 | static inline void *pci_get_drvdata(struct pci_dev *pdev) |
1da177e4 LT |
967 | { |
968 | return dev_get_drvdata(&pdev->dev); | |
969 | } | |
970 | ||
05cca6e5 | 971 | static inline void pci_set_drvdata(struct pci_dev *pdev, void *data) |
1da177e4 LT |
972 | { |
973 | dev_set_drvdata(&pdev->dev, data); | |
974 | } | |
975 | ||
976 | /* If you want to know what to call your pci_dev, ask this function. | |
977 | * Again, it's a wrapper around the generic device. | |
978 | */ | |
979 | static inline char *pci_name(struct pci_dev *pdev) | |
980 | { | |
981 | return pdev->dev.bus_id; | |
982 | } | |
983 | ||
2311b1f2 ME |
984 | |
985 | /* Some archs don't want to expose struct resource to userland as-is | |
986 | * in sysfs and /proc | |
987 | */ | |
988 | #ifndef HAVE_ARCH_PCI_RESOURCE_TO_USER | |
989 | static inline void pci_resource_to_user(const struct pci_dev *dev, int bar, | |
05cca6e5 | 990 | const struct resource *rsrc, resource_size_t *start, |
e31dd6e4 | 991 | resource_size_t *end) |
2311b1f2 ME |
992 | { |
993 | *start = rsrc->start; | |
994 | *end = rsrc->end; | |
995 | } | |
996 | #endif /* HAVE_ARCH_PCI_RESOURCE_TO_USER */ | |
997 | ||
998 | ||
1da177e4 LT |
999 | /* |
1000 | * The world is not perfect and supplies us with broken PCI devices. | |
1001 | * For at least a part of these bugs we need a work-around, so both | |
1002 | * generic (drivers/pci/quirks.c) and per-architecture code can define | |
1003 | * fixup hooks to be called for particular buggy devices. | |
1004 | */ | |
1005 | ||
1006 | struct pci_fixup { | |
1007 | u16 vendor, device; /* You can use PCI_ANY_ID here of course */ | |
1008 | void (*hook)(struct pci_dev *dev); | |
1009 | }; | |
1010 | ||
1011 | enum pci_fixup_pass { | |
1012 | pci_fixup_early, /* Before probing BARs */ | |
1013 | pci_fixup_header, /* After reading configuration header */ | |
1014 | pci_fixup_final, /* Final phase of device fixups */ | |
1015 | pci_fixup_enable, /* pci_enable_device() time */ | |
e1a2a51e RW |
1016 | pci_fixup_resume, /* pci_device_resume() */ |
1017 | pci_fixup_suspend, /* pci_device_suspend */ | |
1018 | pci_fixup_resume_early, /* pci_device_resume_early() */ | |
1da177e4 LT |
1019 | }; |
1020 | ||
1021 | /* Anonymous variables would be nice... */ | |
1022 | #define DECLARE_PCI_FIXUP_SECTION(section, name, vendor, device, hook) \ | |
3ff6eecc | 1023 | static const struct pci_fixup __pci_fixup_##name __used \ |
1da177e4 LT |
1024 | __attribute__((__section__(#section))) = { vendor, device, hook }; |
1025 | #define DECLARE_PCI_FIXUP_EARLY(vendor, device, hook) \ | |
1026 | DECLARE_PCI_FIXUP_SECTION(.pci_fixup_early, \ | |
1027 | vendor##device##hook, vendor, device, hook) | |
1028 | #define DECLARE_PCI_FIXUP_HEADER(vendor, device, hook) \ | |
1029 | DECLARE_PCI_FIXUP_SECTION(.pci_fixup_header, \ | |
1030 | vendor##device##hook, vendor, device, hook) | |
1031 | #define DECLARE_PCI_FIXUP_FINAL(vendor, device, hook) \ | |
1032 | DECLARE_PCI_FIXUP_SECTION(.pci_fixup_final, \ | |
1033 | vendor##device##hook, vendor, device, hook) | |
1034 | #define DECLARE_PCI_FIXUP_ENABLE(vendor, device, hook) \ | |
1035 | DECLARE_PCI_FIXUP_SECTION(.pci_fixup_enable, \ | |
1036 | vendor##device##hook, vendor, device, hook) | |
1597cacb AC |
1037 | #define DECLARE_PCI_FIXUP_RESUME(vendor, device, hook) \ |
1038 | DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume, \ | |
1039 | resume##vendor##device##hook, vendor, device, hook) | |
e1a2a51e RW |
1040 | #define DECLARE_PCI_FIXUP_RESUME_EARLY(vendor, device, hook) \ |
1041 | DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume_early, \ | |
1042 | resume_early##vendor##device##hook, vendor, device, hook) | |
1043 | #define DECLARE_PCI_FIXUP_SUSPEND(vendor, device, hook) \ | |
1044 | DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend, \ | |
1045 | suspend##vendor##device##hook, vendor, device, hook) | |
1da177e4 LT |
1046 | |
1047 | ||
1048 | void pci_fixup_device(enum pci_fixup_pass pass, struct pci_dev *dev); | |
1049 | ||
05cca6e5 | 1050 | void __iomem *pcim_iomap(struct pci_dev *pdev, int bar, unsigned long maxlen); |
5ea81769 | 1051 | void pcim_iounmap(struct pci_dev *pdev, void __iomem *addr); |
05cca6e5 | 1052 | void __iomem * const *pcim_iomap_table(struct pci_dev *pdev); |
5ea81769 | 1053 | int pcim_iomap_regions(struct pci_dev *pdev, u16 mask, const char *name); |
916fbfb7 TH |
1054 | int pcim_iomap_regions_request_all(struct pci_dev *pdev, u16 mask, |
1055 | const char *name); | |
ec04b075 | 1056 | void pcim_iounmap_regions(struct pci_dev *pdev, u16 mask); |
5ea81769 | 1057 | |
1da177e4 | 1058 | extern int pci_pci_problems; |
236561e5 | 1059 | #define PCIPCI_FAIL 1 /* No PCI PCI DMA */ |
1da177e4 LT |
1060 | #define PCIPCI_TRITON 2 |
1061 | #define PCIPCI_NATOMA 4 | |
1062 | #define PCIPCI_VIAETBF 8 | |
1063 | #define PCIPCI_VSFX 16 | |
236561e5 AC |
1064 | #define PCIPCI_ALIMAGIK 32 /* Need low latency setting */ |
1065 | #define PCIAGP_FAIL 64 /* No PCI to AGP DMA */ | |
1da177e4 | 1066 | |
4516a618 AN |
1067 | extern unsigned long pci_cardbus_io_size; |
1068 | extern unsigned long pci_cardbus_mem_size; | |
1069 | ||
19792a08 AB |
1070 | int pcibios_add_platform_entries(struct pci_dev *dev); |
1071 | void pcibios_disable_device(struct pci_dev *dev); | |
1072 | int pcibios_set_pcie_reset_state(struct pci_dev *dev, | |
1073 | enum pcie_reset_state state); | |
575e3348 | 1074 | |
7752d5cf | 1075 | #ifdef CONFIG_PCI_MMCONFIG |
bb63b421 | 1076 | extern void __init pci_mmcfg_early_init(void); |
7752d5cf RH |
1077 | extern void __init pci_mmcfg_late_init(void); |
1078 | #else | |
bb63b421 | 1079 | static inline void pci_mmcfg_early_init(void) { } |
7752d5cf RH |
1080 | static inline void pci_mmcfg_late_init(void) { } |
1081 | #endif | |
1082 | ||
1da177e4 LT |
1083 | #endif /* __KERNEL__ */ |
1084 | #endif /* LINUX_PCI_H */ |