[mirror_ubuntu-artful-kernel.git] / include / linux / perf / arm_pmu.h

/*
 *  linux/arch/arm/include/asm/pmu.h
 *
 *  Copyright (C) 2009 picoChip Designs Ltd, Jamie Iles
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 *
 */

#ifndef __ARM_PMU_H__
#define __ARM_PMU_H__

#include <linux/interrupt.h>
#include <linux/perf_event.h>
#include <linux/sysfs.h>
#include <asm/cputype.h>

/*
 * struct arm_pmu_platdata - ARM PMU platform data
 *
 * @handle_irq: an optional handler which will be called from the
 *	interrupt and passed the address of the low level handler,
 *	and can be used to implement any platform specific handling
 *	before or after calling it.
 *
 * @irq_flags: if non-zero, these flags will be passed to request_irq
 *             when requesting interrupts for this PMU device.
 */
struct arm_pmu_platdata {
	irqreturn_t (*handle_irq)(int irq, void *dev,
				  irq_handler_t pmu_handler);
	unsigned long irq_flags;
};

#ifdef CONFIG_ARM_PMU

/*
 * The ARMv7 CPU PMU supports up to 32 event counters.
 */
#define ARMPMU_MAX_HWEVENTS		32

#define HW_OP_UNSUPPORTED		0xFFFF
#define C(_x)				PERF_COUNT_HW_CACHE_##_x
#define CACHE_OP_UNSUPPORTED		0xFFFF

#define PERF_MAP_ALL_UNSUPPORTED					\
	[0 ... PERF_COUNT_HW_MAX - 1] = HW_OP_UNSUPPORTED

#define PERF_CACHE_MAP_ALL_UNSUPPORTED					\
[0 ... C(MAX) - 1] = {							\
	[0 ... C(OP_MAX) - 1] = {					\
		[0 ... C(RESULT_MAX) - 1] = CACHE_OP_UNSUPPORTED,	\
	},								\
}

/* The events for a given PMU register set. */
struct pmu_hw_events {
	/*
	 * The events that are active on the PMU for the given index.
	 */
	struct perf_event	*events[ARMPMU_MAX_HWEVENTS];

	/*
	 * A 1 bit for an index indicates that the counter is being used for
	 * an event. A 0 means that the counter can be used.
	 */
	DECLARE_BITMAP(used_mask, ARMPMU_MAX_HWEVENTS);

	/*
	 * Hardware lock to serialize accesses to PMU registers. Needed for the
	 * read/modify/write sequences.
	 */
	raw_spinlock_t		pmu_lock;

	/*
	 * When using percpu IRQs, we need a percpu dev_id. Place it here as we
	 * already have to allocate this struct per cpu.
	 */
	struct arm_pmu		*percpu_pmu;

	int irq;
};

enum armpmu_attr_groups {
	ARMPMU_ATTR_GROUP_COMMON,
	ARMPMU_ATTR_GROUP_EVENTS,
	ARMPMU_ATTR_GROUP_FORMATS,
	ARMPMU_NR_ATTR_GROUPS
};

struct arm_pmu {
	struct pmu	pmu;
	cpumask_t	active_irqs;
	cpumask_t	supported_cpus;
	char		*name;
	irqreturn_t	(*handle_irq)(int irq_num, void *dev);
	void		(*enable)(struct perf_event *event);
	void		(*disable)(struct perf_event *event);
	int		(*get_event_idx)(struct pmu_hw_events *hw_events,
					 struct perf_event *event);
	void		(*clear_event_idx)(struct pmu_hw_events *hw_events,
					 struct perf_event *event);
	int		(*set_event_filter)(struct hw_perf_event *evt,
					    struct perf_event_attr *attr);
	u32		(*read_counter)(struct perf_event *event);
	void		(*write_counter)(struct perf_event *event, u32 val);
	void		(*start)(struct arm_pmu *);
	void		(*stop)(struct arm_pmu *);
	void		(*reset)(void *);
	int		(*map_event)(struct perf_event *event);
	int		num_events;
	u64		max_period;
	bool		secure_access; /* 32-bit ARM only */
#define ARMV8_PMUV3_MAX_COMMON_EVENTS 0x40
	DECLARE_BITMAP(pmceid_bitmap, ARMV8_PMUV3_MAX_COMMON_EVENTS);
	struct platform_device	*plat_device;
	struct pmu_hw_events	__percpu *hw_events;
	struct hlist_node	node;
	struct notifier_block	cpu_pm_nb;
	/* the attr_groups array must be NULL-terminated */
	const struct attribute_group *attr_groups[ARMPMU_NR_ATTR_GROUPS + 1];

	/* Only to be used by ACPI probing code */
	unsigned long acpi_cpuid;
};

#define to_arm_pmu(p) (container_of(p, struct arm_pmu, pmu))

u64 armpmu_event_update(struct perf_event *event);

int armpmu_event_set_period(struct perf_event *event);

int armpmu_map_event(struct perf_event *event,
		     const unsigned (*event_map)[PERF_COUNT_HW_MAX],
		     const unsigned (*cache_map)[PERF_COUNT_HW_CACHE_MAX]
						[PERF_COUNT_HW_CACHE_OP_MAX]
						[PERF_COUNT_HW_CACHE_RESULT_MAX],
		     u32 raw_event_mask);

typedef int (*armpmu_init_fn)(struct arm_pmu *);

struct pmu_probe_info {
	unsigned int cpuid;
	unsigned int mask;
	armpmu_init_fn init;
};

#define PMU_PROBE(_cpuid, _mask, _fn)	\
{					\
	.cpuid = (_cpuid),		\
	.mask = (_mask),		\
	.init = (_fn),			\
}

#define ARM_PMU_PROBE(_cpuid, _fn) \
	PMU_PROBE(_cpuid, ARM_CPU_PART_MASK, _fn)

#define ARM_PMU_XSCALE_MASK	((0xff << 24) | ARM_CPU_XSCALE_ARCH_MASK)

#define XSCALE_PMU_PROBE(_version, _fn) \
	PMU_PROBE(ARM_CPU_IMP_INTEL << 24 | _version, ARM_PMU_XSCALE_MASK, _fn)

int arm_pmu_device_probe(struct platform_device *pdev,
			 const struct of_device_id *of_table,
			 const struct pmu_probe_info *probe_table);

#ifdef CONFIG_ACPI
int arm_pmu_acpi_probe(armpmu_init_fn init_fn);
#else
static inline int arm_pmu_acpi_probe(armpmu_init_fn init_fn) { return 0; }
#endif

/* Internal functions only for core arm_pmu code */
struct arm_pmu *armpmu_alloc(void);
void armpmu_free(struct arm_pmu *pmu);
int armpmu_register(struct arm_pmu *pmu);
int armpmu_request_irqs(struct arm_pmu *armpmu);
void armpmu_free_irqs(struct arm_pmu *armpmu);
int armpmu_request_irq(struct arm_pmu *armpmu, int cpu);
void armpmu_free_irq(struct arm_pmu *armpmu, int cpu);

#define ARMV8_PMU_PDEV_NAME "armv8-pmu"

#endif /* CONFIG_ARM_PMU */

#endif /* __ARM_PMU_H__ */
Commit	Line	Data
0f4f0672 JI	1	/*
	2	* linux/arch/arm/include/asm/pmu.h
	3	*
	4	* Copyright (C) 2009 picoChip Designs Ltd, Jamie Iles
	5	*
	6	* This program is free software; you can redistribute it and/or modify
	7	* it under the terms of the GNU General Public License version 2 as
	8	* published by the Free Software Foundation.
	9	*
	10	*/
	11
	12	#ifndef __ARM_PMU_H__
	13	#define __ARM_PMU_H__
	14
0e25a5c9	15	#include <linux/interrupt.h>
0ce47080	16	#include <linux/perf_event.h>
86cdd72a	17	#include <linux/sysfs.h>
548a86ca MR	18	#include <asm/cputype.h>
548a86ca MR	19
0e25a5c9 RV	20	/*
	21	* struct arm_pmu_platdata - ARM PMU platform data
	22	*
e0516a64 ML	23	* @handle_irq: an optional handler which will be called from the
	24	* interrupt and passed the address of the low level handler,
	25	* and can be used to implement any platform specific handling
	26	* before or after calling it.
a3287c41 WD	27	*
	28	* @irq_flags: if non-zero, these flags will be passed to request_irq
	29	* when requesting interrupts for this PMU device.
0e25a5c9 RV	30	*/
	31	struct arm_pmu_platdata {
	32	irqreturn_t (handle_irq)(int irq, void dev,
	33	irq_handler_t pmu_handler);
a3287c41	34	unsigned long irq_flags;
0e25a5c9 RV	35	};
0e25a5c9 RV	36
fa8ad788	37	#ifdef CONFIG_ARM_PMU
0ce47080	38
ac8674dc MR	39	/*
	40	* The ARMv7 CPU PMU supports up to 32 event counters.
	41	*/
	42	#define ARMPMU_MAX_HWEVENTS 32
	43
	44	#define HW_OP_UNSUPPORTED 0xFFFF
	45	#define C(_x) PERF_COUNT_HW_CACHE_##_x
	46	#define CACHE_OP_UNSUPPORTED 0xFFFF
	47
1113ff98 MR	48	#define PERF_MAP_ALL_UNSUPPORTED \
	49	[0 ... PERF_COUNT_HW_MAX - 1] = HW_OP_UNSUPPORTED
	50
	51	#define PERF_CACHE_MAP_ALL_UNSUPPORTED \
	52	[0 ... C(MAX) - 1] = { \
	53	[0 ... C(OP_MAX) - 1] = { \
	54	[0 ... C(RESULT_MAX) - 1] = CACHE_OP_UNSUPPORTED, \
	55	}, \
	56	}
	57
0ce47080 MR	58	/* The events for a given PMU register set. */
	59	struct pmu_hw_events {
	60	/*
	61	* The events that are active on the PMU for the given index.
	62	*/
a4560846	63	struct perf_event *events[ARMPMU_MAX_HWEVENTS];
0ce47080 MR	64
	65	/*
	66	* A 1 bit for an index indicates that the counter is being used for
	67	* an event. A 0 means that the counter can be used.
	68	*/
a4560846	69	DECLARE_BITMAP(used_mask, ARMPMU_MAX_HWEVENTS);
0ce47080 MR	70
	71	/*
	72	* Hardware lock to serialize accesses to PMU registers. Needed for the
	73	* read/modify/write sequences.
	74	*/
	75	raw_spinlock_t pmu_lock;
5ebd9200 MR	76
	77	/*
	78	* When using percpu IRQs, we need a percpu dev_id. Place it here as we
	79	* already have to allocate this struct per cpu.
	80	*/
	81	struct arm_pmu *percpu_pmu;
7ed98e01 MR	82
7ed98e01 MR	83	int irq;
0ce47080 MR	84	};
0ce47080 MR	85
86cdd72a	86	enum armpmu_attr_groups {
48538b58	87	ARMPMU_ATTR_GROUP_COMMON,
86cdd72a MR	88	ARMPMU_ATTR_GROUP_EVENTS,
	89	ARMPMU_ATTR_GROUP_FORMATS,
	90	ARMPMU_NR_ATTR_GROUPS
	91	};
	92
0ce47080 MR	93	struct arm_pmu {
0ce47080 MR	94	struct pmu pmu;
0ce47080	95	cpumask_t active_irqs;
cc88116d	96	cpumask_t supported_cpus;
4295b898	97	char *name;
0ce47080	98	irqreturn_t (handle_irq)(int irq_num, void dev);
ed6f2a52 SH	99	void (enable)(struct perf_event event);
ed6f2a52 SH	100	void (disable)(struct perf_event event);
0ce47080	101	int (get_event_idx)(struct pmu_hw_events hw_events,
ed6f2a52	102	struct perf_event *event);
eab443ef SB	103	void (clear_event_idx)(struct pmu_hw_events hw_events,
eab443ef SB	104	struct perf_event *event);
0ce47080 MR	105	int (set_event_filter)(struct hw_perf_event evt,
0ce47080 MR	106	struct perf_event_attr *attr);
ed6f2a52 SH	107	u32 (read_counter)(struct perf_event event);
	108	void (write_counter)(struct perf_event event, u32 val);
	109	void (start)(struct arm_pmu );
	110	void (stop)(struct arm_pmu );
0ce47080 MR	111	void (reset)(void );
	112	int (map_event)(struct perf_event event);
	113	int num_events;
0ce47080	114	u64 max_period;
8d1a0ae7	115	bool secure_access; /* 32-bit ARM only */
4b1a9e69 AK	116	#define ARMV8_PMUV3_MAX_COMMON_EVENTS 0x40
4b1a9e69 AK	117	DECLARE_BITMAP(pmceid_bitmap, ARMV8_PMUV3_MAX_COMMON_EVENTS);
0ce47080	118	struct platform_device *plat_device;
11679250	119	struct pmu_hw_events __percpu *hw_events;
6e103c0c	120	struct hlist_node node;
da4e4f18	121	struct notifier_block cpu_pm_nb;
86cdd72a MR	122	/* the attr_groups array must be NULL-terminated */
86cdd72a MR	123	const struct attribute_group *attr_groups[ARMPMU_NR_ATTR_GROUPS + 1];
45736a72 MR	124
	125	/* Only to be used by ACPI probing code */
	126	unsigned long acpi_cpuid;
0ce47080 MR	127	};
	128
	129	#define to_arm_pmu(p) (container_of(p, struct arm_pmu, pmu))
	130
ed6f2a52	131	u64 armpmu_event_update(struct perf_event *event);
0ce47080	132
ed6f2a52	133	int armpmu_event_set_period(struct perf_event *event);
0ce47080	134
6dbc0029 WD	135	int armpmu_map_event(struct perf_event *event,
	136	const unsigned (*event_map)[PERF_COUNT_HW_MAX],
	137	const unsigned (*cache_map)[PERF_COUNT_HW_CACHE_MAX]
	138	[PERF_COUNT_HW_CACHE_OP_MAX]
	139	[PERF_COUNT_HW_CACHE_RESULT_MAX],
	140	u32 raw_event_mask);
	141
083c5214 MR	142	typedef int (armpmu_init_fn)(struct arm_pmu );
083c5214 MR	143
548a86ca MR	144	struct pmu_probe_info {
	145	unsigned int cpuid;
	146	unsigned int mask;
083c5214	147	armpmu_init_fn init;
548a86ca MR	148	};
	149
	150	#define PMU_PROBE(_cpuid, _mask, _fn) \
	151	{ \
	152	.cpuid = (_cpuid), \
	153	.mask = (_mask), \
	154	.init = (_fn), \
	155	}
	156
	157	#define ARM_PMU_PROBE(_cpuid, _fn) \
	158	PMU_PROBE(_cpuid, ARM_CPU_PART_MASK, _fn)
	159
	160	#define ARM_PMU_XSCALE_MASK ((0xff << 24) \| ARM_CPU_XSCALE_ARCH_MASK)
	161
	162	#define XSCALE_PMU_PROBE(_version, _fn) \
	163	PMU_PROBE(ARM_CPU_IMP_INTEL << 24 \| _version, ARM_PMU_XSCALE_MASK, _fn)
	164
cfdad299 MR	165	int arm_pmu_device_probe(struct platform_device *pdev,
	166	const struct of_device_id *of_table,
	167	const struct pmu_probe_info *probe_table);
	168
45736a72 MR	169	#ifdef CONFIG_ACPI
	170	int arm_pmu_acpi_probe(armpmu_init_fn init_fn);
	171	#else
	172	static inline int arm_pmu_acpi_probe(armpmu_init_fn init_fn) { return 0; }
	173	#endif
	174
18bfcfe5 MR	175	/* Internal functions only for core arm_pmu code */
	176	struct arm_pmu *armpmu_alloc(void);
	177	void armpmu_free(struct arm_pmu *pmu);
	178	int armpmu_register(struct arm_pmu *pmu);
	179	int armpmu_request_irqs(struct arm_pmu *armpmu);
	180	void armpmu_free_irqs(struct arm_pmu *armpmu);
45736a72 MR	181	int armpmu_request_irq(struct arm_pmu *armpmu, int cpu);
45736a72 MR	182	void armpmu_free_irq(struct arm_pmu *armpmu, int cpu);
18bfcfe5	183
85023b2e JL	184	#define ARMV8_PMU_PDEV_NAME "armv8-pmu"
85023b2e JL	185
fa8ad788	186	#endif /* CONFIG_ARM_PMU */
0ce47080	187
0f4f0672	188	#endif /* __ARM_PMU_H__ */