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0793a61d TG |
1 | /* |
2 | * Performance counters: | |
3 | * | |
4 | * Copyright(C) 2008, Thomas Gleixner <tglx@linutronix.de> | |
5 | * Copyright(C) 2008, Red Hat, Inc., Ingo Molnar | |
6 | * | |
7 | * Data type definitions, declarations, prototypes. | |
8 | * | |
9 | * Started by: Thomas Gleixner and Ingo Molnar | |
10 | * | |
11 | * For licencing details see kernel-base/COPYING | |
12 | */ | |
13 | #ifndef _LINUX_PERF_COUNTER_H | |
14 | #define _LINUX_PERF_COUNTER_H | |
15 | ||
f3dfd265 PM |
16 | #include <linux/types.h> |
17 | #include <linux/ioctl.h> | |
0793a61d TG |
18 | |
19 | /* | |
9f66a381 IM |
20 | * User-space ABI bits: |
21 | */ | |
22 | ||
23 | /* | |
24 | * Generalized performance counter event types, used by the hw_event.type | |
25 | * parameter of the sys_perf_counter_open() syscall: | |
0793a61d TG |
26 | */ |
27 | enum hw_event_types { | |
0793a61d | 28 | /* |
9f66a381 | 29 | * Common hardware events, generalized by the kernel: |
0793a61d | 30 | */ |
f650a672 | 31 | PERF_COUNT_CPU_CYCLES = 0, |
9f66a381 IM |
32 | PERF_COUNT_INSTRUCTIONS = 1, |
33 | PERF_COUNT_CACHE_REFERENCES = 2, | |
34 | PERF_COUNT_CACHE_MISSES = 3, | |
35 | PERF_COUNT_BRANCH_INSTRUCTIONS = 4, | |
36 | PERF_COUNT_BRANCH_MISSES = 5, | |
f650a672 | 37 | PERF_COUNT_BUS_CYCLES = 6, |
9f66a381 | 38 | |
f650a672 | 39 | PERF_HW_EVENTS_MAX = 7, |
6c594c21 | 40 | |
9f66a381 IM |
41 | /* |
42 | * Special "software" counters provided by the kernel, even if | |
43 | * the hardware does not support performance counters. These | |
44 | * counters measure various physical and sw events of the | |
45 | * kernel (and allow the profiling of them as well): | |
46 | */ | |
47 | PERF_COUNT_CPU_CLOCK = -1, | |
48 | PERF_COUNT_TASK_CLOCK = -2, | |
5d6a27d8 IM |
49 | PERF_COUNT_PAGE_FAULTS = -3, |
50 | PERF_COUNT_CONTEXT_SWITCHES = -4, | |
6c594c21 IM |
51 | PERF_COUNT_CPU_MIGRATIONS = -5, |
52 | ||
53 | PERF_SW_EVENTS_MIN = -6, | |
0793a61d TG |
54 | }; |
55 | ||
56 | /* | |
57 | * IRQ-notification data record type: | |
58 | */ | |
9f66a381 IM |
59 | enum perf_counter_record_type { |
60 | PERF_RECORD_SIMPLE = 0, | |
61 | PERF_RECORD_IRQ = 1, | |
62 | PERF_RECORD_GROUP = 2, | |
0793a61d TG |
63 | }; |
64 | ||
9f66a381 IM |
65 | /* |
66 | * Hardware event to monitor via a performance monitoring counter: | |
67 | */ | |
68 | struct perf_counter_hw_event { | |
f3dfd265 | 69 | __s64 type; |
9f66a381 | 70 | |
f3dfd265 | 71 | __u64 irq_period; |
2743a5b0 PM |
72 | __u64 record_type; |
73 | __u64 read_format; | |
9f66a381 | 74 | |
2743a5b0 | 75 | __u64 disabled : 1, /* off by default */ |
0475f9ea PM |
76 | nmi : 1, /* NMI sampling */ |
77 | raw : 1, /* raw event type */ | |
78 | inherit : 1, /* children inherit it */ | |
79 | pinned : 1, /* must always be on PMU */ | |
80 | exclusive : 1, /* only group on PMU */ | |
81 | exclude_user : 1, /* don't count user */ | |
82 | exclude_kernel : 1, /* ditto kernel */ | |
83 | exclude_hv : 1, /* ditto hypervisor */ | |
2743a5b0 | 84 | exclude_idle : 1, /* don't count when idle */ |
0475f9ea | 85 | |
2485e518 | 86 | __reserved_1 : 54; |
2743a5b0 PM |
87 | |
88 | __u32 extra_config_len; | |
89 | __u32 __reserved_4; | |
9f66a381 | 90 | |
f3dfd265 | 91 | __u64 __reserved_2; |
2743a5b0 | 92 | __u64 __reserved_3; |
eab656ae TG |
93 | }; |
94 | ||
d859e29f PM |
95 | /* |
96 | * Ioctls that can be done on a perf counter fd: | |
97 | */ | |
98 | #define PERF_COUNTER_IOC_ENABLE _IO('$', 0) | |
99 | #define PERF_COUNTER_IOC_DISABLE _IO('$', 1) | |
100 | ||
f3dfd265 | 101 | #ifdef __KERNEL__ |
9f66a381 | 102 | /* |
f3dfd265 | 103 | * Kernel-internal data types and definitions: |
9f66a381 IM |
104 | */ |
105 | ||
f3dfd265 PM |
106 | #ifdef CONFIG_PERF_COUNTERS |
107 | # include <asm/perf_counter.h> | |
108 | #endif | |
109 | ||
110 | #include <linux/list.h> | |
111 | #include <linux/mutex.h> | |
112 | #include <linux/rculist.h> | |
113 | #include <linux/rcupdate.h> | |
114 | #include <linux/spinlock.h> | |
115 | #include <asm/atomic.h> | |
116 | ||
117 | struct task_struct; | |
118 | ||
0793a61d | 119 | /** |
9f66a381 | 120 | * struct hw_perf_counter - performance counter hardware details: |
0793a61d TG |
121 | */ |
122 | struct hw_perf_counter { | |
ee06094f | 123 | #ifdef CONFIG_PERF_COUNTERS |
9f66a381 IM |
124 | u64 config; |
125 | unsigned long config_base; | |
126 | unsigned long counter_base; | |
127 | int nmi; | |
128 | unsigned int idx; | |
15dbf27c | 129 | atomic64_t count; /* software */ |
ee06094f | 130 | atomic64_t prev_count; |
9f66a381 | 131 | u64 irq_period; |
ee06094f IM |
132 | atomic64_t period_left; |
133 | #endif | |
0793a61d TG |
134 | }; |
135 | ||
136 | /* | |
137 | * Hardcoded buffer length limit for now, for IRQ-fed events: | |
138 | */ | |
9f66a381 | 139 | #define PERF_DATA_BUFLEN 2048 |
0793a61d TG |
140 | |
141 | /** | |
142 | * struct perf_data - performance counter IRQ data sampling ... | |
143 | */ | |
144 | struct perf_data { | |
9f66a381 IM |
145 | int len; |
146 | int rd_idx; | |
147 | int overrun; | |
148 | u8 data[PERF_DATA_BUFLEN]; | |
0793a61d TG |
149 | }; |
150 | ||
621a01ea IM |
151 | struct perf_counter; |
152 | ||
153 | /** | |
154 | * struct hw_perf_counter_ops - performance counter hw ops | |
155 | */ | |
156 | struct hw_perf_counter_ops { | |
95cdd2e7 | 157 | int (*enable) (struct perf_counter *counter); |
7671581f IM |
158 | void (*disable) (struct perf_counter *counter); |
159 | void (*read) (struct perf_counter *counter); | |
621a01ea IM |
160 | }; |
161 | ||
6a930700 IM |
162 | /** |
163 | * enum perf_counter_active_state - the states of a counter | |
164 | */ | |
165 | enum perf_counter_active_state { | |
3b6f9e5c | 166 | PERF_COUNTER_STATE_ERROR = -2, |
6a930700 IM |
167 | PERF_COUNTER_STATE_OFF = -1, |
168 | PERF_COUNTER_STATE_INACTIVE = 0, | |
169 | PERF_COUNTER_STATE_ACTIVE = 1, | |
170 | }; | |
171 | ||
9b51f66d IM |
172 | struct file; |
173 | ||
0793a61d TG |
174 | /** |
175 | * struct perf_counter - performance counter kernel representation: | |
176 | */ | |
177 | struct perf_counter { | |
ee06094f | 178 | #ifdef CONFIG_PERF_COUNTERS |
04289bb9 IM |
179 | struct list_head list_entry; |
180 | struct list_head sibling_list; | |
181 | struct perf_counter *group_leader; | |
5c92d124 | 182 | const struct hw_perf_counter_ops *hw_ops; |
04289bb9 | 183 | |
6a930700 | 184 | enum perf_counter_active_state state; |
c07c99b6 | 185 | enum perf_counter_active_state prev_state; |
0793a61d | 186 | atomic64_t count; |
ee06094f | 187 | |
9f66a381 | 188 | struct perf_counter_hw_event hw_event; |
0793a61d TG |
189 | struct hw_perf_counter hw; |
190 | ||
191 | struct perf_counter_context *ctx; | |
192 | struct task_struct *task; | |
9b51f66d | 193 | struct file *filp; |
0793a61d | 194 | |
9b51f66d | 195 | struct perf_counter *parent; |
d859e29f PM |
196 | struct list_head child_list; |
197 | ||
0793a61d | 198 | /* |
d859e29f | 199 | * Protect attach/detach and child_list: |
0793a61d TG |
200 | */ |
201 | struct mutex mutex; | |
202 | ||
203 | int oncpu; | |
204 | int cpu; | |
205 | ||
0793a61d TG |
206 | /* read() / irq related data */ |
207 | wait_queue_head_t waitq; | |
208 | /* optional: for NMIs */ | |
209 | int wakeup_pending; | |
210 | struct perf_data *irqdata; | |
211 | struct perf_data *usrdata; | |
212 | struct perf_data data[2]; | |
ee06094f | 213 | #endif |
0793a61d TG |
214 | }; |
215 | ||
216 | /** | |
217 | * struct perf_counter_context - counter context structure | |
218 | * | |
219 | * Used as a container for task counters and CPU counters as well: | |
220 | */ | |
221 | struct perf_counter_context { | |
222 | #ifdef CONFIG_PERF_COUNTERS | |
223 | /* | |
d859e29f PM |
224 | * Protect the states of the counters in the list, |
225 | * nr_active, and the list: | |
0793a61d TG |
226 | */ |
227 | spinlock_t lock; | |
d859e29f PM |
228 | /* |
229 | * Protect the list of counters. Locking either mutex or lock | |
230 | * is sufficient to ensure the list doesn't change; to change | |
231 | * the list you need to lock both the mutex and the spinlock. | |
232 | */ | |
233 | struct mutex mutex; | |
04289bb9 IM |
234 | |
235 | struct list_head counter_list; | |
0793a61d TG |
236 | int nr_counters; |
237 | int nr_active; | |
d859e29f | 238 | int is_active; |
0793a61d TG |
239 | struct task_struct *task; |
240 | #endif | |
241 | }; | |
242 | ||
243 | /** | |
244 | * struct perf_counter_cpu_context - per cpu counter context structure | |
245 | */ | |
246 | struct perf_cpu_context { | |
247 | struct perf_counter_context ctx; | |
248 | struct perf_counter_context *task_ctx; | |
249 | int active_oncpu; | |
250 | int max_pertask; | |
3b6f9e5c | 251 | int exclusive; |
0793a61d TG |
252 | }; |
253 | ||
254 | /* | |
255 | * Set by architecture code: | |
256 | */ | |
257 | extern int perf_max_counters; | |
258 | ||
259 | #ifdef CONFIG_PERF_COUNTERS | |
5c92d124 | 260 | extern const struct hw_perf_counter_ops * |
621a01ea IM |
261 | hw_perf_counter_init(struct perf_counter *counter); |
262 | ||
0793a61d TG |
263 | extern void perf_counter_task_sched_in(struct task_struct *task, int cpu); |
264 | extern void perf_counter_task_sched_out(struct task_struct *task, int cpu); | |
265 | extern void perf_counter_task_tick(struct task_struct *task, int cpu); | |
9b51f66d IM |
266 | extern void perf_counter_init_task(struct task_struct *child); |
267 | extern void perf_counter_exit_task(struct task_struct *child); | |
0793a61d TG |
268 | extern void perf_counter_notify(struct pt_regs *regs); |
269 | extern void perf_counter_print_debug(void); | |
1b023a96 | 270 | extern void perf_counter_unthrottle(void); |
01b2838c IM |
271 | extern u64 hw_perf_save_disable(void); |
272 | extern void hw_perf_restore(u64 ctrl); | |
1d1c7ddb IM |
273 | extern int perf_counter_task_disable(void); |
274 | extern int perf_counter_task_enable(void); | |
3cbed429 PM |
275 | extern int hw_perf_group_sched_in(struct perf_counter *group_leader, |
276 | struct perf_cpu_context *cpuctx, | |
277 | struct perf_counter_context *ctx, int cpu); | |
5c92d124 | 278 | |
3b6f9e5c PM |
279 | /* |
280 | * Return 1 for a software counter, 0 for a hardware counter | |
281 | */ | |
282 | static inline int is_software_counter(struct perf_counter *counter) | |
283 | { | |
284 | return !counter->hw_event.raw && counter->hw_event.type < 0; | |
285 | } | |
286 | ||
15dbf27c PZ |
287 | extern void perf_swcounter_event(enum hw_event_types, u64, int, struct pt_regs *); |
288 | ||
0793a61d TG |
289 | #else |
290 | static inline void | |
291 | perf_counter_task_sched_in(struct task_struct *task, int cpu) { } | |
292 | static inline void | |
293 | perf_counter_task_sched_out(struct task_struct *task, int cpu) { } | |
294 | static inline void | |
295 | perf_counter_task_tick(struct task_struct *task, int cpu) { } | |
9b51f66d IM |
296 | static inline void perf_counter_init_task(struct task_struct *child) { } |
297 | static inline void perf_counter_exit_task(struct task_struct *child) { } | |
0793a61d TG |
298 | static inline void perf_counter_notify(struct pt_regs *regs) { } |
299 | static inline void perf_counter_print_debug(void) { } | |
1b023a96 | 300 | static inline void perf_counter_unthrottle(void) { } |
15dbf27c | 301 | static inline void hw_perf_restore(u64 ctrl) { } |
01b2838c | 302 | static inline u64 hw_perf_save_disable(void) { return 0; } |
1d1c7ddb IM |
303 | static inline int perf_counter_task_disable(void) { return -EINVAL; } |
304 | static inline int perf_counter_task_enable(void) { return -EINVAL; } | |
15dbf27c PZ |
305 | |
306 | static inline void perf_swcounter_event(enum hw_event_types event, u64 nr, | |
307 | int nmi, struct pt_regs *regs) { } | |
0793a61d TG |
308 | #endif |
309 | ||
f3dfd265 | 310 | #endif /* __KERNEL__ */ |
0793a61d | 311 | #endif /* _LINUX_PERF_COUNTER_H */ |