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0793a61d TG |
1 | /* |
2 | * Performance counters: | |
3 | * | |
4 | * Copyright(C) 2008, Thomas Gleixner <tglx@linutronix.de> | |
5 | * Copyright(C) 2008, Red Hat, Inc., Ingo Molnar | |
6 | * | |
7 | * Data type definitions, declarations, prototypes. | |
8 | * | |
9 | * Started by: Thomas Gleixner and Ingo Molnar | |
10 | * | |
11 | * For licencing details see kernel-base/COPYING | |
12 | */ | |
13 | #ifndef _LINUX_PERF_COUNTER_H | |
14 | #define _LINUX_PERF_COUNTER_H | |
15 | ||
f3dfd265 PM |
16 | #include <linux/types.h> |
17 | #include <linux/ioctl.h> | |
9aaa131a | 18 | #include <asm/byteorder.h> |
0793a61d TG |
19 | |
20 | /* | |
9f66a381 IM |
21 | * User-space ABI bits: |
22 | */ | |
23 | ||
24 | /* | |
0d48696f | 25 | * attr.type |
0793a61d | 26 | */ |
1c432d89 | 27 | enum perf_type_id { |
b8e83514 PZ |
28 | PERF_TYPE_HARDWARE = 0, |
29 | PERF_TYPE_SOFTWARE = 1, | |
30 | PERF_TYPE_TRACEPOINT = 2, | |
8326f44d | 31 | PERF_TYPE_HW_CACHE = 3, |
1c432d89 | 32 | PERF_TYPE_RAW = 4, |
b8e83514 | 33 | |
1c432d89 | 34 | PERF_TYPE_MAX, /* non ABI */ |
b8e83514 | 35 | }; |
6c594c21 | 36 | |
b8e83514 | 37 | /* |
0d48696f | 38 | * Generalized performance counter event types, used by the attr.event_id |
b8e83514 PZ |
39 | * parameter of the sys_perf_counter_open() syscall: |
40 | */ | |
1c432d89 | 41 | enum perf_hw_id { |
9f66a381 | 42 | /* |
b8e83514 | 43 | * Common hardware events, generalized by the kernel: |
9f66a381 | 44 | */ |
b8e83514 PZ |
45 | PERF_COUNT_CPU_CYCLES = 0, |
46 | PERF_COUNT_INSTRUCTIONS = 1, | |
47 | PERF_COUNT_CACHE_REFERENCES = 2, | |
48 | PERF_COUNT_CACHE_MISSES = 3, | |
49 | PERF_COUNT_BRANCH_INSTRUCTIONS = 4, | |
50 | PERF_COUNT_BRANCH_MISSES = 5, | |
51 | PERF_COUNT_BUS_CYCLES = 6, | |
52 | ||
1c432d89 | 53 | PERF_HW_EVENTS_MAX, /* non ABI */ |
b8e83514 | 54 | }; |
e077df4f | 55 | |
8326f44d IM |
56 | /* |
57 | * Generalized hardware cache counters: | |
58 | * | |
59 | * { L1-D, L1-I, L2, LLC, ITLB, DTLB, BPU } x | |
60 | * { read, write, prefetch } x | |
61 | * { accesses, misses } | |
62 | */ | |
1c432d89 PZ |
63 | enum perf_hw_cache_id { |
64 | PERF_COUNT_HW_CACHE_L1D = 0, | |
65 | PERF_COUNT_HW_CACHE_L1I = 1, | |
66 | PERF_COUNT_HW_CACHE_L2 = 2, | |
67 | PERF_COUNT_HW_CACHE_DTLB = 3, | |
68 | PERF_COUNT_HW_CACHE_ITLB = 4, | |
69 | PERF_COUNT_HW_CACHE_BPU = 5, | |
70 | ||
71 | PERF_COUNT_HW_CACHE_MAX, /* non ABI */ | |
8326f44d IM |
72 | }; |
73 | ||
1c432d89 PZ |
74 | enum perf_hw_cache_op_id { |
75 | PERF_COUNT_HW_CACHE_OP_READ = 0, | |
76 | PERF_COUNT_HW_CACHE_OP_WRITE = 1, | |
77 | PERF_COUNT_HW_CACHE_OP_PREFETCH = 2, | |
8326f44d | 78 | |
1c432d89 | 79 | PERF_COUNT_HW_CACHE_OP_MAX, /* non ABI */ |
8326f44d IM |
80 | }; |
81 | ||
1c432d89 PZ |
82 | enum perf_hw_cache_op_result_id { |
83 | PERF_COUNT_HW_CACHE_RESULT_ACCESS = 0, | |
84 | PERF_COUNT_HW_CACHE_RESULT_MISS = 1, | |
8326f44d | 85 | |
1c432d89 | 86 | PERF_COUNT_HW_CACHE_RESULT_MAX, /* non ABI */ |
8326f44d IM |
87 | }; |
88 | ||
b8e83514 PZ |
89 | /* |
90 | * Special "software" counters provided by the kernel, even if the hardware | |
91 | * does not support performance counters. These counters measure various | |
92 | * physical and sw events of the kernel (and allow the profiling of them as | |
93 | * well): | |
94 | */ | |
1c432d89 | 95 | enum perf_sw_ids { |
b8e83514 PZ |
96 | PERF_COUNT_CPU_CLOCK = 0, |
97 | PERF_COUNT_TASK_CLOCK = 1, | |
98 | PERF_COUNT_PAGE_FAULTS = 2, | |
99 | PERF_COUNT_CONTEXT_SWITCHES = 3, | |
100 | PERF_COUNT_CPU_MIGRATIONS = 4, | |
101 | PERF_COUNT_PAGE_FAULTS_MIN = 5, | |
102 | PERF_COUNT_PAGE_FAULTS_MAJ = 6, | |
103 | ||
1c432d89 | 104 | PERF_SW_EVENTS_MAX, /* non ABI */ |
0793a61d TG |
105 | }; |
106 | ||
8a057d84 | 107 | /* |
0d48696f | 108 | * Bits that can be set in attr.sample_type to request information |
8a057d84 PZ |
109 | * in the overflow packets. |
110 | */ | |
b23f3325 PZ |
111 | enum perf_counter_sample_format { |
112 | PERF_SAMPLE_IP = 1U << 0, | |
113 | PERF_SAMPLE_TID = 1U << 1, | |
114 | PERF_SAMPLE_TIME = 1U << 2, | |
115 | PERF_SAMPLE_ADDR = 1U << 3, | |
116 | PERF_SAMPLE_GROUP = 1U << 4, | |
117 | PERF_SAMPLE_CALLCHAIN = 1U << 5, | |
ac4bcf88 | 118 | PERF_SAMPLE_ID = 1U << 6, |
b23f3325 | 119 | PERF_SAMPLE_CPU = 1U << 7, |
689802b2 | 120 | PERF_SAMPLE_PERIOD = 1U << 8, |
8a057d84 PZ |
121 | }; |
122 | ||
53cfbf59 | 123 | /* |
0d48696f | 124 | * Bits that can be set in attr.read_format to request that |
53cfbf59 PM |
125 | * reads on the counter should return the indicated quantities, |
126 | * in increasing order of bit value, after the counter value. | |
127 | */ | |
128 | enum perf_counter_read_format { | |
8e5799b1 PZ |
129 | PERF_FORMAT_TOTAL_TIME_ENABLED = 1U << 0, |
130 | PERF_FORMAT_TOTAL_TIME_RUNNING = 1U << 1, | |
131 | PERF_FORMAT_ID = 1U << 2, | |
53cfbf59 PM |
132 | }; |
133 | ||
9f66a381 IM |
134 | /* |
135 | * Hardware event to monitor via a performance monitoring counter: | |
136 | */ | |
0d48696f | 137 | struct perf_counter_attr { |
f4a2deb4 | 138 | /* |
a21ca2ca IM |
139 | * Major type: hardware/software/tracepoint/etc. |
140 | */ | |
141 | __u32 type; | |
142 | __u32 __reserved_1; | |
143 | ||
144 | /* | |
145 | * Type specific configuration information. | |
f4a2deb4 PZ |
146 | */ |
147 | __u64 config; | |
9f66a381 | 148 | |
60db5e09 | 149 | union { |
b23f3325 PZ |
150 | __u64 sample_period; |
151 | __u64 sample_freq; | |
60db5e09 PZ |
152 | }; |
153 | ||
b23f3325 PZ |
154 | __u64 sample_type; |
155 | __u64 read_format; | |
9f66a381 | 156 | |
2743a5b0 | 157 | __u64 disabled : 1, /* off by default */ |
0475f9ea PM |
158 | inherit : 1, /* children inherit it */ |
159 | pinned : 1, /* must always be on PMU */ | |
160 | exclusive : 1, /* only group on PMU */ | |
161 | exclude_user : 1, /* don't count user */ | |
162 | exclude_kernel : 1, /* ditto kernel */ | |
163 | exclude_hv : 1, /* ditto hypervisor */ | |
2743a5b0 | 164 | exclude_idle : 1, /* don't count when idle */ |
0a4a9391 | 165 | mmap : 1, /* include mmap data */ |
8d1b2d93 | 166 | comm : 1, /* include comm data */ |
60db5e09 | 167 | freq : 1, /* use freq, not period */ |
0475f9ea | 168 | |
a21ca2ca | 169 | __reserved_2 : 53; |
2743a5b0 | 170 | |
c457810a | 171 | __u32 wakeup_events; /* wakeup every n events */ |
a21ca2ca | 172 | __u32 __reserved_3; |
9f66a381 | 173 | |
e527ea31 | 174 | __u64 __reserved_4; |
eab656ae TG |
175 | }; |
176 | ||
d859e29f PM |
177 | /* |
178 | * Ioctls that can be done on a perf counter fd: | |
179 | */ | |
08247e31 PZ |
180 | #define PERF_COUNTER_IOC_ENABLE _IO ('$', 0) |
181 | #define PERF_COUNTER_IOC_DISABLE _IO ('$', 1) | |
182 | #define PERF_COUNTER_IOC_REFRESH _IO ('$', 2) | |
183 | #define PERF_COUNTER_IOC_RESET _IO ('$', 3) | |
184 | #define PERF_COUNTER_IOC_PERIOD _IOW('$', 4, u64) | |
3df5edad PZ |
185 | |
186 | enum perf_counter_ioc_flags { | |
187 | PERF_IOC_FLAG_GROUP = 1U << 0, | |
188 | }; | |
d859e29f | 189 | |
37d81828 PM |
190 | /* |
191 | * Structure of the page that can be mapped via mmap | |
192 | */ | |
193 | struct perf_counter_mmap_page { | |
194 | __u32 version; /* version number of this structure */ | |
195 | __u32 compat_version; /* lowest version this is compat with */ | |
38ff667b PZ |
196 | |
197 | /* | |
198 | * Bits needed to read the hw counters in user-space. | |
199 | * | |
92f22a38 PZ |
200 | * u32 seq; |
201 | * s64 count; | |
38ff667b | 202 | * |
a2e87d06 PZ |
203 | * do { |
204 | * seq = pc->lock; | |
38ff667b | 205 | * |
a2e87d06 PZ |
206 | * barrier() |
207 | * if (pc->index) { | |
208 | * count = pmc_read(pc->index - 1); | |
209 | * count += pc->offset; | |
210 | * } else | |
211 | * goto regular_read; | |
38ff667b | 212 | * |
a2e87d06 PZ |
213 | * barrier(); |
214 | * } while (pc->lock != seq); | |
38ff667b | 215 | * |
92f22a38 PZ |
216 | * NOTE: for obvious reason this only works on self-monitoring |
217 | * processes. | |
38ff667b | 218 | */ |
37d81828 PM |
219 | __u32 lock; /* seqlock for synchronization */ |
220 | __u32 index; /* hardware counter identifier */ | |
221 | __s64 offset; /* add to hardware counter value */ | |
7b732a75 | 222 | |
38ff667b PZ |
223 | /* |
224 | * Control data for the mmap() data buffer. | |
225 | * | |
226 | * User-space reading this value should issue an rmb(), on SMP capable | |
227 | * platforms, after reading this value -- see perf_counter_wakeup(). | |
228 | */ | |
8e3747c1 | 229 | __u64 data_head; /* head in the data section */ |
37d81828 PM |
230 | }; |
231 | ||
9d23a90a PM |
232 | #define PERF_EVENT_MISC_CPUMODE_MASK (3 << 0) |
233 | #define PERF_EVENT_MISC_CPUMODE_UNKNOWN (0 << 0) | |
6b6e5486 | 234 | #define PERF_EVENT_MISC_KERNEL (1 << 0) |
9d23a90a PM |
235 | #define PERF_EVENT_MISC_USER (2 << 0) |
236 | #define PERF_EVENT_MISC_HYPERVISOR (3 << 0) | |
6b6e5486 | 237 | #define PERF_EVENT_MISC_OVERFLOW (1 << 2) |
6fab0192 | 238 | |
5c148194 PZ |
239 | struct perf_event_header { |
240 | __u32 type; | |
6fab0192 PZ |
241 | __u16 misc; |
242 | __u16 size; | |
5c148194 PZ |
243 | }; |
244 | ||
245 | enum perf_event_type { | |
5ed00415 | 246 | |
0c593b34 PZ |
247 | /* |
248 | * The MMAP events record the PROT_EXEC mappings so that we can | |
249 | * correlate userspace IPs to code. They have the following structure: | |
250 | * | |
251 | * struct { | |
0127c3ea | 252 | * struct perf_event_header header; |
0c593b34 | 253 | * |
0127c3ea IM |
254 | * u32 pid, tid; |
255 | * u64 addr; | |
256 | * u64 len; | |
257 | * u64 pgoff; | |
258 | * char filename[]; | |
0c593b34 PZ |
259 | * }; |
260 | */ | |
8a057d84 | 261 | PERF_EVENT_MMAP = 1, |
0a4a9391 | 262 | |
8d1b2d93 PZ |
263 | /* |
264 | * struct { | |
0127c3ea | 265 | * struct perf_event_header header; |
8d1b2d93 | 266 | * |
0127c3ea IM |
267 | * u32 pid, tid; |
268 | * char comm[]; | |
8d1b2d93 PZ |
269 | * }; |
270 | */ | |
271 | PERF_EVENT_COMM = 3, | |
272 | ||
26b119bc PZ |
273 | /* |
274 | * struct { | |
0127c3ea IM |
275 | * struct perf_event_header header; |
276 | * u64 time; | |
689802b2 | 277 | * u64 id; |
b23f3325 | 278 | * u64 sample_period; |
26b119bc PZ |
279 | * }; |
280 | */ | |
281 | PERF_EVENT_PERIOD = 4, | |
282 | ||
a78ac325 PZ |
283 | /* |
284 | * struct { | |
0127c3ea IM |
285 | * struct perf_event_header header; |
286 | * u64 time; | |
a78ac325 PZ |
287 | * }; |
288 | */ | |
289 | PERF_EVENT_THROTTLE = 5, | |
290 | PERF_EVENT_UNTHROTTLE = 6, | |
291 | ||
60313ebe PZ |
292 | /* |
293 | * struct { | |
a21ca2ca IM |
294 | * struct perf_event_header header; |
295 | * u32 pid, ppid; | |
60313ebe PZ |
296 | * }; |
297 | */ | |
298 | PERF_EVENT_FORK = 7, | |
299 | ||
8a057d84 | 300 | /* |
6b6e5486 PZ |
301 | * When header.misc & PERF_EVENT_MISC_OVERFLOW the event_type field |
302 | * will be PERF_RECORD_* | |
0c593b34 PZ |
303 | * |
304 | * struct { | |
0127c3ea | 305 | * struct perf_event_header header; |
0c593b34 | 306 | * |
0127c3ea IM |
307 | * { u64 ip; } && PERF_RECORD_IP |
308 | * { u32 pid, tid; } && PERF_RECORD_TID | |
309 | * { u64 time; } && PERF_RECORD_TIME | |
310 | * { u64 addr; } && PERF_RECORD_ADDR | |
311 | * { u64 config; } && PERF_RECORD_CONFIG | |
312 | * { u32 cpu, res; } && PERF_RECORD_CPU | |
0c593b34 | 313 | * |
0127c3ea | 314 | * { u64 nr; |
8e5799b1 | 315 | * { u64 id, val; } cnt[nr]; } && PERF_RECORD_GROUP |
0c593b34 | 316 | * |
0127c3ea IM |
317 | * { u16 nr, |
318 | * hv, | |
319 | * kernel, | |
320 | * user; | |
321 | * u64 ips[nr]; } && PERF_RECORD_CALLCHAIN | |
0c593b34 | 322 | * }; |
8a057d84 | 323 | */ |
5c148194 PZ |
324 | }; |
325 | ||
f3dfd265 | 326 | #ifdef __KERNEL__ |
9f66a381 | 327 | /* |
f3dfd265 | 328 | * Kernel-internal data types and definitions: |
9f66a381 IM |
329 | */ |
330 | ||
f3dfd265 PM |
331 | #ifdef CONFIG_PERF_COUNTERS |
332 | # include <asm/perf_counter.h> | |
333 | #endif | |
334 | ||
335 | #include <linux/list.h> | |
336 | #include <linux/mutex.h> | |
337 | #include <linux/rculist.h> | |
338 | #include <linux/rcupdate.h> | |
339 | #include <linux/spinlock.h> | |
d6d020e9 | 340 | #include <linux/hrtimer.h> |
3c446b3d | 341 | #include <linux/fs.h> |
709e50cf | 342 | #include <linux/pid_namespace.h> |
f3dfd265 PM |
343 | #include <asm/atomic.h> |
344 | ||
345 | struct task_struct; | |
346 | ||
0793a61d | 347 | /** |
9f66a381 | 348 | * struct hw_perf_counter - performance counter hardware details: |
0793a61d TG |
349 | */ |
350 | struct hw_perf_counter { | |
ee06094f | 351 | #ifdef CONFIG_PERF_COUNTERS |
d6d020e9 PZ |
352 | union { |
353 | struct { /* hardware */ | |
354 | u64 config; | |
355 | unsigned long config_base; | |
356 | unsigned long counter_base; | |
6f00cada | 357 | int idx; |
d6d020e9 PZ |
358 | }; |
359 | union { /* software */ | |
360 | atomic64_t count; | |
361 | struct hrtimer hrtimer; | |
362 | }; | |
363 | }; | |
ee06094f | 364 | atomic64_t prev_count; |
b23f3325 | 365 | u64 sample_period; |
9e350de3 | 366 | u64 last_period; |
ee06094f | 367 | atomic64_t period_left; |
60db5e09 | 368 | u64 interrupts; |
6a24ed6c PZ |
369 | |
370 | u64 freq_count; | |
371 | u64 freq_interrupts; | |
bd2b5b12 | 372 | u64 freq_stamp; |
ee06094f | 373 | #endif |
0793a61d TG |
374 | }; |
375 | ||
621a01ea IM |
376 | struct perf_counter; |
377 | ||
378 | /** | |
4aeb0b42 | 379 | * struct pmu - generic performance monitoring unit |
621a01ea | 380 | */ |
4aeb0b42 | 381 | struct pmu { |
95cdd2e7 | 382 | int (*enable) (struct perf_counter *counter); |
7671581f IM |
383 | void (*disable) (struct perf_counter *counter); |
384 | void (*read) (struct perf_counter *counter); | |
a78ac325 | 385 | void (*unthrottle) (struct perf_counter *counter); |
621a01ea IM |
386 | }; |
387 | ||
6a930700 IM |
388 | /** |
389 | * enum perf_counter_active_state - the states of a counter | |
390 | */ | |
391 | enum perf_counter_active_state { | |
3b6f9e5c | 392 | PERF_COUNTER_STATE_ERROR = -2, |
6a930700 IM |
393 | PERF_COUNTER_STATE_OFF = -1, |
394 | PERF_COUNTER_STATE_INACTIVE = 0, | |
395 | PERF_COUNTER_STATE_ACTIVE = 1, | |
396 | }; | |
397 | ||
9b51f66d IM |
398 | struct file; |
399 | ||
7b732a75 PZ |
400 | struct perf_mmap_data { |
401 | struct rcu_head rcu_head; | |
8740f941 | 402 | int nr_pages; /* nr of data pages */ |
c5078f78 | 403 | int nr_locked; /* nr pages mlocked */ |
8740f941 | 404 | |
c33a0bc4 | 405 | atomic_t poll; /* POLL_ for wakeups */ |
8740f941 PZ |
406 | atomic_t events; /* event limit */ |
407 | ||
8e3747c1 PZ |
408 | atomic_long_t head; /* write position */ |
409 | atomic_long_t done_head; /* completed head */ | |
410 | ||
c33a0bc4 PZ |
411 | atomic_t lock; /* concurrent writes */ |
412 | ||
c66de4a5 PZ |
413 | atomic_t wakeup; /* needs a wakeup */ |
414 | ||
7b732a75 | 415 | struct perf_counter_mmap_page *user_page; |
0127c3ea | 416 | void *data_pages[0]; |
7b732a75 PZ |
417 | }; |
418 | ||
671dec5d PZ |
419 | struct perf_pending_entry { |
420 | struct perf_pending_entry *next; | |
421 | void (*func)(struct perf_pending_entry *); | |
925d519a PZ |
422 | }; |
423 | ||
0793a61d TG |
424 | /** |
425 | * struct perf_counter - performance counter kernel representation: | |
426 | */ | |
427 | struct perf_counter { | |
ee06094f | 428 | #ifdef CONFIG_PERF_COUNTERS |
04289bb9 | 429 | struct list_head list_entry; |
592903cd | 430 | struct list_head event_entry; |
04289bb9 | 431 | struct list_head sibling_list; |
0127c3ea | 432 | int nr_siblings; |
04289bb9 | 433 | struct perf_counter *group_leader; |
4aeb0b42 | 434 | const struct pmu *pmu; |
04289bb9 | 435 | |
6a930700 | 436 | enum perf_counter_active_state state; |
0793a61d | 437 | atomic64_t count; |
ee06094f | 438 | |
53cfbf59 PM |
439 | /* |
440 | * These are the total time in nanoseconds that the counter | |
441 | * has been enabled (i.e. eligible to run, and the task has | |
442 | * been scheduled in, if this is a per-task counter) | |
443 | * and running (scheduled onto the CPU), respectively. | |
444 | * | |
445 | * They are computed from tstamp_enabled, tstamp_running and | |
446 | * tstamp_stopped when the counter is in INACTIVE or ACTIVE state. | |
447 | */ | |
448 | u64 total_time_enabled; | |
449 | u64 total_time_running; | |
450 | ||
451 | /* | |
452 | * These are timestamps used for computing total_time_enabled | |
453 | * and total_time_running when the counter is in INACTIVE or | |
454 | * ACTIVE state, measured in nanoseconds from an arbitrary point | |
455 | * in time. | |
456 | * tstamp_enabled: the notional time when the counter was enabled | |
457 | * tstamp_running: the notional time when the counter was scheduled on | |
458 | * tstamp_stopped: in INACTIVE state, the notional time when the | |
459 | * counter was scheduled off. | |
460 | */ | |
461 | u64 tstamp_enabled; | |
462 | u64 tstamp_running; | |
463 | u64 tstamp_stopped; | |
464 | ||
0d48696f | 465 | struct perf_counter_attr attr; |
0793a61d TG |
466 | struct hw_perf_counter hw; |
467 | ||
468 | struct perf_counter_context *ctx; | |
9b51f66d | 469 | struct file *filp; |
0793a61d | 470 | |
53cfbf59 PM |
471 | /* |
472 | * These accumulate total time (in nanoseconds) that children | |
473 | * counters have been enabled and running, respectively. | |
474 | */ | |
475 | atomic64_t child_total_time_enabled; | |
476 | atomic64_t child_total_time_running; | |
477 | ||
0793a61d | 478 | /* |
d859e29f | 479 | * Protect attach/detach and child_list: |
0793a61d | 480 | */ |
fccc714b PZ |
481 | struct mutex child_mutex; |
482 | struct list_head child_list; | |
483 | struct perf_counter *parent; | |
0793a61d TG |
484 | |
485 | int oncpu; | |
486 | int cpu; | |
487 | ||
082ff5a2 PZ |
488 | struct list_head owner_entry; |
489 | struct task_struct *owner; | |
490 | ||
7b732a75 PZ |
491 | /* mmap bits */ |
492 | struct mutex mmap_mutex; | |
493 | atomic_t mmap_count; | |
494 | struct perf_mmap_data *data; | |
37d81828 | 495 | |
7b732a75 | 496 | /* poll related */ |
0793a61d | 497 | wait_queue_head_t waitq; |
3c446b3d | 498 | struct fasync_struct *fasync; |
79f14641 PZ |
499 | |
500 | /* delayed work for NMIs and such */ | |
501 | int pending_wakeup; | |
4c9e2542 | 502 | int pending_kill; |
79f14641 | 503 | int pending_disable; |
671dec5d | 504 | struct perf_pending_entry pending; |
592903cd | 505 | |
79f14641 PZ |
506 | atomic_t event_limit; |
507 | ||
e077df4f | 508 | void (*destroy)(struct perf_counter *); |
592903cd | 509 | struct rcu_head rcu_head; |
709e50cf PZ |
510 | |
511 | struct pid_namespace *ns; | |
8e5799b1 | 512 | u64 id; |
ee06094f | 513 | #endif |
0793a61d TG |
514 | }; |
515 | ||
516 | /** | |
517 | * struct perf_counter_context - counter context structure | |
518 | * | |
519 | * Used as a container for task counters and CPU counters as well: | |
520 | */ | |
521 | struct perf_counter_context { | |
0793a61d | 522 | /* |
d859e29f PM |
523 | * Protect the states of the counters in the list, |
524 | * nr_active, and the list: | |
0793a61d TG |
525 | */ |
526 | spinlock_t lock; | |
d859e29f PM |
527 | /* |
528 | * Protect the list of counters. Locking either mutex or lock | |
529 | * is sufficient to ensure the list doesn't change; to change | |
530 | * the list you need to lock both the mutex and the spinlock. | |
531 | */ | |
532 | struct mutex mutex; | |
04289bb9 IM |
533 | |
534 | struct list_head counter_list; | |
592903cd | 535 | struct list_head event_list; |
0793a61d TG |
536 | int nr_counters; |
537 | int nr_active; | |
d859e29f | 538 | int is_active; |
a63eaf34 | 539 | atomic_t refcount; |
0793a61d | 540 | struct task_struct *task; |
53cfbf59 PM |
541 | |
542 | /* | |
4af4998b | 543 | * Context clock, runs when context enabled. |
53cfbf59 | 544 | */ |
4af4998b PZ |
545 | u64 time; |
546 | u64 timestamp; | |
564c2b21 PM |
547 | |
548 | /* | |
549 | * These fields let us detect when two contexts have both | |
550 | * been cloned (inherited) from a common ancestor. | |
551 | */ | |
552 | struct perf_counter_context *parent_ctx; | |
c93f7669 PM |
553 | u64 parent_gen; |
554 | u64 generation; | |
25346b93 | 555 | int pin_count; |
c93f7669 | 556 | struct rcu_head rcu_head; |
0793a61d TG |
557 | }; |
558 | ||
559 | /** | |
560 | * struct perf_counter_cpu_context - per cpu counter context structure | |
561 | */ | |
562 | struct perf_cpu_context { | |
563 | struct perf_counter_context ctx; | |
564 | struct perf_counter_context *task_ctx; | |
565 | int active_oncpu; | |
566 | int max_pertask; | |
3b6f9e5c | 567 | int exclusive; |
96f6d444 PZ |
568 | |
569 | /* | |
570 | * Recursion avoidance: | |
571 | * | |
572 | * task, softirq, irq, nmi context | |
573 | */ | |
22a4f650 | 574 | int recursion[4]; |
0793a61d TG |
575 | }; |
576 | ||
829b42dd RR |
577 | #ifdef CONFIG_PERF_COUNTERS |
578 | ||
0793a61d TG |
579 | /* |
580 | * Set by architecture code: | |
581 | */ | |
582 | extern int perf_max_counters; | |
583 | ||
4aeb0b42 | 584 | extern const struct pmu *hw_perf_counter_init(struct perf_counter *counter); |
621a01ea | 585 | |
0793a61d | 586 | extern void perf_counter_task_sched_in(struct task_struct *task, int cpu); |
564c2b21 PM |
587 | extern void perf_counter_task_sched_out(struct task_struct *task, |
588 | struct task_struct *next, int cpu); | |
0793a61d | 589 | extern void perf_counter_task_tick(struct task_struct *task, int cpu); |
6ab423e0 | 590 | extern int perf_counter_init_task(struct task_struct *child); |
9b51f66d | 591 | extern void perf_counter_exit_task(struct task_struct *child); |
bbbee908 | 592 | extern void perf_counter_free_task(struct task_struct *task); |
925d519a | 593 | extern void perf_counter_do_pending(void); |
0793a61d | 594 | extern void perf_counter_print_debug(void); |
9e35ad38 PZ |
595 | extern void __perf_disable(void); |
596 | extern bool __perf_enable(void); | |
597 | extern void perf_disable(void); | |
598 | extern void perf_enable(void); | |
1d1c7ddb IM |
599 | extern int perf_counter_task_disable(void); |
600 | extern int perf_counter_task_enable(void); | |
3cbed429 PM |
601 | extern int hw_perf_group_sched_in(struct perf_counter *group_leader, |
602 | struct perf_cpu_context *cpuctx, | |
603 | struct perf_counter_context *ctx, int cpu); | |
37d81828 | 604 | extern void perf_counter_update_userpage(struct perf_counter *counter); |
5c92d124 | 605 | |
df1a132b | 606 | struct perf_sample_data { |
9e350de3 PZ |
607 | struct pt_regs *regs; |
608 | u64 addr; | |
609 | u64 period; | |
df1a132b PZ |
610 | }; |
611 | ||
612 | extern int perf_counter_overflow(struct perf_counter *counter, int nmi, | |
613 | struct perf_sample_data *data); | |
614 | ||
3b6f9e5c PM |
615 | /* |
616 | * Return 1 for a software counter, 0 for a hardware counter | |
617 | */ | |
618 | static inline int is_software_counter(struct perf_counter *counter) | |
619 | { | |
a21ca2ca IM |
620 | return (counter->attr.type != PERF_TYPE_RAW) && |
621 | (counter->attr.type != PERF_TYPE_HARDWARE); | |
3b6f9e5c PM |
622 | } |
623 | ||
78f13e95 | 624 | extern void perf_swcounter_event(u32, u64, int, struct pt_regs *, u64); |
15dbf27c | 625 | |
089dd79d PZ |
626 | extern void __perf_counter_mmap(struct vm_area_struct *vma); |
627 | ||
628 | static inline void perf_counter_mmap(struct vm_area_struct *vma) | |
629 | { | |
630 | if (vma->vm_flags & VM_EXEC) | |
631 | __perf_counter_mmap(vma); | |
632 | } | |
0a4a9391 | 633 | |
8d1b2d93 | 634 | extern void perf_counter_comm(struct task_struct *tsk); |
60313ebe | 635 | extern void perf_counter_fork(struct task_struct *tsk); |
8d1b2d93 | 636 | |
3f731ca6 PM |
637 | extern void perf_counter_task_migration(struct task_struct *task, int cpu); |
638 | ||
9c03d88e | 639 | #define MAX_STACK_DEPTH 255 |
394ee076 PZ |
640 | |
641 | struct perf_callchain_entry { | |
9c03d88e | 642 | u16 nr, hv, kernel, user; |
394ee076 PZ |
643 | u64 ip[MAX_STACK_DEPTH]; |
644 | }; | |
645 | ||
646 | extern struct perf_callchain_entry *perf_callchain(struct pt_regs *regs); | |
647 | ||
0764771d | 648 | extern int sysctl_perf_counter_paranoid; |
c5078f78 | 649 | extern int sysctl_perf_counter_mlock; |
df58ab24 | 650 | extern int sysctl_perf_counter_sample_rate; |
1ccd1549 | 651 | |
0d905bca IM |
652 | extern void perf_counter_init(void); |
653 | ||
9d23a90a PM |
654 | #ifndef perf_misc_flags |
655 | #define perf_misc_flags(regs) (user_mode(regs) ? PERF_EVENT_MISC_USER : \ | |
656 | PERF_EVENT_MISC_KERNEL) | |
657 | #define perf_instruction_pointer(regs) instruction_pointer(regs) | |
658 | #endif | |
659 | ||
0793a61d TG |
660 | #else |
661 | static inline void | |
662 | perf_counter_task_sched_in(struct task_struct *task, int cpu) { } | |
663 | static inline void | |
910431c7 IM |
664 | perf_counter_task_sched_out(struct task_struct *task, |
665 | struct task_struct *next, int cpu) { } | |
0793a61d TG |
666 | static inline void |
667 | perf_counter_task_tick(struct task_struct *task, int cpu) { } | |
d3e78ee3 | 668 | static inline int perf_counter_init_task(struct task_struct *child) { return 0; } |
9b51f66d | 669 | static inline void perf_counter_exit_task(struct task_struct *child) { } |
bbbee908 | 670 | static inline void perf_counter_free_task(struct task_struct *task) { } |
925d519a | 671 | static inline void perf_counter_do_pending(void) { } |
0793a61d | 672 | static inline void perf_counter_print_debug(void) { } |
9e35ad38 PZ |
673 | static inline void perf_disable(void) { } |
674 | static inline void perf_enable(void) { } | |
1d1c7ddb IM |
675 | static inline int perf_counter_task_disable(void) { return -EINVAL; } |
676 | static inline int perf_counter_task_enable(void) { return -EINVAL; } | |
15dbf27c | 677 | |
925d519a | 678 | static inline void |
78f13e95 PZ |
679 | perf_swcounter_event(u32 event, u64 nr, int nmi, |
680 | struct pt_regs *regs, u64 addr) { } | |
0a4a9391 | 681 | |
089dd79d | 682 | static inline void perf_counter_mmap(struct vm_area_struct *vma) { } |
8d1b2d93 | 683 | static inline void perf_counter_comm(struct task_struct *tsk) { } |
60313ebe | 684 | static inline void perf_counter_fork(struct task_struct *tsk) { } |
0d905bca | 685 | static inline void perf_counter_init(void) { } |
3f731ca6 PM |
686 | static inline void perf_counter_task_migration(struct task_struct *task, |
687 | int cpu) { } | |
0793a61d TG |
688 | #endif |
689 | ||
f3dfd265 | 690 | #endif /* __KERNEL__ */ |
0793a61d | 691 | #endif /* _LINUX_PERF_COUNTER_H */ |