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0793a61d TG |
1 | /* |
2 | * Performance counters: | |
3 | * | |
4 | * Copyright(C) 2008, Thomas Gleixner <tglx@linutronix.de> | |
5 | * Copyright(C) 2008, Red Hat, Inc., Ingo Molnar | |
6 | * | |
7 | * Data type definitions, declarations, prototypes. | |
8 | * | |
9 | * Started by: Thomas Gleixner and Ingo Molnar | |
10 | * | |
11 | * For licencing details see kernel-base/COPYING | |
12 | */ | |
13 | #ifndef _LINUX_PERF_COUNTER_H | |
14 | #define _LINUX_PERF_COUNTER_H | |
15 | ||
f3dfd265 PM |
16 | #include <linux/types.h> |
17 | #include <linux/ioctl.h> | |
9aaa131a | 18 | #include <asm/byteorder.h> |
0793a61d TG |
19 | |
20 | /* | |
9f66a381 IM |
21 | * User-space ABI bits: |
22 | */ | |
23 | ||
24 | /* | |
b8e83514 | 25 | * hw_event.type |
0793a61d | 26 | */ |
b8e83514 PZ |
27 | enum perf_event_types { |
28 | PERF_TYPE_HARDWARE = 0, | |
29 | PERF_TYPE_SOFTWARE = 1, | |
30 | PERF_TYPE_TRACEPOINT = 2, | |
31 | ||
0793a61d | 32 | /* |
b8e83514 | 33 | * available TYPE space, raw is the max value. |
0793a61d | 34 | */ |
9f66a381 | 35 | |
b8e83514 PZ |
36 | PERF_TYPE_RAW = 128, |
37 | }; | |
6c594c21 | 38 | |
b8e83514 PZ |
39 | /* |
40 | * Generalized performance counter event types, used by the hw_event.event_id | |
41 | * parameter of the sys_perf_counter_open() syscall: | |
42 | */ | |
43 | enum hw_event_ids { | |
9f66a381 | 44 | /* |
b8e83514 | 45 | * Common hardware events, generalized by the kernel: |
9f66a381 | 46 | */ |
b8e83514 PZ |
47 | PERF_COUNT_CPU_CYCLES = 0, |
48 | PERF_COUNT_INSTRUCTIONS = 1, | |
49 | PERF_COUNT_CACHE_REFERENCES = 2, | |
50 | PERF_COUNT_CACHE_MISSES = 3, | |
51 | PERF_COUNT_BRANCH_INSTRUCTIONS = 4, | |
52 | PERF_COUNT_BRANCH_MISSES = 5, | |
53 | PERF_COUNT_BUS_CYCLES = 6, | |
54 | ||
55 | PERF_HW_EVENTS_MAX = 7, | |
56 | }; | |
e077df4f | 57 | |
b8e83514 PZ |
58 | /* |
59 | * Special "software" counters provided by the kernel, even if the hardware | |
60 | * does not support performance counters. These counters measure various | |
61 | * physical and sw events of the kernel (and allow the profiling of them as | |
62 | * well): | |
63 | */ | |
64 | enum sw_event_ids { | |
65 | PERF_COUNT_CPU_CLOCK = 0, | |
66 | PERF_COUNT_TASK_CLOCK = 1, | |
67 | PERF_COUNT_PAGE_FAULTS = 2, | |
68 | PERF_COUNT_CONTEXT_SWITCHES = 3, | |
69 | PERF_COUNT_CPU_MIGRATIONS = 4, | |
70 | PERF_COUNT_PAGE_FAULTS_MIN = 5, | |
71 | PERF_COUNT_PAGE_FAULTS_MAJ = 6, | |
72 | ||
73 | PERF_SW_EVENTS_MAX = 7, | |
0793a61d TG |
74 | }; |
75 | ||
f4a2deb4 PZ |
76 | #define __PERF_COUNTER_MASK(name) \ |
77 | (((1ULL << PERF_COUNTER_##name##_BITS) - 1) << \ | |
78 | PERF_COUNTER_##name##_SHIFT) | |
79 | ||
80 | #define PERF_COUNTER_RAW_BITS 1 | |
81 | #define PERF_COUNTER_RAW_SHIFT 63 | |
82 | #define PERF_COUNTER_RAW_MASK __PERF_COUNTER_MASK(RAW) | |
83 | ||
84 | #define PERF_COUNTER_CONFIG_BITS 63 | |
85 | #define PERF_COUNTER_CONFIG_SHIFT 0 | |
86 | #define PERF_COUNTER_CONFIG_MASK __PERF_COUNTER_MASK(CONFIG) | |
87 | ||
88 | #define PERF_COUNTER_TYPE_BITS 7 | |
89 | #define PERF_COUNTER_TYPE_SHIFT 56 | |
90 | #define PERF_COUNTER_TYPE_MASK __PERF_COUNTER_MASK(TYPE) | |
91 | ||
92 | #define PERF_COUNTER_EVENT_BITS 56 | |
93 | #define PERF_COUNTER_EVENT_SHIFT 0 | |
94 | #define PERF_COUNTER_EVENT_MASK __PERF_COUNTER_MASK(EVENT) | |
95 | ||
8a057d84 PZ |
96 | /* |
97 | * Bits that can be set in hw_event.record_type to request information | |
98 | * in the overflow packets. | |
99 | */ | |
100 | enum perf_counter_record_format { | |
101 | PERF_RECORD_IP = 1U << 0, | |
102 | PERF_RECORD_TID = 1U << 1, | |
4d855457 | 103 | PERF_RECORD_TIME = 1U << 2, |
78f13e95 PZ |
104 | PERF_RECORD_ADDR = 1U << 3, |
105 | PERF_RECORD_GROUP = 1U << 4, | |
106 | PERF_RECORD_CALLCHAIN = 1U << 5, | |
8a057d84 PZ |
107 | }; |
108 | ||
53cfbf59 PM |
109 | /* |
110 | * Bits that can be set in hw_event.read_format to request that | |
111 | * reads on the counter should return the indicated quantities, | |
112 | * in increasing order of bit value, after the counter value. | |
113 | */ | |
114 | enum perf_counter_read_format { | |
115 | PERF_FORMAT_TOTAL_TIME_ENABLED = 1, | |
116 | PERF_FORMAT_TOTAL_TIME_RUNNING = 2, | |
117 | }; | |
118 | ||
9f66a381 IM |
119 | /* |
120 | * Hardware event to monitor via a performance monitoring counter: | |
121 | */ | |
122 | struct perf_counter_hw_event { | |
f4a2deb4 PZ |
123 | /* |
124 | * The MSB of the config word signifies if the rest contains cpu | |
125 | * specific (raw) counter configuration data, if unset, the next | |
126 | * 7 bits are an event type and the rest of the bits are the event | |
127 | * identifier. | |
128 | */ | |
129 | __u64 config; | |
9f66a381 | 130 | |
f3dfd265 | 131 | __u64 irq_period; |
8a057d84 PZ |
132 | __u32 record_type; |
133 | __u32 read_format; | |
9f66a381 | 134 | |
2743a5b0 | 135 | __u64 disabled : 1, /* off by default */ |
0475f9ea | 136 | nmi : 1, /* NMI sampling */ |
0475f9ea PM |
137 | inherit : 1, /* children inherit it */ |
138 | pinned : 1, /* must always be on PMU */ | |
139 | exclusive : 1, /* only group on PMU */ | |
140 | exclude_user : 1, /* don't count user */ | |
141 | exclude_kernel : 1, /* ditto kernel */ | |
142 | exclude_hv : 1, /* ditto hypervisor */ | |
2743a5b0 | 143 | exclude_idle : 1, /* don't count when idle */ |
0a4a9391 PZ |
144 | mmap : 1, /* include mmap data */ |
145 | munmap : 1, /* include munmap data */ | |
8d1b2d93 | 146 | comm : 1, /* include comm data */ |
0475f9ea | 147 | |
8d1b2d93 | 148 | __reserved_1 : 52; |
2743a5b0 PM |
149 | |
150 | __u32 extra_config_len; | |
c457810a | 151 | __u32 wakeup_events; /* wakeup every n events */ |
9f66a381 | 152 | |
f3dfd265 | 153 | __u64 __reserved_2; |
2743a5b0 | 154 | __u64 __reserved_3; |
eab656ae TG |
155 | }; |
156 | ||
d859e29f PM |
157 | /* |
158 | * Ioctls that can be done on a perf counter fd: | |
159 | */ | |
79f14641 PZ |
160 | #define PERF_COUNTER_IOC_ENABLE _IO ('$', 0) |
161 | #define PERF_COUNTER_IOC_DISABLE _IO ('$', 1) | |
162 | #define PERF_COUNTER_IOC_REFRESH _IOW('$', 2, u32) | |
6de6a7b9 | 163 | #define PERF_COUNTER_IOC_RESET _IO ('$', 3) |
d859e29f | 164 | |
37d81828 PM |
165 | /* |
166 | * Structure of the page that can be mapped via mmap | |
167 | */ | |
168 | struct perf_counter_mmap_page { | |
169 | __u32 version; /* version number of this structure */ | |
170 | __u32 compat_version; /* lowest version this is compat with */ | |
38ff667b PZ |
171 | |
172 | /* | |
173 | * Bits needed to read the hw counters in user-space. | |
174 | * | |
92f22a38 PZ |
175 | * u32 seq; |
176 | * s64 count; | |
38ff667b | 177 | * |
a2e87d06 PZ |
178 | * do { |
179 | * seq = pc->lock; | |
38ff667b | 180 | * |
a2e87d06 PZ |
181 | * barrier() |
182 | * if (pc->index) { | |
183 | * count = pmc_read(pc->index - 1); | |
184 | * count += pc->offset; | |
185 | * } else | |
186 | * goto regular_read; | |
38ff667b | 187 | * |
a2e87d06 PZ |
188 | * barrier(); |
189 | * } while (pc->lock != seq); | |
38ff667b | 190 | * |
92f22a38 PZ |
191 | * NOTE: for obvious reason this only works on self-monitoring |
192 | * processes. | |
38ff667b | 193 | */ |
37d81828 PM |
194 | __u32 lock; /* seqlock for synchronization */ |
195 | __u32 index; /* hardware counter identifier */ | |
196 | __s64 offset; /* add to hardware counter value */ | |
7b732a75 | 197 | |
38ff667b PZ |
198 | /* |
199 | * Control data for the mmap() data buffer. | |
200 | * | |
201 | * User-space reading this value should issue an rmb(), on SMP capable | |
202 | * platforms, after reading this value -- see perf_counter_wakeup(). | |
203 | */ | |
7b732a75 | 204 | __u32 data_head; /* head in the data section */ |
37d81828 PM |
205 | }; |
206 | ||
6b6e5486 PZ |
207 | #define PERF_EVENT_MISC_KERNEL (1 << 0) |
208 | #define PERF_EVENT_MISC_USER (1 << 1) | |
209 | #define PERF_EVENT_MISC_OVERFLOW (1 << 2) | |
6fab0192 | 210 | |
5c148194 PZ |
211 | struct perf_event_header { |
212 | __u32 type; | |
6fab0192 PZ |
213 | __u16 misc; |
214 | __u16 size; | |
5c148194 PZ |
215 | }; |
216 | ||
217 | enum perf_event_type { | |
5ed00415 | 218 | |
0c593b34 PZ |
219 | /* |
220 | * The MMAP events record the PROT_EXEC mappings so that we can | |
221 | * correlate userspace IPs to code. They have the following structure: | |
222 | * | |
223 | * struct { | |
224 | * struct perf_event_header header; | |
225 | * | |
226 | * u32 pid, tid; | |
227 | * u64 addr; | |
228 | * u64 len; | |
229 | * u64 pgoff; | |
230 | * char filename[]; | |
231 | * }; | |
232 | */ | |
8a057d84 PZ |
233 | PERF_EVENT_MMAP = 1, |
234 | PERF_EVENT_MUNMAP = 2, | |
0a4a9391 | 235 | |
8d1b2d93 PZ |
236 | /* |
237 | * struct { | |
238 | * struct perf_event_header header; | |
239 | * | |
240 | * u32 pid, tid; | |
241 | * char comm[]; | |
242 | * }; | |
243 | */ | |
244 | PERF_EVENT_COMM = 3, | |
245 | ||
8a057d84 | 246 | /* |
6b6e5486 PZ |
247 | * When header.misc & PERF_EVENT_MISC_OVERFLOW the event_type field |
248 | * will be PERF_RECORD_* | |
0c593b34 PZ |
249 | * |
250 | * struct { | |
251 | * struct perf_event_header header; | |
252 | * | |
6b6e5486 PZ |
253 | * { u64 ip; } && PERF_RECORD_IP |
254 | * { u32 pid, tid; } && PERF_RECORD_TID | |
4d855457 | 255 | * { u64 time; } && PERF_RECORD_TIME |
78f13e95 | 256 | * { u64 addr; } && PERF_RECORD_ADDR |
0c593b34 PZ |
257 | * |
258 | * { u64 nr; | |
6b6e5486 | 259 | * { u64 event, val; } cnt[nr]; } && PERF_RECORD_GROUP |
0c593b34 PZ |
260 | * |
261 | * { u16 nr, | |
262 | * hv, | |
263 | * kernel, | |
264 | * user; | |
6b6e5486 | 265 | * u64 ips[nr]; } && PERF_RECORD_CALLCHAIN |
0c593b34 | 266 | * }; |
8a057d84 | 267 | */ |
5c148194 PZ |
268 | }; |
269 | ||
f3dfd265 | 270 | #ifdef __KERNEL__ |
9f66a381 | 271 | /* |
f3dfd265 | 272 | * Kernel-internal data types and definitions: |
9f66a381 IM |
273 | */ |
274 | ||
f3dfd265 PM |
275 | #ifdef CONFIG_PERF_COUNTERS |
276 | # include <asm/perf_counter.h> | |
277 | #endif | |
278 | ||
279 | #include <linux/list.h> | |
280 | #include <linux/mutex.h> | |
281 | #include <linux/rculist.h> | |
282 | #include <linux/rcupdate.h> | |
283 | #include <linux/spinlock.h> | |
d6d020e9 | 284 | #include <linux/hrtimer.h> |
3c446b3d | 285 | #include <linux/fs.h> |
f3dfd265 PM |
286 | #include <asm/atomic.h> |
287 | ||
288 | struct task_struct; | |
289 | ||
f4a2deb4 PZ |
290 | static inline u64 perf_event_raw(struct perf_counter_hw_event *hw_event) |
291 | { | |
292 | return hw_event->config & PERF_COUNTER_RAW_MASK; | |
293 | } | |
294 | ||
295 | static inline u64 perf_event_config(struct perf_counter_hw_event *hw_event) | |
296 | { | |
297 | return hw_event->config & PERF_COUNTER_CONFIG_MASK; | |
298 | } | |
299 | ||
300 | static inline u64 perf_event_type(struct perf_counter_hw_event *hw_event) | |
301 | { | |
302 | return (hw_event->config & PERF_COUNTER_TYPE_MASK) >> | |
303 | PERF_COUNTER_TYPE_SHIFT; | |
304 | } | |
305 | ||
306 | static inline u64 perf_event_id(struct perf_counter_hw_event *hw_event) | |
307 | { | |
308 | return hw_event->config & PERF_COUNTER_EVENT_MASK; | |
309 | } | |
310 | ||
0793a61d | 311 | /** |
9f66a381 | 312 | * struct hw_perf_counter - performance counter hardware details: |
0793a61d TG |
313 | */ |
314 | struct hw_perf_counter { | |
ee06094f | 315 | #ifdef CONFIG_PERF_COUNTERS |
d6d020e9 PZ |
316 | union { |
317 | struct { /* hardware */ | |
318 | u64 config; | |
319 | unsigned long config_base; | |
320 | unsigned long counter_base; | |
321 | int nmi; | |
6f00cada | 322 | int idx; |
d6d020e9 PZ |
323 | }; |
324 | union { /* software */ | |
325 | atomic64_t count; | |
326 | struct hrtimer hrtimer; | |
327 | }; | |
328 | }; | |
ee06094f | 329 | atomic64_t prev_count; |
9f66a381 | 330 | u64 irq_period; |
ee06094f IM |
331 | atomic64_t period_left; |
332 | #endif | |
0793a61d TG |
333 | }; |
334 | ||
621a01ea IM |
335 | struct perf_counter; |
336 | ||
337 | /** | |
4aeb0b42 | 338 | * struct pmu - generic performance monitoring unit |
621a01ea | 339 | */ |
4aeb0b42 | 340 | struct pmu { |
95cdd2e7 | 341 | int (*enable) (struct perf_counter *counter); |
7671581f IM |
342 | void (*disable) (struct perf_counter *counter); |
343 | void (*read) (struct perf_counter *counter); | |
621a01ea IM |
344 | }; |
345 | ||
6a930700 IM |
346 | /** |
347 | * enum perf_counter_active_state - the states of a counter | |
348 | */ | |
349 | enum perf_counter_active_state { | |
3b6f9e5c | 350 | PERF_COUNTER_STATE_ERROR = -2, |
6a930700 IM |
351 | PERF_COUNTER_STATE_OFF = -1, |
352 | PERF_COUNTER_STATE_INACTIVE = 0, | |
353 | PERF_COUNTER_STATE_ACTIVE = 1, | |
354 | }; | |
355 | ||
9b51f66d IM |
356 | struct file; |
357 | ||
7b732a75 PZ |
358 | struct perf_mmap_data { |
359 | struct rcu_head rcu_head; | |
8740f941 PZ |
360 | int nr_pages; /* nr of data pages */ |
361 | ||
c33a0bc4 | 362 | atomic_t poll; /* POLL_ for wakeups */ |
8740f941 PZ |
363 | atomic_t head; /* write position */ |
364 | atomic_t events; /* event limit */ | |
365 | ||
c66de4a5 | 366 | atomic_t done_head; /* completed head */ |
c33a0bc4 PZ |
367 | atomic_t lock; /* concurrent writes */ |
368 | ||
c66de4a5 PZ |
369 | atomic_t wakeup; /* needs a wakeup */ |
370 | ||
7b732a75 PZ |
371 | struct perf_counter_mmap_page *user_page; |
372 | void *data_pages[0]; | |
373 | }; | |
374 | ||
671dec5d PZ |
375 | struct perf_pending_entry { |
376 | struct perf_pending_entry *next; | |
377 | void (*func)(struct perf_pending_entry *); | |
925d519a PZ |
378 | }; |
379 | ||
0793a61d TG |
380 | /** |
381 | * struct perf_counter - performance counter kernel representation: | |
382 | */ | |
383 | struct perf_counter { | |
ee06094f | 384 | #ifdef CONFIG_PERF_COUNTERS |
04289bb9 | 385 | struct list_head list_entry; |
592903cd | 386 | struct list_head event_entry; |
04289bb9 | 387 | struct list_head sibling_list; |
5c148194 | 388 | int nr_siblings; |
04289bb9 | 389 | struct perf_counter *group_leader; |
4aeb0b42 | 390 | const struct pmu *pmu; |
04289bb9 | 391 | |
6a930700 | 392 | enum perf_counter_active_state state; |
c07c99b6 | 393 | enum perf_counter_active_state prev_state; |
0793a61d | 394 | atomic64_t count; |
ee06094f | 395 | |
53cfbf59 PM |
396 | /* |
397 | * These are the total time in nanoseconds that the counter | |
398 | * has been enabled (i.e. eligible to run, and the task has | |
399 | * been scheduled in, if this is a per-task counter) | |
400 | * and running (scheduled onto the CPU), respectively. | |
401 | * | |
402 | * They are computed from tstamp_enabled, tstamp_running and | |
403 | * tstamp_stopped when the counter is in INACTIVE or ACTIVE state. | |
404 | */ | |
405 | u64 total_time_enabled; | |
406 | u64 total_time_running; | |
407 | ||
408 | /* | |
409 | * These are timestamps used for computing total_time_enabled | |
410 | * and total_time_running when the counter is in INACTIVE or | |
411 | * ACTIVE state, measured in nanoseconds from an arbitrary point | |
412 | * in time. | |
413 | * tstamp_enabled: the notional time when the counter was enabled | |
414 | * tstamp_running: the notional time when the counter was scheduled on | |
415 | * tstamp_stopped: in INACTIVE state, the notional time when the | |
416 | * counter was scheduled off. | |
417 | */ | |
418 | u64 tstamp_enabled; | |
419 | u64 tstamp_running; | |
420 | u64 tstamp_stopped; | |
421 | ||
9f66a381 | 422 | struct perf_counter_hw_event hw_event; |
0793a61d TG |
423 | struct hw_perf_counter hw; |
424 | ||
425 | struct perf_counter_context *ctx; | |
426 | struct task_struct *task; | |
9b51f66d | 427 | struct file *filp; |
0793a61d | 428 | |
9b51f66d | 429 | struct perf_counter *parent; |
d859e29f PM |
430 | struct list_head child_list; |
431 | ||
53cfbf59 PM |
432 | /* |
433 | * These accumulate total time (in nanoseconds) that children | |
434 | * counters have been enabled and running, respectively. | |
435 | */ | |
436 | atomic64_t child_total_time_enabled; | |
437 | atomic64_t child_total_time_running; | |
438 | ||
0793a61d | 439 | /* |
d859e29f | 440 | * Protect attach/detach and child_list: |
0793a61d TG |
441 | */ |
442 | struct mutex mutex; | |
443 | ||
444 | int oncpu; | |
445 | int cpu; | |
446 | ||
7b732a75 PZ |
447 | /* mmap bits */ |
448 | struct mutex mmap_mutex; | |
449 | atomic_t mmap_count; | |
450 | struct perf_mmap_data *data; | |
37d81828 | 451 | |
7b732a75 | 452 | /* poll related */ |
0793a61d | 453 | wait_queue_head_t waitq; |
3c446b3d | 454 | struct fasync_struct *fasync; |
79f14641 PZ |
455 | |
456 | /* delayed work for NMIs and such */ | |
457 | int pending_wakeup; | |
4c9e2542 | 458 | int pending_kill; |
79f14641 | 459 | int pending_disable; |
671dec5d | 460 | struct perf_pending_entry pending; |
592903cd | 461 | |
79f14641 PZ |
462 | atomic_t event_limit; |
463 | ||
e077df4f | 464 | void (*destroy)(struct perf_counter *); |
592903cd | 465 | struct rcu_head rcu_head; |
ee06094f | 466 | #endif |
0793a61d TG |
467 | }; |
468 | ||
469 | /** | |
470 | * struct perf_counter_context - counter context structure | |
471 | * | |
472 | * Used as a container for task counters and CPU counters as well: | |
473 | */ | |
474 | struct perf_counter_context { | |
475 | #ifdef CONFIG_PERF_COUNTERS | |
476 | /* | |
d859e29f PM |
477 | * Protect the states of the counters in the list, |
478 | * nr_active, and the list: | |
0793a61d TG |
479 | */ |
480 | spinlock_t lock; | |
d859e29f PM |
481 | /* |
482 | * Protect the list of counters. Locking either mutex or lock | |
483 | * is sufficient to ensure the list doesn't change; to change | |
484 | * the list you need to lock both the mutex and the spinlock. | |
485 | */ | |
486 | struct mutex mutex; | |
04289bb9 IM |
487 | |
488 | struct list_head counter_list; | |
592903cd | 489 | struct list_head event_list; |
0793a61d TG |
490 | int nr_counters; |
491 | int nr_active; | |
d859e29f | 492 | int is_active; |
0793a61d | 493 | struct task_struct *task; |
53cfbf59 PM |
494 | |
495 | /* | |
4af4998b | 496 | * Context clock, runs when context enabled. |
53cfbf59 | 497 | */ |
4af4998b PZ |
498 | u64 time; |
499 | u64 timestamp; | |
0793a61d TG |
500 | #endif |
501 | }; | |
502 | ||
503 | /** | |
504 | * struct perf_counter_cpu_context - per cpu counter context structure | |
505 | */ | |
506 | struct perf_cpu_context { | |
507 | struct perf_counter_context ctx; | |
508 | struct perf_counter_context *task_ctx; | |
509 | int active_oncpu; | |
510 | int max_pertask; | |
3b6f9e5c | 511 | int exclusive; |
96f6d444 PZ |
512 | |
513 | /* | |
514 | * Recursion avoidance: | |
515 | * | |
516 | * task, softirq, irq, nmi context | |
517 | */ | |
518 | int recursion[4]; | |
0793a61d TG |
519 | }; |
520 | ||
829b42dd RR |
521 | #ifdef CONFIG_PERF_COUNTERS |
522 | ||
0793a61d TG |
523 | /* |
524 | * Set by architecture code: | |
525 | */ | |
526 | extern int perf_max_counters; | |
527 | ||
4aeb0b42 | 528 | extern const struct pmu *hw_perf_counter_init(struct perf_counter *counter); |
621a01ea | 529 | |
0793a61d TG |
530 | extern void perf_counter_task_sched_in(struct task_struct *task, int cpu); |
531 | extern void perf_counter_task_sched_out(struct task_struct *task, int cpu); | |
532 | extern void perf_counter_task_tick(struct task_struct *task, int cpu); | |
9b51f66d IM |
533 | extern void perf_counter_init_task(struct task_struct *child); |
534 | extern void perf_counter_exit_task(struct task_struct *child); | |
925d519a | 535 | extern void perf_counter_do_pending(void); |
0793a61d | 536 | extern void perf_counter_print_debug(void); |
1b023a96 | 537 | extern void perf_counter_unthrottle(void); |
01b2838c IM |
538 | extern u64 hw_perf_save_disable(void); |
539 | extern void hw_perf_restore(u64 ctrl); | |
1d1c7ddb IM |
540 | extern int perf_counter_task_disable(void); |
541 | extern int perf_counter_task_enable(void); | |
3cbed429 PM |
542 | extern int hw_perf_group_sched_in(struct perf_counter *group_leader, |
543 | struct perf_cpu_context *cpuctx, | |
544 | struct perf_counter_context *ctx, int cpu); | |
37d81828 | 545 | extern void perf_counter_update_userpage(struct perf_counter *counter); |
5c92d124 | 546 | |
f6c7d5fe | 547 | extern int perf_counter_overflow(struct perf_counter *counter, |
78f13e95 | 548 | int nmi, struct pt_regs *regs, u64 addr); |
3b6f9e5c PM |
549 | /* |
550 | * Return 1 for a software counter, 0 for a hardware counter | |
551 | */ | |
552 | static inline int is_software_counter(struct perf_counter *counter) | |
553 | { | |
f4a2deb4 PZ |
554 | return !perf_event_raw(&counter->hw_event) && |
555 | perf_event_type(&counter->hw_event) != PERF_TYPE_HARDWARE; | |
3b6f9e5c PM |
556 | } |
557 | ||
78f13e95 | 558 | extern void perf_swcounter_event(u32, u64, int, struct pt_regs *, u64); |
15dbf27c | 559 | |
0a4a9391 PZ |
560 | extern void perf_counter_mmap(unsigned long addr, unsigned long len, |
561 | unsigned long pgoff, struct file *file); | |
562 | ||
563 | extern void perf_counter_munmap(unsigned long addr, unsigned long len, | |
564 | unsigned long pgoff, struct file *file); | |
565 | ||
8d1b2d93 PZ |
566 | extern void perf_counter_comm(struct task_struct *tsk); |
567 | ||
9c03d88e | 568 | #define MAX_STACK_DEPTH 255 |
394ee076 PZ |
569 | |
570 | struct perf_callchain_entry { | |
9c03d88e | 571 | u16 nr, hv, kernel, user; |
394ee076 PZ |
572 | u64 ip[MAX_STACK_DEPTH]; |
573 | }; | |
574 | ||
575 | extern struct perf_callchain_entry *perf_callchain(struct pt_regs *regs); | |
576 | ||
1ccd1549 PZ |
577 | extern int sysctl_perf_counter_priv; |
578 | ||
0d905bca IM |
579 | extern void perf_counter_init(void); |
580 | ||
0793a61d TG |
581 | #else |
582 | static inline void | |
583 | perf_counter_task_sched_in(struct task_struct *task, int cpu) { } | |
584 | static inline void | |
585 | perf_counter_task_sched_out(struct task_struct *task, int cpu) { } | |
586 | static inline void | |
587 | perf_counter_task_tick(struct task_struct *task, int cpu) { } | |
9b51f66d IM |
588 | static inline void perf_counter_init_task(struct task_struct *child) { } |
589 | static inline void perf_counter_exit_task(struct task_struct *child) { } | |
925d519a | 590 | static inline void perf_counter_do_pending(void) { } |
0793a61d | 591 | static inline void perf_counter_print_debug(void) { } |
1b023a96 | 592 | static inline void perf_counter_unthrottle(void) { } |
15dbf27c | 593 | static inline void hw_perf_restore(u64 ctrl) { } |
01b2838c | 594 | static inline u64 hw_perf_save_disable(void) { return 0; } |
1d1c7ddb IM |
595 | static inline int perf_counter_task_disable(void) { return -EINVAL; } |
596 | static inline int perf_counter_task_enable(void) { return -EINVAL; } | |
15dbf27c | 597 | |
925d519a | 598 | static inline void |
78f13e95 PZ |
599 | perf_swcounter_event(u32 event, u64 nr, int nmi, |
600 | struct pt_regs *regs, u64 addr) { } | |
0a4a9391 PZ |
601 | |
602 | static inline void | |
603 | perf_counter_mmap(unsigned long addr, unsigned long len, | |
604 | unsigned long pgoff, struct file *file) { } | |
605 | ||
606 | static inline void | |
607 | perf_counter_munmap(unsigned long addr, unsigned long len, | |
0d905bca | 608 | unsigned long pgoff, struct file *file) { } |
0a4a9391 | 609 | |
8d1b2d93 | 610 | static inline void perf_counter_comm(struct task_struct *tsk) { } |
0d905bca | 611 | static inline void perf_counter_init(void) { } |
0793a61d TG |
612 | #endif |
613 | ||
f3dfd265 | 614 | #endif /* __KERNEL__ */ |
0793a61d | 615 | #endif /* _LINUX_PERF_COUNTER_H */ |