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0793a61d TG |
1 | /* |
2 | * Performance counters: | |
3 | * | |
4 | * Copyright(C) 2008, Thomas Gleixner <tglx@linutronix.de> | |
5 | * Copyright(C) 2008, Red Hat, Inc., Ingo Molnar | |
6 | * | |
7 | * Data type definitions, declarations, prototypes. | |
8 | * | |
9 | * Started by: Thomas Gleixner and Ingo Molnar | |
10 | * | |
11 | * For licencing details see kernel-base/COPYING | |
12 | */ | |
13 | #ifndef _LINUX_PERF_COUNTER_H | |
14 | #define _LINUX_PERF_COUNTER_H | |
15 | ||
f3dfd265 PM |
16 | #include <linux/types.h> |
17 | #include <linux/ioctl.h> | |
9aaa131a | 18 | #include <asm/byteorder.h> |
0793a61d TG |
19 | |
20 | /* | |
9f66a381 IM |
21 | * User-space ABI bits: |
22 | */ | |
23 | ||
24 | /* | |
b8e83514 | 25 | * hw_event.type |
0793a61d | 26 | */ |
b8e83514 PZ |
27 | enum perf_event_types { |
28 | PERF_TYPE_HARDWARE = 0, | |
29 | PERF_TYPE_SOFTWARE = 1, | |
30 | PERF_TYPE_TRACEPOINT = 2, | |
31 | ||
0793a61d | 32 | /* |
b8e83514 | 33 | * available TYPE space, raw is the max value. |
0793a61d | 34 | */ |
9f66a381 | 35 | |
b8e83514 PZ |
36 | PERF_TYPE_RAW = 128, |
37 | }; | |
6c594c21 | 38 | |
b8e83514 PZ |
39 | /* |
40 | * Generalized performance counter event types, used by the hw_event.event_id | |
41 | * parameter of the sys_perf_counter_open() syscall: | |
42 | */ | |
43 | enum hw_event_ids { | |
9f66a381 | 44 | /* |
b8e83514 | 45 | * Common hardware events, generalized by the kernel: |
9f66a381 | 46 | */ |
b8e83514 PZ |
47 | PERF_COUNT_CPU_CYCLES = 0, |
48 | PERF_COUNT_INSTRUCTIONS = 1, | |
49 | PERF_COUNT_CACHE_REFERENCES = 2, | |
50 | PERF_COUNT_CACHE_MISSES = 3, | |
51 | PERF_COUNT_BRANCH_INSTRUCTIONS = 4, | |
52 | PERF_COUNT_BRANCH_MISSES = 5, | |
53 | PERF_COUNT_BUS_CYCLES = 6, | |
54 | ||
55 | PERF_HW_EVENTS_MAX = 7, | |
56 | }; | |
e077df4f | 57 | |
b8e83514 PZ |
58 | /* |
59 | * Special "software" counters provided by the kernel, even if the hardware | |
60 | * does not support performance counters. These counters measure various | |
61 | * physical and sw events of the kernel (and allow the profiling of them as | |
62 | * well): | |
63 | */ | |
64 | enum sw_event_ids { | |
65 | PERF_COUNT_CPU_CLOCK = 0, | |
66 | PERF_COUNT_TASK_CLOCK = 1, | |
67 | PERF_COUNT_PAGE_FAULTS = 2, | |
68 | PERF_COUNT_CONTEXT_SWITCHES = 3, | |
69 | PERF_COUNT_CPU_MIGRATIONS = 4, | |
70 | PERF_COUNT_PAGE_FAULTS_MIN = 5, | |
71 | PERF_COUNT_PAGE_FAULTS_MAJ = 6, | |
72 | ||
73 | PERF_SW_EVENTS_MAX = 7, | |
0793a61d TG |
74 | }; |
75 | ||
0127c3ea | 76 | #define __PERF_COUNTER_MASK(name) \ |
f4a2deb4 PZ |
77 | (((1ULL << PERF_COUNTER_##name##_BITS) - 1) << \ |
78 | PERF_COUNTER_##name##_SHIFT) | |
79 | ||
80 | #define PERF_COUNTER_RAW_BITS 1 | |
81 | #define PERF_COUNTER_RAW_SHIFT 63 | |
82 | #define PERF_COUNTER_RAW_MASK __PERF_COUNTER_MASK(RAW) | |
83 | ||
84 | #define PERF_COUNTER_CONFIG_BITS 63 | |
85 | #define PERF_COUNTER_CONFIG_SHIFT 0 | |
86 | #define PERF_COUNTER_CONFIG_MASK __PERF_COUNTER_MASK(CONFIG) | |
87 | ||
88 | #define PERF_COUNTER_TYPE_BITS 7 | |
89 | #define PERF_COUNTER_TYPE_SHIFT 56 | |
90 | #define PERF_COUNTER_TYPE_MASK __PERF_COUNTER_MASK(TYPE) | |
91 | ||
92 | #define PERF_COUNTER_EVENT_BITS 56 | |
93 | #define PERF_COUNTER_EVENT_SHIFT 0 | |
94 | #define PERF_COUNTER_EVENT_MASK __PERF_COUNTER_MASK(EVENT) | |
95 | ||
8a057d84 | 96 | /* |
b23f3325 | 97 | * Bits that can be set in hw_event.sample_type to request information |
8a057d84 PZ |
98 | * in the overflow packets. |
99 | */ | |
b23f3325 PZ |
100 | enum perf_counter_sample_format { |
101 | PERF_SAMPLE_IP = 1U << 0, | |
102 | PERF_SAMPLE_TID = 1U << 1, | |
103 | PERF_SAMPLE_TIME = 1U << 2, | |
104 | PERF_SAMPLE_ADDR = 1U << 3, | |
105 | PERF_SAMPLE_GROUP = 1U << 4, | |
106 | PERF_SAMPLE_CALLCHAIN = 1U << 5, | |
107 | PERF_SAMPLE_CONFIG = 1U << 6, | |
108 | PERF_SAMPLE_CPU = 1U << 7, | |
8a057d84 PZ |
109 | }; |
110 | ||
53cfbf59 PM |
111 | /* |
112 | * Bits that can be set in hw_event.read_format to request that | |
113 | * reads on the counter should return the indicated quantities, | |
114 | * in increasing order of bit value, after the counter value. | |
115 | */ | |
116 | enum perf_counter_read_format { | |
8e5799b1 PZ |
117 | PERF_FORMAT_TOTAL_TIME_ENABLED = 1U << 0, |
118 | PERF_FORMAT_TOTAL_TIME_RUNNING = 1U << 1, | |
119 | PERF_FORMAT_ID = 1U << 2, | |
53cfbf59 PM |
120 | }; |
121 | ||
9f66a381 IM |
122 | /* |
123 | * Hardware event to monitor via a performance monitoring counter: | |
124 | */ | |
125 | struct perf_counter_hw_event { | |
f4a2deb4 PZ |
126 | /* |
127 | * The MSB of the config word signifies if the rest contains cpu | |
128 | * specific (raw) counter configuration data, if unset, the next | |
129 | * 7 bits are an event type and the rest of the bits are the event | |
130 | * identifier. | |
131 | */ | |
132 | __u64 config; | |
9f66a381 | 133 | |
60db5e09 | 134 | union { |
b23f3325 PZ |
135 | __u64 sample_period; |
136 | __u64 sample_freq; | |
60db5e09 PZ |
137 | }; |
138 | ||
b23f3325 PZ |
139 | __u64 sample_type; |
140 | __u64 read_format; | |
9f66a381 | 141 | |
2743a5b0 | 142 | __u64 disabled : 1, /* off by default */ |
0475f9ea PM |
143 | inherit : 1, /* children inherit it */ |
144 | pinned : 1, /* must always be on PMU */ | |
145 | exclusive : 1, /* only group on PMU */ | |
146 | exclude_user : 1, /* don't count user */ | |
147 | exclude_kernel : 1, /* ditto kernel */ | |
148 | exclude_hv : 1, /* ditto hypervisor */ | |
2743a5b0 | 149 | exclude_idle : 1, /* don't count when idle */ |
0a4a9391 PZ |
150 | mmap : 1, /* include mmap data */ |
151 | munmap : 1, /* include munmap data */ | |
8d1b2d93 | 152 | comm : 1, /* include comm data */ |
60db5e09 | 153 | freq : 1, /* use freq, not period */ |
0475f9ea | 154 | |
8a016db3 | 155 | __reserved_1 : 52; |
2743a5b0 | 156 | |
c457810a | 157 | __u32 wakeup_events; /* wakeup every n events */ |
e527ea31 | 158 | __u32 __reserved_2; |
9f66a381 | 159 | |
2743a5b0 | 160 | __u64 __reserved_3; |
e527ea31 | 161 | __u64 __reserved_4; |
eab656ae TG |
162 | }; |
163 | ||
d859e29f PM |
164 | /* |
165 | * Ioctls that can be done on a perf counter fd: | |
166 | */ | |
3df5edad PZ |
167 | #define PERF_COUNTER_IOC_ENABLE _IOW('$', 0, u32) |
168 | #define PERF_COUNTER_IOC_DISABLE _IOW('$', 1, u32) | |
79f14641 | 169 | #define PERF_COUNTER_IOC_REFRESH _IOW('$', 2, u32) |
3df5edad PZ |
170 | #define PERF_COUNTER_IOC_RESET _IOW('$', 3, u32) |
171 | ||
172 | enum perf_counter_ioc_flags { | |
173 | PERF_IOC_FLAG_GROUP = 1U << 0, | |
174 | }; | |
d859e29f | 175 | |
37d81828 PM |
176 | /* |
177 | * Structure of the page that can be mapped via mmap | |
178 | */ | |
179 | struct perf_counter_mmap_page { | |
180 | __u32 version; /* version number of this structure */ | |
181 | __u32 compat_version; /* lowest version this is compat with */ | |
38ff667b PZ |
182 | |
183 | /* | |
184 | * Bits needed to read the hw counters in user-space. | |
185 | * | |
92f22a38 PZ |
186 | * u32 seq; |
187 | * s64 count; | |
38ff667b | 188 | * |
a2e87d06 PZ |
189 | * do { |
190 | * seq = pc->lock; | |
38ff667b | 191 | * |
a2e87d06 PZ |
192 | * barrier() |
193 | * if (pc->index) { | |
194 | * count = pmc_read(pc->index - 1); | |
195 | * count += pc->offset; | |
196 | * } else | |
197 | * goto regular_read; | |
38ff667b | 198 | * |
a2e87d06 PZ |
199 | * barrier(); |
200 | * } while (pc->lock != seq); | |
38ff667b | 201 | * |
92f22a38 PZ |
202 | * NOTE: for obvious reason this only works on self-monitoring |
203 | * processes. | |
38ff667b | 204 | */ |
37d81828 PM |
205 | __u32 lock; /* seqlock for synchronization */ |
206 | __u32 index; /* hardware counter identifier */ | |
207 | __s64 offset; /* add to hardware counter value */ | |
7b732a75 | 208 | |
38ff667b PZ |
209 | /* |
210 | * Control data for the mmap() data buffer. | |
211 | * | |
212 | * User-space reading this value should issue an rmb(), on SMP capable | |
213 | * platforms, after reading this value -- see perf_counter_wakeup(). | |
214 | */ | |
7b732a75 | 215 | __u32 data_head; /* head in the data section */ |
37d81828 PM |
216 | }; |
217 | ||
9d23a90a PM |
218 | #define PERF_EVENT_MISC_CPUMODE_MASK (3 << 0) |
219 | #define PERF_EVENT_MISC_CPUMODE_UNKNOWN (0 << 0) | |
6b6e5486 | 220 | #define PERF_EVENT_MISC_KERNEL (1 << 0) |
9d23a90a PM |
221 | #define PERF_EVENT_MISC_USER (2 << 0) |
222 | #define PERF_EVENT_MISC_HYPERVISOR (3 << 0) | |
6b6e5486 | 223 | #define PERF_EVENT_MISC_OVERFLOW (1 << 2) |
6fab0192 | 224 | |
5c148194 PZ |
225 | struct perf_event_header { |
226 | __u32 type; | |
6fab0192 PZ |
227 | __u16 misc; |
228 | __u16 size; | |
5c148194 PZ |
229 | }; |
230 | ||
231 | enum perf_event_type { | |
5ed00415 | 232 | |
0c593b34 PZ |
233 | /* |
234 | * The MMAP events record the PROT_EXEC mappings so that we can | |
235 | * correlate userspace IPs to code. They have the following structure: | |
236 | * | |
237 | * struct { | |
0127c3ea | 238 | * struct perf_event_header header; |
0c593b34 | 239 | * |
0127c3ea IM |
240 | * u32 pid, tid; |
241 | * u64 addr; | |
242 | * u64 len; | |
243 | * u64 pgoff; | |
244 | * char filename[]; | |
0c593b34 PZ |
245 | * }; |
246 | */ | |
8a057d84 PZ |
247 | PERF_EVENT_MMAP = 1, |
248 | PERF_EVENT_MUNMAP = 2, | |
0a4a9391 | 249 | |
8d1b2d93 PZ |
250 | /* |
251 | * struct { | |
0127c3ea | 252 | * struct perf_event_header header; |
8d1b2d93 | 253 | * |
0127c3ea IM |
254 | * u32 pid, tid; |
255 | * char comm[]; | |
8d1b2d93 PZ |
256 | * }; |
257 | */ | |
258 | PERF_EVENT_COMM = 3, | |
259 | ||
26b119bc PZ |
260 | /* |
261 | * struct { | |
0127c3ea IM |
262 | * struct perf_event_header header; |
263 | * u64 time; | |
b23f3325 | 264 | * u64 sample_period; |
26b119bc PZ |
265 | * }; |
266 | */ | |
267 | PERF_EVENT_PERIOD = 4, | |
268 | ||
a78ac325 PZ |
269 | /* |
270 | * struct { | |
0127c3ea IM |
271 | * struct perf_event_header header; |
272 | * u64 time; | |
a78ac325 PZ |
273 | * }; |
274 | */ | |
275 | PERF_EVENT_THROTTLE = 5, | |
276 | PERF_EVENT_UNTHROTTLE = 6, | |
277 | ||
8a057d84 | 278 | /* |
6b6e5486 PZ |
279 | * When header.misc & PERF_EVENT_MISC_OVERFLOW the event_type field |
280 | * will be PERF_RECORD_* | |
0c593b34 PZ |
281 | * |
282 | * struct { | |
0127c3ea | 283 | * struct perf_event_header header; |
0c593b34 | 284 | * |
0127c3ea IM |
285 | * { u64 ip; } && PERF_RECORD_IP |
286 | * { u32 pid, tid; } && PERF_RECORD_TID | |
287 | * { u64 time; } && PERF_RECORD_TIME | |
288 | * { u64 addr; } && PERF_RECORD_ADDR | |
289 | * { u64 config; } && PERF_RECORD_CONFIG | |
290 | * { u32 cpu, res; } && PERF_RECORD_CPU | |
0c593b34 | 291 | * |
0127c3ea | 292 | * { u64 nr; |
8e5799b1 | 293 | * { u64 id, val; } cnt[nr]; } && PERF_RECORD_GROUP |
0c593b34 | 294 | * |
0127c3ea IM |
295 | * { u16 nr, |
296 | * hv, | |
297 | * kernel, | |
298 | * user; | |
299 | * u64 ips[nr]; } && PERF_RECORD_CALLCHAIN | |
0c593b34 | 300 | * }; |
8a057d84 | 301 | */ |
5c148194 PZ |
302 | }; |
303 | ||
f3dfd265 | 304 | #ifdef __KERNEL__ |
9f66a381 | 305 | /* |
f3dfd265 | 306 | * Kernel-internal data types and definitions: |
9f66a381 IM |
307 | */ |
308 | ||
f3dfd265 PM |
309 | #ifdef CONFIG_PERF_COUNTERS |
310 | # include <asm/perf_counter.h> | |
311 | #endif | |
312 | ||
313 | #include <linux/list.h> | |
314 | #include <linux/mutex.h> | |
315 | #include <linux/rculist.h> | |
316 | #include <linux/rcupdate.h> | |
317 | #include <linux/spinlock.h> | |
d6d020e9 | 318 | #include <linux/hrtimer.h> |
3c446b3d | 319 | #include <linux/fs.h> |
709e50cf | 320 | #include <linux/pid_namespace.h> |
f3dfd265 PM |
321 | #include <asm/atomic.h> |
322 | ||
323 | struct task_struct; | |
324 | ||
f4a2deb4 PZ |
325 | static inline u64 perf_event_raw(struct perf_counter_hw_event *hw_event) |
326 | { | |
327 | return hw_event->config & PERF_COUNTER_RAW_MASK; | |
328 | } | |
329 | ||
330 | static inline u64 perf_event_config(struct perf_counter_hw_event *hw_event) | |
331 | { | |
332 | return hw_event->config & PERF_COUNTER_CONFIG_MASK; | |
333 | } | |
334 | ||
335 | static inline u64 perf_event_type(struct perf_counter_hw_event *hw_event) | |
336 | { | |
337 | return (hw_event->config & PERF_COUNTER_TYPE_MASK) >> | |
338 | PERF_COUNTER_TYPE_SHIFT; | |
339 | } | |
340 | ||
341 | static inline u64 perf_event_id(struct perf_counter_hw_event *hw_event) | |
342 | { | |
343 | return hw_event->config & PERF_COUNTER_EVENT_MASK; | |
344 | } | |
345 | ||
0793a61d | 346 | /** |
9f66a381 | 347 | * struct hw_perf_counter - performance counter hardware details: |
0793a61d TG |
348 | */ |
349 | struct hw_perf_counter { | |
ee06094f | 350 | #ifdef CONFIG_PERF_COUNTERS |
d6d020e9 PZ |
351 | union { |
352 | struct { /* hardware */ | |
353 | u64 config; | |
354 | unsigned long config_base; | |
355 | unsigned long counter_base; | |
6f00cada | 356 | int idx; |
d6d020e9 PZ |
357 | }; |
358 | union { /* software */ | |
359 | atomic64_t count; | |
360 | struct hrtimer hrtimer; | |
361 | }; | |
362 | }; | |
ee06094f | 363 | atomic64_t prev_count; |
b23f3325 | 364 | u64 sample_period; |
ee06094f | 365 | atomic64_t period_left; |
60db5e09 | 366 | u64 interrupts; |
ee06094f | 367 | #endif |
0793a61d TG |
368 | }; |
369 | ||
621a01ea IM |
370 | struct perf_counter; |
371 | ||
372 | /** | |
4aeb0b42 | 373 | * struct pmu - generic performance monitoring unit |
621a01ea | 374 | */ |
4aeb0b42 | 375 | struct pmu { |
95cdd2e7 | 376 | int (*enable) (struct perf_counter *counter); |
7671581f IM |
377 | void (*disable) (struct perf_counter *counter); |
378 | void (*read) (struct perf_counter *counter); | |
a78ac325 | 379 | void (*unthrottle) (struct perf_counter *counter); |
621a01ea IM |
380 | }; |
381 | ||
6a930700 IM |
382 | /** |
383 | * enum perf_counter_active_state - the states of a counter | |
384 | */ | |
385 | enum perf_counter_active_state { | |
3b6f9e5c | 386 | PERF_COUNTER_STATE_ERROR = -2, |
6a930700 IM |
387 | PERF_COUNTER_STATE_OFF = -1, |
388 | PERF_COUNTER_STATE_INACTIVE = 0, | |
389 | PERF_COUNTER_STATE_ACTIVE = 1, | |
390 | }; | |
391 | ||
9b51f66d IM |
392 | struct file; |
393 | ||
7b732a75 PZ |
394 | struct perf_mmap_data { |
395 | struct rcu_head rcu_head; | |
8740f941 | 396 | int nr_pages; /* nr of data pages */ |
c5078f78 | 397 | int nr_locked; /* nr pages mlocked */ |
8740f941 | 398 | |
c33a0bc4 | 399 | atomic_t poll; /* POLL_ for wakeups */ |
8740f941 PZ |
400 | atomic_t head; /* write position */ |
401 | atomic_t events; /* event limit */ | |
402 | ||
c66de4a5 | 403 | atomic_t done_head; /* completed head */ |
c33a0bc4 PZ |
404 | atomic_t lock; /* concurrent writes */ |
405 | ||
c66de4a5 PZ |
406 | atomic_t wakeup; /* needs a wakeup */ |
407 | ||
7b732a75 | 408 | struct perf_counter_mmap_page *user_page; |
0127c3ea | 409 | void *data_pages[0]; |
7b732a75 PZ |
410 | }; |
411 | ||
671dec5d PZ |
412 | struct perf_pending_entry { |
413 | struct perf_pending_entry *next; | |
414 | void (*func)(struct perf_pending_entry *); | |
925d519a PZ |
415 | }; |
416 | ||
0793a61d TG |
417 | /** |
418 | * struct perf_counter - performance counter kernel representation: | |
419 | */ | |
420 | struct perf_counter { | |
ee06094f | 421 | #ifdef CONFIG_PERF_COUNTERS |
04289bb9 | 422 | struct list_head list_entry; |
592903cd | 423 | struct list_head event_entry; |
04289bb9 | 424 | struct list_head sibling_list; |
0127c3ea | 425 | int nr_siblings; |
04289bb9 | 426 | struct perf_counter *group_leader; |
4aeb0b42 | 427 | const struct pmu *pmu; |
04289bb9 | 428 | |
6a930700 | 429 | enum perf_counter_active_state state; |
0793a61d | 430 | atomic64_t count; |
ee06094f | 431 | |
53cfbf59 PM |
432 | /* |
433 | * These are the total time in nanoseconds that the counter | |
434 | * has been enabled (i.e. eligible to run, and the task has | |
435 | * been scheduled in, if this is a per-task counter) | |
436 | * and running (scheduled onto the CPU), respectively. | |
437 | * | |
438 | * They are computed from tstamp_enabled, tstamp_running and | |
439 | * tstamp_stopped when the counter is in INACTIVE or ACTIVE state. | |
440 | */ | |
441 | u64 total_time_enabled; | |
442 | u64 total_time_running; | |
443 | ||
444 | /* | |
445 | * These are timestamps used for computing total_time_enabled | |
446 | * and total_time_running when the counter is in INACTIVE or | |
447 | * ACTIVE state, measured in nanoseconds from an arbitrary point | |
448 | * in time. | |
449 | * tstamp_enabled: the notional time when the counter was enabled | |
450 | * tstamp_running: the notional time when the counter was scheduled on | |
451 | * tstamp_stopped: in INACTIVE state, the notional time when the | |
452 | * counter was scheduled off. | |
453 | */ | |
454 | u64 tstamp_enabled; | |
455 | u64 tstamp_running; | |
456 | u64 tstamp_stopped; | |
457 | ||
9f66a381 | 458 | struct perf_counter_hw_event hw_event; |
0793a61d TG |
459 | struct hw_perf_counter hw; |
460 | ||
461 | struct perf_counter_context *ctx; | |
9b51f66d | 462 | struct file *filp; |
0793a61d | 463 | |
53cfbf59 PM |
464 | /* |
465 | * These accumulate total time (in nanoseconds) that children | |
466 | * counters have been enabled and running, respectively. | |
467 | */ | |
468 | atomic64_t child_total_time_enabled; | |
469 | atomic64_t child_total_time_running; | |
470 | ||
0793a61d | 471 | /* |
d859e29f | 472 | * Protect attach/detach and child_list: |
0793a61d | 473 | */ |
fccc714b PZ |
474 | struct mutex child_mutex; |
475 | struct list_head child_list; | |
476 | struct perf_counter *parent; | |
0793a61d TG |
477 | |
478 | int oncpu; | |
479 | int cpu; | |
480 | ||
082ff5a2 PZ |
481 | struct list_head owner_entry; |
482 | struct task_struct *owner; | |
483 | ||
7b732a75 PZ |
484 | /* mmap bits */ |
485 | struct mutex mmap_mutex; | |
486 | atomic_t mmap_count; | |
487 | struct perf_mmap_data *data; | |
37d81828 | 488 | |
7b732a75 | 489 | /* poll related */ |
0793a61d | 490 | wait_queue_head_t waitq; |
3c446b3d | 491 | struct fasync_struct *fasync; |
79f14641 PZ |
492 | |
493 | /* delayed work for NMIs and such */ | |
494 | int pending_wakeup; | |
4c9e2542 | 495 | int pending_kill; |
79f14641 | 496 | int pending_disable; |
671dec5d | 497 | struct perf_pending_entry pending; |
592903cd | 498 | |
79f14641 PZ |
499 | atomic_t event_limit; |
500 | ||
e077df4f | 501 | void (*destroy)(struct perf_counter *); |
592903cd | 502 | struct rcu_head rcu_head; |
709e50cf PZ |
503 | |
504 | struct pid_namespace *ns; | |
8e5799b1 | 505 | u64 id; |
ee06094f | 506 | #endif |
0793a61d TG |
507 | }; |
508 | ||
509 | /** | |
510 | * struct perf_counter_context - counter context structure | |
511 | * | |
512 | * Used as a container for task counters and CPU counters as well: | |
513 | */ | |
514 | struct perf_counter_context { | |
0793a61d | 515 | /* |
d859e29f PM |
516 | * Protect the states of the counters in the list, |
517 | * nr_active, and the list: | |
0793a61d TG |
518 | */ |
519 | spinlock_t lock; | |
d859e29f PM |
520 | /* |
521 | * Protect the list of counters. Locking either mutex or lock | |
522 | * is sufficient to ensure the list doesn't change; to change | |
523 | * the list you need to lock both the mutex and the spinlock. | |
524 | */ | |
525 | struct mutex mutex; | |
04289bb9 IM |
526 | |
527 | struct list_head counter_list; | |
592903cd | 528 | struct list_head event_list; |
0793a61d TG |
529 | int nr_counters; |
530 | int nr_active; | |
d859e29f | 531 | int is_active; |
a63eaf34 | 532 | atomic_t refcount; |
0793a61d | 533 | struct task_struct *task; |
53cfbf59 PM |
534 | |
535 | /* | |
4af4998b | 536 | * Context clock, runs when context enabled. |
53cfbf59 | 537 | */ |
4af4998b PZ |
538 | u64 time; |
539 | u64 timestamp; | |
564c2b21 PM |
540 | |
541 | /* | |
542 | * These fields let us detect when two contexts have both | |
543 | * been cloned (inherited) from a common ancestor. | |
544 | */ | |
545 | struct perf_counter_context *parent_ctx; | |
c93f7669 PM |
546 | u64 parent_gen; |
547 | u64 generation; | |
25346b93 | 548 | int pin_count; |
c93f7669 | 549 | struct rcu_head rcu_head; |
0793a61d TG |
550 | }; |
551 | ||
552 | /** | |
553 | * struct perf_counter_cpu_context - per cpu counter context structure | |
554 | */ | |
555 | struct perf_cpu_context { | |
556 | struct perf_counter_context ctx; | |
557 | struct perf_counter_context *task_ctx; | |
558 | int active_oncpu; | |
559 | int max_pertask; | |
3b6f9e5c | 560 | int exclusive; |
96f6d444 PZ |
561 | |
562 | /* | |
563 | * Recursion avoidance: | |
564 | * | |
565 | * task, softirq, irq, nmi context | |
566 | */ | |
22a4f650 | 567 | int recursion[4]; |
0793a61d TG |
568 | }; |
569 | ||
829b42dd RR |
570 | #ifdef CONFIG_PERF_COUNTERS |
571 | ||
0793a61d TG |
572 | /* |
573 | * Set by architecture code: | |
574 | */ | |
575 | extern int perf_max_counters; | |
576 | ||
4aeb0b42 | 577 | extern const struct pmu *hw_perf_counter_init(struct perf_counter *counter); |
621a01ea | 578 | |
0793a61d | 579 | extern void perf_counter_task_sched_in(struct task_struct *task, int cpu); |
564c2b21 PM |
580 | extern void perf_counter_task_sched_out(struct task_struct *task, |
581 | struct task_struct *next, int cpu); | |
0793a61d | 582 | extern void perf_counter_task_tick(struct task_struct *task, int cpu); |
6ab423e0 | 583 | extern int perf_counter_init_task(struct task_struct *child); |
9b51f66d | 584 | extern void perf_counter_exit_task(struct task_struct *child); |
bbbee908 | 585 | extern void perf_counter_free_task(struct task_struct *task); |
925d519a | 586 | extern void perf_counter_do_pending(void); |
0793a61d | 587 | extern void perf_counter_print_debug(void); |
9e35ad38 PZ |
588 | extern void __perf_disable(void); |
589 | extern bool __perf_enable(void); | |
590 | extern void perf_disable(void); | |
591 | extern void perf_enable(void); | |
1d1c7ddb IM |
592 | extern int perf_counter_task_disable(void); |
593 | extern int perf_counter_task_enable(void); | |
3cbed429 PM |
594 | extern int hw_perf_group_sched_in(struct perf_counter *group_leader, |
595 | struct perf_cpu_context *cpuctx, | |
596 | struct perf_counter_context *ctx, int cpu); | |
37d81828 | 597 | extern void perf_counter_update_userpage(struct perf_counter *counter); |
5c92d124 | 598 | |
f6c7d5fe | 599 | extern int perf_counter_overflow(struct perf_counter *counter, |
78f13e95 | 600 | int nmi, struct pt_regs *regs, u64 addr); |
3b6f9e5c PM |
601 | /* |
602 | * Return 1 for a software counter, 0 for a hardware counter | |
603 | */ | |
604 | static inline int is_software_counter(struct perf_counter *counter) | |
605 | { | |
f4a2deb4 PZ |
606 | return !perf_event_raw(&counter->hw_event) && |
607 | perf_event_type(&counter->hw_event) != PERF_TYPE_HARDWARE; | |
3b6f9e5c PM |
608 | } |
609 | ||
78f13e95 | 610 | extern void perf_swcounter_event(u32, u64, int, struct pt_regs *, u64); |
15dbf27c | 611 | |
0a4a9391 PZ |
612 | extern void perf_counter_mmap(unsigned long addr, unsigned long len, |
613 | unsigned long pgoff, struct file *file); | |
614 | ||
615 | extern void perf_counter_munmap(unsigned long addr, unsigned long len, | |
616 | unsigned long pgoff, struct file *file); | |
617 | ||
8d1b2d93 PZ |
618 | extern void perf_counter_comm(struct task_struct *tsk); |
619 | ||
3f731ca6 PM |
620 | extern void perf_counter_task_migration(struct task_struct *task, int cpu); |
621 | ||
9c03d88e | 622 | #define MAX_STACK_DEPTH 255 |
394ee076 PZ |
623 | |
624 | struct perf_callchain_entry { | |
9c03d88e | 625 | u16 nr, hv, kernel, user; |
394ee076 PZ |
626 | u64 ip[MAX_STACK_DEPTH]; |
627 | }; | |
628 | ||
629 | extern struct perf_callchain_entry *perf_callchain(struct pt_regs *regs); | |
630 | ||
1ccd1549 | 631 | extern int sysctl_perf_counter_priv; |
c5078f78 | 632 | extern int sysctl_perf_counter_mlock; |
a78ac325 | 633 | extern int sysctl_perf_counter_limit; |
1ccd1549 | 634 | |
0d905bca IM |
635 | extern void perf_counter_init(void); |
636 | ||
9d23a90a PM |
637 | #ifndef perf_misc_flags |
638 | #define perf_misc_flags(regs) (user_mode(regs) ? PERF_EVENT_MISC_USER : \ | |
639 | PERF_EVENT_MISC_KERNEL) | |
640 | #define perf_instruction_pointer(regs) instruction_pointer(regs) | |
641 | #endif | |
642 | ||
0793a61d TG |
643 | #else |
644 | static inline void | |
645 | perf_counter_task_sched_in(struct task_struct *task, int cpu) { } | |
646 | static inline void | |
910431c7 IM |
647 | perf_counter_task_sched_out(struct task_struct *task, |
648 | struct task_struct *next, int cpu) { } | |
0793a61d TG |
649 | static inline void |
650 | perf_counter_task_tick(struct task_struct *task, int cpu) { } | |
d3e78ee3 | 651 | static inline int perf_counter_init_task(struct task_struct *child) { return 0; } |
9b51f66d | 652 | static inline void perf_counter_exit_task(struct task_struct *child) { } |
bbbee908 | 653 | static inline void perf_counter_free_task(struct task_struct *task) { } |
925d519a | 654 | static inline void perf_counter_do_pending(void) { } |
0793a61d | 655 | static inline void perf_counter_print_debug(void) { } |
9e35ad38 PZ |
656 | static inline void perf_disable(void) { } |
657 | static inline void perf_enable(void) { } | |
1d1c7ddb IM |
658 | static inline int perf_counter_task_disable(void) { return -EINVAL; } |
659 | static inline int perf_counter_task_enable(void) { return -EINVAL; } | |
15dbf27c | 660 | |
925d519a | 661 | static inline void |
78f13e95 PZ |
662 | perf_swcounter_event(u32 event, u64 nr, int nmi, |
663 | struct pt_regs *regs, u64 addr) { } | |
0a4a9391 PZ |
664 | |
665 | static inline void | |
666 | perf_counter_mmap(unsigned long addr, unsigned long len, | |
667 | unsigned long pgoff, struct file *file) { } | |
668 | ||
669 | static inline void | |
670 | perf_counter_munmap(unsigned long addr, unsigned long len, | |
0d905bca | 671 | unsigned long pgoff, struct file *file) { } |
0a4a9391 | 672 | |
8d1b2d93 | 673 | static inline void perf_counter_comm(struct task_struct *tsk) { } |
0d905bca | 674 | static inline void perf_counter_init(void) { } |
3f731ca6 PM |
675 | static inline void perf_counter_task_migration(struct task_struct *task, |
676 | int cpu) { } | |
0793a61d TG |
677 | #endif |
678 | ||
f3dfd265 | 679 | #endif /* __KERNEL__ */ |
0793a61d | 680 | #endif /* _LINUX_PERF_COUNTER_H */ |