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Commit | Line | Data |
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0793a61d | 1 | /* |
57c0c15b | 2 | * Performance events: |
0793a61d | 3 | * |
a308444c IM |
4 | * Copyright (C) 2008-2009, Thomas Gleixner <tglx@linutronix.de> |
5 | * Copyright (C) 2008-2009, Red Hat, Inc., Ingo Molnar | |
6 | * Copyright (C) 2008-2009, Red Hat, Inc., Peter Zijlstra | |
0793a61d | 7 | * |
57c0c15b | 8 | * Data type definitions, declarations, prototypes. |
0793a61d | 9 | * |
a308444c | 10 | * Started by: Thomas Gleixner and Ingo Molnar |
0793a61d | 11 | * |
57c0c15b | 12 | * For licencing details see kernel-base/COPYING |
0793a61d | 13 | */ |
cdd6c482 IM |
14 | #ifndef _LINUX_PERF_EVENT_H |
15 | #define _LINUX_PERF_EVENT_H | |
0793a61d | 16 | |
f3dfd265 PM |
17 | #include <linux/types.h> |
18 | #include <linux/ioctl.h> | |
9aaa131a | 19 | #include <asm/byteorder.h> |
0793a61d TG |
20 | |
21 | /* | |
9f66a381 IM |
22 | * User-space ABI bits: |
23 | */ | |
24 | ||
25 | /* | |
0d48696f | 26 | * attr.type |
0793a61d | 27 | */ |
1c432d89 | 28 | enum perf_type_id { |
a308444c IM |
29 | PERF_TYPE_HARDWARE = 0, |
30 | PERF_TYPE_SOFTWARE = 1, | |
31 | PERF_TYPE_TRACEPOINT = 2, | |
32 | PERF_TYPE_HW_CACHE = 3, | |
33 | PERF_TYPE_RAW = 4, | |
24f1e32c | 34 | PERF_TYPE_BREAKPOINT = 5, |
b8e83514 | 35 | |
a308444c | 36 | PERF_TYPE_MAX, /* non-ABI */ |
b8e83514 | 37 | }; |
6c594c21 | 38 | |
b8e83514 | 39 | /* |
cdd6c482 IM |
40 | * Generalized performance event event_id types, used by the |
41 | * attr.event_id parameter of the sys_perf_event_open() | |
a308444c | 42 | * syscall: |
b8e83514 | 43 | */ |
1c432d89 | 44 | enum perf_hw_id { |
9f66a381 | 45 | /* |
b8e83514 | 46 | * Common hardware events, generalized by the kernel: |
9f66a381 | 47 | */ |
f4dbfa8f PZ |
48 | PERF_COUNT_HW_CPU_CYCLES = 0, |
49 | PERF_COUNT_HW_INSTRUCTIONS = 1, | |
50 | PERF_COUNT_HW_CACHE_REFERENCES = 2, | |
51 | PERF_COUNT_HW_CACHE_MISSES = 3, | |
52 | PERF_COUNT_HW_BRANCH_INSTRUCTIONS = 4, | |
53 | PERF_COUNT_HW_BRANCH_MISSES = 5, | |
54 | PERF_COUNT_HW_BUS_CYCLES = 6, | |
55 | ||
a308444c | 56 | PERF_COUNT_HW_MAX, /* non-ABI */ |
b8e83514 | 57 | }; |
e077df4f | 58 | |
8326f44d | 59 | /* |
cdd6c482 | 60 | * Generalized hardware cache events: |
8326f44d | 61 | * |
8be6e8f3 | 62 | * { L1-D, L1-I, LLC, ITLB, DTLB, BPU } x |
8326f44d IM |
63 | * { read, write, prefetch } x |
64 | * { accesses, misses } | |
65 | */ | |
1c432d89 | 66 | enum perf_hw_cache_id { |
a308444c IM |
67 | PERF_COUNT_HW_CACHE_L1D = 0, |
68 | PERF_COUNT_HW_CACHE_L1I = 1, | |
69 | PERF_COUNT_HW_CACHE_LL = 2, | |
70 | PERF_COUNT_HW_CACHE_DTLB = 3, | |
71 | PERF_COUNT_HW_CACHE_ITLB = 4, | |
72 | PERF_COUNT_HW_CACHE_BPU = 5, | |
73 | ||
74 | PERF_COUNT_HW_CACHE_MAX, /* non-ABI */ | |
8326f44d IM |
75 | }; |
76 | ||
1c432d89 | 77 | enum perf_hw_cache_op_id { |
a308444c IM |
78 | PERF_COUNT_HW_CACHE_OP_READ = 0, |
79 | PERF_COUNT_HW_CACHE_OP_WRITE = 1, | |
80 | PERF_COUNT_HW_CACHE_OP_PREFETCH = 2, | |
8326f44d | 81 | |
a308444c | 82 | PERF_COUNT_HW_CACHE_OP_MAX, /* non-ABI */ |
8326f44d IM |
83 | }; |
84 | ||
1c432d89 PZ |
85 | enum perf_hw_cache_op_result_id { |
86 | PERF_COUNT_HW_CACHE_RESULT_ACCESS = 0, | |
87 | PERF_COUNT_HW_CACHE_RESULT_MISS = 1, | |
8326f44d | 88 | |
a308444c | 89 | PERF_COUNT_HW_CACHE_RESULT_MAX, /* non-ABI */ |
8326f44d IM |
90 | }; |
91 | ||
b8e83514 | 92 | /* |
cdd6c482 IM |
93 | * Special "software" events provided by the kernel, even if the hardware |
94 | * does not support performance events. These events measure various | |
b8e83514 PZ |
95 | * physical and sw events of the kernel (and allow the profiling of them as |
96 | * well): | |
97 | */ | |
1c432d89 | 98 | enum perf_sw_ids { |
a308444c IM |
99 | PERF_COUNT_SW_CPU_CLOCK = 0, |
100 | PERF_COUNT_SW_TASK_CLOCK = 1, | |
101 | PERF_COUNT_SW_PAGE_FAULTS = 2, | |
102 | PERF_COUNT_SW_CONTEXT_SWITCHES = 3, | |
103 | PERF_COUNT_SW_CPU_MIGRATIONS = 4, | |
104 | PERF_COUNT_SW_PAGE_FAULTS_MIN = 5, | |
105 | PERF_COUNT_SW_PAGE_FAULTS_MAJ = 6, | |
f7d79860 AB |
106 | PERF_COUNT_SW_ALIGNMENT_FAULTS = 7, |
107 | PERF_COUNT_SW_EMULATION_FAULTS = 8, | |
a308444c IM |
108 | |
109 | PERF_COUNT_SW_MAX, /* non-ABI */ | |
0793a61d TG |
110 | }; |
111 | ||
8a057d84 | 112 | /* |
0d48696f | 113 | * Bits that can be set in attr.sample_type to request information |
8a057d84 PZ |
114 | * in the overflow packets. |
115 | */ | |
cdd6c482 | 116 | enum perf_event_sample_format { |
a308444c IM |
117 | PERF_SAMPLE_IP = 1U << 0, |
118 | PERF_SAMPLE_TID = 1U << 1, | |
119 | PERF_SAMPLE_TIME = 1U << 2, | |
120 | PERF_SAMPLE_ADDR = 1U << 3, | |
3dab77fb | 121 | PERF_SAMPLE_READ = 1U << 4, |
a308444c IM |
122 | PERF_SAMPLE_CALLCHAIN = 1U << 5, |
123 | PERF_SAMPLE_ID = 1U << 6, | |
124 | PERF_SAMPLE_CPU = 1U << 7, | |
125 | PERF_SAMPLE_PERIOD = 1U << 8, | |
7f453c24 | 126 | PERF_SAMPLE_STREAM_ID = 1U << 9, |
3a43ce68 | 127 | PERF_SAMPLE_RAW = 1U << 10, |
974802ea | 128 | |
f413cdb8 | 129 | PERF_SAMPLE_MAX = 1U << 11, /* non-ABI */ |
8a057d84 PZ |
130 | }; |
131 | ||
53cfbf59 | 132 | /* |
cdd6c482 | 133 | * The format of the data returned by read() on a perf event fd, |
3dab77fb PZ |
134 | * as specified by attr.read_format: |
135 | * | |
136 | * struct read_format { | |
57c0c15b IM |
137 | * { u64 value; |
138 | * { u64 time_enabled; } && PERF_FORMAT_ENABLED | |
139 | * { u64 time_running; } && PERF_FORMAT_RUNNING | |
140 | * { u64 id; } && PERF_FORMAT_ID | |
141 | * } && !PERF_FORMAT_GROUP | |
3dab77fb | 142 | * |
57c0c15b IM |
143 | * { u64 nr; |
144 | * { u64 time_enabled; } && PERF_FORMAT_ENABLED | |
145 | * { u64 time_running; } && PERF_FORMAT_RUNNING | |
146 | * { u64 value; | |
147 | * { u64 id; } && PERF_FORMAT_ID | |
148 | * } cntr[nr]; | |
149 | * } && PERF_FORMAT_GROUP | |
3dab77fb | 150 | * }; |
53cfbf59 | 151 | */ |
cdd6c482 | 152 | enum perf_event_read_format { |
a308444c IM |
153 | PERF_FORMAT_TOTAL_TIME_ENABLED = 1U << 0, |
154 | PERF_FORMAT_TOTAL_TIME_RUNNING = 1U << 1, | |
155 | PERF_FORMAT_ID = 1U << 2, | |
3dab77fb | 156 | PERF_FORMAT_GROUP = 1U << 3, |
974802ea | 157 | |
57c0c15b | 158 | PERF_FORMAT_MAX = 1U << 4, /* non-ABI */ |
53cfbf59 PM |
159 | }; |
160 | ||
974802ea PZ |
161 | #define PERF_ATTR_SIZE_VER0 64 /* sizeof first published struct */ |
162 | ||
9f66a381 | 163 | /* |
cdd6c482 | 164 | * Hardware event_id to monitor via a performance monitoring event: |
9f66a381 | 165 | */ |
cdd6c482 | 166 | struct perf_event_attr { |
974802ea | 167 | |
f4a2deb4 | 168 | /* |
a21ca2ca IM |
169 | * Major type: hardware/software/tracepoint/etc. |
170 | */ | |
171 | __u32 type; | |
974802ea PZ |
172 | |
173 | /* | |
174 | * Size of the attr structure, for fwd/bwd compat. | |
175 | */ | |
176 | __u32 size; | |
a21ca2ca IM |
177 | |
178 | /* | |
179 | * Type specific configuration information. | |
f4a2deb4 PZ |
180 | */ |
181 | __u64 config; | |
9f66a381 | 182 | |
60db5e09 | 183 | union { |
b23f3325 PZ |
184 | __u64 sample_period; |
185 | __u64 sample_freq; | |
60db5e09 PZ |
186 | }; |
187 | ||
b23f3325 PZ |
188 | __u64 sample_type; |
189 | __u64 read_format; | |
9f66a381 | 190 | |
2743a5b0 | 191 | __u64 disabled : 1, /* off by default */ |
0475f9ea PM |
192 | inherit : 1, /* children inherit it */ |
193 | pinned : 1, /* must always be on PMU */ | |
194 | exclusive : 1, /* only group on PMU */ | |
195 | exclude_user : 1, /* don't count user */ | |
196 | exclude_kernel : 1, /* ditto kernel */ | |
197 | exclude_hv : 1, /* ditto hypervisor */ | |
2743a5b0 | 198 | exclude_idle : 1, /* don't count when idle */ |
0a4a9391 | 199 | mmap : 1, /* include mmap data */ |
8d1b2d93 | 200 | comm : 1, /* include comm data */ |
60db5e09 | 201 | freq : 1, /* use freq, not period */ |
bfbd3381 | 202 | inherit_stat : 1, /* per task counts */ |
57e7986e | 203 | enable_on_exec : 1, /* next exec enables */ |
9f498cc5 | 204 | task : 1, /* trace fork/exit */ |
2667de81 | 205 | watermark : 1, /* wakeup_watermark */ |
ab608344 PZ |
206 | /* |
207 | * precise_ip: | |
208 | * | |
209 | * 0 - SAMPLE_IP can have arbitrary skid | |
210 | * 1 - SAMPLE_IP must have constant skid | |
211 | * 2 - SAMPLE_IP requested to have 0 skid | |
212 | * 3 - SAMPLE_IP must have 0 skid | |
213 | * | |
214 | * See also PERF_RECORD_MISC_EXACT_IP | |
215 | */ | |
216 | precise_ip : 2, /* skid constraint */ | |
3af9e859 | 217 | mmap_data : 1, /* non-exec mmap data */ |
ab608344 | 218 | |
3af9e859 | 219 | __reserved_1 : 46; |
2743a5b0 | 220 | |
2667de81 PZ |
221 | union { |
222 | __u32 wakeup_events; /* wakeup every n events */ | |
223 | __u32 wakeup_watermark; /* bytes before wakeup */ | |
224 | }; | |
24f1e32c | 225 | |
f13c12c6 | 226 | __u32 bp_type; |
cd757645 MS |
227 | __u64 bp_addr; |
228 | __u64 bp_len; | |
eab656ae TG |
229 | }; |
230 | ||
d859e29f | 231 | /* |
cdd6c482 | 232 | * Ioctls that can be done on a perf event fd: |
d859e29f | 233 | */ |
cdd6c482 | 234 | #define PERF_EVENT_IOC_ENABLE _IO ('$', 0) |
57c0c15b IM |
235 | #define PERF_EVENT_IOC_DISABLE _IO ('$', 1) |
236 | #define PERF_EVENT_IOC_REFRESH _IO ('$', 2) | |
cdd6c482 | 237 | #define PERF_EVENT_IOC_RESET _IO ('$', 3) |
4c49b128 | 238 | #define PERF_EVENT_IOC_PERIOD _IOW('$', 4, __u64) |
cdd6c482 | 239 | #define PERF_EVENT_IOC_SET_OUTPUT _IO ('$', 5) |
6fb2915d | 240 | #define PERF_EVENT_IOC_SET_FILTER _IOW('$', 6, char *) |
cdd6c482 IM |
241 | |
242 | enum perf_event_ioc_flags { | |
3df5edad PZ |
243 | PERF_IOC_FLAG_GROUP = 1U << 0, |
244 | }; | |
d859e29f | 245 | |
37d81828 PM |
246 | /* |
247 | * Structure of the page that can be mapped via mmap | |
248 | */ | |
cdd6c482 | 249 | struct perf_event_mmap_page { |
37d81828 PM |
250 | __u32 version; /* version number of this structure */ |
251 | __u32 compat_version; /* lowest version this is compat with */ | |
38ff667b PZ |
252 | |
253 | /* | |
cdd6c482 | 254 | * Bits needed to read the hw events in user-space. |
38ff667b | 255 | * |
92f22a38 PZ |
256 | * u32 seq; |
257 | * s64 count; | |
38ff667b | 258 | * |
a2e87d06 PZ |
259 | * do { |
260 | * seq = pc->lock; | |
38ff667b | 261 | * |
a2e87d06 PZ |
262 | * barrier() |
263 | * if (pc->index) { | |
264 | * count = pmc_read(pc->index - 1); | |
265 | * count += pc->offset; | |
266 | * } else | |
267 | * goto regular_read; | |
38ff667b | 268 | * |
a2e87d06 PZ |
269 | * barrier(); |
270 | * } while (pc->lock != seq); | |
38ff667b | 271 | * |
92f22a38 PZ |
272 | * NOTE: for obvious reason this only works on self-monitoring |
273 | * processes. | |
38ff667b | 274 | */ |
37d81828 | 275 | __u32 lock; /* seqlock for synchronization */ |
cdd6c482 IM |
276 | __u32 index; /* hardware event identifier */ |
277 | __s64 offset; /* add to hardware event value */ | |
278 | __u64 time_enabled; /* time event active */ | |
279 | __u64 time_running; /* time event on cpu */ | |
7b732a75 | 280 | |
41f95331 PZ |
281 | /* |
282 | * Hole for extension of the self monitor capabilities | |
283 | */ | |
284 | ||
7f8b4e4e | 285 | __u64 __reserved[123]; /* align to 1k */ |
41f95331 | 286 | |
38ff667b PZ |
287 | /* |
288 | * Control data for the mmap() data buffer. | |
289 | * | |
43a21ea8 PZ |
290 | * User-space reading the @data_head value should issue an rmb(), on |
291 | * SMP capable platforms, after reading this value -- see | |
cdd6c482 | 292 | * perf_event_wakeup(). |
43a21ea8 PZ |
293 | * |
294 | * When the mapping is PROT_WRITE the @data_tail value should be | |
295 | * written by userspace to reflect the last read data. In this case | |
296 | * the kernel will not over-write unread data. | |
38ff667b | 297 | */ |
8e3747c1 | 298 | __u64 data_head; /* head in the data section */ |
43a21ea8 | 299 | __u64 data_tail; /* user-space written tail */ |
37d81828 PM |
300 | }; |
301 | ||
39447b38 | 302 | #define PERF_RECORD_MISC_CPUMODE_MASK (7 << 0) |
184f412c | 303 | #define PERF_RECORD_MISC_CPUMODE_UNKNOWN (0 << 0) |
cdd6c482 IM |
304 | #define PERF_RECORD_MISC_KERNEL (1 << 0) |
305 | #define PERF_RECORD_MISC_USER (2 << 0) | |
306 | #define PERF_RECORD_MISC_HYPERVISOR (3 << 0) | |
39447b38 ZY |
307 | #define PERF_RECORD_MISC_GUEST_KERNEL (4 << 0) |
308 | #define PERF_RECORD_MISC_GUEST_USER (5 << 0) | |
6fab0192 | 309 | |
ab608344 PZ |
310 | /* |
311 | * Indicates that the content of PERF_SAMPLE_IP points to | |
312 | * the actual instruction that triggered the event. See also | |
313 | * perf_event_attr::precise_ip. | |
314 | */ | |
315 | #define PERF_RECORD_MISC_EXACT_IP (1 << 14) | |
ef21f683 PZ |
316 | /* |
317 | * Reserve the last bit to indicate some extended misc field | |
318 | */ | |
319 | #define PERF_RECORD_MISC_EXT_RESERVED (1 << 15) | |
320 | ||
5c148194 PZ |
321 | struct perf_event_header { |
322 | __u32 type; | |
6fab0192 PZ |
323 | __u16 misc; |
324 | __u16 size; | |
5c148194 PZ |
325 | }; |
326 | ||
327 | enum perf_event_type { | |
5ed00415 | 328 | |
0c593b34 PZ |
329 | /* |
330 | * The MMAP events record the PROT_EXEC mappings so that we can | |
331 | * correlate userspace IPs to code. They have the following structure: | |
332 | * | |
333 | * struct { | |
0127c3ea | 334 | * struct perf_event_header header; |
0c593b34 | 335 | * |
0127c3ea IM |
336 | * u32 pid, tid; |
337 | * u64 addr; | |
338 | * u64 len; | |
339 | * u64 pgoff; | |
340 | * char filename[]; | |
0c593b34 PZ |
341 | * }; |
342 | */ | |
cdd6c482 | 343 | PERF_RECORD_MMAP = 1, |
0a4a9391 | 344 | |
43a21ea8 PZ |
345 | /* |
346 | * struct { | |
57c0c15b IM |
347 | * struct perf_event_header header; |
348 | * u64 id; | |
349 | * u64 lost; | |
43a21ea8 PZ |
350 | * }; |
351 | */ | |
cdd6c482 | 352 | PERF_RECORD_LOST = 2, |
43a21ea8 | 353 | |
8d1b2d93 PZ |
354 | /* |
355 | * struct { | |
0127c3ea | 356 | * struct perf_event_header header; |
8d1b2d93 | 357 | * |
0127c3ea IM |
358 | * u32 pid, tid; |
359 | * char comm[]; | |
8d1b2d93 PZ |
360 | * }; |
361 | */ | |
cdd6c482 | 362 | PERF_RECORD_COMM = 3, |
8d1b2d93 | 363 | |
9f498cc5 PZ |
364 | /* |
365 | * struct { | |
366 | * struct perf_event_header header; | |
367 | * u32 pid, ppid; | |
368 | * u32 tid, ptid; | |
393b2ad8 | 369 | * u64 time; |
9f498cc5 PZ |
370 | * }; |
371 | */ | |
cdd6c482 | 372 | PERF_RECORD_EXIT = 4, |
9f498cc5 | 373 | |
26b119bc PZ |
374 | /* |
375 | * struct { | |
0127c3ea IM |
376 | * struct perf_event_header header; |
377 | * u64 time; | |
689802b2 | 378 | * u64 id; |
7f453c24 | 379 | * u64 stream_id; |
a78ac325 PZ |
380 | * }; |
381 | */ | |
184f412c IM |
382 | PERF_RECORD_THROTTLE = 5, |
383 | PERF_RECORD_UNTHROTTLE = 6, | |
a78ac325 | 384 | |
60313ebe PZ |
385 | /* |
386 | * struct { | |
a21ca2ca IM |
387 | * struct perf_event_header header; |
388 | * u32 pid, ppid; | |
9f498cc5 | 389 | * u32 tid, ptid; |
a6f10a2f | 390 | * u64 time; |
60313ebe PZ |
391 | * }; |
392 | */ | |
cdd6c482 | 393 | PERF_RECORD_FORK = 7, |
60313ebe | 394 | |
38b200d6 PZ |
395 | /* |
396 | * struct { | |
184f412c IM |
397 | * struct perf_event_header header; |
398 | * u32 pid, tid; | |
3dab77fb | 399 | * |
184f412c | 400 | * struct read_format values; |
38b200d6 PZ |
401 | * }; |
402 | */ | |
cdd6c482 | 403 | PERF_RECORD_READ = 8, |
38b200d6 | 404 | |
8a057d84 | 405 | /* |
0c593b34 | 406 | * struct { |
0127c3ea | 407 | * struct perf_event_header header; |
0c593b34 | 408 | * |
43a21ea8 PZ |
409 | * { u64 ip; } && PERF_SAMPLE_IP |
410 | * { u32 pid, tid; } && PERF_SAMPLE_TID | |
411 | * { u64 time; } && PERF_SAMPLE_TIME | |
412 | * { u64 addr; } && PERF_SAMPLE_ADDR | |
e6e18ec7 | 413 | * { u64 id; } && PERF_SAMPLE_ID |
7f453c24 | 414 | * { u64 stream_id;} && PERF_SAMPLE_STREAM_ID |
43a21ea8 | 415 | * { u32 cpu, res; } && PERF_SAMPLE_CPU |
57c0c15b | 416 | * { u64 period; } && PERF_SAMPLE_PERIOD |
0c593b34 | 417 | * |
3dab77fb | 418 | * { struct read_format values; } && PERF_SAMPLE_READ |
0c593b34 | 419 | * |
f9188e02 | 420 | * { u64 nr, |
43a21ea8 | 421 | * u64 ips[nr]; } && PERF_SAMPLE_CALLCHAIN |
3dab77fb | 422 | * |
57c0c15b IM |
423 | * # |
424 | * # The RAW record below is opaque data wrt the ABI | |
425 | * # | |
426 | * # That is, the ABI doesn't make any promises wrt to | |
427 | * # the stability of its content, it may vary depending | |
428 | * # on event, hardware, kernel version and phase of | |
429 | * # the moon. | |
430 | * # | |
431 | * # In other words, PERF_SAMPLE_RAW contents are not an ABI. | |
432 | * # | |
3dab77fb | 433 | * |
a044560c PZ |
434 | * { u32 size; |
435 | * char data[size];}&& PERF_SAMPLE_RAW | |
0c593b34 | 436 | * }; |
8a057d84 | 437 | */ |
184f412c | 438 | PERF_RECORD_SAMPLE = 9, |
e6e18ec7 | 439 | |
cdd6c482 | 440 | PERF_RECORD_MAX, /* non-ABI */ |
5c148194 PZ |
441 | }; |
442 | ||
f9188e02 PZ |
443 | enum perf_callchain_context { |
444 | PERF_CONTEXT_HV = (__u64)-32, | |
445 | PERF_CONTEXT_KERNEL = (__u64)-128, | |
446 | PERF_CONTEXT_USER = (__u64)-512, | |
7522060c | 447 | |
f9188e02 PZ |
448 | PERF_CONTEXT_GUEST = (__u64)-2048, |
449 | PERF_CONTEXT_GUEST_KERNEL = (__u64)-2176, | |
450 | PERF_CONTEXT_GUEST_USER = (__u64)-2560, | |
451 | ||
452 | PERF_CONTEXT_MAX = (__u64)-4095, | |
7522060c IM |
453 | }; |
454 | ||
a4be7c27 PZ |
455 | #define PERF_FLAG_FD_NO_GROUP (1U << 0) |
456 | #define PERF_FLAG_FD_OUTPUT (1U << 1) | |
457 | ||
f3dfd265 | 458 | #ifdef __KERNEL__ |
9f66a381 | 459 | /* |
f3dfd265 | 460 | * Kernel-internal data types and definitions: |
9f66a381 IM |
461 | */ |
462 | ||
cdd6c482 IM |
463 | #ifdef CONFIG_PERF_EVENTS |
464 | # include <asm/perf_event.h> | |
7be79236 | 465 | # include <asm/local64.h> |
f3dfd265 PM |
466 | #endif |
467 | ||
39447b38 ZY |
468 | struct perf_guest_info_callbacks { |
469 | int (*is_in_guest) (void); | |
470 | int (*is_user_mode) (void); | |
471 | unsigned long (*get_guest_ip) (void); | |
472 | }; | |
473 | ||
2ff6cfd7 AB |
474 | #ifdef CONFIG_HAVE_HW_BREAKPOINT |
475 | #include <asm/hw_breakpoint.h> | |
476 | #endif | |
477 | ||
f3dfd265 PM |
478 | #include <linux/list.h> |
479 | #include <linux/mutex.h> | |
480 | #include <linux/rculist.h> | |
481 | #include <linux/rcupdate.h> | |
482 | #include <linux/spinlock.h> | |
d6d020e9 | 483 | #include <linux/hrtimer.h> |
3c446b3d | 484 | #include <linux/fs.h> |
709e50cf | 485 | #include <linux/pid_namespace.h> |
906010b2 | 486 | #include <linux/workqueue.h> |
5331d7b8 | 487 | #include <linux/ftrace.h> |
85cfabbc | 488 | #include <linux/cpu.h> |
f3dfd265 | 489 | #include <asm/atomic.h> |
fa588151 | 490 | #include <asm/local.h> |
f3dfd265 | 491 | |
f9188e02 PZ |
492 | #define PERF_MAX_STACK_DEPTH 255 |
493 | ||
494 | struct perf_callchain_entry { | |
495 | __u64 nr; | |
496 | __u64 ip[PERF_MAX_STACK_DEPTH]; | |
497 | }; | |
498 | ||
3a43ce68 FW |
499 | struct perf_raw_record { |
500 | u32 size; | |
501 | void *data; | |
f413cdb8 FW |
502 | }; |
503 | ||
caff2bef PZ |
504 | struct perf_branch_entry { |
505 | __u64 from; | |
506 | __u64 to; | |
507 | __u64 flags; | |
508 | }; | |
509 | ||
510 | struct perf_branch_stack { | |
511 | __u64 nr; | |
512 | struct perf_branch_entry entries[0]; | |
513 | }; | |
514 | ||
f3dfd265 PM |
515 | struct task_struct; |
516 | ||
0793a61d | 517 | /** |
cdd6c482 | 518 | * struct hw_perf_event - performance event hardware details: |
0793a61d | 519 | */ |
cdd6c482 IM |
520 | struct hw_perf_event { |
521 | #ifdef CONFIG_PERF_EVENTS | |
d6d020e9 PZ |
522 | union { |
523 | struct { /* hardware */ | |
a308444c | 524 | u64 config; |
447a194b | 525 | u64 last_tag; |
a308444c | 526 | unsigned long config_base; |
cdd6c482 | 527 | unsigned long event_base; |
a308444c | 528 | int idx; |
447a194b | 529 | int last_cpu; |
d6d020e9 | 530 | }; |
721a669b | 531 | struct { /* software */ |
a308444c | 532 | struct hrtimer hrtimer; |
d6d020e9 | 533 | }; |
24f1e32c | 534 | #ifdef CONFIG_HAVE_HW_BREAKPOINT |
45a73372 FW |
535 | struct { /* breakpoint */ |
536 | struct arch_hw_breakpoint info; | |
537 | struct list_head bp_list; | |
538 | }; | |
24f1e32c | 539 | #endif |
d6d020e9 | 540 | }; |
a4eaf7f1 | 541 | int state; |
e7850595 | 542 | local64_t prev_count; |
b23f3325 | 543 | u64 sample_period; |
9e350de3 | 544 | u64 last_period; |
e7850595 | 545 | local64_t period_left; |
60db5e09 | 546 | u64 interrupts; |
6a24ed6c | 547 | |
abd50713 PZ |
548 | u64 freq_time_stamp; |
549 | u64 freq_count_stamp; | |
ee06094f | 550 | #endif |
0793a61d TG |
551 | }; |
552 | ||
a4eaf7f1 PZ |
553 | /* |
554 | * hw_perf_event::state flags | |
555 | */ | |
556 | #define PERF_HES_STOPPED 0x01 /* the counter is stopped */ | |
557 | #define PERF_HES_UPTODATE 0x02 /* event->count up-to-date */ | |
558 | #define PERF_HES_ARCH 0x04 | |
559 | ||
cdd6c482 | 560 | struct perf_event; |
621a01ea | 561 | |
8d2cacbb PZ |
562 | /* |
563 | * Common implementation detail of pmu::{start,commit,cancel}_txn | |
564 | */ | |
565 | #define PERF_EVENT_TXN 0x1 | |
6bde9b6c | 566 | |
621a01ea | 567 | /** |
4aeb0b42 | 568 | * struct pmu - generic performance monitoring unit |
621a01ea | 569 | */ |
4aeb0b42 | 570 | struct pmu { |
b0a873eb PZ |
571 | struct list_head entry; |
572 | ||
108b02cf PZ |
573 | int * __percpu pmu_disable_count; |
574 | struct perf_cpu_context * __percpu pmu_cpu_context; | |
33696fc0 | 575 | |
a4eaf7f1 PZ |
576 | /* |
577 | * Fully disable/enable this PMU, can be used to protect from the PMI | |
578 | * as well as for lazy/batch writing of the MSRs. | |
579 | */ | |
ad5133b7 PZ |
580 | void (*pmu_enable) (struct pmu *pmu); /* optional */ |
581 | void (*pmu_disable) (struct pmu *pmu); /* optional */ | |
33696fc0 | 582 | |
b0a873eb | 583 | /* |
a4eaf7f1 | 584 | * Try and initialize the event for this PMU. |
24cd7f54 | 585 | * Should return -ENOENT when the @event doesn't match this PMU. |
b0a873eb PZ |
586 | */ |
587 | int (*event_init) (struct perf_event *event); | |
588 | ||
a4eaf7f1 PZ |
589 | #define PERF_EF_START 0x01 /* start the counter when adding */ |
590 | #define PERF_EF_RELOAD 0x02 /* reload the counter when starting */ | |
591 | #define PERF_EF_UPDATE 0x04 /* update the counter when stopping */ | |
592 | ||
593 | /* | |
594 | * Adds/Removes a counter to/from the PMU, can be done inside | |
595 | * a transaction, see the ->*_txn() methods. | |
596 | */ | |
597 | int (*add) (struct perf_event *event, int flags); | |
598 | void (*del) (struct perf_event *event, int flags); | |
599 | ||
600 | /* | |
601 | * Starts/Stops a counter present on the PMU. The PMI handler | |
602 | * should stop the counter when perf_event_overflow() returns | |
603 | * !0. ->start() will be used to continue. | |
604 | */ | |
605 | void (*start) (struct perf_event *event, int flags); | |
606 | void (*stop) (struct perf_event *event, int flags); | |
607 | ||
608 | /* | |
609 | * Updates the counter value of the event. | |
610 | */ | |
cdd6c482 | 611 | void (*read) (struct perf_event *event); |
6bde9b6c LM |
612 | |
613 | /* | |
24cd7f54 PZ |
614 | * Group events scheduling is treated as a transaction, add |
615 | * group events as a whole and perform one schedulability test. | |
616 | * If the test fails, roll back the whole group | |
a4eaf7f1 PZ |
617 | * |
618 | * Start the transaction, after this ->add() doesn't need to | |
24cd7f54 | 619 | * do schedulability tests. |
8d2cacbb | 620 | */ |
ad5133b7 | 621 | void (*start_txn) (struct pmu *pmu); /* optional */ |
8d2cacbb | 622 | /* |
a4eaf7f1 | 623 | * If ->start_txn() disabled the ->add() schedulability test |
8d2cacbb PZ |
624 | * then ->commit_txn() is required to perform one. On success |
625 | * the transaction is closed. On error the transaction is kept | |
626 | * open until ->cancel_txn() is called. | |
627 | */ | |
ad5133b7 | 628 | int (*commit_txn) (struct pmu *pmu); /* optional */ |
8d2cacbb | 629 | /* |
a4eaf7f1 PZ |
630 | * Will cancel the transaction, assumes ->del() is called |
631 | * for each successfull ->add() during the transaction. | |
8d2cacbb | 632 | */ |
ad5133b7 | 633 | void (*cancel_txn) (struct pmu *pmu); /* optional */ |
621a01ea IM |
634 | }; |
635 | ||
6a930700 | 636 | /** |
cdd6c482 | 637 | * enum perf_event_active_state - the states of a event |
6a930700 | 638 | */ |
cdd6c482 | 639 | enum perf_event_active_state { |
57c0c15b | 640 | PERF_EVENT_STATE_ERROR = -2, |
cdd6c482 IM |
641 | PERF_EVENT_STATE_OFF = -1, |
642 | PERF_EVENT_STATE_INACTIVE = 0, | |
57c0c15b | 643 | PERF_EVENT_STATE_ACTIVE = 1, |
6a930700 IM |
644 | }; |
645 | ||
9b51f66d IM |
646 | struct file; |
647 | ||
d57e34fd PZ |
648 | #define PERF_BUFFER_WRITABLE 0x01 |
649 | ||
ca5135e6 | 650 | struct perf_buffer { |
ac9721f3 | 651 | atomic_t refcount; |
7b732a75 | 652 | struct rcu_head rcu_head; |
906010b2 PZ |
653 | #ifdef CONFIG_PERF_USE_VMALLOC |
654 | struct work_struct work; | |
3cafa9fb | 655 | int page_order; /* allocation order */ |
906010b2 | 656 | #endif |
8740f941 | 657 | int nr_pages; /* nr of data pages */ |
43a21ea8 | 658 | int writable; /* are we writable */ |
8740f941 | 659 | |
c33a0bc4 | 660 | atomic_t poll; /* POLL_ for wakeups */ |
8740f941 | 661 | |
fa588151 PZ |
662 | local_t head; /* write position */ |
663 | local_t nest; /* nested writers */ | |
664 | local_t events; /* event limit */ | |
adb8e118 | 665 | local_t wakeup; /* wakeup stamp */ |
fa588151 | 666 | local_t lost; /* nr records lost */ |
ef60777c | 667 | |
2667de81 PZ |
668 | long watermark; /* wakeup watermark */ |
669 | ||
57c0c15b | 670 | struct perf_event_mmap_page *user_page; |
0127c3ea | 671 | void *data_pages[0]; |
7b732a75 PZ |
672 | }; |
673 | ||
671dec5d PZ |
674 | struct perf_pending_entry { |
675 | struct perf_pending_entry *next; | |
676 | void (*func)(struct perf_pending_entry *); | |
925d519a PZ |
677 | }; |
678 | ||
453f19ee PZ |
679 | struct perf_sample_data; |
680 | ||
b326e956 FW |
681 | typedef void (*perf_overflow_handler_t)(struct perf_event *, int, |
682 | struct perf_sample_data *, | |
683 | struct pt_regs *regs); | |
684 | ||
d6f962b5 FW |
685 | enum perf_group_flag { |
686 | PERF_GROUP_SOFTWARE = 0x1, | |
687 | }; | |
688 | ||
76e1d904 FW |
689 | #define SWEVENT_HLIST_BITS 8 |
690 | #define SWEVENT_HLIST_SIZE (1 << SWEVENT_HLIST_BITS) | |
691 | ||
692 | struct swevent_hlist { | |
693 | struct hlist_head heads[SWEVENT_HLIST_SIZE]; | |
694 | struct rcu_head rcu_head; | |
695 | }; | |
696 | ||
8a49542c PZ |
697 | #define PERF_ATTACH_CONTEXT 0x01 |
698 | #define PERF_ATTACH_GROUP 0x02 | |
699 | ||
0793a61d | 700 | /** |
cdd6c482 | 701 | * struct perf_event - performance event kernel representation: |
0793a61d | 702 | */ |
cdd6c482 IM |
703 | struct perf_event { |
704 | #ifdef CONFIG_PERF_EVENTS | |
65abc865 | 705 | struct list_head group_entry; |
592903cd | 706 | struct list_head event_entry; |
04289bb9 | 707 | struct list_head sibling_list; |
76e1d904 | 708 | struct hlist_node hlist_entry; |
0127c3ea | 709 | int nr_siblings; |
d6f962b5 | 710 | int group_flags; |
cdd6c482 | 711 | struct perf_event *group_leader; |
a4eaf7f1 | 712 | struct pmu *pmu; |
04289bb9 | 713 | |
cdd6c482 | 714 | enum perf_event_active_state state; |
8a49542c | 715 | unsigned int attach_state; |
e7850595 | 716 | local64_t count; |
a6e6dea6 | 717 | atomic64_t child_count; |
ee06094f | 718 | |
53cfbf59 | 719 | /* |
cdd6c482 | 720 | * These are the total time in nanoseconds that the event |
53cfbf59 | 721 | * has been enabled (i.e. eligible to run, and the task has |
cdd6c482 | 722 | * been scheduled in, if this is a per-task event) |
53cfbf59 PM |
723 | * and running (scheduled onto the CPU), respectively. |
724 | * | |
725 | * They are computed from tstamp_enabled, tstamp_running and | |
cdd6c482 | 726 | * tstamp_stopped when the event is in INACTIVE or ACTIVE state. |
53cfbf59 PM |
727 | */ |
728 | u64 total_time_enabled; | |
729 | u64 total_time_running; | |
730 | ||
731 | /* | |
732 | * These are timestamps used for computing total_time_enabled | |
cdd6c482 | 733 | * and total_time_running when the event is in INACTIVE or |
53cfbf59 PM |
734 | * ACTIVE state, measured in nanoseconds from an arbitrary point |
735 | * in time. | |
cdd6c482 IM |
736 | * tstamp_enabled: the notional time when the event was enabled |
737 | * tstamp_running: the notional time when the event was scheduled on | |
53cfbf59 | 738 | * tstamp_stopped: in INACTIVE state, the notional time when the |
cdd6c482 | 739 | * event was scheduled off. |
53cfbf59 PM |
740 | */ |
741 | u64 tstamp_enabled; | |
742 | u64 tstamp_running; | |
743 | u64 tstamp_stopped; | |
744 | ||
24f1e32c | 745 | struct perf_event_attr attr; |
cdd6c482 | 746 | struct hw_perf_event hw; |
0793a61d | 747 | |
cdd6c482 | 748 | struct perf_event_context *ctx; |
9b51f66d | 749 | struct file *filp; |
0793a61d | 750 | |
53cfbf59 PM |
751 | /* |
752 | * These accumulate total time (in nanoseconds) that children | |
cdd6c482 | 753 | * events have been enabled and running, respectively. |
53cfbf59 PM |
754 | */ |
755 | atomic64_t child_total_time_enabled; | |
756 | atomic64_t child_total_time_running; | |
757 | ||
0793a61d | 758 | /* |
d859e29f | 759 | * Protect attach/detach and child_list: |
0793a61d | 760 | */ |
fccc714b PZ |
761 | struct mutex child_mutex; |
762 | struct list_head child_list; | |
cdd6c482 | 763 | struct perf_event *parent; |
0793a61d TG |
764 | |
765 | int oncpu; | |
766 | int cpu; | |
767 | ||
082ff5a2 PZ |
768 | struct list_head owner_entry; |
769 | struct task_struct *owner; | |
770 | ||
7b732a75 PZ |
771 | /* mmap bits */ |
772 | struct mutex mmap_mutex; | |
773 | atomic_t mmap_count; | |
ac9721f3 PZ |
774 | int mmap_locked; |
775 | struct user_struct *mmap_user; | |
ca5135e6 | 776 | struct perf_buffer *buffer; |
37d81828 | 777 | |
7b732a75 | 778 | /* poll related */ |
0793a61d | 779 | wait_queue_head_t waitq; |
3c446b3d | 780 | struct fasync_struct *fasync; |
79f14641 PZ |
781 | |
782 | /* delayed work for NMIs and such */ | |
783 | int pending_wakeup; | |
4c9e2542 | 784 | int pending_kill; |
79f14641 | 785 | int pending_disable; |
671dec5d | 786 | struct perf_pending_entry pending; |
592903cd | 787 | |
79f14641 PZ |
788 | atomic_t event_limit; |
789 | ||
cdd6c482 | 790 | void (*destroy)(struct perf_event *); |
592903cd | 791 | struct rcu_head rcu_head; |
709e50cf PZ |
792 | |
793 | struct pid_namespace *ns; | |
8e5799b1 | 794 | u64 id; |
6fb2915d | 795 | |
b326e956 | 796 | perf_overflow_handler_t overflow_handler; |
453f19ee | 797 | |
07b139c8 | 798 | #ifdef CONFIG_EVENT_TRACING |
1c024eca | 799 | struct ftrace_event_call *tp_event; |
6fb2915d | 800 | struct event_filter *filter; |
ee06094f | 801 | #endif |
6fb2915d LZ |
802 | |
803 | #endif /* CONFIG_PERF_EVENTS */ | |
0793a61d TG |
804 | }; |
805 | ||
806 | /** | |
cdd6c482 | 807 | * struct perf_event_context - event context structure |
0793a61d | 808 | * |
cdd6c482 | 809 | * Used as a container for task events and CPU events as well: |
0793a61d | 810 | */ |
cdd6c482 | 811 | struct perf_event_context { |
108b02cf | 812 | struct pmu *pmu; |
0793a61d | 813 | /* |
cdd6c482 | 814 | * Protect the states of the events in the list, |
d859e29f | 815 | * nr_active, and the list: |
0793a61d | 816 | */ |
e625cce1 | 817 | raw_spinlock_t lock; |
d859e29f | 818 | /* |
cdd6c482 | 819 | * Protect the list of events. Locking either mutex or lock |
d859e29f PM |
820 | * is sufficient to ensure the list doesn't change; to change |
821 | * the list you need to lock both the mutex and the spinlock. | |
822 | */ | |
a308444c | 823 | struct mutex mutex; |
04289bb9 | 824 | |
889ff015 FW |
825 | struct list_head pinned_groups; |
826 | struct list_head flexible_groups; | |
a308444c | 827 | struct list_head event_list; |
cdd6c482 | 828 | int nr_events; |
a308444c IM |
829 | int nr_active; |
830 | int is_active; | |
bfbd3381 | 831 | int nr_stat; |
a308444c IM |
832 | atomic_t refcount; |
833 | struct task_struct *task; | |
53cfbf59 PM |
834 | |
835 | /* | |
4af4998b | 836 | * Context clock, runs when context enabled. |
53cfbf59 | 837 | */ |
a308444c IM |
838 | u64 time; |
839 | u64 timestamp; | |
564c2b21 PM |
840 | |
841 | /* | |
842 | * These fields let us detect when two contexts have both | |
843 | * been cloned (inherited) from a common ancestor. | |
844 | */ | |
cdd6c482 | 845 | struct perf_event_context *parent_ctx; |
a308444c IM |
846 | u64 parent_gen; |
847 | u64 generation; | |
848 | int pin_count; | |
849 | struct rcu_head rcu_head; | |
0793a61d TG |
850 | }; |
851 | ||
7ae07ea3 FW |
852 | /* |
853 | * Number of contexts where an event can trigger: | |
854 | * task, softirq, hardirq, nmi. | |
855 | */ | |
856 | #define PERF_NR_CONTEXTS 4 | |
857 | ||
0793a61d | 858 | /** |
cdd6c482 | 859 | * struct perf_event_cpu_context - per cpu event context structure |
0793a61d TG |
860 | */ |
861 | struct perf_cpu_context { | |
cdd6c482 IM |
862 | struct perf_event_context ctx; |
863 | struct perf_event_context *task_ctx; | |
0793a61d | 864 | int active_oncpu; |
3b6f9e5c | 865 | int exclusive; |
b5ab4cd5 PZ |
866 | u64 timer_interval; |
867 | struct hrtimer timer; | |
0793a61d TG |
868 | }; |
869 | ||
5622f295 | 870 | struct perf_output_handle { |
57c0c15b | 871 | struct perf_event *event; |
ca5135e6 | 872 | struct perf_buffer *buffer; |
6d1acfd5 | 873 | unsigned long wakeup; |
5d967a8b PZ |
874 | unsigned long size; |
875 | void *addr; | |
876 | int page; | |
57c0c15b IM |
877 | int nmi; |
878 | int sample; | |
5622f295 MM |
879 | }; |
880 | ||
cdd6c482 | 881 | #ifdef CONFIG_PERF_EVENTS |
829b42dd | 882 | |
b0a873eb PZ |
883 | extern int perf_pmu_register(struct pmu *pmu); |
884 | extern void perf_pmu_unregister(struct pmu *pmu); | |
621a01ea | 885 | |
49f47433 | 886 | extern void perf_event_task_sched_in(struct task_struct *task); |
184f412c | 887 | extern void perf_event_task_sched_out(struct task_struct *task, struct task_struct *next); |
cdd6c482 IM |
888 | extern int perf_event_init_task(struct task_struct *child); |
889 | extern void perf_event_exit_task(struct task_struct *child); | |
890 | extern void perf_event_free_task(struct task_struct *task); | |
891 | extern void set_perf_event_pending(void); | |
892 | extern void perf_event_do_pending(void); | |
893 | extern void perf_event_print_debug(void); | |
33696fc0 PZ |
894 | extern void perf_pmu_disable(struct pmu *pmu); |
895 | extern void perf_pmu_enable(struct pmu *pmu); | |
cdd6c482 IM |
896 | extern int perf_event_task_disable(void); |
897 | extern int perf_event_task_enable(void); | |
cdd6c482 | 898 | extern void perf_event_update_userpage(struct perf_event *event); |
fb0459d7 AV |
899 | extern int perf_event_release_kernel(struct perf_event *event); |
900 | extern struct perf_event * | |
901 | perf_event_create_kernel_counter(struct perf_event_attr *attr, | |
902 | int cpu, | |
97eaf530 | 903 | pid_t pid, |
b326e956 | 904 | perf_overflow_handler_t callback); |
59ed446f PZ |
905 | extern u64 perf_event_read_value(struct perf_event *event, |
906 | u64 *enabled, u64 *running); | |
5c92d124 | 907 | |
df1a132b | 908 | struct perf_sample_data { |
5622f295 MM |
909 | u64 type; |
910 | ||
911 | u64 ip; | |
912 | struct { | |
913 | u32 pid; | |
914 | u32 tid; | |
915 | } tid_entry; | |
916 | u64 time; | |
a308444c | 917 | u64 addr; |
5622f295 MM |
918 | u64 id; |
919 | u64 stream_id; | |
920 | struct { | |
921 | u32 cpu; | |
922 | u32 reserved; | |
923 | } cpu_entry; | |
a308444c | 924 | u64 period; |
5622f295 | 925 | struct perf_callchain_entry *callchain; |
3a43ce68 | 926 | struct perf_raw_record *raw; |
df1a132b PZ |
927 | }; |
928 | ||
dc1d628a PZ |
929 | static inline |
930 | void perf_sample_data_init(struct perf_sample_data *data, u64 addr) | |
931 | { | |
932 | data->addr = addr; | |
933 | data->raw = NULL; | |
934 | } | |
935 | ||
5622f295 MM |
936 | extern void perf_output_sample(struct perf_output_handle *handle, |
937 | struct perf_event_header *header, | |
938 | struct perf_sample_data *data, | |
cdd6c482 | 939 | struct perf_event *event); |
5622f295 MM |
940 | extern void perf_prepare_sample(struct perf_event_header *header, |
941 | struct perf_sample_data *data, | |
cdd6c482 | 942 | struct perf_event *event, |
5622f295 MM |
943 | struct pt_regs *regs); |
944 | ||
cdd6c482 | 945 | extern int perf_event_overflow(struct perf_event *event, int nmi, |
5622f295 MM |
946 | struct perf_sample_data *data, |
947 | struct pt_regs *regs); | |
df1a132b | 948 | |
3b6f9e5c | 949 | /* |
cdd6c482 | 950 | * Return 1 for a software event, 0 for a hardware event |
3b6f9e5c | 951 | */ |
cdd6c482 | 952 | static inline int is_software_event(struct perf_event *event) |
3b6f9e5c | 953 | { |
92b67598 PZ |
954 | switch (event->attr.type) { |
955 | case PERF_TYPE_SOFTWARE: | |
956 | case PERF_TYPE_TRACEPOINT: | |
957 | /* for now the breakpoint stuff also works as software event */ | |
958 | case PERF_TYPE_BREAKPOINT: | |
959 | return 1; | |
960 | } | |
961 | return 0; | |
3b6f9e5c PM |
962 | } |
963 | ||
cdd6c482 | 964 | extern atomic_t perf_swevent_enabled[PERF_COUNT_SW_MAX]; |
f29ac756 | 965 | |
cdd6c482 | 966 | extern void __perf_sw_event(u32, u64, int, struct pt_regs *, u64); |
f29ac756 | 967 | |
b0f82b81 FW |
968 | #ifndef perf_arch_fetch_caller_regs |
969 | static inline void | |
5cfaf214 | 970 | perf_arch_fetch_caller_regs(struct pt_regs *regs, unsigned long ip) { } |
b0f82b81 | 971 | #endif |
5331d7b8 FW |
972 | |
973 | /* | |
974 | * Take a snapshot of the regs. Skip ip and frame pointer to | |
975 | * the nth caller. We only need a few of the regs: | |
976 | * - ip for PERF_SAMPLE_IP | |
977 | * - cs for user_mode() tests | |
978 | * - bp for callchains | |
979 | * - eflags, for future purposes, just in case | |
980 | */ | |
b0f82b81 | 981 | static inline void perf_fetch_caller_regs(struct pt_regs *regs) |
5331d7b8 | 982 | { |
5331d7b8 FW |
983 | memset(regs, 0, sizeof(*regs)); |
984 | ||
b0f82b81 | 985 | perf_arch_fetch_caller_regs(regs, CALLER_ADDR0); |
5331d7b8 FW |
986 | } |
987 | ||
e49a5bd3 FW |
988 | static inline void |
989 | perf_sw_event(u32 event_id, u64 nr, int nmi, struct pt_regs *regs, u64 addr) | |
990 | { | |
991 | if (atomic_read(&perf_swevent_enabled[event_id])) { | |
992 | struct pt_regs hot_regs; | |
993 | ||
994 | if (!regs) { | |
b0f82b81 | 995 | perf_fetch_caller_regs(&hot_regs); |
e49a5bd3 FW |
996 | regs = &hot_regs; |
997 | } | |
998 | __perf_sw_event(event_id, nr, nmi, regs, addr); | |
999 | } | |
1000 | } | |
1001 | ||
3af9e859 | 1002 | extern void perf_event_mmap(struct vm_area_struct *vma); |
39447b38 | 1003 | extern struct perf_guest_info_callbacks *perf_guest_cbs; |
dcf46b94 ZY |
1004 | extern int perf_register_guest_info_callbacks(struct perf_guest_info_callbacks *callbacks); |
1005 | extern int perf_unregister_guest_info_callbacks(struct perf_guest_info_callbacks *callbacks); | |
39447b38 | 1006 | |
cdd6c482 IM |
1007 | extern void perf_event_comm(struct task_struct *tsk); |
1008 | extern void perf_event_fork(struct task_struct *tsk); | |
8d1b2d93 | 1009 | |
56962b44 FW |
1010 | /* Callchains */ |
1011 | DECLARE_PER_CPU(struct perf_callchain_entry, perf_callchain_entry); | |
1012 | ||
1013 | extern void perf_callchain_user(struct perf_callchain_entry *entry, | |
1014 | struct pt_regs *regs); | |
1015 | extern void perf_callchain_kernel(struct perf_callchain_entry *entry, | |
1016 | struct pt_regs *regs); | |
56962b44 | 1017 | |
394ee076 | 1018 | |
70791ce9 FW |
1019 | static inline void |
1020 | perf_callchain_store(struct perf_callchain_entry *entry, u64 ip) | |
1021 | { | |
1022 | if (entry->nr < PERF_MAX_STACK_DEPTH) | |
1023 | entry->ip[entry->nr++] = ip; | |
1024 | } | |
1025 | ||
cdd6c482 IM |
1026 | extern int sysctl_perf_event_paranoid; |
1027 | extern int sysctl_perf_event_mlock; | |
1028 | extern int sysctl_perf_event_sample_rate; | |
1ccd1549 | 1029 | |
320ebf09 PZ |
1030 | static inline bool perf_paranoid_tracepoint_raw(void) |
1031 | { | |
1032 | return sysctl_perf_event_paranoid > -1; | |
1033 | } | |
1034 | ||
1035 | static inline bool perf_paranoid_cpu(void) | |
1036 | { | |
1037 | return sysctl_perf_event_paranoid > 0; | |
1038 | } | |
1039 | ||
1040 | static inline bool perf_paranoid_kernel(void) | |
1041 | { | |
1042 | return sysctl_perf_event_paranoid > 1; | |
1043 | } | |
1044 | ||
cdd6c482 | 1045 | extern void perf_event_init(void); |
1c024eca PZ |
1046 | extern void perf_tp_event(u64 addr, u64 count, void *record, |
1047 | int entry_size, struct pt_regs *regs, | |
ecc55f84 | 1048 | struct hlist_head *head, int rctx); |
24f1e32c | 1049 | extern void perf_bp_event(struct perf_event *event, void *data); |
0d905bca | 1050 | |
9d23a90a | 1051 | #ifndef perf_misc_flags |
cdd6c482 IM |
1052 | #define perf_misc_flags(regs) (user_mode(regs) ? PERF_RECORD_MISC_USER : \ |
1053 | PERF_RECORD_MISC_KERNEL) | |
9d23a90a PM |
1054 | #define perf_instruction_pointer(regs) instruction_pointer(regs) |
1055 | #endif | |
1056 | ||
5622f295 | 1057 | extern int perf_output_begin(struct perf_output_handle *handle, |
cdd6c482 | 1058 | struct perf_event *event, unsigned int size, |
5622f295 MM |
1059 | int nmi, int sample); |
1060 | extern void perf_output_end(struct perf_output_handle *handle); | |
1061 | extern void perf_output_copy(struct perf_output_handle *handle, | |
1062 | const void *buf, unsigned int len); | |
4ed7c92d PZ |
1063 | extern int perf_swevent_get_recursion_context(void); |
1064 | extern void perf_swevent_put_recursion_context(int rctx); | |
44234adc FW |
1065 | extern void perf_event_enable(struct perf_event *event); |
1066 | extern void perf_event_disable(struct perf_event *event); | |
0793a61d TG |
1067 | #else |
1068 | static inline void | |
49f47433 | 1069 | perf_event_task_sched_in(struct task_struct *task) { } |
0793a61d | 1070 | static inline void |
cdd6c482 | 1071 | perf_event_task_sched_out(struct task_struct *task, |
49f47433 | 1072 | struct task_struct *next) { } |
cdd6c482 IM |
1073 | static inline int perf_event_init_task(struct task_struct *child) { return 0; } |
1074 | static inline void perf_event_exit_task(struct task_struct *child) { } | |
1075 | static inline void perf_event_free_task(struct task_struct *task) { } | |
57c0c15b IM |
1076 | static inline void perf_event_do_pending(void) { } |
1077 | static inline void perf_event_print_debug(void) { } | |
57c0c15b IM |
1078 | static inline int perf_event_task_disable(void) { return -EINVAL; } |
1079 | static inline int perf_event_task_enable(void) { return -EINVAL; } | |
15dbf27c | 1080 | |
925d519a | 1081 | static inline void |
cdd6c482 | 1082 | perf_sw_event(u32 event_id, u64 nr, int nmi, |
78f13e95 | 1083 | struct pt_regs *regs, u64 addr) { } |
24f1e32c | 1084 | static inline void |
184f412c | 1085 | perf_bp_event(struct perf_event *event, void *data) { } |
0a4a9391 | 1086 | |
39447b38 | 1087 | static inline int perf_register_guest_info_callbacks |
dcf46b94 | 1088 | (struct perf_guest_info_callbacks *callbacks) { return 0; } |
39447b38 | 1089 | static inline int perf_unregister_guest_info_callbacks |
dcf46b94 | 1090 | (struct perf_guest_info_callbacks *callbacks) { return 0; } |
39447b38 | 1091 | |
57c0c15b | 1092 | static inline void perf_event_mmap(struct vm_area_struct *vma) { } |
cdd6c482 IM |
1093 | static inline void perf_event_comm(struct task_struct *tsk) { } |
1094 | static inline void perf_event_fork(struct task_struct *tsk) { } | |
1095 | static inline void perf_event_init(void) { } | |
184f412c | 1096 | static inline int perf_swevent_get_recursion_context(void) { return -1; } |
4ed7c92d | 1097 | static inline void perf_swevent_put_recursion_context(int rctx) { } |
44234adc FW |
1098 | static inline void perf_event_enable(struct perf_event *event) { } |
1099 | static inline void perf_event_disable(struct perf_event *event) { } | |
0793a61d TG |
1100 | #endif |
1101 | ||
5622f295 MM |
1102 | #define perf_output_put(handle, x) \ |
1103 | perf_output_copy((handle), &(x), sizeof(x)) | |
1104 | ||
3f6da390 PZ |
1105 | /* |
1106 | * This has to have a higher priority than migration_notifier in sched.c. | |
1107 | */ | |
1108 | #define perf_cpu_notifier(fn) \ | |
1109 | do { \ | |
1110 | static struct notifier_block fn##_nb __cpuinitdata = \ | |
50a323b7 | 1111 | { .notifier_call = fn, .priority = CPU_PRI_PERF }; \ |
3f6da390 PZ |
1112 | fn(&fn##_nb, (unsigned long)CPU_UP_PREPARE, \ |
1113 | (void *)(unsigned long)smp_processor_id()); \ | |
1114 | fn(&fn##_nb, (unsigned long)CPU_STARTING, \ | |
1115 | (void *)(unsigned long)smp_processor_id()); \ | |
1116 | fn(&fn##_nb, (unsigned long)CPU_ONLINE, \ | |
1117 | (void *)(unsigned long)smp_processor_id()); \ | |
1118 | register_cpu_notifier(&fn##_nb); \ | |
1119 | } while (0) | |
1120 | ||
f3dfd265 | 1121 | #endif /* __KERNEL__ */ |
cdd6c482 | 1122 | #endif /* _LINUX_PERF_EVENT_H */ |