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b2441318 | 1 | /* SPDX-License-Identifier: GPL-2.0 */ |
ca5999fd MR |
2 | #ifndef _LINUX_PGTABLE_H |
3 | #define _LINUX_PGTABLE_H | |
1da177e4 | 4 | |
f25748e3 | 5 | #include <linux/pfn.h> |
ca5999fd | 6 | #include <asm/pgtable.h> |
f25748e3 | 7 | |
673eae82 | 8 | #ifndef __ASSEMBLY__ |
9535239f | 9 | #ifdef CONFIG_MMU |
673eae82 | 10 | |
fbd71844 | 11 | #include <linux/mm_types.h> |
187f1882 | 12 | #include <linux/bug.h> |
e61ce6ad | 13 | #include <linux/errno.h> |
5a281062 | 14 | #include <asm-generic/pgtable_uffd.h> |
fbd71844 | 15 | |
c2febafc KS |
16 | #if 5 - defined(__PAGETABLE_P4D_FOLDED) - defined(__PAGETABLE_PUD_FOLDED) - \ |
17 | defined(__PAGETABLE_PMD_FOLDED) != CONFIG_PGTABLE_LEVELS | |
18 | #error CONFIG_PGTABLE_LEVELS is not consistent with __PAGETABLE_{P4D,PUD,PMD}_FOLDED | |
235a8f02 KS |
19 | #endif |
20 | ||
6ee8630e HD |
21 | /* |
22 | * On almost all architectures and configurations, 0 can be used as the | |
23 | * upper ceiling to free_pgtables(): on many architectures it has the same | |
24 | * effect as using TASK_SIZE. However, there is one configuration which | |
25 | * must impose a more careful limit, to avoid freeing kernel pgtables. | |
26 | */ | |
27 | #ifndef USER_PGTABLES_CEILING | |
28 | #define USER_PGTABLES_CEILING 0UL | |
29 | #endif | |
30 | ||
974b9b2c MR |
31 | /* |
32 | * A page table page can be thought of an array like this: pXd_t[PTRS_PER_PxD] | |
33 | * | |
34 | * The pXx_index() functions return the index of the entry in the page | |
35 | * table page which would control the given virtual address | |
36 | * | |
37 | * As these functions may be used by the same code for different levels of | |
38 | * the page table folding, they are always available, regardless of | |
39 | * CONFIG_PGTABLE_LEVELS value. For the folded levels they simply return 0 | |
40 | * because in such cases PTRS_PER_PxD equals 1. | |
41 | */ | |
42 | ||
43 | static inline unsigned long pte_index(unsigned long address) | |
44 | { | |
45 | return (address >> PAGE_SHIFT) & (PTRS_PER_PTE - 1); | |
46 | } | |
47 | ||
48 | #ifndef pmd_index | |
49 | static inline unsigned long pmd_index(unsigned long address) | |
50 | { | |
51 | return (address >> PMD_SHIFT) & (PTRS_PER_PMD - 1); | |
52 | } | |
53 | #define pmd_index pmd_index | |
54 | #endif | |
55 | ||
56 | #ifndef pud_index | |
57 | static inline unsigned long pud_index(unsigned long address) | |
58 | { | |
59 | return (address >> PUD_SHIFT) & (PTRS_PER_PUD - 1); | |
60 | } | |
61 | #define pud_index pud_index | |
62 | #endif | |
63 | ||
64 | #ifndef pgd_index | |
65 | /* Must be a compile-time constant, so implement it as a macro */ | |
66 | #define pgd_index(a) (((a) >> PGDIR_SHIFT) & (PTRS_PER_PGD - 1)) | |
67 | #endif | |
68 | ||
69 | #ifndef pte_offset_kernel | |
70 | static inline pte_t *pte_offset_kernel(pmd_t *pmd, unsigned long address) | |
71 | { | |
72 | return (pte_t *)pmd_page_vaddr(*pmd) + pte_index(address); | |
73 | } | |
74 | #define pte_offset_kernel pte_offset_kernel | |
75 | #endif | |
76 | ||
77 | #if defined(CONFIG_HIGHPTE) | |
78 | #define pte_offset_map(dir, address) \ | |
79 | ((pte_t *)kmap_atomic(pmd_page(*(dir))) + \ | |
80 | pte_index((address))) | |
81 | #define pte_unmap(pte) kunmap_atomic((pte)) | |
82 | #else | |
83 | #define pte_offset_map(dir, address) pte_offset_kernel((dir), (address)) | |
84 | #define pte_unmap(pte) ((void)(pte)) /* NOP */ | |
85 | #endif | |
86 | ||
87 | /* Find an entry in the second-level page table.. */ | |
88 | #ifndef pmd_offset | |
89 | static inline pmd_t *pmd_offset(pud_t *pud, unsigned long address) | |
90 | { | |
91 | return (pmd_t *)pud_page_vaddr(*pud) + pmd_index(address); | |
92 | } | |
93 | #define pmd_offset pmd_offset | |
94 | #endif | |
95 | ||
96 | #ifndef pud_offset | |
97 | static inline pud_t *pud_offset(p4d_t *p4d, unsigned long address) | |
98 | { | |
99 | return (pud_t *)p4d_page_vaddr(*p4d) + pud_index(address); | |
100 | } | |
101 | #define pud_offset pud_offset | |
102 | #endif | |
103 | ||
104 | static inline pgd_t *pgd_offset_pgd(pgd_t *pgd, unsigned long address) | |
105 | { | |
106 | return (pgd + pgd_index(address)); | |
107 | }; | |
108 | ||
109 | /* | |
110 | * a shortcut to get a pgd_t in a given mm | |
111 | */ | |
112 | #ifndef pgd_offset | |
113 | #define pgd_offset(mm, address) pgd_offset_pgd((mm)->pgd, (address)) | |
114 | #endif | |
115 | ||
116 | /* | |
117 | * a shortcut which implies the use of the kernel's pgd, instead | |
118 | * of a process's | |
119 | */ | |
bd05220c | 120 | #ifndef pgd_offset_k |
974b9b2c | 121 | #define pgd_offset_k(address) pgd_offset(&init_mm, (address)) |
bd05220c | 122 | #endif |
974b9b2c | 123 | |
e05c7b1f MR |
124 | /* |
125 | * In many cases it is known that a virtual address is mapped at PMD or PTE | |
126 | * level, so instead of traversing all the page table levels, we can get a | |
127 | * pointer to the PMD entry in user or kernel page table or translate a virtual | |
128 | * address to the pointer in the PTE in the kernel page tables with simple | |
129 | * helpers. | |
130 | */ | |
131 | static inline pmd_t *pmd_off(struct mm_struct *mm, unsigned long va) | |
132 | { | |
133 | return pmd_offset(pud_offset(p4d_offset(pgd_offset(mm, va), va), va), va); | |
134 | } | |
135 | ||
136 | static inline pmd_t *pmd_off_k(unsigned long va) | |
137 | { | |
138 | return pmd_offset(pud_offset(p4d_offset(pgd_offset_k(va), va), va), va); | |
139 | } | |
140 | ||
141 | static inline pte_t *virt_to_kpte(unsigned long vaddr) | |
142 | { | |
143 | pmd_t *pmd = pmd_off_k(vaddr); | |
144 | ||
145 | return pmd_none(*pmd) ? NULL : pte_offset_kernel(pmd, vaddr); | |
146 | } | |
147 | ||
1da177e4 | 148 | #ifndef __HAVE_ARCH_PTEP_SET_ACCESS_FLAGS |
e2cda322 AA |
149 | extern int ptep_set_access_flags(struct vm_area_struct *vma, |
150 | unsigned long address, pte_t *ptep, | |
151 | pte_t entry, int dirty); | |
152 | #endif | |
153 | ||
154 | #ifndef __HAVE_ARCH_PMDP_SET_ACCESS_FLAGS | |
bd5e88ad | 155 | #ifdef CONFIG_TRANSPARENT_HUGEPAGE |
e2cda322 AA |
156 | extern int pmdp_set_access_flags(struct vm_area_struct *vma, |
157 | unsigned long address, pmd_t *pmdp, | |
158 | pmd_t entry, int dirty); | |
a00cc7d9 MW |
159 | extern int pudp_set_access_flags(struct vm_area_struct *vma, |
160 | unsigned long address, pud_t *pudp, | |
161 | pud_t entry, int dirty); | |
bd5e88ad VG |
162 | #else |
163 | static inline int pmdp_set_access_flags(struct vm_area_struct *vma, | |
164 | unsigned long address, pmd_t *pmdp, | |
165 | pmd_t entry, int dirty) | |
166 | { | |
167 | BUILD_BUG(); | |
168 | return 0; | |
169 | } | |
a00cc7d9 MW |
170 | static inline int pudp_set_access_flags(struct vm_area_struct *vma, |
171 | unsigned long address, pud_t *pudp, | |
172 | pud_t entry, int dirty) | |
173 | { | |
174 | BUILD_BUG(); | |
175 | return 0; | |
176 | } | |
bd5e88ad | 177 | #endif /* CONFIG_TRANSPARENT_HUGEPAGE */ |
1da177e4 LT |
178 | #endif |
179 | ||
180 | #ifndef __HAVE_ARCH_PTEP_TEST_AND_CLEAR_YOUNG | |
e2cda322 AA |
181 | static inline int ptep_test_and_clear_young(struct vm_area_struct *vma, |
182 | unsigned long address, | |
183 | pte_t *ptep) | |
184 | { | |
185 | pte_t pte = *ptep; | |
186 | int r = 1; | |
187 | if (!pte_young(pte)) | |
188 | r = 0; | |
189 | else | |
190 | set_pte_at(vma->vm_mm, address, ptep, pte_mkold(pte)); | |
191 | return r; | |
192 | } | |
193 | #endif | |
194 | ||
195 | #ifndef __HAVE_ARCH_PMDP_TEST_AND_CLEAR_YOUNG | |
196 | #ifdef CONFIG_TRANSPARENT_HUGEPAGE | |
197 | static inline int pmdp_test_and_clear_young(struct vm_area_struct *vma, | |
198 | unsigned long address, | |
199 | pmd_t *pmdp) | |
200 | { | |
201 | pmd_t pmd = *pmdp; | |
202 | int r = 1; | |
203 | if (!pmd_young(pmd)) | |
204 | r = 0; | |
205 | else | |
206 | set_pmd_at(vma->vm_mm, address, pmdp, pmd_mkold(pmd)); | |
207 | return r; | |
208 | } | |
bd5e88ad | 209 | #else |
e2cda322 AA |
210 | static inline int pmdp_test_and_clear_young(struct vm_area_struct *vma, |
211 | unsigned long address, | |
212 | pmd_t *pmdp) | |
213 | { | |
bd5e88ad | 214 | BUILD_BUG(); |
e2cda322 AA |
215 | return 0; |
216 | } | |
217 | #endif /* CONFIG_TRANSPARENT_HUGEPAGE */ | |
1da177e4 LT |
218 | #endif |
219 | ||
220 | #ifndef __HAVE_ARCH_PTEP_CLEAR_YOUNG_FLUSH | |
e2cda322 AA |
221 | int ptep_clear_flush_young(struct vm_area_struct *vma, |
222 | unsigned long address, pte_t *ptep); | |
223 | #endif | |
224 | ||
225 | #ifndef __HAVE_ARCH_PMDP_CLEAR_YOUNG_FLUSH | |
bd5e88ad VG |
226 | #ifdef CONFIG_TRANSPARENT_HUGEPAGE |
227 | extern int pmdp_clear_flush_young(struct vm_area_struct *vma, | |
228 | unsigned long address, pmd_t *pmdp); | |
229 | #else | |
230 | /* | |
231 | * Despite relevant to THP only, this API is called from generic rmap code | |
232 | * under PageTransHuge(), hence needs a dummy implementation for !THP | |
233 | */ | |
234 | static inline int pmdp_clear_flush_young(struct vm_area_struct *vma, | |
235 | unsigned long address, pmd_t *pmdp) | |
236 | { | |
237 | BUILD_BUG(); | |
238 | return 0; | |
239 | } | |
240 | #endif /* CONFIG_TRANSPARENT_HUGEPAGE */ | |
1da177e4 LT |
241 | #endif |
242 | ||
1da177e4 | 243 | #ifndef __HAVE_ARCH_PTEP_GET_AND_CLEAR |
e2cda322 AA |
244 | static inline pte_t ptep_get_and_clear(struct mm_struct *mm, |
245 | unsigned long address, | |
246 | pte_t *ptep) | |
247 | { | |
248 | pte_t pte = *ptep; | |
249 | pte_clear(mm, address, ptep); | |
250 | return pte; | |
251 | } | |
252 | #endif | |
253 | ||
481e980a CL |
254 | #ifndef __HAVE_ARCH_PTEP_GET |
255 | static inline pte_t ptep_get(pte_t *ptep) | |
256 | { | |
257 | return READ_ONCE(*ptep); | |
258 | } | |
259 | #endif | |
260 | ||
2a4a06da PZ |
261 | #ifdef CONFIG_GUP_GET_PTE_LOW_HIGH |
262 | /* | |
263 | * WARNING: only to be used in the get_user_pages_fast() implementation. | |
264 | * | |
265 | * With get_user_pages_fast(), we walk down the pagetables without taking any | |
266 | * locks. For this we would like to load the pointers atomically, but sometimes | |
267 | * that is not possible (e.g. without expensive cmpxchg8b on x86_32 PAE). What | |
268 | * we do have is the guarantee that a PTE will only either go from not present | |
269 | * to present, or present to not present or both -- it will not switch to a | |
270 | * completely different present page without a TLB flush in between; something | |
271 | * that we are blocking by holding interrupts off. | |
272 | * | |
273 | * Setting ptes from not present to present goes: | |
274 | * | |
275 | * ptep->pte_high = h; | |
276 | * smp_wmb(); | |
277 | * ptep->pte_low = l; | |
278 | * | |
279 | * And present to not present goes: | |
280 | * | |
281 | * ptep->pte_low = 0; | |
282 | * smp_wmb(); | |
283 | * ptep->pte_high = 0; | |
284 | * | |
285 | * We must ensure here that the load of pte_low sees 'l' IFF pte_high sees 'h'. | |
286 | * We load pte_high *after* loading pte_low, which ensures we don't see an older | |
287 | * value of pte_high. *Then* we recheck pte_low, which ensures that we haven't | |
288 | * picked up a changed pte high. We might have gotten rubbish values from | |
289 | * pte_low and pte_high, but we are guaranteed that pte_low will not have the | |
290 | * present bit set *unless* it is 'l'. Because get_user_pages_fast() only | |
291 | * operates on present ptes we're safe. | |
292 | */ | |
293 | static inline pte_t ptep_get_lockless(pte_t *ptep) | |
294 | { | |
295 | pte_t pte; | |
296 | ||
297 | do { | |
298 | pte.pte_low = ptep->pte_low; | |
299 | smp_rmb(); | |
300 | pte.pte_high = ptep->pte_high; | |
301 | smp_rmb(); | |
302 | } while (unlikely(pte.pte_low != ptep->pte_low)); | |
303 | ||
304 | return pte; | |
305 | } | |
306 | #else /* CONFIG_GUP_GET_PTE_LOW_HIGH */ | |
307 | /* | |
308 | * We require that the PTE can be read atomically. | |
309 | */ | |
310 | static inline pte_t ptep_get_lockless(pte_t *ptep) | |
311 | { | |
312 | return ptep_get(ptep); | |
313 | } | |
314 | #endif /* CONFIG_GUP_GET_PTE_LOW_HIGH */ | |
315 | ||
e2cda322 | 316 | #ifdef CONFIG_TRANSPARENT_HUGEPAGE |
a00cc7d9 | 317 | #ifndef __HAVE_ARCH_PMDP_HUGE_GET_AND_CLEAR |
8809aa2d AK |
318 | static inline pmd_t pmdp_huge_get_and_clear(struct mm_struct *mm, |
319 | unsigned long address, | |
320 | pmd_t *pmdp) | |
e2cda322 AA |
321 | { |
322 | pmd_t pmd = *pmdp; | |
2d28a227 | 323 | pmd_clear(pmdp); |
e2cda322 | 324 | return pmd; |
49b24d6b | 325 | } |
a00cc7d9 MW |
326 | #endif /* __HAVE_ARCH_PMDP_HUGE_GET_AND_CLEAR */ |
327 | #ifndef __HAVE_ARCH_PUDP_HUGE_GET_AND_CLEAR | |
328 | static inline pud_t pudp_huge_get_and_clear(struct mm_struct *mm, | |
329 | unsigned long address, | |
330 | pud_t *pudp) | |
331 | { | |
332 | pud_t pud = *pudp; | |
333 | ||
334 | pud_clear(pudp); | |
335 | return pud; | |
336 | } | |
337 | #endif /* __HAVE_ARCH_PUDP_HUGE_GET_AND_CLEAR */ | |
e2cda322 | 338 | #endif /* CONFIG_TRANSPARENT_HUGEPAGE */ |
1da177e4 | 339 | |
fcbe08d6 | 340 | #ifdef CONFIG_TRANSPARENT_HUGEPAGE |
a00cc7d9 | 341 | #ifndef __HAVE_ARCH_PMDP_HUGE_GET_AND_CLEAR_FULL |
93a98695 | 342 | static inline pmd_t pmdp_huge_get_and_clear_full(struct vm_area_struct *vma, |
fcbe08d6 MS |
343 | unsigned long address, pmd_t *pmdp, |
344 | int full) | |
345 | { | |
93a98695 | 346 | return pmdp_huge_get_and_clear(vma->vm_mm, address, pmdp); |
fcbe08d6 | 347 | } |
fcbe08d6 MS |
348 | #endif |
349 | ||
a00cc7d9 MW |
350 | #ifndef __HAVE_ARCH_PUDP_HUGE_GET_AND_CLEAR_FULL |
351 | static inline pud_t pudp_huge_get_and_clear_full(struct mm_struct *mm, | |
352 | unsigned long address, pud_t *pudp, | |
353 | int full) | |
354 | { | |
355 | return pudp_huge_get_and_clear(mm, address, pudp); | |
356 | } | |
357 | #endif | |
358 | #endif /* CONFIG_TRANSPARENT_HUGEPAGE */ | |
359 | ||
a600388d | 360 | #ifndef __HAVE_ARCH_PTEP_GET_AND_CLEAR_FULL |
e2cda322 AA |
361 | static inline pte_t ptep_get_and_clear_full(struct mm_struct *mm, |
362 | unsigned long address, pte_t *ptep, | |
363 | int full) | |
364 | { | |
365 | pte_t pte; | |
366 | pte = ptep_get_and_clear(mm, address, ptep); | |
367 | return pte; | |
368 | } | |
a600388d ZA |
369 | #endif |
370 | ||
7df67697 BM |
371 | |
372 | /* | |
373 | * If two threads concurrently fault at the same page, the thread that | |
374 | * won the race updates the PTE and its local TLB/Cache. The other thread | |
375 | * gives up, simply does nothing, and continues; on architectures where | |
376 | * software can update TLB, local TLB can be updated here to avoid next page | |
377 | * fault. This function updates TLB only, do nothing with cache or others. | |
378 | * It is the difference with function update_mmu_cache. | |
379 | */ | |
380 | #ifndef __HAVE_ARCH_UPDATE_MMU_TLB | |
381 | static inline void update_mmu_tlb(struct vm_area_struct *vma, | |
382 | unsigned long address, pte_t *ptep) | |
383 | { | |
384 | } | |
385 | #define __HAVE_ARCH_UPDATE_MMU_TLB | |
386 | #endif | |
387 | ||
9888a1ca ZA |
388 | /* |
389 | * Some architectures may be able to avoid expensive synchronization | |
390 | * primitives when modifications are made to PTE's which are already | |
391 | * not present, or in the process of an address space destruction. | |
392 | */ | |
393 | #ifndef __HAVE_ARCH_PTE_CLEAR_NOT_PRESENT_FULL | |
e2cda322 AA |
394 | static inline void pte_clear_not_present_full(struct mm_struct *mm, |
395 | unsigned long address, | |
396 | pte_t *ptep, | |
397 | int full) | |
398 | { | |
399 | pte_clear(mm, address, ptep); | |
400 | } | |
a600388d ZA |
401 | #endif |
402 | ||
1da177e4 | 403 | #ifndef __HAVE_ARCH_PTEP_CLEAR_FLUSH |
e2cda322 AA |
404 | extern pte_t ptep_clear_flush(struct vm_area_struct *vma, |
405 | unsigned long address, | |
406 | pte_t *ptep); | |
407 | #endif | |
408 | ||
8809aa2d AK |
409 | #ifndef __HAVE_ARCH_PMDP_HUGE_CLEAR_FLUSH |
410 | extern pmd_t pmdp_huge_clear_flush(struct vm_area_struct *vma, | |
e2cda322 AA |
411 | unsigned long address, |
412 | pmd_t *pmdp); | |
a00cc7d9 MW |
413 | extern pud_t pudp_huge_clear_flush(struct vm_area_struct *vma, |
414 | unsigned long address, | |
415 | pud_t *pudp); | |
1da177e4 LT |
416 | #endif |
417 | ||
418 | #ifndef __HAVE_ARCH_PTEP_SET_WRPROTECT | |
8c65b4a6 | 419 | struct mm_struct; |
1da177e4 LT |
420 | static inline void ptep_set_wrprotect(struct mm_struct *mm, unsigned long address, pte_t *ptep) |
421 | { | |
422 | pte_t old_pte = *ptep; | |
423 | set_pte_at(mm, address, ptep, pte_wrprotect(old_pte)); | |
424 | } | |
425 | #endif | |
426 | ||
44bf431b BM |
427 | /* |
428 | * On some architectures hardware does not set page access bit when accessing | |
429 | * memory page, it is responsibilty of software setting this bit. It brings | |
430 | * out extra page fault penalty to track page access bit. For optimization page | |
431 | * access bit can be set during all page fault flow on these arches. | |
432 | * To be differentiate with macro pte_mkyoung, this macro is used on platforms | |
433 | * where software maintains page access bit. | |
434 | */ | |
435 | #ifndef pte_sw_mkyoung | |
436 | static inline pte_t pte_sw_mkyoung(pte_t pte) | |
437 | { | |
438 | return pte; | |
439 | } | |
440 | #define pte_sw_mkyoung pte_sw_mkyoung | |
441 | #endif | |
442 | ||
288bc549 AK |
443 | #ifndef pte_savedwrite |
444 | #define pte_savedwrite pte_write | |
445 | #endif | |
446 | ||
447 | #ifndef pte_mk_savedwrite | |
448 | #define pte_mk_savedwrite pte_mkwrite | |
449 | #endif | |
450 | ||
595cd8f2 AK |
451 | #ifndef pte_clear_savedwrite |
452 | #define pte_clear_savedwrite pte_wrprotect | |
453 | #endif | |
454 | ||
288bc549 AK |
455 | #ifndef pmd_savedwrite |
456 | #define pmd_savedwrite pmd_write | |
457 | #endif | |
458 | ||
459 | #ifndef pmd_mk_savedwrite | |
460 | #define pmd_mk_savedwrite pmd_mkwrite | |
461 | #endif | |
462 | ||
595cd8f2 AK |
463 | #ifndef pmd_clear_savedwrite |
464 | #define pmd_clear_savedwrite pmd_wrprotect | |
465 | #endif | |
466 | ||
e2cda322 AA |
467 | #ifndef __HAVE_ARCH_PMDP_SET_WRPROTECT |
468 | #ifdef CONFIG_TRANSPARENT_HUGEPAGE | |
469 | static inline void pmdp_set_wrprotect(struct mm_struct *mm, | |
470 | unsigned long address, pmd_t *pmdp) | |
471 | { | |
472 | pmd_t old_pmd = *pmdp; | |
473 | set_pmd_at(mm, address, pmdp, pmd_wrprotect(old_pmd)); | |
474 | } | |
bd5e88ad | 475 | #else |
e2cda322 AA |
476 | static inline void pmdp_set_wrprotect(struct mm_struct *mm, |
477 | unsigned long address, pmd_t *pmdp) | |
478 | { | |
bd5e88ad | 479 | BUILD_BUG(); |
e2cda322 AA |
480 | } |
481 | #endif /* CONFIG_TRANSPARENT_HUGEPAGE */ | |
482 | #endif | |
a00cc7d9 MW |
483 | #ifndef __HAVE_ARCH_PUDP_SET_WRPROTECT |
484 | #ifdef CONFIG_HAVE_ARCH_TRANSPARENT_HUGEPAGE_PUD | |
485 | static inline void pudp_set_wrprotect(struct mm_struct *mm, | |
486 | unsigned long address, pud_t *pudp) | |
487 | { | |
488 | pud_t old_pud = *pudp; | |
489 | ||
490 | set_pud_at(mm, address, pudp, pud_wrprotect(old_pud)); | |
491 | } | |
492 | #else | |
493 | static inline void pudp_set_wrprotect(struct mm_struct *mm, | |
494 | unsigned long address, pud_t *pudp) | |
495 | { | |
496 | BUILD_BUG(); | |
497 | } | |
498 | #endif /* CONFIG_HAVE_ARCH_TRANSPARENT_HUGEPAGE_PUD */ | |
499 | #endif | |
e2cda322 | 500 | |
15a25b2e AK |
501 | #ifndef pmdp_collapse_flush |
502 | #ifdef CONFIG_TRANSPARENT_HUGEPAGE | |
f28b6ff8 AK |
503 | extern pmd_t pmdp_collapse_flush(struct vm_area_struct *vma, |
504 | unsigned long address, pmd_t *pmdp); | |
15a25b2e AK |
505 | #else |
506 | static inline pmd_t pmdp_collapse_flush(struct vm_area_struct *vma, | |
507 | unsigned long address, | |
508 | pmd_t *pmdp) | |
509 | { | |
510 | BUILD_BUG(); | |
511 | return *pmdp; | |
512 | } | |
513 | #define pmdp_collapse_flush pmdp_collapse_flush | |
514 | #endif /* CONFIG_TRANSPARENT_HUGEPAGE */ | |
515 | #endif | |
516 | ||
e3ebcf64 | 517 | #ifndef __HAVE_ARCH_PGTABLE_DEPOSIT |
6b0b50b0 AK |
518 | extern void pgtable_trans_huge_deposit(struct mm_struct *mm, pmd_t *pmdp, |
519 | pgtable_t pgtable); | |
e3ebcf64 GS |
520 | #endif |
521 | ||
522 | #ifndef __HAVE_ARCH_PGTABLE_WITHDRAW | |
6b0b50b0 | 523 | extern pgtable_t pgtable_trans_huge_withdraw(struct mm_struct *mm, pmd_t *pmdp); |
e3ebcf64 GS |
524 | #endif |
525 | ||
c58f0bb7 KS |
526 | #ifdef CONFIG_TRANSPARENT_HUGEPAGE |
527 | /* | |
528 | * This is an implementation of pmdp_establish() that is only suitable for an | |
529 | * architecture that doesn't have hardware dirty/accessed bits. In this case we | |
530 | * can't race with CPU which sets these bits and non-atomic aproach is fine. | |
531 | */ | |
532 | static inline pmd_t generic_pmdp_establish(struct vm_area_struct *vma, | |
533 | unsigned long address, pmd_t *pmdp, pmd_t pmd) | |
534 | { | |
535 | pmd_t old_pmd = *pmdp; | |
536 | set_pmd_at(vma->vm_mm, address, pmdp, pmd); | |
537 | return old_pmd; | |
538 | } | |
539 | #endif | |
540 | ||
46dcde73 | 541 | #ifndef __HAVE_ARCH_PMDP_INVALIDATE |
d52605d7 | 542 | extern pmd_t pmdp_invalidate(struct vm_area_struct *vma, unsigned long address, |
46dcde73 GS |
543 | pmd_t *pmdp); |
544 | #endif | |
545 | ||
1da177e4 | 546 | #ifndef __HAVE_ARCH_PTE_SAME |
e2cda322 AA |
547 | static inline int pte_same(pte_t pte_a, pte_t pte_b) |
548 | { | |
549 | return pte_val(pte_a) == pte_val(pte_b); | |
550 | } | |
551 | #endif | |
552 | ||
45961722 KW |
553 | #ifndef __HAVE_ARCH_PTE_UNUSED |
554 | /* | |
555 | * Some architectures provide facilities to virtualization guests | |
556 | * so that they can flag allocated pages as unused. This allows the | |
557 | * host to transparently reclaim unused pages. This function returns | |
558 | * whether the pte's page is unused. | |
559 | */ | |
560 | static inline int pte_unused(pte_t pte) | |
561 | { | |
562 | return 0; | |
563 | } | |
564 | #endif | |
565 | ||
e7884f8e KS |
566 | #ifndef pte_access_permitted |
567 | #define pte_access_permitted(pte, write) \ | |
568 | (pte_present(pte) && (!(write) || pte_write(pte))) | |
569 | #endif | |
570 | ||
571 | #ifndef pmd_access_permitted | |
572 | #define pmd_access_permitted(pmd, write) \ | |
573 | (pmd_present(pmd) && (!(write) || pmd_write(pmd))) | |
574 | #endif | |
575 | ||
576 | #ifndef pud_access_permitted | |
577 | #define pud_access_permitted(pud, write) \ | |
578 | (pud_present(pud) && (!(write) || pud_write(pud))) | |
579 | #endif | |
580 | ||
581 | #ifndef p4d_access_permitted | |
582 | #define p4d_access_permitted(p4d, write) \ | |
583 | (p4d_present(p4d) && (!(write) || p4d_write(p4d))) | |
584 | #endif | |
585 | ||
586 | #ifndef pgd_access_permitted | |
587 | #define pgd_access_permitted(pgd, write) \ | |
588 | (pgd_present(pgd) && (!(write) || pgd_write(pgd))) | |
589 | #endif | |
590 | ||
e2cda322 | 591 | #ifndef __HAVE_ARCH_PMD_SAME |
e2cda322 AA |
592 | static inline int pmd_same(pmd_t pmd_a, pmd_t pmd_b) |
593 | { | |
594 | return pmd_val(pmd_a) == pmd_val(pmd_b); | |
595 | } | |
a00cc7d9 MW |
596 | |
597 | static inline int pud_same(pud_t pud_a, pud_t pud_b) | |
598 | { | |
599 | return pud_val(pud_a) == pud_val(pud_b); | |
600 | } | |
1da177e4 LT |
601 | #endif |
602 | ||
0cebbb60 DW |
603 | #ifndef __HAVE_ARCH_P4D_SAME |
604 | static inline int p4d_same(p4d_t p4d_a, p4d_t p4d_b) | |
605 | { | |
606 | return p4d_val(p4d_a) == p4d_val(p4d_b); | |
607 | } | |
608 | #endif | |
609 | ||
610 | #ifndef __HAVE_ARCH_PGD_SAME | |
611 | static inline int pgd_same(pgd_t pgd_a, pgd_t pgd_b) | |
612 | { | |
613 | return pgd_val(pgd_a) == pgd_val(pgd_b); | |
614 | } | |
615 | #endif | |
616 | ||
4369deaa DW |
617 | /* |
618 | * Use set_p*_safe(), and elide TLB flushing, when confident that *no* | |
619 | * TLB flush will be required as a result of the "set". For example, use | |
620 | * in scenarios where it is known ahead of time that the routine is | |
621 | * setting non-present entries, or re-setting an existing entry to the | |
622 | * same value. Otherwise, use the typical "set" helpers and flush the | |
623 | * TLB. | |
624 | */ | |
625 | #define set_pte_safe(ptep, pte) \ | |
626 | ({ \ | |
627 | WARN_ON_ONCE(pte_present(*ptep) && !pte_same(*ptep, pte)); \ | |
628 | set_pte(ptep, pte); \ | |
629 | }) | |
630 | ||
631 | #define set_pmd_safe(pmdp, pmd) \ | |
632 | ({ \ | |
633 | WARN_ON_ONCE(pmd_present(*pmdp) && !pmd_same(*pmdp, pmd)); \ | |
634 | set_pmd(pmdp, pmd); \ | |
635 | }) | |
636 | ||
637 | #define set_pud_safe(pudp, pud) \ | |
638 | ({ \ | |
639 | WARN_ON_ONCE(pud_present(*pudp) && !pud_same(*pudp, pud)); \ | |
640 | set_pud(pudp, pud); \ | |
641 | }) | |
642 | ||
643 | #define set_p4d_safe(p4dp, p4d) \ | |
644 | ({ \ | |
645 | WARN_ON_ONCE(p4d_present(*p4dp) && !p4d_same(*p4dp, p4d)); \ | |
646 | set_p4d(p4dp, p4d); \ | |
647 | }) | |
648 | ||
649 | #define set_pgd_safe(pgdp, pgd) \ | |
650 | ({ \ | |
651 | WARN_ON_ONCE(pgd_present(*pgdp) && !pgd_same(*pgdp, pgd)); \ | |
652 | set_pgd(pgdp, pgd); \ | |
653 | }) | |
654 | ||
ca827d55 KA |
655 | #ifndef __HAVE_ARCH_DO_SWAP_PAGE |
656 | /* | |
657 | * Some architectures support metadata associated with a page. When a | |
658 | * page is being swapped out, this metadata must be saved so it can be | |
659 | * restored when the page is swapped back in. SPARC M7 and newer | |
660 | * processors support an ADI (Application Data Integrity) tag for the | |
661 | * page as metadata for the page. arch_do_swap_page() can restore this | |
662 | * metadata when a page is swapped back in. | |
663 | */ | |
664 | static inline void arch_do_swap_page(struct mm_struct *mm, | |
665 | struct vm_area_struct *vma, | |
666 | unsigned long addr, | |
667 | pte_t pte, pte_t oldpte) | |
668 | { | |
669 | ||
670 | } | |
671 | #endif | |
672 | ||
673 | #ifndef __HAVE_ARCH_UNMAP_ONE | |
674 | /* | |
675 | * Some architectures support metadata associated with a page. When a | |
676 | * page is being swapped out, this metadata must be saved so it can be | |
677 | * restored when the page is swapped back in. SPARC M7 and newer | |
678 | * processors support an ADI (Application Data Integrity) tag for the | |
679 | * page as metadata for the page. arch_unmap_one() can save this | |
680 | * metadata on a swap-out of a page. | |
681 | */ | |
682 | static inline int arch_unmap_one(struct mm_struct *mm, | |
683 | struct vm_area_struct *vma, | |
684 | unsigned long addr, | |
685 | pte_t orig_pte) | |
686 | { | |
687 | return 0; | |
688 | } | |
689 | #endif | |
690 | ||
8a84802e SP |
691 | /* |
692 | * Allow architectures to preserve additional metadata associated with | |
693 | * swapped-out pages. The corresponding __HAVE_ARCH_SWAP_* macros and function | |
694 | * prototypes must be defined in the arch-specific asm/pgtable.h file. | |
695 | */ | |
696 | #ifndef __HAVE_ARCH_PREPARE_TO_SWAP | |
697 | static inline int arch_prepare_to_swap(struct page *page) | |
698 | { | |
699 | return 0; | |
700 | } | |
701 | #endif | |
702 | ||
703 | #ifndef __HAVE_ARCH_SWAP_INVALIDATE | |
704 | static inline void arch_swap_invalidate_page(int type, pgoff_t offset) | |
705 | { | |
706 | } | |
707 | ||
708 | static inline void arch_swap_invalidate_area(int type) | |
709 | { | |
710 | } | |
711 | #endif | |
712 | ||
713 | #ifndef __HAVE_ARCH_SWAP_RESTORE | |
714 | static inline void arch_swap_restore(swp_entry_t entry, struct page *page) | |
715 | { | |
716 | } | |
717 | #endif | |
718 | ||
1da177e4 LT |
719 | #ifndef __HAVE_ARCH_PGD_OFFSET_GATE |
720 | #define pgd_offset_gate(mm, addr) pgd_offset(mm, addr) | |
721 | #endif | |
722 | ||
0b0968a3 | 723 | #ifndef __HAVE_ARCH_MOVE_PTE |
8b1f3124 | 724 | #define move_pte(pte, prot, old_addr, new_addr) (pte) |
8b1f3124 NP |
725 | #endif |
726 | ||
2c3cf556 | 727 | #ifndef pte_accessible |
20841405 | 728 | # define pte_accessible(mm, pte) ((void)(pte), 1) |
2c3cf556 RR |
729 | #endif |
730 | ||
61c77326 SL |
731 | #ifndef flush_tlb_fix_spurious_fault |
732 | #define flush_tlb_fix_spurious_fault(vma, address) flush_tlb_page(vma, address) | |
733 | #endif | |
734 | ||
1da177e4 | 735 | /* |
8f6c99c1 HD |
736 | * When walking page tables, get the address of the next boundary, |
737 | * or the end address of the range if that comes earlier. Although no | |
738 | * vma end wraps to 0, rounded up __boundary may wrap to 0 throughout. | |
1da177e4 LT |
739 | */ |
740 | ||
1da177e4 LT |
741 | #define pgd_addr_end(addr, end) \ |
742 | ({ unsigned long __boundary = ((addr) + PGDIR_SIZE) & PGDIR_MASK; \ | |
743 | (__boundary - 1 < (end) - 1)? __boundary: (end); \ | |
744 | }) | |
1da177e4 | 745 | |
c2febafc KS |
746 | #ifndef p4d_addr_end |
747 | #define p4d_addr_end(addr, end) \ | |
748 | ({ unsigned long __boundary = ((addr) + P4D_SIZE) & P4D_MASK; \ | |
749 | (__boundary - 1 < (end) - 1)? __boundary: (end); \ | |
750 | }) | |
751 | #endif | |
752 | ||
1da177e4 LT |
753 | #ifndef pud_addr_end |
754 | #define pud_addr_end(addr, end) \ | |
755 | ({ unsigned long __boundary = ((addr) + PUD_SIZE) & PUD_MASK; \ | |
756 | (__boundary - 1 < (end) - 1)? __boundary: (end); \ | |
757 | }) | |
758 | #endif | |
759 | ||
760 | #ifndef pmd_addr_end | |
761 | #define pmd_addr_end(addr, end) \ | |
762 | ({ unsigned long __boundary = ((addr) + PMD_SIZE) & PMD_MASK; \ | |
763 | (__boundary - 1 < (end) - 1)? __boundary: (end); \ | |
764 | }) | |
765 | #endif | |
766 | ||
1da177e4 LT |
767 | /* |
768 | * When walking page tables, we usually want to skip any p?d_none entries; | |
769 | * and any p?d_bad entries - reporting the error before resetting to none. | |
770 | * Do the tests inline, but report and clear the bad entry in mm/memory.c. | |
771 | */ | |
772 | void pgd_clear_bad(pgd_t *); | |
f2400abc VG |
773 | |
774 | #ifndef __PAGETABLE_P4D_FOLDED | |
c2febafc | 775 | void p4d_clear_bad(p4d_t *); |
f2400abc VG |
776 | #else |
777 | #define p4d_clear_bad(p4d) do { } while (0) | |
778 | #endif | |
779 | ||
780 | #ifndef __PAGETABLE_PUD_FOLDED | |
1da177e4 | 781 | void pud_clear_bad(pud_t *); |
f2400abc VG |
782 | #else |
783 | #define pud_clear_bad(p4d) do { } while (0) | |
784 | #endif | |
785 | ||
1da177e4 LT |
786 | void pmd_clear_bad(pmd_t *); |
787 | ||
788 | static inline int pgd_none_or_clear_bad(pgd_t *pgd) | |
789 | { | |
790 | if (pgd_none(*pgd)) | |
791 | return 1; | |
792 | if (unlikely(pgd_bad(*pgd))) { | |
793 | pgd_clear_bad(pgd); | |
794 | return 1; | |
795 | } | |
796 | return 0; | |
797 | } | |
798 | ||
c2febafc KS |
799 | static inline int p4d_none_or_clear_bad(p4d_t *p4d) |
800 | { | |
801 | if (p4d_none(*p4d)) | |
802 | return 1; | |
803 | if (unlikely(p4d_bad(*p4d))) { | |
804 | p4d_clear_bad(p4d); | |
805 | return 1; | |
806 | } | |
807 | return 0; | |
808 | } | |
809 | ||
1da177e4 LT |
810 | static inline int pud_none_or_clear_bad(pud_t *pud) |
811 | { | |
812 | if (pud_none(*pud)) | |
813 | return 1; | |
814 | if (unlikely(pud_bad(*pud))) { | |
815 | pud_clear_bad(pud); | |
816 | return 1; | |
817 | } | |
818 | return 0; | |
819 | } | |
820 | ||
821 | static inline int pmd_none_or_clear_bad(pmd_t *pmd) | |
822 | { | |
823 | if (pmd_none(*pmd)) | |
824 | return 1; | |
825 | if (unlikely(pmd_bad(*pmd))) { | |
826 | pmd_clear_bad(pmd); | |
827 | return 1; | |
828 | } | |
829 | return 0; | |
830 | } | |
9535239f | 831 | |
0cbe3e26 | 832 | static inline pte_t __ptep_modify_prot_start(struct vm_area_struct *vma, |
1ea0704e JF |
833 | unsigned long addr, |
834 | pte_t *ptep) | |
835 | { | |
836 | /* | |
837 | * Get the current pte state, but zero it out to make it | |
838 | * non-present, preventing the hardware from asynchronously | |
839 | * updating it. | |
840 | */ | |
0cbe3e26 | 841 | return ptep_get_and_clear(vma->vm_mm, addr, ptep); |
1ea0704e JF |
842 | } |
843 | ||
0cbe3e26 | 844 | static inline void __ptep_modify_prot_commit(struct vm_area_struct *vma, |
1ea0704e JF |
845 | unsigned long addr, |
846 | pte_t *ptep, pte_t pte) | |
847 | { | |
848 | /* | |
849 | * The pte is non-present, so there's no hardware state to | |
850 | * preserve. | |
851 | */ | |
0cbe3e26 | 852 | set_pte_at(vma->vm_mm, addr, ptep, pte); |
1ea0704e JF |
853 | } |
854 | ||
855 | #ifndef __HAVE_ARCH_PTEP_MODIFY_PROT_TRANSACTION | |
856 | /* | |
857 | * Start a pte protection read-modify-write transaction, which | |
858 | * protects against asynchronous hardware modifications to the pte. | |
859 | * The intention is not to prevent the hardware from making pte | |
860 | * updates, but to prevent any updates it may make from being lost. | |
861 | * | |
862 | * This does not protect against other software modifications of the | |
863 | * pte; the appropriate pte lock must be held over the transation. | |
864 | * | |
865 | * Note that this interface is intended to be batchable, meaning that | |
866 | * ptep_modify_prot_commit may not actually update the pte, but merely | |
867 | * queue the update to be done at some later time. The update must be | |
868 | * actually committed before the pte lock is released, however. | |
869 | */ | |
0cbe3e26 | 870 | static inline pte_t ptep_modify_prot_start(struct vm_area_struct *vma, |
1ea0704e JF |
871 | unsigned long addr, |
872 | pte_t *ptep) | |
873 | { | |
0cbe3e26 | 874 | return __ptep_modify_prot_start(vma, addr, ptep); |
1ea0704e JF |
875 | } |
876 | ||
877 | /* | |
878 | * Commit an update to a pte, leaving any hardware-controlled bits in | |
879 | * the PTE unmodified. | |
880 | */ | |
0cbe3e26 | 881 | static inline void ptep_modify_prot_commit(struct vm_area_struct *vma, |
1ea0704e | 882 | unsigned long addr, |
04a86453 | 883 | pte_t *ptep, pte_t old_pte, pte_t pte) |
1ea0704e | 884 | { |
0cbe3e26 | 885 | __ptep_modify_prot_commit(vma, addr, ptep, pte); |
1ea0704e JF |
886 | } |
887 | #endif /* __HAVE_ARCH_PTEP_MODIFY_PROT_TRANSACTION */ | |
fe1a6875 | 888 | #endif /* CONFIG_MMU */ |
1ea0704e | 889 | |
21729f81 TL |
890 | /* |
891 | * No-op macros that just return the current protection value. Defined here | |
1067b261 | 892 | * because these macros can be used even if CONFIG_MMU is not defined. |
21729f81 | 893 | */ |
63bb76de PE |
894 | |
895 | #ifndef pgprot_nx | |
896 | #define pgprot_nx(prot) (prot) | |
897 | #endif | |
898 | ||
899 | #ifndef pgprot_noncached | |
900 | #define pgprot_noncached(prot) (prot) | |
901 | #endif | |
902 | ||
903 | #ifndef pgprot_writecombine | |
904 | #define pgprot_writecombine pgprot_noncached | |
905 | #endif | |
906 | ||
907 | #ifndef pgprot_writethrough | |
908 | #define pgprot_writethrough pgprot_noncached | |
909 | #endif | |
910 | ||
911 | #ifndef pgprot_device | |
912 | #define pgprot_device pgprot_noncached | |
913 | #endif | |
914 | ||
302cba40 CM |
915 | #ifndef pgprot_mhp |
916 | #define pgprot_mhp(prot) (prot) | |
917 | #endif | |
918 | ||
63bb76de PE |
919 | #ifdef CONFIG_MMU |
920 | #ifndef pgprot_modify | |
921 | #define pgprot_modify pgprot_modify | |
922 | static inline pgprot_t pgprot_modify(pgprot_t oldprot, pgprot_t newprot) | |
923 | { | |
924 | if (pgprot_val(oldprot) == pgprot_val(pgprot_noncached(oldprot))) | |
925 | newprot = pgprot_noncached(newprot); | |
926 | if (pgprot_val(oldprot) == pgprot_val(pgprot_writecombine(oldprot))) | |
927 | newprot = pgprot_writecombine(newprot); | |
928 | if (pgprot_val(oldprot) == pgprot_val(pgprot_device(oldprot))) | |
929 | newprot = pgprot_device(newprot); | |
930 | return newprot; | |
931 | } | |
932 | #endif | |
933 | #endif /* CONFIG_MMU */ | |
934 | ||
21729f81 TL |
935 | #ifndef pgprot_encrypted |
936 | #define pgprot_encrypted(prot) (prot) | |
937 | #endif | |
938 | ||
939 | #ifndef pgprot_decrypted | |
940 | #define pgprot_decrypted(prot) (prot) | |
941 | #endif | |
942 | ||
9535239f GU |
943 | /* |
944 | * A facility to provide lazy MMU batching. This allows PTE updates and | |
945 | * page invalidations to be delayed until a call to leave lazy MMU mode | |
946 | * is issued. Some architectures may benefit from doing this, and it is | |
947 | * beneficial for both shadow and direct mode hypervisors, which may batch | |
948 | * the PTE updates which happen during this window. Note that using this | |
949 | * interface requires that read hazards be removed from the code. A read | |
950 | * hazard could result in the direct mode hypervisor case, since the actual | |
951 | * write to the page tables may not yet have taken place, so reads though | |
952 | * a raw PTE pointer after it has been modified are not guaranteed to be | |
953 | * up to date. This mode can only be entered and left under the protection of | |
954 | * the page table locks for all page tables which may be modified. In the UP | |
955 | * case, this is required so that preemption is disabled, and in the SMP case, | |
956 | * it must synchronize the delayed page table writes properly on other CPUs. | |
957 | */ | |
958 | #ifndef __HAVE_ARCH_ENTER_LAZY_MMU_MODE | |
959 | #define arch_enter_lazy_mmu_mode() do {} while (0) | |
960 | #define arch_leave_lazy_mmu_mode() do {} while (0) | |
961 | #define arch_flush_lazy_mmu_mode() do {} while (0) | |
962 | #endif | |
963 | ||
964 | /* | |
7fd7d83d JF |
965 | * A facility to provide batching of the reload of page tables and |
966 | * other process state with the actual context switch code for | |
967 | * paravirtualized guests. By convention, only one of the batched | |
968 | * update (lazy) modes (CPU, MMU) should be active at any given time, | |
969 | * entry should never be nested, and entry and exits should always be | |
970 | * paired. This is for sanity of maintaining and reasoning about the | |
971 | * kernel code. In this case, the exit (end of the context switch) is | |
972 | * in architecture-specific code, and so doesn't need a generic | |
973 | * definition. | |
9535239f | 974 | */ |
7fd7d83d | 975 | #ifndef __HAVE_ARCH_START_CONTEXT_SWITCH |
224101ed | 976 | #define arch_start_context_switch(prev) do {} while (0) |
9535239f GU |
977 | #endif |
978 | ||
ab6e3d09 NH |
979 | #ifdef CONFIG_HAVE_ARCH_SOFT_DIRTY |
980 | #ifndef CONFIG_ARCH_ENABLE_THP_MIGRATION | |
981 | static inline pmd_t pmd_swp_mksoft_dirty(pmd_t pmd) | |
982 | { | |
983 | return pmd; | |
984 | } | |
985 | ||
986 | static inline int pmd_swp_soft_dirty(pmd_t pmd) | |
987 | { | |
988 | return 0; | |
989 | } | |
990 | ||
991 | static inline pmd_t pmd_swp_clear_soft_dirty(pmd_t pmd) | |
992 | { | |
993 | return pmd; | |
994 | } | |
995 | #endif | |
996 | #else /* !CONFIG_HAVE_ARCH_SOFT_DIRTY */ | |
0f8975ec PE |
997 | static inline int pte_soft_dirty(pte_t pte) |
998 | { | |
999 | return 0; | |
1000 | } | |
1001 | ||
1002 | static inline int pmd_soft_dirty(pmd_t pmd) | |
1003 | { | |
1004 | return 0; | |
1005 | } | |
1006 | ||
1007 | static inline pte_t pte_mksoft_dirty(pte_t pte) | |
1008 | { | |
1009 | return pte; | |
1010 | } | |
1011 | ||
1012 | static inline pmd_t pmd_mksoft_dirty(pmd_t pmd) | |
1013 | { | |
1014 | return pmd; | |
1015 | } | |
179ef71c | 1016 | |
a7b76174 MS |
1017 | static inline pte_t pte_clear_soft_dirty(pte_t pte) |
1018 | { | |
1019 | return pte; | |
1020 | } | |
1021 | ||
1022 | static inline pmd_t pmd_clear_soft_dirty(pmd_t pmd) | |
1023 | { | |
1024 | return pmd; | |
1025 | } | |
1026 | ||
179ef71c CG |
1027 | static inline pte_t pte_swp_mksoft_dirty(pte_t pte) |
1028 | { | |
1029 | return pte; | |
1030 | } | |
1031 | ||
1032 | static inline int pte_swp_soft_dirty(pte_t pte) | |
1033 | { | |
1034 | return 0; | |
1035 | } | |
1036 | ||
1037 | static inline pte_t pte_swp_clear_soft_dirty(pte_t pte) | |
1038 | { | |
1039 | return pte; | |
1040 | } | |
ab6e3d09 NH |
1041 | |
1042 | static inline pmd_t pmd_swp_mksoft_dirty(pmd_t pmd) | |
1043 | { | |
1044 | return pmd; | |
1045 | } | |
1046 | ||
1047 | static inline int pmd_swp_soft_dirty(pmd_t pmd) | |
1048 | { | |
1049 | return 0; | |
1050 | } | |
1051 | ||
1052 | static inline pmd_t pmd_swp_clear_soft_dirty(pmd_t pmd) | |
1053 | { | |
1054 | return pmd; | |
1055 | } | |
0f8975ec PE |
1056 | #endif |
1057 | ||
34801ba9 | 1058 | #ifndef __HAVE_PFNMAP_TRACKING |
1059 | /* | |
5180da41 SS |
1060 | * Interfaces that can be used by architecture code to keep track of |
1061 | * memory type of pfn mappings specified by the remap_pfn_range, | |
67fa1666 | 1062 | * vmf_insert_pfn. |
5180da41 SS |
1063 | */ |
1064 | ||
1065 | /* | |
1066 | * track_pfn_remap is called when a _new_ pfn mapping is being established | |
1067 | * by remap_pfn_range() for physical range indicated by pfn and size. | |
34801ba9 | 1068 | */ |
5180da41 | 1069 | static inline int track_pfn_remap(struct vm_area_struct *vma, pgprot_t *prot, |
b3b9c293 KK |
1070 | unsigned long pfn, unsigned long addr, |
1071 | unsigned long size) | |
34801ba9 | 1072 | { |
1073 | return 0; | |
1074 | } | |
1075 | ||
1076 | /* | |
5180da41 | 1077 | * track_pfn_insert is called when a _new_ single pfn is established |
67fa1666 | 1078 | * by vmf_insert_pfn(). |
5180da41 | 1079 | */ |
308a047c BP |
1080 | static inline void track_pfn_insert(struct vm_area_struct *vma, pgprot_t *prot, |
1081 | pfn_t pfn) | |
5180da41 | 1082 | { |
5180da41 SS |
1083 | } |
1084 | ||
1085 | /* | |
1086 | * track_pfn_copy is called when vma that is covering the pfnmap gets | |
34801ba9 | 1087 | * copied through copy_page_range(). |
1088 | */ | |
5180da41 | 1089 | static inline int track_pfn_copy(struct vm_area_struct *vma) |
34801ba9 | 1090 | { |
1091 | return 0; | |
1092 | } | |
1093 | ||
1094 | /* | |
d9fe4fab | 1095 | * untrack_pfn is called while unmapping a pfnmap for a region. |
34801ba9 | 1096 | * untrack can be called for a specific region indicated by pfn and size or |
5180da41 | 1097 | * can be for the entire vma (in which case pfn, size are zero). |
34801ba9 | 1098 | */ |
5180da41 SS |
1099 | static inline void untrack_pfn(struct vm_area_struct *vma, |
1100 | unsigned long pfn, unsigned long size) | |
34801ba9 | 1101 | { |
1102 | } | |
d9fe4fab TK |
1103 | |
1104 | /* | |
1105 | * untrack_pfn_moved is called while mremapping a pfnmap for a new region. | |
1106 | */ | |
1107 | static inline void untrack_pfn_moved(struct vm_area_struct *vma) | |
1108 | { | |
1109 | } | |
34801ba9 | 1110 | #else |
5180da41 | 1111 | extern int track_pfn_remap(struct vm_area_struct *vma, pgprot_t *prot, |
b3b9c293 KK |
1112 | unsigned long pfn, unsigned long addr, |
1113 | unsigned long size); | |
308a047c BP |
1114 | extern void track_pfn_insert(struct vm_area_struct *vma, pgprot_t *prot, |
1115 | pfn_t pfn); | |
5180da41 SS |
1116 | extern int track_pfn_copy(struct vm_area_struct *vma); |
1117 | extern void untrack_pfn(struct vm_area_struct *vma, unsigned long pfn, | |
1118 | unsigned long size); | |
d9fe4fab | 1119 | extern void untrack_pfn_moved(struct vm_area_struct *vma); |
34801ba9 | 1120 | #endif |
1121 | ||
816422ad KS |
1122 | #ifdef __HAVE_COLOR_ZERO_PAGE |
1123 | static inline int is_zero_pfn(unsigned long pfn) | |
1124 | { | |
1125 | extern unsigned long zero_pfn; | |
1126 | unsigned long offset_from_zero_pfn = pfn - zero_pfn; | |
1127 | return offset_from_zero_pfn <= (zero_page_mask >> PAGE_SHIFT); | |
1128 | } | |
1129 | ||
2f91ec8c KS |
1130 | #define my_zero_pfn(addr) page_to_pfn(ZERO_PAGE(addr)) |
1131 | ||
816422ad KS |
1132 | #else |
1133 | static inline int is_zero_pfn(unsigned long pfn) | |
1134 | { | |
1135 | extern unsigned long zero_pfn; | |
1136 | return pfn == zero_pfn; | |
1137 | } | |
1138 | ||
1139 | static inline unsigned long my_zero_pfn(unsigned long addr) | |
1140 | { | |
1141 | extern unsigned long zero_pfn; | |
1142 | return zero_pfn; | |
1143 | } | |
1144 | #endif | |
1145 | ||
1a5a9906 AA |
1146 | #ifdef CONFIG_MMU |
1147 | ||
5f6e8da7 AA |
1148 | #ifndef CONFIG_TRANSPARENT_HUGEPAGE |
1149 | static inline int pmd_trans_huge(pmd_t pmd) | |
1150 | { | |
1151 | return 0; | |
1152 | } | |
e4e40e02 | 1153 | #ifndef pmd_write |
e2cda322 AA |
1154 | static inline int pmd_write(pmd_t pmd) |
1155 | { | |
1156 | BUG(); | |
1157 | return 0; | |
1158 | } | |
e4e40e02 | 1159 | #endif /* pmd_write */ |
1a5a9906 AA |
1160 | #endif /* CONFIG_TRANSPARENT_HUGEPAGE */ |
1161 | ||
1501899a DW |
1162 | #ifndef pud_write |
1163 | static inline int pud_write(pud_t pud) | |
1164 | { | |
1165 | BUG(); | |
1166 | return 0; | |
1167 | } | |
1168 | #endif /* pud_write */ | |
1169 | ||
bf1a12a8 TH |
1170 | #if !defined(CONFIG_ARCH_HAS_PTE_DEVMAP) || !defined(CONFIG_TRANSPARENT_HUGEPAGE) |
1171 | static inline int pmd_devmap(pmd_t pmd) | |
1172 | { | |
1173 | return 0; | |
1174 | } | |
1175 | static inline int pud_devmap(pud_t pud) | |
1176 | { | |
1177 | return 0; | |
1178 | } | |
1179 | static inline int pgd_devmap(pgd_t pgd) | |
1180 | { | |
1181 | return 0; | |
1182 | } | |
1183 | #endif | |
1184 | ||
a00cc7d9 MW |
1185 | #if !defined(CONFIG_TRANSPARENT_HUGEPAGE) || \ |
1186 | (defined(CONFIG_TRANSPARENT_HUGEPAGE) && \ | |
1187 | !defined(CONFIG_HAVE_ARCH_TRANSPARENT_HUGEPAGE_PUD)) | |
1188 | static inline int pud_trans_huge(pud_t pud) | |
1189 | { | |
1190 | return 0; | |
1191 | } | |
1192 | #endif | |
1193 | ||
625110b5 TH |
1194 | /* See pmd_none_or_trans_huge_or_clear_bad for discussion. */ |
1195 | static inline int pud_none_or_trans_huge_or_dev_or_clear_bad(pud_t *pud) | |
1196 | { | |
1197 | pud_t pudval = READ_ONCE(*pud); | |
1198 | ||
1199 | if (pud_none(pudval) || pud_trans_huge(pudval) || pud_devmap(pudval)) | |
1200 | return 1; | |
1201 | if (unlikely(pud_bad(pudval))) { | |
1202 | pud_clear_bad(pud); | |
1203 | return 1; | |
1204 | } | |
1205 | return 0; | |
1206 | } | |
1207 | ||
1208 | /* See pmd_trans_unstable for discussion. */ | |
1209 | static inline int pud_trans_unstable(pud_t *pud) | |
1210 | { | |
1211 | #if defined(CONFIG_TRANSPARENT_HUGEPAGE) && \ | |
1212 | defined(CONFIG_HAVE_ARCH_TRANSPARENT_HUGEPAGE_PUD) | |
1213 | return pud_none_or_trans_huge_or_dev_or_clear_bad(pud); | |
1214 | #else | |
1215 | return 0; | |
1216 | #endif | |
1217 | } | |
1218 | ||
26c19178 AA |
1219 | #ifndef pmd_read_atomic |
1220 | static inline pmd_t pmd_read_atomic(pmd_t *pmdp) | |
1221 | { | |
1222 | /* | |
1223 | * Depend on compiler for an atomic pmd read. NOTE: this is | |
1224 | * only going to work, if the pmdval_t isn't larger than | |
1225 | * an unsigned long. | |
1226 | */ | |
1227 | return *pmdp; | |
1228 | } | |
1229 | #endif | |
1230 | ||
953c66c2 AK |
1231 | #ifndef arch_needs_pgtable_deposit |
1232 | #define arch_needs_pgtable_deposit() (false) | |
1233 | #endif | |
1a5a9906 AA |
1234 | /* |
1235 | * This function is meant to be used by sites walking pagetables with | |
c1e8d7c6 | 1236 | * the mmap_lock held in read mode to protect against MADV_DONTNEED and |
1a5a9906 AA |
1237 | * transhuge page faults. MADV_DONTNEED can convert a transhuge pmd |
1238 | * into a null pmd and the transhuge page fault can convert a null pmd | |
1239 | * into an hugepmd or into a regular pmd (if the hugepage allocation | |
c1e8d7c6 | 1240 | * fails). While holding the mmap_lock in read mode the pmd becomes |
1a5a9906 AA |
1241 | * stable and stops changing under us only if it's not null and not a |
1242 | * transhuge pmd. When those races occurs and this function makes a | |
1243 | * difference vs the standard pmd_none_or_clear_bad, the result is | |
1244 | * undefined so behaving like if the pmd was none is safe (because it | |
1245 | * can return none anyway). The compiler level barrier() is critically | |
1246 | * important to compute the two checks atomically on the same pmdval. | |
26c19178 AA |
1247 | * |
1248 | * For 32bit kernels with a 64bit large pmd_t this automatically takes | |
1249 | * care of reading the pmd atomically to avoid SMP race conditions | |
c1e8d7c6 | 1250 | * against pmd_populate() when the mmap_lock is hold for reading by the |
26c19178 AA |
1251 | * caller (a special atomic read not done by "gcc" as in the generic |
1252 | * version above, is also needed when THP is disabled because the page | |
1253 | * fault can populate the pmd from under us). | |
1a5a9906 AA |
1254 | */ |
1255 | static inline int pmd_none_or_trans_huge_or_clear_bad(pmd_t *pmd) | |
1256 | { | |
26c19178 | 1257 | pmd_t pmdval = pmd_read_atomic(pmd); |
1a5a9906 AA |
1258 | /* |
1259 | * The barrier will stabilize the pmdval in a register or on | |
1260 | * the stack so that it will stop changing under the code. | |
e4eed03f AA |
1261 | * |
1262 | * When CONFIG_TRANSPARENT_HUGEPAGE=y on x86 32bit PAE, | |
1263 | * pmd_read_atomic is allowed to return a not atomic pmdval | |
1264 | * (for example pointing to an hugepage that has never been | |
1265 | * mapped in the pmd). The below checks will only care about | |
1266 | * the low part of the pmd with 32bit PAE x86 anyway, with the | |
1267 | * exception of pmd_none(). So the important thing is that if | |
1268 | * the low part of the pmd is found null, the high part will | |
1269 | * be also null or the pmd_none() check below would be | |
1270 | * confused. | |
1a5a9906 AA |
1271 | */ |
1272 | #ifdef CONFIG_TRANSPARENT_HUGEPAGE | |
1273 | barrier(); | |
1274 | #endif | |
84c3fc4e ZY |
1275 | /* |
1276 | * !pmd_present() checks for pmd migration entries | |
1277 | * | |
1278 | * The complete check uses is_pmd_migration_entry() in linux/swapops.h | |
1279 | * But using that requires moving current function and pmd_trans_unstable() | |
1280 | * to linux/swapops.h to resovle dependency, which is too much code move. | |
1281 | * | |
1282 | * !pmd_present() is equivalent to is_pmd_migration_entry() currently, | |
1283 | * because !pmd_present() pages can only be under migration not swapped | |
1284 | * out. | |
1285 | * | |
1286 | * pmd_none() is preseved for future condition checks on pmd migration | |
1287 | * entries and not confusing with this function name, although it is | |
1288 | * redundant with !pmd_present(). | |
1289 | */ | |
1290 | if (pmd_none(pmdval) || pmd_trans_huge(pmdval) || | |
1291 | (IS_ENABLED(CONFIG_ARCH_ENABLE_THP_MIGRATION) && !pmd_present(pmdval))) | |
1a5a9906 AA |
1292 | return 1; |
1293 | if (unlikely(pmd_bad(pmdval))) { | |
ee53664b | 1294 | pmd_clear_bad(pmd); |
1a5a9906 AA |
1295 | return 1; |
1296 | } | |
1297 | return 0; | |
1298 | } | |
1299 | ||
1300 | /* | |
1301 | * This is a noop if Transparent Hugepage Support is not built into | |
1302 | * the kernel. Otherwise it is equivalent to | |
1303 | * pmd_none_or_trans_huge_or_clear_bad(), and shall only be called in | |
1304 | * places that already verified the pmd is not none and they want to | |
1305 | * walk ptes while holding the mmap sem in read mode (write mode don't | |
1306 | * need this). If THP is not enabled, the pmd can't go away under the | |
1307 | * code even if MADV_DONTNEED runs, but if THP is enabled we need to | |
1308 | * run a pmd_trans_unstable before walking the ptes after | |
9ef258ba KW |
1309 | * split_huge_pmd returns (because it may have run when the pmd become |
1310 | * null, but then a page fault can map in a THP and not a regular page). | |
1a5a9906 AA |
1311 | */ |
1312 | static inline int pmd_trans_unstable(pmd_t *pmd) | |
1313 | { | |
1314 | #ifdef CONFIG_TRANSPARENT_HUGEPAGE | |
1315 | return pmd_none_or_trans_huge_or_clear_bad(pmd); | |
1316 | #else | |
1317 | return 0; | |
5f6e8da7 | 1318 | #endif |
1a5a9906 AA |
1319 | } |
1320 | ||
e7bb4b6d MG |
1321 | #ifndef CONFIG_NUMA_BALANCING |
1322 | /* | |
1323 | * Technically a PTE can be PROTNONE even when not doing NUMA balancing but | |
1324 | * the only case the kernel cares is for NUMA balancing and is only ever set | |
1325 | * when the VMA is accessible. For PROT_NONE VMAs, the PTEs are not marked | |
1067b261 | 1326 | * _PAGE_PROTNONE so by default, implement the helper as "always no". It |
e7bb4b6d MG |
1327 | * is the responsibility of the caller to distinguish between PROT_NONE |
1328 | * protections and NUMA hinting fault protections. | |
1329 | */ | |
1330 | static inline int pte_protnone(pte_t pte) | |
1331 | { | |
1332 | return 0; | |
1333 | } | |
1334 | ||
1335 | static inline int pmd_protnone(pmd_t pmd) | |
1336 | { | |
1337 | return 0; | |
1338 | } | |
1339 | #endif /* CONFIG_NUMA_BALANCING */ | |
1340 | ||
1a5a9906 | 1341 | #endif /* CONFIG_MMU */ |
5f6e8da7 | 1342 | |
e61ce6ad | 1343 | #ifdef CONFIG_HAVE_ARCH_HUGE_VMAP |
c2febafc KS |
1344 | |
1345 | #ifndef __PAGETABLE_P4D_FOLDED | |
1346 | int p4d_set_huge(p4d_t *p4d, phys_addr_t addr, pgprot_t prot); | |
1347 | int p4d_clear_huge(p4d_t *p4d); | |
1348 | #else | |
1349 | static inline int p4d_set_huge(p4d_t *p4d, phys_addr_t addr, pgprot_t prot) | |
1350 | { | |
1351 | return 0; | |
1352 | } | |
1353 | static inline int p4d_clear_huge(p4d_t *p4d) | |
1354 | { | |
1355 | return 0; | |
1356 | } | |
1357 | #endif /* !__PAGETABLE_P4D_FOLDED */ | |
1358 | ||
e61ce6ad TK |
1359 | int pud_set_huge(pud_t *pud, phys_addr_t addr, pgprot_t prot); |
1360 | int pmd_set_huge(pmd_t *pmd, phys_addr_t addr, pgprot_t prot); | |
b9820d8f TK |
1361 | int pud_clear_huge(pud_t *pud); |
1362 | int pmd_clear_huge(pmd_t *pmd); | |
8e2d4340 | 1363 | int p4d_free_pud_page(p4d_t *p4d, unsigned long addr); |
785a19f9 CP |
1364 | int pud_free_pmd_page(pud_t *pud, unsigned long addr); |
1365 | int pmd_free_pte_page(pmd_t *pmd, unsigned long addr); | |
e61ce6ad | 1366 | #else /* !CONFIG_HAVE_ARCH_HUGE_VMAP */ |
c2febafc KS |
1367 | static inline int p4d_set_huge(p4d_t *p4d, phys_addr_t addr, pgprot_t prot) |
1368 | { | |
1369 | return 0; | |
1370 | } | |
e61ce6ad TK |
1371 | static inline int pud_set_huge(pud_t *pud, phys_addr_t addr, pgprot_t prot) |
1372 | { | |
1373 | return 0; | |
1374 | } | |
1375 | static inline int pmd_set_huge(pmd_t *pmd, phys_addr_t addr, pgprot_t prot) | |
1376 | { | |
1377 | return 0; | |
1378 | } | |
c2febafc KS |
1379 | static inline int p4d_clear_huge(p4d_t *p4d) |
1380 | { | |
1381 | return 0; | |
1382 | } | |
b9820d8f TK |
1383 | static inline int pud_clear_huge(pud_t *pud) |
1384 | { | |
1385 | return 0; | |
1386 | } | |
1387 | static inline int pmd_clear_huge(pmd_t *pmd) | |
1388 | { | |
1389 | return 0; | |
1390 | } | |
8e2d4340 WD |
1391 | static inline int p4d_free_pud_page(p4d_t *p4d, unsigned long addr) |
1392 | { | |
1393 | return 0; | |
1394 | } | |
785a19f9 | 1395 | static inline int pud_free_pmd_page(pud_t *pud, unsigned long addr) |
b6bdb751 TK |
1396 | { |
1397 | return 0; | |
1398 | } | |
785a19f9 | 1399 | static inline int pmd_free_pte_page(pmd_t *pmd, unsigned long addr) |
b6bdb751 TK |
1400 | { |
1401 | return 0; | |
1402 | } | |
e61ce6ad TK |
1403 | #endif /* CONFIG_HAVE_ARCH_HUGE_VMAP */ |
1404 | ||
458aa76d AK |
1405 | #ifndef __HAVE_ARCH_FLUSH_PMD_TLB_RANGE |
1406 | #ifdef CONFIG_TRANSPARENT_HUGEPAGE | |
1407 | /* | |
1408 | * ARCHes with special requirements for evicting THP backing TLB entries can | |
1409 | * implement this. Otherwise also, it can help optimize normal TLB flush in | |
1067b261 RD |
1410 | * THP regime. Stock flush_tlb_range() typically has optimization to nuke the |
1411 | * entire TLB if flush span is greater than a threshold, which will | |
1412 | * likely be true for a single huge page. Thus a single THP flush will | |
1413 | * invalidate the entire TLB which is not desirable. | |
458aa76d AK |
1414 | * e.g. see arch/arc: flush_pmd_tlb_range |
1415 | */ | |
1416 | #define flush_pmd_tlb_range(vma, addr, end) flush_tlb_range(vma, addr, end) | |
a00cc7d9 | 1417 | #define flush_pud_tlb_range(vma, addr, end) flush_tlb_range(vma, addr, end) |
458aa76d AK |
1418 | #else |
1419 | #define flush_pmd_tlb_range(vma, addr, end) BUILD_BUG() | |
a00cc7d9 | 1420 | #define flush_pud_tlb_range(vma, addr, end) BUILD_BUG() |
458aa76d AK |
1421 | #endif |
1422 | #endif | |
1423 | ||
08ea8c07 BX |
1424 | struct file; |
1425 | int phys_mem_access_prot_allowed(struct file *file, unsigned long pfn, | |
1426 | unsigned long size, pgprot_t *vma_prot); | |
613e396b TG |
1427 | |
1428 | #ifndef CONFIG_X86_ESPFIX64 | |
1429 | static inline void init_espfix_bsp(void) { } | |
1430 | #endif | |
1431 | ||
782de70c | 1432 | extern void __init pgtable_cache_init(void); |
caa84136 | 1433 | |
6c26fcd2 JK |
1434 | #ifndef __HAVE_ARCH_PFN_MODIFY_ALLOWED |
1435 | static inline bool pfn_modify_allowed(unsigned long pfn, pgprot_t prot) | |
1436 | { | |
1437 | return true; | |
1438 | } | |
1439 | ||
1440 | static inline bool arch_has_pfn_modify_check(void) | |
1441 | { | |
1442 | return false; | |
1443 | } | |
1444 | #endif /* !_HAVE_ARCH_PFN_MODIFY_ALLOWED */ | |
1445 | ||
a3266bd4 LR |
1446 | /* |
1447 | * Architecture PAGE_KERNEL_* fallbacks | |
1448 | * | |
1449 | * Some architectures don't define certain PAGE_KERNEL_* flags. This is either | |
1450 | * because they really don't support them, or the port needs to be updated to | |
1451 | * reflect the required functionality. Below are a set of relatively safe | |
1452 | * fallbacks, as best effort, which we can count on in lieu of the architectures | |
1453 | * not defining them on their own yet. | |
1454 | */ | |
1455 | ||
1456 | #ifndef PAGE_KERNEL_RO | |
1457 | # define PAGE_KERNEL_RO PAGE_KERNEL | |
1458 | #endif | |
1459 | ||
1a9b4b3d LR |
1460 | #ifndef PAGE_KERNEL_EXEC |
1461 | # define PAGE_KERNEL_EXEC PAGE_KERNEL | |
1462 | #endif | |
1463 | ||
d8626138 JR |
1464 | /* |
1465 | * Page Table Modification bits for pgtbl_mod_mask. | |
1466 | * | |
1467 | * These are used by the p?d_alloc_track*() set of functions an in the generic | |
1468 | * vmalloc/ioremap code to track at which page-table levels entries have been | |
1469 | * modified. Based on that the code can better decide when vmalloc and ioremap | |
1470 | * mapping changes need to be synchronized to other page-tables in the system. | |
1471 | */ | |
1472 | #define __PGTBL_PGD_MODIFIED 0 | |
1473 | #define __PGTBL_P4D_MODIFIED 1 | |
1474 | #define __PGTBL_PUD_MODIFIED 2 | |
1475 | #define __PGTBL_PMD_MODIFIED 3 | |
1476 | #define __PGTBL_PTE_MODIFIED 4 | |
1477 | ||
1478 | #define PGTBL_PGD_MODIFIED BIT(__PGTBL_PGD_MODIFIED) | |
1479 | #define PGTBL_P4D_MODIFIED BIT(__PGTBL_P4D_MODIFIED) | |
1480 | #define PGTBL_PUD_MODIFIED BIT(__PGTBL_PUD_MODIFIED) | |
1481 | #define PGTBL_PMD_MODIFIED BIT(__PGTBL_PMD_MODIFIED) | |
1482 | #define PGTBL_PTE_MODIFIED BIT(__PGTBL_PTE_MODIFIED) | |
1483 | ||
1484 | /* Page-Table Modification Mask */ | |
1485 | typedef unsigned int pgtbl_mod_mask; | |
1486 | ||
1da177e4 LT |
1487 | #endif /* !__ASSEMBLY__ */ |
1488 | ||
cef39703 AB |
1489 | #if !defined(MAX_POSSIBLE_PHYSMEM_BITS) && !defined(CONFIG_64BIT) |
1490 | #ifdef CONFIG_PHYS_ADDR_T_64BIT | |
1491 | /* | |
1492 | * ZSMALLOC needs to know the highest PFN on 32-bit architectures | |
1493 | * with physical address space extension, but falls back to | |
1494 | * BITS_PER_LONG otherwise. | |
1495 | */ | |
1496 | #error Missing MAX_POSSIBLE_PHYSMEM_BITS definition | |
1497 | #else | |
1498 | #define MAX_POSSIBLE_PHYSMEM_BITS 32 | |
1499 | #endif | |
1500 | #endif | |
1501 | ||
fd8cfd30 HD |
1502 | #ifndef has_transparent_hugepage |
1503 | #ifdef CONFIG_TRANSPARENT_HUGEPAGE | |
1504 | #define has_transparent_hugepage() 1 | |
1505 | #else | |
1506 | #define has_transparent_hugepage() 0 | |
1507 | #endif | |
1508 | #endif | |
1509 | ||
1071fc57 MS |
1510 | /* |
1511 | * On some architectures it depends on the mm if the p4d/pud or pmd | |
1512 | * layer of the page table hierarchy is folded or not. | |
1513 | */ | |
1514 | #ifndef mm_p4d_folded | |
1515 | #define mm_p4d_folded(mm) __is_defined(__PAGETABLE_P4D_FOLDED) | |
1516 | #endif | |
1517 | ||
1518 | #ifndef mm_pud_folded | |
1519 | #define mm_pud_folded(mm) __is_defined(__PAGETABLE_PUD_FOLDED) | |
1520 | #endif | |
1521 | ||
1522 | #ifndef mm_pmd_folded | |
1523 | #define mm_pmd_folded(mm) __is_defined(__PAGETABLE_PMD_FOLDED) | |
1524 | #endif | |
1525 | ||
d3f7b1bb VG |
1526 | #ifndef p4d_offset_lockless |
1527 | #define p4d_offset_lockless(pgdp, pgd, address) p4d_offset(&(pgd), address) | |
1528 | #endif | |
1529 | #ifndef pud_offset_lockless | |
1530 | #define pud_offset_lockless(p4dp, p4d, address) pud_offset(&(p4d), address) | |
1531 | #endif | |
1532 | #ifndef pmd_offset_lockless | |
1533 | #define pmd_offset_lockless(pudp, pud, address) pmd_offset(&(pud), address) | |
1534 | #endif | |
1535 | ||
93fab1b2 SP |
1536 | /* |
1537 | * p?d_leaf() - true if this entry is a final mapping to a physical address. | |
1538 | * This differs from p?d_huge() by the fact that they are always available (if | |
1539 | * the architecture supports large pages at the appropriate level) even | |
1540 | * if CONFIG_HUGETLB_PAGE is not defined. | |
1541 | * Only meaningful when called on a valid entry. | |
1542 | */ | |
1543 | #ifndef pgd_leaf | |
1544 | #define pgd_leaf(x) 0 | |
1545 | #endif | |
1546 | #ifndef p4d_leaf | |
1547 | #define p4d_leaf(x) 0 | |
1548 | #endif | |
1549 | #ifndef pud_leaf | |
1550 | #define pud_leaf(x) 0 | |
1551 | #endif | |
1552 | #ifndef pmd_leaf | |
1553 | #define pmd_leaf(x) 0 | |
1554 | #endif | |
1555 | ||
560dabbd PZ |
1556 | #ifndef pgd_leaf_size |
1557 | #define pgd_leaf_size(x) (1ULL << PGDIR_SHIFT) | |
1558 | #endif | |
1559 | #ifndef p4d_leaf_size | |
1560 | #define p4d_leaf_size(x) P4D_SIZE | |
1561 | #endif | |
1562 | #ifndef pud_leaf_size | |
1563 | #define pud_leaf_size(x) PUD_SIZE | |
1564 | #endif | |
1565 | #ifndef pmd_leaf_size | |
1566 | #define pmd_leaf_size(x) PMD_SIZE | |
1567 | #endif | |
1568 | #ifndef pte_leaf_size | |
1569 | #define pte_leaf_size(x) PAGE_SIZE | |
1570 | #endif | |
1571 | ||
ca5999fd | 1572 | #endif /* _LINUX_PGTABLE_H */ |