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00db8189 1/*
00db8189 2 * Framework and drivers for configuring and reading different PHYs
d8de01b7 3 * Based on code in sungem_phy.c and (long-removed) gianfar_phy.c
00db8189
AF
4 *
5 * Author: Andy Fleming
6 *
7 * Copyright (c) 2004 Freescale Semiconductor, Inc.
8 *
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License as published by the
11 * Free Software Foundation; either version 2 of the License, or (at your
12 * option) any later version.
13 *
14 */
15
16#ifndef __PHY_H
17#define __PHY_H
18
2220943a 19#include <linux/compiler.h>
00db8189 20#include <linux/spinlock.h>
13df29f6 21#include <linux/ethtool.h>
b31cdffa 22#include <linux/linkmode.h>
bac83c65 23#include <linux/mdio.h>
13df29f6 24#include <linux/mii.h>
3e3aaf64 25#include <linux/module.h>
13df29f6
MR
26#include <linux/timer.h>
27#include <linux/workqueue.h>
8626d3b4 28#include <linux/mod_devicetable.h>
00db8189 29
60063497 30#include <linux/atomic.h>
0ac49527 31
e9fbdf17 32#define PHY_DEFAULT_FEATURES (SUPPORTED_Autoneg | \
00db8189
AF
33 SUPPORTED_TP | \
34 SUPPORTED_MII)
35
e9fbdf17
FF
36#define PHY_10BT_FEATURES (SUPPORTED_10baseT_Half | \
37 SUPPORTED_10baseT_Full)
38
39#define PHY_100BT_FEATURES (SUPPORTED_100baseT_Half | \
40 SUPPORTED_100baseT_Full)
41
42#define PHY_1000BT_FEATURES (SUPPORTED_1000baseT_Half | \
00db8189
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43 SUPPORTED_1000baseT_Full)
44
719655a1
AL
45extern __ETHTOOL_DECLARE_LINK_MODE_MASK(phy_basic_features) __ro_after_init;
46extern __ETHTOOL_DECLARE_LINK_MODE_MASK(phy_basic_t1_features) __ro_after_init;
47extern __ETHTOOL_DECLARE_LINK_MODE_MASK(phy_gbit_features) __ro_after_init;
48extern __ETHTOOL_DECLARE_LINK_MODE_MASK(phy_gbit_fibre_features) __ro_after_init;
49extern __ETHTOOL_DECLARE_LINK_MODE_MASK(phy_gbit_all_ports_features) __ro_after_init;
50extern __ETHTOOL_DECLARE_LINK_MODE_MASK(phy_10gbit_features) __ro_after_init;
9e857a40 51extern __ETHTOOL_DECLARE_LINK_MODE_MASK(phy_10gbit_fec_features) __ro_after_init;
719655a1
AL
52extern __ETHTOOL_DECLARE_LINK_MODE_MASK(phy_10gbit_full_features) __ro_after_init;
53
54#define PHY_BASIC_FEATURES ((unsigned long *)&phy_basic_features)
55#define PHY_BASIC_T1_FEATURES ((unsigned long *)&phy_basic_t1_features)
56#define PHY_GBIT_FEATURES ((unsigned long *)&phy_gbit_features)
57#define PHY_GBIT_FIBRE_FEATURES ((unsigned long *)&phy_gbit_fibre_features)
58#define PHY_GBIT_ALL_PORTS_FEATURES ((unsigned long *)&phy_gbit_all_ports_features)
59#define PHY_10GBIT_FEATURES ((unsigned long *)&phy_10gbit_features)
9e857a40 60#define PHY_10GBIT_FEC_FEATURES ((unsigned long *)&phy_10gbit_fec_features)
719655a1 61#define PHY_10GBIT_FULL_FEATURES ((unsigned long *)&phy_10gbit_full_features)
e9fbdf17 62
3c1bcc86
AL
63extern const int phy_10_100_features_array[4];
64extern const int phy_basic_t1_features_array[2];
65extern const int phy_gbit_features_array[2];
66extern const int phy_10gbit_features_array[1];
67
c5e38a94
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68/*
69 * Set phydev->irq to PHY_POLL if interrupts are not supported,
00db8189
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70 * or not desired for this PHY. Set to PHY_IGNORE_INTERRUPT if
71 * the attached driver handles the interrupt
72 */
73#define PHY_POLL -1
74#define PHY_IGNORE_INTERRUPT -2
75
a4307c0e
HK
76#define PHY_IS_INTERNAL 0x00000001
77#define PHY_RST_AFTER_CLK_EN 0x00000002
a9049e0c 78#define MDIO_DEVICE_IS_PHY 0x80000000
00db8189 79
e8a2b6a4
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80/* Interface Mode definitions */
81typedef enum {
4157ef1b 82 PHY_INTERFACE_MODE_NA,
735d8a18 83 PHY_INTERFACE_MODE_INTERNAL,
e8a2b6a4
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84 PHY_INTERFACE_MODE_MII,
85 PHY_INTERFACE_MODE_GMII,
86 PHY_INTERFACE_MODE_SGMII,
87 PHY_INTERFACE_MODE_TBI,
2cc70ba4 88 PHY_INTERFACE_MODE_REVMII,
e8a2b6a4
AF
89 PHY_INTERFACE_MODE_RMII,
90 PHY_INTERFACE_MODE_RGMII,
a999589c 91 PHY_INTERFACE_MODE_RGMII_ID,
7d400a4c
KP
92 PHY_INTERFACE_MODE_RGMII_RXID,
93 PHY_INTERFACE_MODE_RGMII_TXID,
4157ef1b
SG
94 PHY_INTERFACE_MODE_RTBI,
95 PHY_INTERFACE_MODE_SMII,
898dd0bd 96 PHY_INTERFACE_MODE_XGMII,
fd70f72c 97 PHY_INTERFACE_MODE_MOCA,
b9d12085 98 PHY_INTERFACE_MODE_QSGMII,
572de608 99 PHY_INTERFACE_MODE_TRGMII,
55601a88
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100 PHY_INTERFACE_MODE_1000BASEX,
101 PHY_INTERFACE_MODE_2500BASEX,
102 PHY_INTERFACE_MODE_RXAUI,
c125ca09
RK
103 PHY_INTERFACE_MODE_XAUI,
104 /* 10GBASE-KR, XFI, SFI - single lane 10G Serdes */
105 PHY_INTERFACE_MODE_10GKR,
8a2fe56e 106 PHY_INTERFACE_MODE_MAX,
e8a2b6a4
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107} phy_interface_t;
108
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109/**
110 * phy_supported_speeds - return all speeds currently supported by a phy device
111 * @phy: The phy device to return supported speeds of.
112 * @speeds: buffer to store supported speeds in.
113 * @size: size of speeds buffer.
114 *
d8de01b7
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115 * Description: Returns the number of supported speeds, and fills
116 * the speeds buffer with the supported speeds. If speeds buffer is
117 * too small to contain all currently supported speeds, will return as
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ZB
118 * many speeds as can fit.
119 */
120unsigned int phy_supported_speeds(struct phy_device *phy,
121 unsigned int *speeds,
122 unsigned int size);
123
8a2fe56e 124/**
d8de01b7
RD
125 * phy_modes - map phy_interface_t enum to device tree binding of phy-mode
126 * @interface: enum phy_interface_t value
127 *
128 * Description: maps 'enum phy_interface_t' defined in this file
8a2fe56e
FF
129 * into the device tree binding of 'phy-mode', so that Ethernet
130 * device driver can get phy interface from device tree.
131 */
132static inline const char *phy_modes(phy_interface_t interface)
133{
134 switch (interface) {
135 case PHY_INTERFACE_MODE_NA:
136 return "";
735d8a18
FF
137 case PHY_INTERFACE_MODE_INTERNAL:
138 return "internal";
8a2fe56e
FF
139 case PHY_INTERFACE_MODE_MII:
140 return "mii";
141 case PHY_INTERFACE_MODE_GMII:
142 return "gmii";
143 case PHY_INTERFACE_MODE_SGMII:
144 return "sgmii";
145 case PHY_INTERFACE_MODE_TBI:
146 return "tbi";
147 case PHY_INTERFACE_MODE_REVMII:
148 return "rev-mii";
149 case PHY_INTERFACE_MODE_RMII:
150 return "rmii";
151 case PHY_INTERFACE_MODE_RGMII:
152 return "rgmii";
153 case PHY_INTERFACE_MODE_RGMII_ID:
154 return "rgmii-id";
155 case PHY_INTERFACE_MODE_RGMII_RXID:
156 return "rgmii-rxid";
157 case PHY_INTERFACE_MODE_RGMII_TXID:
158 return "rgmii-txid";
159 case PHY_INTERFACE_MODE_RTBI:
160 return "rtbi";
161 case PHY_INTERFACE_MODE_SMII:
162 return "smii";
163 case PHY_INTERFACE_MODE_XGMII:
164 return "xgmii";
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FF
165 case PHY_INTERFACE_MODE_MOCA:
166 return "moca";
b9d12085
TP
167 case PHY_INTERFACE_MODE_QSGMII:
168 return "qsgmii";
572de608
SW
169 case PHY_INTERFACE_MODE_TRGMII:
170 return "trgmii";
55601a88
AL
171 case PHY_INTERFACE_MODE_1000BASEX:
172 return "1000base-x";
173 case PHY_INTERFACE_MODE_2500BASEX:
174 return "2500base-x";
175 case PHY_INTERFACE_MODE_RXAUI:
176 return "rxaui";
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RK
177 case PHY_INTERFACE_MODE_XAUI:
178 return "xaui";
179 case PHY_INTERFACE_MODE_10GKR:
180 return "10gbase-kr";
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FF
181 default:
182 return "unknown";
183 }
184}
185
00db8189 186
e8a2b6a4 187#define PHY_INIT_TIMEOUT 100000
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188#define PHY_STATE_TIME 1
189#define PHY_FORCE_TIMEOUT 10
00db8189 190
e8a2b6a4 191#define PHY_MAX_ADDR 32
00db8189 192
a4d00f17 193/* Used when trying to connect to a specific phy (mii bus id:phy device id) */
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194#define PHY_ID_FMT "%s:%02x"
195
4567d686 196#define MII_BUS_ID_SIZE 61
a4d00f17 197
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198/* Or MII_ADDR_C45 into regnum for read/write on mii_bus to enable the 21 bit
199 IEEE 802.3ae clause 45 addressing mode used by 10GIGE phy chips. */
200#define MII_ADDR_C45 (1<<30)
201
313162d0 202struct device;
9525ae83 203struct phylink;
313162d0
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204struct sk_buff;
205
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206/*
207 * The Bus class for PHYs. Devices which provide access to
208 * PHYs should register using this structure
209 */
00db8189 210struct mii_bus {
3e3aaf64 211 struct module *owner;
00db8189 212 const char *name;
9d9326d3 213 char id[MII_BUS_ID_SIZE];
00db8189 214 void *priv;
ccaa953e
AL
215 int (*read)(struct mii_bus *bus, int addr, int regnum);
216 int (*write)(struct mii_bus *bus, int addr, int regnum, u16 val);
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217 int (*reset)(struct mii_bus *bus);
218
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219 /*
220 * A lock to ensure that only one thing can read/write
221 * the MDIO bus at a time
222 */
35b5f6b1 223 struct mutex mdio_lock;
00db8189 224
18ee49dd 225 struct device *parent;
46abc021
LB
226 enum {
227 MDIOBUS_ALLOCATED = 1,
228 MDIOBUS_REGISTERED,
229 MDIOBUS_UNREGISTERED,
230 MDIOBUS_RELEASED,
231 } state;
232 struct device dev;
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233
234 /* list of all PHYs on bus */
7f854420 235 struct mdio_device *mdio_map[PHY_MAX_ADDR];
00db8189 236
c6883996 237 /* PHY addresses to be ignored when probing */
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MP
238 u32 phy_mask;
239
922f2dd1
FF
240 /* PHY addresses to ignore the TA/read failure */
241 u32 phy_ignore_ta_mask;
242
c5e38a94 243 /*
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AL
244 * An array of interrupts, each PHY's interrupt at the index
245 * matching its address
c5e38a94 246 */
e7f4dc35 247 int irq[PHY_MAX_ADDR];
69226896
RQ
248
249 /* GPIO reset pulse width in microseconds */
250 int reset_delay_us;
d396e84c
SS
251 /* RESET GPIO descriptor pointer */
252 struct gpio_desc *reset_gpiod;
00db8189 253};
46abc021 254#define to_mii_bus(d) container_of(d, struct mii_bus, dev)
00db8189 255
eb8a54a7
TT
256struct mii_bus *mdiobus_alloc_size(size_t);
257static inline struct mii_bus *mdiobus_alloc(void)
258{
259 return mdiobus_alloc_size(0);
260}
261
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262int __mdiobus_register(struct mii_bus *bus, struct module *owner);
263#define mdiobus_register(bus) __mdiobus_register(bus, THIS_MODULE)
2e888103
LB
264void mdiobus_unregister(struct mii_bus *bus);
265void mdiobus_free(struct mii_bus *bus);
6d48f44b
GS
266struct mii_bus *devm_mdiobus_alloc_size(struct device *dev, int sizeof_priv);
267static inline struct mii_bus *devm_mdiobus_alloc(struct device *dev)
268{
269 return devm_mdiobus_alloc_size(dev, 0);
270}
271
272void devm_mdiobus_free(struct device *dev, struct mii_bus *bus);
2e888103 273struct phy_device *mdiobus_scan(struct mii_bus *bus, int addr);
2e888103 274
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275#define PHY_INTERRUPT_DISABLED false
276#define PHY_INTERRUPT_ENABLED true
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277
278/* PHY state machine states:
279 *
280 * DOWN: PHY device and driver are not ready for anything. probe
281 * should be called if and only if the PHY is in this state,
282 * given that the PHY device exists.
899a3cbb 283 * - PHY driver probe function will set the state to READY
00db8189
AF
284 *
285 * READY: PHY is ready to send and receive packets, but the
286 * controller is not. By default, PHYs which do not implement
899a3cbb 287 * probe will be set to this state by phy_probe().
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288 * - start will set the state to UP
289 *
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290 * UP: The PHY and attached device are ready to do work.
291 * Interrupts should be started here.
85a1f31d 292 * - timer moves to NOLINK or RUNNING
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293 *
294 * NOLINK: PHY is up, but not currently plugged in.
8deeb630 295 * - irq or timer will set RUNNING if link comes back
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296 * - phy_stop moves to HALTED
297 *
298 * FORCING: PHY is being configured with forced settings
299 * - if link is up, move to RUNNING
300 * - If link is down, we drop to the next highest setting, and
301 * retry (FORCING) after a timeout
302 * - phy_stop moves to HALTED
303 *
304 * RUNNING: PHY is currently up, running, and possibly sending
305 * and/or receiving packets
8deeb630 306 * - irq or timer will set NOLINK if link goes down
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AF
307 * - phy_stop moves to HALTED
308 *
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309 * HALTED: PHY is up, but no polling or interrupts are done. Or
310 * PHY is in an error state.
f24098f8 311 * - phy_start moves to UP
00db8189
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312 */
313enum phy_state {
4017b4d3 314 PHY_DOWN = 0,
00db8189 315 PHY_READY,
2b3e88ea 316 PHY_HALTED,
00db8189 317 PHY_UP,
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AF
318 PHY_RUNNING,
319 PHY_NOLINK,
320 PHY_FORCING,
00db8189
AF
321};
322
ac28b9f8
DD
323/**
324 * struct phy_c45_device_ids - 802.3-c45 Device Identifiers
325 * @devices_in_package: Bit vector of devices present.
326 * @device_ids: The device identifer for each present device.
327 */
328struct phy_c45_device_ids {
329 u32 devices_in_package;
330 u32 device_ids[8];
331};
c1f19b51 332
00db8189
AF
333/* phy_device: An instance of a PHY
334 *
335 * drv: Pointer to the driver for this PHY instance
00db8189 336 * phy_id: UID for this device found during discovery
ac28b9f8
DD
337 * c45_ids: 802.3-c45 Device Identifers if is_c45.
338 * is_c45: Set to true if this phy uses clause 45 addressing.
4284b6a5 339 * is_internal: Set to true if this phy is internal to a MAC.
5a11dd7d 340 * is_pseudo_fixed_link: Set to true if this phy is an Ethernet switch, etc.
3b8b11f9 341 * is_gigabit_capable: Set to true if PHY supports 1000Mbps
aae88261 342 * has_fixups: Set to true if this phy has fixups/quirks.
8a477a6f 343 * suspended: Set to true if this phy has been suspended successfully.
a3995460 344 * sysfs_links: Internal boolean tracking sysfs symbolic links setup/removal.
f0f9b4ed 345 * loopback_enabled: Set true if this phy has been loopbacked successfully.
00db8189
AF
346 * state: state of the PHY for management purposes
347 * dev_flags: Device-specific flags used by the PHY driver.
00db8189
AF
348 * link_timeout: The number of timer firings to wait before the
349 * giving up on the current attempt at acquiring a link
350 * irq: IRQ number of the PHY's interrupt (-1 if none)
351 * phy_timer: The timer for handling the state machine
00db8189
AF
352 * attached_dev: The attached enet driver's device instance ptr
353 * adjust_link: Callback for the enet controller to respond to
354 * changes in the link state.
00db8189 355 *
114002bc
FF
356 * speed, duplex, pause, supported, advertising, lp_advertising,
357 * and autoneg are used like in mii_if_info
00db8189
AF
358 *
359 * interrupts currently only supports enabled or disabled,
360 * but could be changed in the future to support enabling
361 * and disabling specific interrupts
362 *
363 * Contains some infrastructure for polling and interrupt
364 * handling, as well as handling shifts in PHY hardware state
365 */
366struct phy_device {
e5a03bfd
AL
367 struct mdio_device mdio;
368
00db8189
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369 /* Information about the PHY type */
370 /* And management functions */
371 struct phy_driver *drv;
372
00db8189
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373 u32 phy_id;
374
ac28b9f8 375 struct phy_c45_device_ids c45_ids;
87e5808d
HK
376 unsigned is_c45:1;
377 unsigned is_internal:1;
378 unsigned is_pseudo_fixed_link:1;
3b8b11f9 379 unsigned is_gigabit_capable:1;
87e5808d
HK
380 unsigned has_fixups:1;
381 unsigned suspended:1;
382 unsigned sysfs_links:1;
383 unsigned loopback_enabled:1;
384
385 unsigned autoneg:1;
386 /* The most recently read link state */
387 unsigned link:1;
4950c2ba 388 unsigned autoneg_complete:1;
ac28b9f8 389
695bce8f
HK
390 /* Interrupts are enabled */
391 unsigned interrupts:1;
392
00db8189
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393 enum phy_state state;
394
395 u32 dev_flags;
396
e8a2b6a4
AF
397 phy_interface_t interface;
398
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399 /*
400 * forced speed & duplex (no autoneg)
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401 * partner speed & duplex & pause (autoneg)
402 */
403 int speed;
404 int duplex;
405 int pause;
406 int asym_pause;
407
3c1bcc86
AL
408 /* Union of PHY and Attached devices' supported link modes */
409 /* See ethtool.h for more info */
410 __ETHTOOL_DECLARE_LINK_MODE_MASK(supported);
411 __ETHTOOL_DECLARE_LINK_MODE_MASK(advertising);
c0ec3c27 412 __ETHTOOL_DECLARE_LINK_MODE_MASK(lp_advertising);
00db8189 413
d853d145 414 /* Energy efficient ethernet modes which should be prohibited */
415 u32 eee_broken_modes;
416
00db8189
AF
417 int link_timeout;
418
2e0bc452
ZB
419#ifdef CONFIG_LED_TRIGGER_PHY
420 struct phy_led_trigger *phy_led_triggers;
421 unsigned int phy_num_led_triggers;
422 struct phy_led_trigger *last_triggered;
3928ee64
MS
423
424 struct phy_led_trigger *led_link_trigger;
2e0bc452
ZB
425#endif
426
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427 /*
428 * Interrupt number for this PHY
429 * -1 means no interrupt
430 */
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431 int irq;
432
433 /* private data pointer */
434 /* For use by PHYs to maintain extra state */
435 void *priv;
436
437 /* Interrupt and Polling infrastructure */
a390d1f3 438 struct delayed_work state_queue;
00db8189 439
35b5f6b1 440 struct mutex lock;
00db8189 441
9525ae83 442 struct phylink *phylink;
00db8189
AF
443 struct net_device *attached_dev;
444
634ec36c 445 u8 mdix;
f4ed2fe3 446 u8 mdix_ctrl;
634ec36c 447
a81497be 448 void (*phy_link_change)(struct phy_device *, bool up, bool do_carrier);
00db8189 449 void (*adjust_link)(struct net_device *dev);
00db8189 450};
e5a03bfd
AL
451#define to_phy_device(d) container_of(to_mdio_device(d), \
452 struct phy_device, mdio)
00db8189
AF
453
454/* struct phy_driver: Driver structure for a particular PHY type
455 *
a9049e0c 456 * driver_data: static driver data
00db8189
AF
457 * phy_id: The result of reading the UID registers of this PHY
458 * type, and ANDing them with the phy_id_mask. This driver
459 * only works for PHYs with IDs which match this field
460 * name: The friendly name of this PHY type
461 * phy_id_mask: Defines the important bits of the phy_id
3e64cf7a
CG
462 * features: A mandatory list of features (speed, duplex, etc)
463 * supported by this PHY
00db8189
AF
464 * flags: A bitfield defining certain other features this PHY
465 * supports (like interrupts)
466 *
00fde795
HK
467 * All functions are optional. If config_aneg or read_status
468 * are not implemented, the phy core uses the genphy versions.
469 * Note that none of these functions should be called from
470 * interrupt time. The goal is for the bus read/write functions
471 * to be able to block when the bus transaction is happening,
472 * and be freed up by an interrupt (The MPC85xx has this ability,
473 * though it is not currently supported in the driver).
00db8189
AF
474 */
475struct phy_driver {
a9049e0c 476 struct mdio_driver_common mdiodrv;
00db8189
AF
477 u32 phy_id;
478 char *name;
511e3036 479 u32 phy_id_mask;
719655a1 480 const unsigned long * const features;
00db8189 481 u32 flags;
860f6e9e 482 const void *driver_data;
00db8189 483
c5e38a94 484 /*
9df81dd7
FF
485 * Called to issue a PHY software reset
486 */
487 int (*soft_reset)(struct phy_device *phydev);
488
489 /*
c5e38a94
AF
490 * Called to initialize the PHY,
491 * including after a reset
492 */
00db8189
AF
493 int (*config_init)(struct phy_device *phydev);
494
c5e38a94
AF
495 /*
496 * Called during discovery. Used to set
497 * up device-specific structures, if any
498 */
00db8189
AF
499 int (*probe)(struct phy_device *phydev);
500
efbdfdc2
AL
501 /*
502 * Probe the hardware to determine what abilities it has.
503 * Should only set phydev->supported.
504 */
505 int (*get_features)(struct phy_device *phydev);
506
00db8189
AF
507 /* PHY Power Management */
508 int (*suspend)(struct phy_device *phydev);
509 int (*resume)(struct phy_device *phydev);
510
c5e38a94
AF
511 /*
512 * Configures the advertisement and resets
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AF
513 * autonegotiation if phydev->autoneg is on,
514 * forces the speed to the current settings in phydev
c5e38a94
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515 * if phydev->autoneg is off
516 */
00db8189
AF
517 int (*config_aneg)(struct phy_device *phydev);
518
76a423a3
FF
519 /* Determines the auto negotiation result */
520 int (*aneg_done)(struct phy_device *phydev);
521
00db8189
AF
522 /* Determines the negotiated speed and duplex */
523 int (*read_status)(struct phy_device *phydev);
524
525 /* Clears any pending interrupts */
526 int (*ack_interrupt)(struct phy_device *phydev);
527
528 /* Enables or disables interrupts */
529 int (*config_intr)(struct phy_device *phydev);
530
a8729eb3
AG
531 /*
532 * Checks if the PHY generated an interrupt.
533 * For multi-PHY devices with shared PHY interrupt pin
534 */
535 int (*did_interrupt)(struct phy_device *phydev);
536
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AF
537 /* Clears up any memory if needed */
538 void (*remove)(struct phy_device *phydev);
539
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540 /* Returns true if this is a suitable driver for the given
541 * phydev. If NULL, matching is based on phy_id and
542 * phy_id_mask.
543 */
544 int (*match_phy_device)(struct phy_device *phydev);
545
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546 /* Handles ethtool queries for hardware time stamping. */
547 int (*ts_info)(struct phy_device *phydev, struct ethtool_ts_info *ti);
548
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549 /* Handles SIOCSHWTSTAMP ioctl for hardware time stamping. */
550 int (*hwtstamp)(struct phy_device *phydev, struct ifreq *ifr);
551
552 /*
553 * Requests a Rx timestamp for 'skb'. If the skb is accepted,
554 * the phy driver promises to deliver it using netif_rx() as
555 * soon as a timestamp becomes available. One of the
556 * PTP_CLASS_ values is passed in 'type'. The function must
557 * return true if the skb is accepted for delivery.
558 */
559 bool (*rxtstamp)(struct phy_device *dev, struct sk_buff *skb, int type);
560
561 /*
562 * Requests a Tx timestamp for 'skb'. The phy driver promises
da92b194 563 * to deliver it using skb_complete_tx_timestamp() as soon as a
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564 * timestamp becomes available. One of the PTP_CLASS_ values
565 * is passed in 'type'.
566 */
567 void (*txtstamp)(struct phy_device *dev, struct sk_buff *skb, int type);
568
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569 /* Some devices (e.g. qnap TS-119P II) require PHY register changes to
570 * enable Wake on LAN, so set_wol is provided to be called in the
571 * ethernet driver's set_wol function. */
572 int (*set_wol)(struct phy_device *dev, struct ethtool_wolinfo *wol);
573
574 /* See set_wol, but for checking whether Wake on LAN is enabled. */
575 void (*get_wol)(struct phy_device *dev, struct ethtool_wolinfo *wol);
576
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577 /*
578 * Called to inform a PHY device driver when the core is about to
579 * change the link state. This callback is supposed to be used as
580 * fixup hook for drivers that need to take action when the link
581 * state changes. Drivers are by no means allowed to mess with the
582 * PHY device structure in their implementations.
583 */
584 void (*link_change_notify)(struct phy_device *dev);
585
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586 /*
587 * Phy specific driver override for reading a MMD register.
588 * This function is optional for PHY specific drivers. When
589 * not provided, the default MMD read function will be used
590 * by phy_read_mmd(), which will use either a direct read for
591 * Clause 45 PHYs or an indirect read for Clause 22 PHYs.
592 * devnum is the MMD device number within the PHY device,
593 * regnum is the register within the selected MMD device.
594 */
595 int (*read_mmd)(struct phy_device *dev, int devnum, u16 regnum);
596
597 /*
598 * Phy specific driver override for writing a MMD register.
599 * This function is optional for PHY specific drivers. When
600 * not provided, the default MMD write function will be used
601 * by phy_write_mmd(), which will use either a direct write for
602 * Clause 45 PHYs, or an indirect write for Clause 22 PHYs.
603 * devnum is the MMD device number within the PHY device,
604 * regnum is the register within the selected MMD device.
605 * val is the value to be written.
606 */
607 int (*write_mmd)(struct phy_device *dev, int devnum, u16 regnum,
608 u16 val);
609
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610 int (*read_page)(struct phy_device *dev);
611 int (*write_page)(struct phy_device *dev, int page);
612
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613 /* Get the size and type of the eeprom contained within a plug-in
614 * module */
615 int (*module_info)(struct phy_device *dev,
616 struct ethtool_modinfo *modinfo);
617
618 /* Get the eeprom information from the plug-in module */
619 int (*module_eeprom)(struct phy_device *dev,
620 struct ethtool_eeprom *ee, u8 *data);
621
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622 /* Get statistics from the phy using ethtool */
623 int (*get_sset_count)(struct phy_device *dev);
624 void (*get_strings)(struct phy_device *dev, u8 *data);
625 void (*get_stats)(struct phy_device *dev,
626 struct ethtool_stats *stats, u64 *data);
968ad9da
RL
627
628 /* Get and Set PHY tunables */
629 int (*get_tunable)(struct phy_device *dev,
630 struct ethtool_tunable *tuna, void *data);
631 int (*set_tunable)(struct phy_device *dev,
632 struct ethtool_tunable *tuna,
633 const void *data);
f0f9b4ed 634 int (*set_loopback)(struct phy_device *dev, bool enable);
00db8189 635};
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AL
636#define to_phy_driver(d) container_of(to_mdio_common_driver(d), \
637 struct phy_driver, mdiodrv)
00db8189 638
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AF
639#define PHY_ANY_ID "MATCH ANY PHY"
640#define PHY_ANY_UID 0xffffffff
641
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642#define PHY_ID_MATCH_EXACT(id) .phy_id = (id), .phy_id_mask = GENMASK(31, 0)
643#define PHY_ID_MATCH_MODEL(id) .phy_id = (id), .phy_id_mask = GENMASK(31, 4)
644#define PHY_ID_MATCH_VENDOR(id) .phy_id = (id), .phy_id_mask = GENMASK(31, 10)
645
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646/* A Structure for boards to register fixups with the PHY Lib */
647struct phy_fixup {
648 struct list_head list;
4567d686 649 char bus_id[MII_BUS_ID_SIZE + 3];
f62220d3
AF
650 u32 phy_uid;
651 u32 phy_uid_mask;
652 int (*run)(struct phy_device *phydev);
653};
654
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655const char *phy_speed_to_str(int speed);
656const char *phy_duplex_to_str(unsigned int duplex);
657
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658/* A structure for mapping a particular speed and duplex
659 * combination to a particular SUPPORTED and ADVERTISED value
660 */
661struct phy_setting {
662 u32 speed;
663 u8 duplex;
664 u8 bit;
665};
666
667const struct phy_setting *
668phy_lookup_setting(int speed, int duplex, const unsigned long *mask,
3c1bcc86 669 bool exact);
0ccb4fc6 670size_t phy_speeds(unsigned int *speeds, size_t size,
3c1bcc86 671 unsigned long *mask);
a4eaed9f 672void of_set_phy_supported(struct phy_device *phydev);
3feb9b23 673void of_set_phy_eee_broken(struct phy_device *phydev);
0ccb4fc6 674
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HK
675/**
676 * phy_is_started - Convenience function to check whether PHY is started
677 * @phydev: The phy_device struct
678 */
679static inline bool phy_is_started(struct phy_device *phydev)
680{
a2fc9d7e 681 return phydev->state >= PHY_UP;
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HK
682}
683
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RK
684void phy_resolve_aneg_linkmode(struct phy_device *phydev);
685
2e888103
LB
686/**
687 * phy_read - Convenience function for reading a given PHY register
688 * @phydev: the phy_device struct
689 * @regnum: register number to read
690 *
691 * NOTE: MUST NOT be called from interrupt context,
692 * because the bus read/write functions may wait for an interrupt
693 * to conclude the operation.
694 */
abf35df2 695static inline int phy_read(struct phy_device *phydev, u32 regnum)
2e888103 696{
e5a03bfd 697 return mdiobus_read(phydev->mdio.bus, phydev->mdio.addr, regnum);
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LB
698}
699
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700/**
701 * __phy_read - convenience function for reading a given PHY register
702 * @phydev: the phy_device struct
703 * @regnum: register number to read
704 *
705 * The caller must have taken the MDIO bus lock.
706 */
707static inline int __phy_read(struct phy_device *phydev, u32 regnum)
708{
709 return __mdiobus_read(phydev->mdio.bus, phydev->mdio.addr, regnum);
710}
711
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LB
712/**
713 * phy_write - Convenience function for writing a given PHY register
714 * @phydev: the phy_device struct
715 * @regnum: register number to write
716 * @val: value to write to @regnum
717 *
718 * NOTE: MUST NOT be called from interrupt context,
719 * because the bus read/write functions may wait for an interrupt
720 * to conclude the operation.
721 */
abf35df2 722static inline int phy_write(struct phy_device *phydev, u32 regnum, u16 val)
2e888103 723{
e5a03bfd 724 return mdiobus_write(phydev->mdio.bus, phydev->mdio.addr, regnum, val);
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LB
725}
726
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727/**
728 * __phy_write - Convenience function for writing a given PHY register
729 * @phydev: the phy_device struct
730 * @regnum: register number to write
731 * @val: value to write to @regnum
732 *
733 * The caller must have taken the MDIO bus lock.
734 */
735static inline int __phy_write(struct phy_device *phydev, u32 regnum, u16 val)
736{
737 return __mdiobus_write(phydev->mdio.bus, phydev->mdio.addr, regnum,
738 val);
739}
740
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741/**
742 * phy_read_mmd - Convenience function for reading a register
743 * from an MMD on a given PHY.
744 * @phydev: The phy_device struct
745 * @devad: The MMD to read from
746 * @regnum: The register on the MMD to read
747 *
748 * Same rules as for phy_read();
749 */
750int phy_read_mmd(struct phy_device *phydev, int devad, u32 regnum);
751
752/**
753 * __phy_read_mmd - Convenience function for reading a register
754 * from an MMD on a given PHY.
755 * @phydev: The phy_device struct
756 * @devad: The MMD to read from
757 * @regnum: The register on the MMD to read
758 *
759 * Same rules as for __phy_read();
760 */
761int __phy_read_mmd(struct phy_device *phydev, int devad, u32 regnum);
762
763/**
764 * phy_write_mmd - Convenience function for writing a register
765 * on an MMD on a given PHY.
766 * @phydev: The phy_device struct
767 * @devad: The MMD to write to
768 * @regnum: The register on the MMD to read
769 * @val: value to write to @regnum
770 *
771 * Same rules as for phy_write();
772 */
773int phy_write_mmd(struct phy_device *phydev, int devad, u32 regnum, u16 val);
774
775/**
776 * __phy_write_mmd - Convenience function for writing a register
777 * on an MMD on a given PHY.
778 * @phydev: The phy_device struct
779 * @devad: The MMD to write to
780 * @regnum: The register on the MMD to read
781 * @val: value to write to @regnum
782 *
783 * Same rules as for __phy_write();
784 */
785int __phy_write_mmd(struct phy_device *phydev, int devad, u32 regnum, u16 val);
786
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787int __phy_modify_changed(struct phy_device *phydev, u32 regnum, u16 mask,
788 u16 set);
789int phy_modify_changed(struct phy_device *phydev, u32 regnum, u16 mask,
790 u16 set);
788f9933 791int __phy_modify(struct phy_device *phydev, u32 regnum, u16 mask, u16 set);
2b74e5be 792int phy_modify(struct phy_device *phydev, u32 regnum, u16 mask, u16 set);
788f9933 793
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794int __phy_modify_mmd_changed(struct phy_device *phydev, int devad, u32 regnum,
795 u16 mask, u16 set);
796int phy_modify_mmd_changed(struct phy_device *phydev, int devad, u32 regnum,
797 u16 mask, u16 set);
1878f0dc 798int __phy_modify_mmd(struct phy_device *phydev, int devad, u32 regnum,
b8554d4f 799 u16 mask, u16 set);
1878f0dc 800int phy_modify_mmd(struct phy_device *phydev, int devad, u32 regnum,
b8554d4f 801 u16 mask, u16 set);
1878f0dc 802
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HK
803/**
804 * __phy_set_bits - Convenience function for setting bits in a PHY register
805 * @phydev: the phy_device struct
806 * @regnum: register number to write
807 * @val: bits to set
808 *
809 * The caller must have taken the MDIO bus lock.
810 */
811static inline int __phy_set_bits(struct phy_device *phydev, u32 regnum, u16 val)
812{
813 return __phy_modify(phydev, regnum, 0, val);
814}
815
816/**
817 * __phy_clear_bits - Convenience function for clearing bits in a PHY register
818 * @phydev: the phy_device struct
819 * @regnum: register number to write
820 * @val: bits to clear
821 *
822 * The caller must have taken the MDIO bus lock.
823 */
824static inline int __phy_clear_bits(struct phy_device *phydev, u32 regnum,
825 u16 val)
826{
827 return __phy_modify(phydev, regnum, val, 0);
828}
829
830/**
831 * phy_set_bits - Convenience function for setting bits in a PHY register
832 * @phydev: the phy_device struct
833 * @regnum: register number to write
834 * @val: bits to set
835 */
836static inline int phy_set_bits(struct phy_device *phydev, u32 regnum, u16 val)
837{
838 return phy_modify(phydev, regnum, 0, val);
839}
840
841/**
842 * phy_clear_bits - Convenience function for clearing bits in a PHY register
843 * @phydev: the phy_device struct
844 * @regnum: register number to write
845 * @val: bits to clear
846 */
847static inline int phy_clear_bits(struct phy_device *phydev, u32 regnum, u16 val)
848{
849 return phy_modify(phydev, regnum, val, 0);
850}
851
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852/**
853 * __phy_set_bits_mmd - Convenience function for setting bits in a register
854 * on MMD
855 * @phydev: the phy_device struct
856 * @devad: the MMD containing register to modify
857 * @regnum: register number to modify
858 * @val: bits to set
859 *
860 * The caller must have taken the MDIO bus lock.
861 */
862static inline int __phy_set_bits_mmd(struct phy_device *phydev, int devad,
863 u32 regnum, u16 val)
864{
865 return __phy_modify_mmd(phydev, devad, regnum, 0, val);
866}
867
868/**
869 * __phy_clear_bits_mmd - Convenience function for clearing bits in a register
870 * on MMD
871 * @phydev: the phy_device struct
872 * @devad: the MMD containing register to modify
873 * @regnum: register number to modify
874 * @val: bits to clear
875 *
876 * The caller must have taken the MDIO bus lock.
877 */
878static inline int __phy_clear_bits_mmd(struct phy_device *phydev, int devad,
879 u32 regnum, u16 val)
880{
881 return __phy_modify_mmd(phydev, devad, regnum, val, 0);
882}
883
884/**
885 * phy_set_bits_mmd - Convenience function for setting bits in a register
886 * on MMD
887 * @phydev: the phy_device struct
888 * @devad: the MMD containing register to modify
889 * @regnum: register number to modify
890 * @val: bits to set
891 */
892static inline int phy_set_bits_mmd(struct phy_device *phydev, int devad,
893 u32 regnum, u16 val)
894{
895 return phy_modify_mmd(phydev, devad, regnum, 0, val);
896}
897
898/**
899 * phy_clear_bits_mmd - Convenience function for clearing bits in a register
900 * on MMD
901 * @phydev: the phy_device struct
902 * @devad: the MMD containing register to modify
903 * @regnum: register number to modify
904 * @val: bits to clear
905 */
906static inline int phy_clear_bits_mmd(struct phy_device *phydev, int devad,
907 u32 regnum, u16 val)
908{
909 return phy_modify_mmd(phydev, devad, regnum, val, 0);
910}
911
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912/**
913 * phy_interrupt_is_valid - Convenience function for testing a given PHY irq
914 * @phydev: the phy_device struct
915 *
916 * NOTE: must be kept in sync with addition/removal of PHY_POLL and
917 * PHY_IGNORE_INTERRUPT
918 */
919static inline bool phy_interrupt_is_valid(struct phy_device *phydev)
920{
921 return phydev->irq != PHY_POLL && phydev->irq != PHY_IGNORE_INTERRUPT;
922}
923
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924/**
925 * phy_polling_mode - Convenience function for testing whether polling is
926 * used to detect PHY status changes
927 * @phydev: the phy_device struct
928 */
929static inline bool phy_polling_mode(struct phy_device *phydev)
930{
931 return phydev->irq == PHY_POLL;
932}
933
4284b6a5
FF
934/**
935 * phy_is_internal - Convenience function for testing if a PHY is internal
936 * @phydev: the phy_device struct
937 */
938static inline bool phy_is_internal(struct phy_device *phydev)
939{
940 return phydev->is_internal;
941}
942
32d0f783
IS
943/**
944 * phy_interface_mode_is_rgmii - Convenience function for testing if a
945 * PHY interface mode is RGMII (all variants)
946 * @mode: the phy_interface_t enum
947 */
948static inline bool phy_interface_mode_is_rgmii(phy_interface_t mode)
949{
950 return mode >= PHY_INTERFACE_MODE_RGMII &&
951 mode <= PHY_INTERFACE_MODE_RGMII_TXID;
952};
953
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954/**
955 * phy_interface_mode_is_8023z() - does the phy interface mode use 802.3z
956 * negotiation
957 * @mode: one of &enum phy_interface_t
958 *
959 * Returns true if the phy interface mode uses the 16-bit negotiation
960 * word as defined in 802.3z. (See 802.3-2015 37.2.1 Config_Reg encoding)
961 */
962static inline bool phy_interface_mode_is_8023z(phy_interface_t mode)
963{
964 return mode == PHY_INTERFACE_MODE_1000BASEX ||
965 mode == PHY_INTERFACE_MODE_2500BASEX;
966}
967
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968/**
969 * phy_interface_is_rgmii - Convenience function for testing if a PHY interface
970 * is RGMII (all variants)
971 * @phydev: the phy_device struct
972 */
973static inline bool phy_interface_is_rgmii(struct phy_device *phydev)
974{
32d0f783 975 return phy_interface_mode_is_rgmii(phydev->interface);
5a11dd7d
FF
976};
977
978/*
979 * phy_is_pseudo_fixed_link - Convenience function for testing if this
980 * PHY is the CPU port facing side of an Ethernet switch, or similar.
981 * @phydev: the phy_device struct
982 */
983static inline bool phy_is_pseudo_fixed_link(struct phy_device *phydev)
984{
985 return phydev->is_pseudo_fixed_link;
e463d88c
FF
986}
987
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988int phy_save_page(struct phy_device *phydev);
989int phy_select_page(struct phy_device *phydev, int page);
990int phy_restore_page(struct phy_device *phydev, int oldpage, int ret);
991int phy_read_paged(struct phy_device *phydev, int page, u32 regnum);
992int phy_write_paged(struct phy_device *phydev, int page, u32 regnum, u16 val);
993int phy_modify_paged(struct phy_device *phydev, int page, u32 regnum,
994 u16 mask, u16 set);
995
ac28b9f8 996struct phy_device *phy_device_create(struct mii_bus *bus, int addr, int phy_id,
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997 bool is_c45,
998 struct phy_c45_device_ids *c45_ids);
90eff909 999#if IS_ENABLED(CONFIG_PHYLIB)
ac28b9f8 1000struct phy_device *get_phy_device(struct mii_bus *bus, int addr, bool is_c45);
4dea547f 1001int phy_device_register(struct phy_device *phy);
90eff909
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1002void phy_device_free(struct phy_device *phydev);
1003#else
1004static inline
1005struct phy_device *get_phy_device(struct mii_bus *bus, int addr, bool is_c45)
1006{
1007 return NULL;
1008}
1009
1010static inline int phy_device_register(struct phy_device *phy)
1011{
1012 return 0;
1013}
1014
1015static inline void phy_device_free(struct phy_device *phydev) { }
1016#endif /* CONFIG_PHYLIB */
38737e49 1017void phy_device_remove(struct phy_device *phydev);
2f5cb434 1018int phy_init_hw(struct phy_device *phydev);
481b5d93
SH
1019int phy_suspend(struct phy_device *phydev);
1020int phy_resume(struct phy_device *phydev);
9c2c2e62 1021int __phy_resume(struct phy_device *phydev);
f0f9b4ed 1022int phy_loopback(struct phy_device *phydev, bool enable);
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SS
1023struct phy_device *phy_attach(struct net_device *dev, const char *bus_id,
1024 phy_interface_t interface);
f8f76db1 1025struct phy_device *phy_find_first(struct mii_bus *bus);
257184d7
AF
1026int phy_attach_direct(struct net_device *dev, struct phy_device *phydev,
1027 u32 flags, phy_interface_t interface);
fa94f6d9 1028int phy_connect_direct(struct net_device *dev, struct phy_device *phydev,
4017b4d3
SS
1029 void (*handler)(struct net_device *),
1030 phy_interface_t interface);
1031struct phy_device *phy_connect(struct net_device *dev, const char *bus_id,
1032 void (*handler)(struct net_device *),
1033 phy_interface_t interface);
e1393456
AF
1034void phy_disconnect(struct phy_device *phydev);
1035void phy_detach(struct phy_device *phydev);
1036void phy_start(struct phy_device *phydev);
1037void phy_stop(struct phy_device *phydev);
1038int phy_start_aneg(struct phy_device *phydev);
372788f9 1039int phy_aneg_done(struct phy_device *phydev);
2b9672dd
HK
1040int phy_speed_down(struct phy_device *phydev, bool sync);
1041int phy_speed_up(struct phy_device *phydev);
e1393456 1042
002ba705 1043int phy_restart_aneg(struct phy_device *phydev);
a9668491 1044int phy_reset_after_clk_enable(struct phy_device *phydev);
00db8189 1045
bafbdd52
SS
1046static inline void phy_device_reset(struct phy_device *phydev, int value)
1047{
1048 mdio_device_reset(&phydev->mdio, value);
1049}
1050
72ba48be 1051#define phydev_err(_phydev, format, args...) \
e5a03bfd 1052 dev_err(&_phydev->mdio.dev, format, ##args)
72ba48be 1053
c4fabb8b
AL
1054#define phydev_info(_phydev, format, args...) \
1055 dev_info(&_phydev->mdio.dev, format, ##args)
1056
ab2a605f
AL
1057#define phydev_warn(_phydev, format, args...) \
1058 dev_warn(&_phydev->mdio.dev, format, ##args)
1059
72ba48be 1060#define phydev_dbg(_phydev, format, args...) \
2eaa38d9 1061 dev_dbg(&_phydev->mdio.dev, format, ##args)
72ba48be 1062
84eff6d1
AL
1063static inline const char *phydev_name(const struct phy_device *phydev)
1064{
e5a03bfd 1065 return dev_name(&phydev->mdio.dev);
84eff6d1
AL
1066}
1067
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AL
1068void phy_attached_print(struct phy_device *phydev, const char *fmt, ...)
1069 __printf(2, 3);
1070void phy_attached_info(struct phy_device *phydev);
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1071
1072/* Clause 22 PHY */
af6b6967 1073int genphy_config_init(struct phy_device *phydev);
045925e3 1074int genphy_read_abilities(struct phy_device *phydev);
3fb69bca 1075int genphy_setup_forced(struct phy_device *phydev);
00db8189 1076int genphy_restart_aneg(struct phy_device *phydev);
cd34499c 1077int genphy_config_eee_advert(struct phy_device *phydev);
00db8189 1078int genphy_config_aneg(struct phy_device *phydev);
a9fa6e6a 1079int genphy_aneg_done(struct phy_device *phydev);
00db8189
AF
1080int genphy_update_link(struct phy_device *phydev);
1081int genphy_read_status(struct phy_device *phydev);
0f0ca340
GC
1082int genphy_suspend(struct phy_device *phydev);
1083int genphy_resume(struct phy_device *phydev);
f0f9b4ed 1084int genphy_loopback(struct phy_device *phydev, bool enable);
797ac071 1085int genphy_soft_reset(struct phy_device *phydev);
0878fff1
FF
1086static inline int genphy_no_soft_reset(struct phy_device *phydev)
1087{
1088 return 0;
1089}
4c8e0459
LW
1090static inline int genphy_no_ack_interrupt(struct phy_device *phydev)
1091{
1092 return 0;
1093}
1094static inline int genphy_no_config_intr(struct phy_device *phydev)
1095{
1096 return 0;
1097}
5df7af85
KH
1098int genphy_read_mmd_unsupported(struct phy_device *phdev, int devad,
1099 u16 regnum);
1100int genphy_write_mmd_unsupported(struct phy_device *phdev, int devnum,
1101 u16 regnum, u16 val);
5acde34a
RK
1102
1103/* Clause 45 PHY */
1104int genphy_c45_restart_aneg(struct phy_device *phydev);
1af9f168 1105int genphy_c45_check_and_restart_aneg(struct phy_device *phydev, bool restart);
5acde34a 1106int genphy_c45_aneg_done(struct phy_device *phydev);
998a8a83 1107int genphy_c45_read_link(struct phy_device *phydev);
5acde34a
RK
1108int genphy_c45_read_lpa(struct phy_device *phydev);
1109int genphy_c45_read_pma(struct phy_device *phydev);
1110int genphy_c45_pma_setup_forced(struct phy_device *phydev);
9a5dc8af 1111int genphy_c45_an_config_aneg(struct phy_device *phydev);
5acde34a 1112int genphy_c45_an_disable_aneg(struct phy_device *phydev);
ea4efe25 1113int genphy_c45_read_mdix(struct phy_device *phydev);
ac3f5533 1114int genphy_c45_pma_read_abilities(struct phy_device *phydev);
70fa3a96 1115int genphy_c45_read_status(struct phy_device *phydev);
5acde34a 1116
e8a714e0
FF
1117/* The gen10g_* functions are the old Clause 45 stub */
1118int gen10g_config_aneg(struct phy_device *phydev);
e8a714e0 1119
00fde795
HK
1120static inline int phy_read_status(struct phy_device *phydev)
1121{
1122 if (!phydev->drv)
1123 return -EIO;
1124
1125 if (phydev->drv->read_status)
1126 return phydev->drv->read_status(phydev);
1127 else
1128 return genphy_read_status(phydev);
1129}
1130
00db8189 1131void phy_driver_unregister(struct phy_driver *drv);
d5bf9071 1132void phy_drivers_unregister(struct phy_driver *drv, int n);
be01da72
AL
1133int phy_driver_register(struct phy_driver *new_driver, struct module *owner);
1134int phy_drivers_register(struct phy_driver *new_driver, int n,
1135 struct module *owner);
4f9c85a1 1136void phy_state_machine(struct work_struct *work);
28b2e0d2 1137void phy_mac_interrupt(struct phy_device *phydev);
29935aeb 1138void phy_start_machine(struct phy_device *phydev);
00db8189
AF
1139void phy_stop_machine(struct phy_device *phydev);
1140int phy_ethtool_sset(struct phy_device *phydev, struct ethtool_cmd *cmd);
5514174f 1141void phy_ethtool_ksettings_get(struct phy_device *phydev,
1142 struct ethtool_link_ksettings *cmd);
2d55173e
PR
1143int phy_ethtool_ksettings_set(struct phy_device *phydev,
1144 const struct ethtool_link_ksettings *cmd);
4017b4d3 1145int phy_mii_ioctl(struct phy_device *phydev, struct ifreq *ifr, int cmd);
434a4315 1146void phy_request_interrupt(struct phy_device *phydev);
e1393456 1147void phy_print_status(struct phy_device *phydev);
f3a6bd39 1148int phy_set_max_speed(struct phy_device *phydev, u32 max_speed);
41124fa6 1149void phy_remove_link_mode(struct phy_device *phydev, u32 link_mode);
22c0ef6b 1150void phy_advertise_supported(struct phy_device *phydev);
c306ad36 1151void phy_support_sym_pause(struct phy_device *phydev);
af8d9bb2 1152void phy_support_asym_pause(struct phy_device *phydev);
0c122405
AL
1153void phy_set_sym_pause(struct phy_device *phydev, bool rx, bool tx,
1154 bool autoneg);
70814e81 1155void phy_set_asym_pause(struct phy_device *phydev, bool rx, bool tx);
22b7d299
AL
1156bool phy_validate_pause(struct phy_device *phydev,
1157 struct ethtool_pauseparam *pp);
00db8189 1158
f62220d3 1159int phy_register_fixup(const char *bus_id, u32 phy_uid, u32 phy_uid_mask,
4017b4d3 1160 int (*run)(struct phy_device *));
f62220d3 1161int phy_register_fixup_for_id(const char *bus_id,
4017b4d3 1162 int (*run)(struct phy_device *));
f62220d3 1163int phy_register_fixup_for_uid(u32 phy_uid, u32 phy_uid_mask,
4017b4d3 1164 int (*run)(struct phy_device *));
f62220d3 1165
f38e7a32
WH
1166int phy_unregister_fixup(const char *bus_id, u32 phy_uid, u32 phy_uid_mask);
1167int phy_unregister_fixup_for_id(const char *bus_id);
1168int phy_unregister_fixup_for_uid(u32 phy_uid, u32 phy_uid_mask);
1169
a59a4d19
GC
1170int phy_init_eee(struct phy_device *phydev, bool clk_stop_enable);
1171int phy_get_eee_err(struct phy_device *phydev);
1172int phy_ethtool_set_eee(struct phy_device *phydev, struct ethtool_eee *data);
1173int phy_ethtool_get_eee(struct phy_device *phydev, struct ethtool_eee *data);
42e836eb 1174int phy_ethtool_set_wol(struct phy_device *phydev, struct ethtool_wolinfo *wol);
4017b4d3
SS
1175void phy_ethtool_get_wol(struct phy_device *phydev,
1176 struct ethtool_wolinfo *wol);
9d9a77ce
PR
1177int phy_ethtool_get_link_ksettings(struct net_device *ndev,
1178 struct ethtool_link_ksettings *cmd);
1179int phy_ethtool_set_link_ksettings(struct net_device *ndev,
1180 const struct ethtool_link_ksettings *cmd);
e86a8987 1181int phy_ethtool_nway_reset(struct net_device *ndev);
a59a4d19 1182
90eff909 1183#if IS_ENABLED(CONFIG_PHYLIB)
9b9a8bfc
AF
1184int __init mdio_bus_init(void);
1185void mdio_bus_exit(void);
9e8d438e
FF
1186#endif
1187
1188/* Inline function for use within net/core/ethtool.c (built-in) */
1189static inline int phy_ethtool_get_strings(struct phy_device *phydev, u8 *data)
c59530d0 1190{
9e8d438e
FF
1191 if (!phydev->drv)
1192 return -EIO;
1193
1194 mutex_lock(&phydev->lock);
1195 phydev->drv->get_strings(phydev, data);
1196 mutex_unlock(&phydev->lock);
1197
1198 return 0;
c59530d0
FF
1199}
1200
9e8d438e 1201static inline int phy_ethtool_get_sset_count(struct phy_device *phydev)
c59530d0 1202{
9e8d438e
FF
1203 int ret;
1204
1205 if (!phydev->drv)
1206 return -EIO;
1207
1208 if (phydev->drv->get_sset_count &&
1209 phydev->drv->get_strings &&
1210 phydev->drv->get_stats) {
1211 mutex_lock(&phydev->lock);
1212 ret = phydev->drv->get_sset_count(phydev);
1213 mutex_unlock(&phydev->lock);
1214
1215 return ret;
1216 }
1217
c59530d0
FF
1218 return -EOPNOTSUPP;
1219}
1220
9e8d438e
FF
1221static inline int phy_ethtool_get_stats(struct phy_device *phydev,
1222 struct ethtool_stats *stats, u64 *data)
c59530d0 1223{
9e8d438e
FF
1224 if (!phydev->drv)
1225 return -EIO;
1226
1227 mutex_lock(&phydev->lock);
1228 phydev->drv->get_stats(phydev, stats, data);
1229 mutex_unlock(&phydev->lock);
1230
1231 return 0;
c59530d0 1232}
9b9a8bfc 1233
00db8189 1234extern struct bus_type mdio_bus_type;
c31accd1 1235
648ea013
FF
1236struct mdio_board_info {
1237 const char *bus_id;
1238 char modalias[MDIO_NAME_SIZE];
1239 int mdio_addr;
1240 const void *platform_data;
1241};
1242
90eff909 1243#if IS_ENABLED(CONFIG_MDIO_DEVICE)
648ea013
FF
1244int mdiobus_register_board_info(const struct mdio_board_info *info,
1245 unsigned int n);
1246#else
1247static inline int mdiobus_register_board_info(const struct mdio_board_info *i,
1248 unsigned int n)
1249{
1250 return 0;
1251}
1252#endif
1253
1254
c31accd1
JH
1255/**
1256 * module_phy_driver() - Helper macro for registering PHY drivers
1257 * @__phy_drivers: array of PHY drivers to register
1258 *
1259 * Helper macro for PHY drivers which do not do anything special in module
1260 * init/exit. Each module may only use this macro once, and calling it
1261 * replaces module_init() and module_exit().
1262 */
1263#define phy_module_driver(__phy_drivers, __count) \
1264static int __init phy_module_init(void) \
1265{ \
be01da72 1266 return phy_drivers_register(__phy_drivers, __count, THIS_MODULE); \
c31accd1
JH
1267} \
1268module_init(phy_module_init); \
1269static void __exit phy_module_exit(void) \
1270{ \
1271 phy_drivers_unregister(__phy_drivers, __count); \
1272} \
1273module_exit(phy_module_exit)
1274
1275#define module_phy_driver(__phy_drivers) \
1276 phy_module_driver(__phy_drivers, ARRAY_SIZE(__phy_drivers))
1277
5db5ea99
FF
1278bool phy_driver_is_genphy(struct phy_device *phydev);
1279bool phy_driver_is_genphy_10g(struct phy_device *phydev);
1280
00db8189 1281#endif /* __PHY_H */