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2874c5fd 1/* SPDX-License-Identifier: GPL-2.0-or-later */
00db8189 2/*
00db8189 3 * Framework and drivers for configuring and reading different PHYs
d8de01b7 4 * Based on code in sungem_phy.c and (long-removed) gianfar_phy.c
00db8189
AF
5 *
6 * Author: Andy Fleming
7 *
8 * Copyright (c) 2004 Freescale Semiconductor, Inc.
00db8189
AF
9 */
10
11#ifndef __PHY_H
12#define __PHY_H
13
2220943a 14#include <linux/compiler.h>
00db8189 15#include <linux/spinlock.h>
13df29f6 16#include <linux/ethtool.h>
b31cdffa 17#include <linux/linkmode.h>
bac83c65 18#include <linux/mdio.h>
13df29f6 19#include <linux/mii.h>
4715f65f 20#include <linux/mii_timestamper.h>
3e3aaf64 21#include <linux/module.h>
13df29f6
MR
22#include <linux/timer.h>
23#include <linux/workqueue.h>
8626d3b4 24#include <linux/mod_devicetable.h>
080bb352 25#include <linux/u64_stats_sync.h>
9010f9de 26#include <linux/irqreturn.h>
bd971ff0 27#include <linux/iopoll.h>
63490847 28#include <linux/refcount.h>
00db8189 29
60063497 30#include <linux/atomic.h>
0ac49527 31
e9fbdf17 32#define PHY_DEFAULT_FEATURES (SUPPORTED_Autoneg | \
00db8189
AF
33 SUPPORTED_TP | \
34 SUPPORTED_MII)
35
e9fbdf17
FF
36#define PHY_10BT_FEATURES (SUPPORTED_10baseT_Half | \
37 SUPPORTED_10baseT_Full)
38
39#define PHY_100BT_FEATURES (SUPPORTED_100baseT_Half | \
40 SUPPORTED_100baseT_Full)
41
42#define PHY_1000BT_FEATURES (SUPPORTED_1000baseT_Half | \
00db8189
AF
43 SUPPORTED_1000baseT_Full)
44
719655a1
AL
45extern __ETHTOOL_DECLARE_LINK_MODE_MASK(phy_basic_features) __ro_after_init;
46extern __ETHTOOL_DECLARE_LINK_MODE_MASK(phy_basic_t1_features) __ro_after_init;
47extern __ETHTOOL_DECLARE_LINK_MODE_MASK(phy_gbit_features) __ro_after_init;
48extern __ETHTOOL_DECLARE_LINK_MODE_MASK(phy_gbit_fibre_features) __ro_after_init;
49extern __ETHTOOL_DECLARE_LINK_MODE_MASK(phy_gbit_all_ports_features) __ro_after_init;
50extern __ETHTOOL_DECLARE_LINK_MODE_MASK(phy_10gbit_features) __ro_after_init;
9e857a40 51extern __ETHTOOL_DECLARE_LINK_MODE_MASK(phy_10gbit_fec_features) __ro_after_init;
719655a1
AL
52extern __ETHTOOL_DECLARE_LINK_MODE_MASK(phy_10gbit_full_features) __ro_after_init;
53
54#define PHY_BASIC_FEATURES ((unsigned long *)&phy_basic_features)
55#define PHY_BASIC_T1_FEATURES ((unsigned long *)&phy_basic_t1_features)
56#define PHY_GBIT_FEATURES ((unsigned long *)&phy_gbit_features)
57#define PHY_GBIT_FIBRE_FEATURES ((unsigned long *)&phy_gbit_fibre_features)
58#define PHY_GBIT_ALL_PORTS_FEATURES ((unsigned long *)&phy_gbit_all_ports_features)
59#define PHY_10GBIT_FEATURES ((unsigned long *)&phy_10gbit_features)
9e857a40 60#define PHY_10GBIT_FEC_FEATURES ((unsigned long *)&phy_10gbit_fec_features)
719655a1 61#define PHY_10GBIT_FULL_FEATURES ((unsigned long *)&phy_10gbit_full_features)
e9fbdf17 62
54638c6e
DE
63extern const int phy_basic_ports_array[3];
64extern const int phy_fibre_port_array[1];
65extern const int phy_all_ports_features_array[7];
3c1bcc86
AL
66extern const int phy_10_100_features_array[4];
67extern const int phy_basic_t1_features_array[2];
68extern const int phy_gbit_features_array[2];
69extern const int phy_10gbit_features_array[1];
70
c5e38a94
AF
71/*
72 * Set phydev->irq to PHY_POLL if interrupts are not supported,
00db8189
AF
73 * or not desired for this PHY. Set to PHY_IGNORE_INTERRUPT if
74 * the attached driver handles the interrupt
75 */
76#define PHY_POLL -1
77#define PHY_IGNORE_INTERRUPT -2
78
a4307c0e
HK
79#define PHY_IS_INTERNAL 0x00000001
80#define PHY_RST_AFTER_CLK_EN 0x00000002
a9049e0c 81#define MDIO_DEVICE_IS_PHY 0x80000000
00db8189 82
e8a2b6a4
AF
83/* Interface Mode definitions */
84typedef enum {
4157ef1b 85 PHY_INTERFACE_MODE_NA,
735d8a18 86 PHY_INTERFACE_MODE_INTERNAL,
e8a2b6a4
AF
87 PHY_INTERFACE_MODE_MII,
88 PHY_INTERFACE_MODE_GMII,
89 PHY_INTERFACE_MODE_SGMII,
90 PHY_INTERFACE_MODE_TBI,
2cc70ba4 91 PHY_INTERFACE_MODE_REVMII,
e8a2b6a4
AF
92 PHY_INTERFACE_MODE_RMII,
93 PHY_INTERFACE_MODE_RGMII,
a999589c 94 PHY_INTERFACE_MODE_RGMII_ID,
7d400a4c
KP
95 PHY_INTERFACE_MODE_RGMII_RXID,
96 PHY_INTERFACE_MODE_RGMII_TXID,
4157ef1b
SG
97 PHY_INTERFACE_MODE_RTBI,
98 PHY_INTERFACE_MODE_SMII,
898dd0bd 99 PHY_INTERFACE_MODE_XGMII,
58b05e58 100 PHY_INTERFACE_MODE_XLGMII,
fd70f72c 101 PHY_INTERFACE_MODE_MOCA,
b9d12085 102 PHY_INTERFACE_MODE_QSGMII,
572de608 103 PHY_INTERFACE_MODE_TRGMII,
55601a88
AL
104 PHY_INTERFACE_MODE_1000BASEX,
105 PHY_INTERFACE_MODE_2500BASEX,
106 PHY_INTERFACE_MODE_RXAUI,
c125ca09 107 PHY_INTERFACE_MODE_XAUI,
c114574e
RK
108 /* 10GBASE-R, XFI, SFI - single lane 10G Serdes */
109 PHY_INTERFACE_MODE_10GBASER,
4618d671 110 PHY_INTERFACE_MODE_USXGMII,
c114574e
RK
111 /* 10GBASE-KR - with Clause 73 AN */
112 PHY_INTERFACE_MODE_10GKR,
8a2fe56e 113 PHY_INTERFACE_MODE_MAX,
e8a2b6a4
AF
114} phy_interface_t;
115
1f9127ca
ZB
116/**
117 * phy_supported_speeds - return all speeds currently supported by a phy device
118 * @phy: The phy device to return supported speeds of.
119 * @speeds: buffer to store supported speeds in.
120 * @size: size of speeds buffer.
121 *
d8de01b7
RD
122 * Description: Returns the number of supported speeds, and fills
123 * the speeds buffer with the supported speeds. If speeds buffer is
124 * too small to contain all currently supported speeds, will return as
1f9127ca
ZB
125 * many speeds as can fit.
126 */
127unsigned int phy_supported_speeds(struct phy_device *phy,
128 unsigned int *speeds,
129 unsigned int size);
130
8a2fe56e 131/**
d8de01b7
RD
132 * phy_modes - map phy_interface_t enum to device tree binding of phy-mode
133 * @interface: enum phy_interface_t value
134 *
135 * Description: maps 'enum phy_interface_t' defined in this file
8a2fe56e
FF
136 * into the device tree binding of 'phy-mode', so that Ethernet
137 * device driver can get phy interface from device tree.
138 */
139static inline const char *phy_modes(phy_interface_t interface)
140{
141 switch (interface) {
142 case PHY_INTERFACE_MODE_NA:
143 return "";
735d8a18
FF
144 case PHY_INTERFACE_MODE_INTERNAL:
145 return "internal";
8a2fe56e
FF
146 case PHY_INTERFACE_MODE_MII:
147 return "mii";
148 case PHY_INTERFACE_MODE_GMII:
149 return "gmii";
150 case PHY_INTERFACE_MODE_SGMII:
151 return "sgmii";
152 case PHY_INTERFACE_MODE_TBI:
153 return "tbi";
154 case PHY_INTERFACE_MODE_REVMII:
155 return "rev-mii";
156 case PHY_INTERFACE_MODE_RMII:
157 return "rmii";
158 case PHY_INTERFACE_MODE_RGMII:
159 return "rgmii";
160 case PHY_INTERFACE_MODE_RGMII_ID:
161 return "rgmii-id";
162 case PHY_INTERFACE_MODE_RGMII_RXID:
163 return "rgmii-rxid";
164 case PHY_INTERFACE_MODE_RGMII_TXID:
165 return "rgmii-txid";
166 case PHY_INTERFACE_MODE_RTBI:
167 return "rtbi";
168 case PHY_INTERFACE_MODE_SMII:
169 return "smii";
170 case PHY_INTERFACE_MODE_XGMII:
171 return "xgmii";
58b05e58
JA
172 case PHY_INTERFACE_MODE_XLGMII:
173 return "xlgmii";
fd70f72c
FF
174 case PHY_INTERFACE_MODE_MOCA:
175 return "moca";
b9d12085
TP
176 case PHY_INTERFACE_MODE_QSGMII:
177 return "qsgmii";
572de608
SW
178 case PHY_INTERFACE_MODE_TRGMII:
179 return "trgmii";
55601a88
AL
180 case PHY_INTERFACE_MODE_1000BASEX:
181 return "1000base-x";
182 case PHY_INTERFACE_MODE_2500BASEX:
183 return "2500base-x";
184 case PHY_INTERFACE_MODE_RXAUI:
185 return "rxaui";
c125ca09
RK
186 case PHY_INTERFACE_MODE_XAUI:
187 return "xaui";
c114574e
RK
188 case PHY_INTERFACE_MODE_10GBASER:
189 return "10gbase-r";
4618d671
HK
190 case PHY_INTERFACE_MODE_USXGMII:
191 return "usxgmii";
c114574e
RK
192 case PHY_INTERFACE_MODE_10GKR:
193 return "10gbase-kr";
8a2fe56e
FF
194 default:
195 return "unknown";
196 }
197}
198
00db8189 199
e8a2b6a4 200#define PHY_INIT_TIMEOUT 100000
00db8189 201#define PHY_FORCE_TIMEOUT 10
00db8189 202
e8a2b6a4 203#define PHY_MAX_ADDR 32
00db8189 204
a4d00f17 205/* Used when trying to connect to a specific phy (mii bus id:phy device id) */
9d9326d3
AF
206#define PHY_ID_FMT "%s:%02x"
207
4567d686 208#define MII_BUS_ID_SIZE 61
a4d00f17 209
abf35df2
JG
210/* Or MII_ADDR_C45 into regnum for read/write on mii_bus to enable the 21 bit
211 IEEE 802.3ae clause 45 addressing mode used by 10GIGE phy chips. */
212#define MII_ADDR_C45 (1<<30)
d4117d63
KHL
213#define MII_DEVADDR_C45_SHIFT 16
214#define MII_REGADDR_C45_MASK GENMASK(15, 0)
abf35df2 215
313162d0 216struct device;
9525ae83 217struct phylink;
298e54fa
RK
218struct sfp_bus;
219struct sfp_upstream_ops;
313162d0
PG
220struct sk_buff;
221
080bb352
FF
222struct mdio_bus_stats {
223 u64_stats_t transfers;
224 u64_stats_t errors;
225 u64_stats_t writes;
226 u64_stats_t reads;
227 /* Must be last, add new statistics above */
228 struct u64_stats_sync syncp;
229};
230
63490847
MW
231/* Represents a shared structure between different phydev's in the same
232 * package, for example a quad PHY. See phy_package_join() and
233 * phy_package_leave().
234 */
235struct phy_package_shared {
236 int addr;
237 refcount_t refcnt;
238 unsigned long flags;
239 size_t priv_size;
240
241 /* private data pointer */
242 /* note that this pointer is shared between different phydevs and
243 * the user has to take care of appropriate locking. It is allocated
244 * and freed automatically by phy_package_join() and
245 * phy_package_leave().
246 */
247 void *priv;
248};
249
250/* used as bit number in atomic bitops */
251#define PHY_SHARED_F_INIT_DONE 0
252
c5e38a94
AF
253/*
254 * The Bus class for PHYs. Devices which provide access to
255 * PHYs should register using this structure
256 */
00db8189 257struct mii_bus {
3e3aaf64 258 struct module *owner;
00db8189 259 const char *name;
9d9326d3 260 char id[MII_BUS_ID_SIZE];
00db8189 261 void *priv;
ccaa953e
AL
262 int (*read)(struct mii_bus *bus, int addr, int regnum);
263 int (*write)(struct mii_bus *bus, int addr, int regnum, u16 val);
00db8189 264 int (*reset)(struct mii_bus *bus);
080bb352 265 struct mdio_bus_stats stats[PHY_MAX_ADDR];
00db8189 266
38f961e7
HK
267 unsigned int is_managed:1; /* is device-managed */
268 unsigned int is_managed_registered:1;
269
c5e38a94
AF
270 /*
271 * A lock to ensure that only one thing can read/write
272 * the MDIO bus at a time
273 */
35b5f6b1 274 struct mutex mdio_lock;
00db8189 275
18ee49dd 276 struct device *parent;
46abc021
LB
277 enum {
278 MDIOBUS_ALLOCATED = 1,
279 MDIOBUS_REGISTERED,
280 MDIOBUS_UNREGISTERED,
281 MDIOBUS_RELEASED,
282 } state;
283 struct device dev;
00db8189
AF
284
285 /* list of all PHYs on bus */
7f854420 286 struct mdio_device *mdio_map[PHY_MAX_ADDR];
00db8189 287
c6883996 288 /* PHY addresses to be ignored when probing */
f896424c
MP
289 u32 phy_mask;
290
922f2dd1
FF
291 /* PHY addresses to ignore the TA/read failure */
292 u32 phy_ignore_ta_mask;
293
c5e38a94 294 /*
e7f4dc35
AL
295 * An array of interrupts, each PHY's interrupt at the index
296 * matching its address
c5e38a94 297 */
e7f4dc35 298 int irq[PHY_MAX_ADDR];
69226896
RQ
299
300 /* GPIO reset pulse width in microseconds */
301 int reset_delay_us;
d396e84c
SS
302 /* RESET GPIO descriptor pointer */
303 struct gpio_desc *reset_gpiod;
63490847
MW
304
305 /* protect access to the shared element */
306 struct mutex shared_lock;
307
308 /* shared state across different PHYs */
309 struct phy_package_shared *shared[PHY_MAX_ADDR];
00db8189 310};
46abc021 311#define to_mii_bus(d) container_of(d, struct mii_bus, dev)
00db8189 312
eb8a54a7
TT
313struct mii_bus *mdiobus_alloc_size(size_t);
314static inline struct mii_bus *mdiobus_alloc(void)
315{
316 return mdiobus_alloc_size(0);
317}
318
3e3aaf64
RK
319int __mdiobus_register(struct mii_bus *bus, struct module *owner);
320#define mdiobus_register(bus) __mdiobus_register(bus, THIS_MODULE)
38f961e7
HK
321static inline int devm_mdiobus_register(struct mii_bus *bus)
322{
323 int ret;
324
325 if (!bus->is_managed)
326 return -EPERM;
327
328 ret = mdiobus_register(bus);
329 if (!ret)
330 bus->is_managed_registered = 1;
331
332 return ret;
333}
334
2e888103
LB
335void mdiobus_unregister(struct mii_bus *bus);
336void mdiobus_free(struct mii_bus *bus);
6d48f44b
GS
337struct mii_bus *devm_mdiobus_alloc_size(struct device *dev, int sizeof_priv);
338static inline struct mii_bus *devm_mdiobus_alloc(struct device *dev)
339{
340 return devm_mdiobus_alloc_size(dev, 0);
341}
342
ce69e216 343struct mii_bus *mdio_find_bus(const char *mdio_name);
6d48f44b 344void devm_mdiobus_free(struct device *dev, struct mii_bus *bus);
2e888103 345struct phy_device *mdiobus_scan(struct mii_bus *bus, int addr);
2e888103 346
695bce8f
HK
347#define PHY_INTERRUPT_DISABLED false
348#define PHY_INTERRUPT_ENABLED true
00db8189
AF
349
350/* PHY state machine states:
351 *
352 * DOWN: PHY device and driver are not ready for anything. probe
353 * should be called if and only if the PHY is in this state,
354 * given that the PHY device exists.
899a3cbb 355 * - PHY driver probe function will set the state to READY
00db8189
AF
356 *
357 * READY: PHY is ready to send and receive packets, but the
358 * controller is not. By default, PHYs which do not implement
899a3cbb 359 * probe will be set to this state by phy_probe().
00db8189
AF
360 * - start will set the state to UP
361 *
00db8189
AF
362 * UP: The PHY and attached device are ready to do work.
363 * Interrupts should be started here.
85a1f31d 364 * - timer moves to NOLINK or RUNNING
00db8189
AF
365 *
366 * NOLINK: PHY is up, but not currently plugged in.
8deeb630 367 * - irq or timer will set RUNNING if link comes back
00db8189
AF
368 * - phy_stop moves to HALTED
369 *
00db8189
AF
370 * RUNNING: PHY is currently up, running, and possibly sending
371 * and/or receiving packets
8deeb630 372 * - irq or timer will set NOLINK if link goes down
00db8189
AF
373 * - phy_stop moves to HALTED
374 *
00db8189
AF
375 * HALTED: PHY is up, but no polling or interrupts are done. Or
376 * PHY is in an error state.
f24098f8 377 * - phy_start moves to UP
00db8189
AF
378 */
379enum phy_state {
4017b4d3 380 PHY_DOWN = 0,
00db8189 381 PHY_READY,
2b3e88ea 382 PHY_HALTED,
00db8189 383 PHY_UP,
00db8189
AF
384 PHY_RUNNING,
385 PHY_NOLINK,
00db8189
AF
386};
387
ac28b9f8
DD
388/**
389 * struct phy_c45_device_ids - 802.3-c45 Device Identifiers
390 * @devices_in_package: Bit vector of devices present.
391 * @device_ids: The device identifer for each present device.
392 */
393struct phy_c45_device_ids {
394 u32 devices_in_package;
395 u32 device_ids[8];
396};
c1f19b51 397
76564261 398struct macsec_context;
2e181358 399struct macsec_ops;
76564261 400
00db8189
AF
401/* phy_device: An instance of a PHY
402 *
403 * drv: Pointer to the driver for this PHY instance
00db8189 404 * phy_id: UID for this device found during discovery
ac28b9f8
DD
405 * c45_ids: 802.3-c45 Device Identifers if is_c45.
406 * is_c45: Set to true if this phy uses clause 45 addressing.
4284b6a5 407 * is_internal: Set to true if this phy is internal to a MAC.
5a11dd7d 408 * is_pseudo_fixed_link: Set to true if this phy is an Ethernet switch, etc.
3b8b11f9 409 * is_gigabit_capable: Set to true if PHY supports 1000Mbps
aae88261 410 * has_fixups: Set to true if this phy has fixups/quirks.
8a477a6f 411 * suspended: Set to true if this phy has been suspended successfully.
611d779a 412 * suspended_by_mdio_bus: Set to true if this phy was suspended by MDIO bus.
a3995460 413 * sysfs_links: Internal boolean tracking sysfs symbolic links setup/removal.
f0f9b4ed 414 * loopback_enabled: Set true if this phy has been loopbacked successfully.
5eee3bb7 415 * downshifted_rate: Set true if link speed has been downshifted.
00db8189
AF
416 * state: state of the PHY for management purposes
417 * dev_flags: Device-specific flags used by the PHY driver.
00db8189
AF
418 * irq: IRQ number of the PHY's interrupt (-1 if none)
419 * phy_timer: The timer for handling the state machine
298e54fa
RK
420 * sfp_bus_attached: flag indicating whether the SFP bus has been attached
421 * sfp_bus: SFP bus attached to this PHY's fiber port
00db8189
AF
422 * attached_dev: The attached enet driver's device instance ptr
423 * adjust_link: Callback for the enet controller to respond to
424 * changes in the link state.
2e181358 425 * macsec_ops: MACsec offloading ops.
00db8189 426 *
114002bc
FF
427 * speed, duplex, pause, supported, advertising, lp_advertising,
428 * and autoneg are used like in mii_if_info
00db8189
AF
429 *
430 * interrupts currently only supports enabled or disabled,
431 * but could be changed in the future to support enabling
432 * and disabling specific interrupts
433 *
434 * Contains some infrastructure for polling and interrupt
435 * handling, as well as handling shifts in PHY hardware state
436 */
437struct phy_device {
e5a03bfd
AL
438 struct mdio_device mdio;
439
00db8189
AF
440 /* Information about the PHY type */
441 /* And management functions */
442 struct phy_driver *drv;
443
00db8189
AF
444 u32 phy_id;
445
ac28b9f8 446 struct phy_c45_device_ids c45_ids;
87e5808d
HK
447 unsigned is_c45:1;
448 unsigned is_internal:1;
449 unsigned is_pseudo_fixed_link:1;
3b8b11f9 450 unsigned is_gigabit_capable:1;
87e5808d
HK
451 unsigned has_fixups:1;
452 unsigned suspended:1;
611d779a 453 unsigned suspended_by_mdio_bus:1;
87e5808d
HK
454 unsigned sysfs_links:1;
455 unsigned loopback_enabled:1;
5eee3bb7 456 unsigned downshifted_rate:1;
87e5808d
HK
457
458 unsigned autoneg:1;
459 /* The most recently read link state */
460 unsigned link:1;
4950c2ba 461 unsigned autoneg_complete:1;
ac28b9f8 462
695bce8f
HK
463 /* Interrupts are enabled */
464 unsigned interrupts:1;
465
00db8189
AF
466 enum phy_state state;
467
468 u32 dev_flags;
469
e8a2b6a4
AF
470 phy_interface_t interface;
471
c5e38a94
AF
472 /*
473 * forced speed & duplex (no autoneg)
00db8189
AF
474 * partner speed & duplex & pause (autoneg)
475 */
476 int speed;
477 int duplex;
478 int pause;
479 int asym_pause;
bdbdac76
OR
480 u8 master_slave_get;
481 u8 master_slave_set;
482 u8 master_slave_state;
00db8189 483
3c1bcc86
AL
484 /* Union of PHY and Attached devices' supported link modes */
485 /* See ethtool.h for more info */
486 __ETHTOOL_DECLARE_LINK_MODE_MASK(supported);
487 __ETHTOOL_DECLARE_LINK_MODE_MASK(advertising);
c0ec3c27 488 __ETHTOOL_DECLARE_LINK_MODE_MASK(lp_advertising);
65b27995
HK
489 /* used with phy_speed_down */
490 __ETHTOOL_DECLARE_LINK_MODE_MASK(adv_old);
00db8189 491
d853d145 492 /* Energy efficient ethernet modes which should be prohibited */
493 u32 eee_broken_modes;
494
2e0bc452
ZB
495#ifdef CONFIG_LED_TRIGGER_PHY
496 struct phy_led_trigger *phy_led_triggers;
497 unsigned int phy_num_led_triggers;
498 struct phy_led_trigger *last_triggered;
3928ee64
MS
499
500 struct phy_led_trigger *led_link_trigger;
2e0bc452
ZB
501#endif
502
c5e38a94
AF
503 /*
504 * Interrupt number for this PHY
505 * -1 means no interrupt
506 */
00db8189
AF
507 int irq;
508
509 /* private data pointer */
510 /* For use by PHYs to maintain extra state */
511 void *priv;
512
63490847
MW
513 /* shared data pointer */
514 /* For use by PHYs inside the same package that need a shared state. */
515 struct phy_package_shared *shared;
516
00db8189 517 /* Interrupt and Polling infrastructure */
a390d1f3 518 struct delayed_work state_queue;
00db8189 519
35b5f6b1 520 struct mutex lock;
00db8189 521
298e54fa
RK
522 /* This may be modified under the rtnl lock */
523 bool sfp_bus_attached;
524 struct sfp_bus *sfp_bus;
9525ae83 525 struct phylink *phylink;
00db8189 526 struct net_device *attached_dev;
4715f65f 527 struct mii_timestamper *mii_ts;
00db8189 528
634ec36c 529 u8 mdix;
f4ed2fe3 530 u8 mdix_ctrl;
634ec36c 531
a81497be 532 void (*phy_link_change)(struct phy_device *, bool up, bool do_carrier);
00db8189 533 void (*adjust_link)(struct net_device *dev);
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534
535#if IS_ENABLED(CONFIG_MACSEC)
536 /* MACsec management functions */
537 const struct macsec_ops *macsec_ops;
538#endif
00db8189 539};
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540#define to_phy_device(d) container_of(to_mdio_device(d), \
541 struct phy_device, mdio)
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542
543/* struct phy_driver: Driver structure for a particular PHY type
544 *
a9049e0c 545 * driver_data: static driver data
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546 * phy_id: The result of reading the UID registers of this PHY
547 * type, and ANDing them with the phy_id_mask. This driver
548 * only works for PHYs with IDs which match this field
549 * name: The friendly name of this PHY type
550 * phy_id_mask: Defines the important bits of the phy_id
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551 * features: A mandatory list of features (speed, duplex, etc)
552 * supported by this PHY
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553 * flags: A bitfield defining certain other features this PHY
554 * supports (like interrupts)
555 *
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556 * All functions are optional. If config_aneg or read_status
557 * are not implemented, the phy core uses the genphy versions.
558 * Note that none of these functions should be called from
559 * interrupt time. The goal is for the bus read/write functions
560 * to be able to block when the bus transaction is happening,
561 * and be freed up by an interrupt (The MPC85xx has this ability,
562 * though it is not currently supported in the driver).
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563 */
564struct phy_driver {
a9049e0c 565 struct mdio_driver_common mdiodrv;
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566 u32 phy_id;
567 char *name;
511e3036 568 u32 phy_id_mask;
719655a1 569 const unsigned long * const features;
00db8189 570 u32 flags;
860f6e9e 571 const void *driver_data;
00db8189 572
c5e38a94 573 /*
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574 * Called to issue a PHY software reset
575 */
576 int (*soft_reset)(struct phy_device *phydev);
577
578 /*
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579 * Called to initialize the PHY,
580 * including after a reset
581 */
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582 int (*config_init)(struct phy_device *phydev);
583
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584 /*
585 * Called during discovery. Used to set
586 * up device-specific structures, if any
587 */
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588 int (*probe)(struct phy_device *phydev);
589
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590 /*
591 * Probe the hardware to determine what abilities it has.
592 * Should only set phydev->supported.
593 */
594 int (*get_features)(struct phy_device *phydev);
595
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596 /* PHY Power Management */
597 int (*suspend)(struct phy_device *phydev);
598 int (*resume)(struct phy_device *phydev);
599
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600 /*
601 * Configures the advertisement and resets
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602 * autonegotiation if phydev->autoneg is on,
603 * forces the speed to the current settings in phydev
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604 * if phydev->autoneg is off
605 */
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606 int (*config_aneg)(struct phy_device *phydev);
607
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608 /* Determines the auto negotiation result */
609 int (*aneg_done)(struct phy_device *phydev);
610
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611 /* Determines the negotiated speed and duplex */
612 int (*read_status)(struct phy_device *phydev);
613
614 /* Clears any pending interrupts */
615 int (*ack_interrupt)(struct phy_device *phydev);
616
617 /* Enables or disables interrupts */
618 int (*config_intr)(struct phy_device *phydev);
619
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620 /*
621 * Checks if the PHY generated an interrupt.
622 * For multi-PHY devices with shared PHY interrupt pin
249bc974 623 * Set interrupt bits have to be cleared.
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624 */
625 int (*did_interrupt)(struct phy_device *phydev);
626
49644e68 627 /* Override default interrupt handling */
9010f9de 628 irqreturn_t (*handle_interrupt)(struct phy_device *phydev);
49644e68 629
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630 /* Clears up any memory if needed */
631 void (*remove)(struct phy_device *phydev);
632
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633 /* Returns true if this is a suitable driver for the given
634 * phydev. If NULL, matching is based on phy_id and
635 * phy_id_mask.
636 */
637 int (*match_phy_device)(struct phy_device *phydev);
638
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639 /* Some devices (e.g. qnap TS-119P II) require PHY register changes to
640 * enable Wake on LAN, so set_wol is provided to be called in the
641 * ethernet driver's set_wol function. */
642 int (*set_wol)(struct phy_device *dev, struct ethtool_wolinfo *wol);
643
644 /* See set_wol, but for checking whether Wake on LAN is enabled. */
645 void (*get_wol)(struct phy_device *dev, struct ethtool_wolinfo *wol);
646
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647 /*
648 * Called to inform a PHY device driver when the core is about to
649 * change the link state. This callback is supposed to be used as
650 * fixup hook for drivers that need to take action when the link
651 * state changes. Drivers are by no means allowed to mess with the
652 * PHY device structure in their implementations.
653 */
654 void (*link_change_notify)(struct phy_device *dev);
655
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656 /*
657 * Phy specific driver override for reading a MMD register.
658 * This function is optional for PHY specific drivers. When
659 * not provided, the default MMD read function will be used
660 * by phy_read_mmd(), which will use either a direct read for
661 * Clause 45 PHYs or an indirect read for Clause 22 PHYs.
662 * devnum is the MMD device number within the PHY device,
663 * regnum is the register within the selected MMD device.
664 */
665 int (*read_mmd)(struct phy_device *dev, int devnum, u16 regnum);
666
667 /*
668 * Phy specific driver override for writing a MMD register.
669 * This function is optional for PHY specific drivers. When
670 * not provided, the default MMD write function will be used
671 * by phy_write_mmd(), which will use either a direct write for
672 * Clause 45 PHYs, or an indirect write for Clause 22 PHYs.
673 * devnum is the MMD device number within the PHY device,
674 * regnum is the register within the selected MMD device.
675 * val is the value to be written.
676 */
677 int (*write_mmd)(struct phy_device *dev, int devnum, u16 regnum,
678 u16 val);
679
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680 int (*read_page)(struct phy_device *dev);
681 int (*write_page)(struct phy_device *dev, int page);
682
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683 /* Get the size and type of the eeprom contained within a plug-in
684 * module */
685 int (*module_info)(struct phy_device *dev,
686 struct ethtool_modinfo *modinfo);
687
688 /* Get the eeprom information from the plug-in module */
689 int (*module_eeprom)(struct phy_device *dev,
690 struct ethtool_eeprom *ee, u8 *data);
691
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692 /* Get statistics from the phy using ethtool */
693 int (*get_sset_count)(struct phy_device *dev);
694 void (*get_strings)(struct phy_device *dev, u8 *data);
695 void (*get_stats)(struct phy_device *dev,
696 struct ethtool_stats *stats, u64 *data);
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697
698 /* Get and Set PHY tunables */
699 int (*get_tunable)(struct phy_device *dev,
700 struct ethtool_tunable *tuna, void *data);
701 int (*set_tunable)(struct phy_device *dev,
702 struct ethtool_tunable *tuna,
703 const void *data);
f0f9b4ed 704 int (*set_loopback)(struct phy_device *dev, bool enable);
00db8189 705};
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706#define to_phy_driver(d) container_of(to_mdio_common_driver(d), \
707 struct phy_driver, mdiodrv)
00db8189 708
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709#define PHY_ANY_ID "MATCH ANY PHY"
710#define PHY_ANY_UID 0xffffffff
711
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712#define PHY_ID_MATCH_EXACT(id) .phy_id = (id), .phy_id_mask = GENMASK(31, 0)
713#define PHY_ID_MATCH_MODEL(id) .phy_id = (id), .phy_id_mask = GENMASK(31, 4)
714#define PHY_ID_MATCH_VENDOR(id) .phy_id = (id), .phy_id_mask = GENMASK(31, 10)
715
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716/* A Structure for boards to register fixups with the PHY Lib */
717struct phy_fixup {
718 struct list_head list;
4567d686 719 char bus_id[MII_BUS_ID_SIZE + 3];
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720 u32 phy_uid;
721 u32 phy_uid_mask;
722 int (*run)(struct phy_device *phydev);
723};
724
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725const char *phy_speed_to_str(int speed);
726const char *phy_duplex_to_str(unsigned int duplex);
727
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728/* A structure for mapping a particular speed and duplex
729 * combination to a particular SUPPORTED and ADVERTISED value
730 */
731struct phy_setting {
732 u32 speed;
733 u8 duplex;
734 u8 bit;
735};
736
737const struct phy_setting *
738phy_lookup_setting(int speed, int duplex, const unsigned long *mask,
3c1bcc86 739 bool exact);
0ccb4fc6 740size_t phy_speeds(unsigned int *speeds, size_t size,
3c1bcc86 741 unsigned long *mask);
a4eaed9f 742void of_set_phy_supported(struct phy_device *phydev);
3feb9b23 743void of_set_phy_eee_broken(struct phy_device *phydev);
331c56ac 744int phy_speed_down_core(struct phy_device *phydev);
0ccb4fc6 745
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746/**
747 * phy_is_started - Convenience function to check whether PHY is started
748 * @phydev: The phy_device struct
749 */
750static inline bool phy_is_started(struct phy_device *phydev)
751{
a2fc9d7e 752 return phydev->state >= PHY_UP;
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753}
754
2d880b87 755void phy_resolve_aneg_pause(struct phy_device *phydev);
8c5e850c 756void phy_resolve_aneg_linkmode(struct phy_device *phydev);
5eee3bb7 757void phy_check_downshift(struct phy_device *phydev);
8c5e850c 758
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759/**
760 * phy_read - Convenience function for reading a given PHY register
761 * @phydev: the phy_device struct
762 * @regnum: register number to read
763 *
764 * NOTE: MUST NOT be called from interrupt context,
765 * because the bus read/write functions may wait for an interrupt
766 * to conclude the operation.
767 */
abf35df2 768static inline int phy_read(struct phy_device *phydev, u32 regnum)
2e888103 769{
e5a03bfd 770 return mdiobus_read(phydev->mdio.bus, phydev->mdio.addr, regnum);
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771}
772
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773#define phy_read_poll_timeout(phydev, regnum, val, cond, sleep_us, \
774 timeout_us, sleep_before_read) \
775({ \
776 int __ret = read_poll_timeout(phy_read, val, (cond) || val < 0, \
777 sleep_us, timeout_us, sleep_before_read, phydev, regnum); \
778 if (val < 0) \
779 __ret = val; \
780 if (__ret) \
781 phydev_err(phydev, "%s failed: %d\n", __func__, __ret); \
782 __ret; \
783})
784
785
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786/**
787 * __phy_read - convenience function for reading a given PHY register
788 * @phydev: the phy_device struct
789 * @regnum: register number to read
790 *
791 * The caller must have taken the MDIO bus lock.
792 */
793static inline int __phy_read(struct phy_device *phydev, u32 regnum)
794{
795 return __mdiobus_read(phydev->mdio.bus, phydev->mdio.addr, regnum);
796}
797
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798/**
799 * phy_write - Convenience function for writing a given PHY register
800 * @phydev: the phy_device struct
801 * @regnum: register number to write
802 * @val: value to write to @regnum
803 *
804 * NOTE: MUST NOT be called from interrupt context,
805 * because the bus read/write functions may wait for an interrupt
806 * to conclude the operation.
807 */
abf35df2 808static inline int phy_write(struct phy_device *phydev, u32 regnum, u16 val)
2e888103 809{
e5a03bfd 810 return mdiobus_write(phydev->mdio.bus, phydev->mdio.addr, regnum, val);
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811}
812
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813/**
814 * __phy_write - Convenience function for writing a given PHY register
815 * @phydev: the phy_device struct
816 * @regnum: register number to write
817 * @val: value to write to @regnum
818 *
819 * The caller must have taken the MDIO bus lock.
820 */
821static inline int __phy_write(struct phy_device *phydev, u32 regnum, u16 val)
822{
823 return __mdiobus_write(phydev->mdio.bus, phydev->mdio.addr, regnum,
824 val);
825}
826
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827/**
828 * __phy_modify_changed() - Convenience function for modifying a PHY register
829 * @phydev: a pointer to a &struct phy_device
830 * @regnum: register number
831 * @mask: bit mask of bits to clear
832 * @set: bit mask of bits to set
833 *
834 * Unlocked helper function which allows a PHY register to be modified as
835 * new register value = (old register value & ~mask) | set
836 *
837 * Returns negative errno, 0 if there was no change, and 1 in case of change
838 */
839static inline int __phy_modify_changed(struct phy_device *phydev, u32 regnum,
840 u16 mask, u16 set)
841{
842 return __mdiobus_modify_changed(phydev->mdio.bus, phydev->mdio.addr,
843 regnum, mask, set);
844}
845
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846/**
847 * phy_read_mmd - Convenience function for reading a register
848 * from an MMD on a given PHY.
849 * @phydev: The phy_device struct
850 * @devad: The MMD to read from
851 * @regnum: The register on the MMD to read
852 *
853 * Same rules as for phy_read();
854 */
855int phy_read_mmd(struct phy_device *phydev, int devad, u32 regnum);
856
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857#define phy_read_mmd_poll_timeout(phydev, devaddr, regnum, val, cond, \
858 sleep_us, timeout_us, sleep_before_read) \
859({ \
860 int __ret = read_poll_timeout(phy_read_mmd, val, (cond) || val < 0, \
861 sleep_us, timeout_us, sleep_before_read, \
862 phydev, devaddr, regnum); \
863 if (val < 0) \
864 __ret = val; \
865 if (__ret) \
866 phydev_err(phydev, "%s failed: %d\n", __func__, __ret); \
867 __ret; \
868})
869
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870/**
871 * __phy_read_mmd - Convenience function for reading a register
872 * from an MMD on a given PHY.
873 * @phydev: The phy_device struct
874 * @devad: The MMD to read from
875 * @regnum: The register on the MMD to read
876 *
877 * Same rules as for __phy_read();
878 */
879int __phy_read_mmd(struct phy_device *phydev, int devad, u32 regnum);
880
881/**
882 * phy_write_mmd - Convenience function for writing a register
883 * on an MMD on a given PHY.
884 * @phydev: The phy_device struct
885 * @devad: The MMD to write to
886 * @regnum: The register on the MMD to read
887 * @val: value to write to @regnum
888 *
889 * Same rules as for phy_write();
890 */
891int phy_write_mmd(struct phy_device *phydev, int devad, u32 regnum, u16 val);
892
893/**
894 * __phy_write_mmd - Convenience function for writing a register
895 * on an MMD on a given PHY.
896 * @phydev: The phy_device struct
897 * @devad: The MMD to write to
898 * @regnum: The register on the MMD to read
899 * @val: value to write to @regnum
900 *
901 * Same rules as for __phy_write();
902 */
903int __phy_write_mmd(struct phy_device *phydev, int devad, u32 regnum, u16 val);
904
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905int __phy_modify_changed(struct phy_device *phydev, u32 regnum, u16 mask,
906 u16 set);
907int phy_modify_changed(struct phy_device *phydev, u32 regnum, u16 mask,
908 u16 set);
788f9933 909int __phy_modify(struct phy_device *phydev, u32 regnum, u16 mask, u16 set);
2b74e5be 910int phy_modify(struct phy_device *phydev, u32 regnum, u16 mask, u16 set);
788f9933 911
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912int __phy_modify_mmd_changed(struct phy_device *phydev, int devad, u32 regnum,
913 u16 mask, u16 set);
914int phy_modify_mmd_changed(struct phy_device *phydev, int devad, u32 regnum,
915 u16 mask, u16 set);
1878f0dc 916int __phy_modify_mmd(struct phy_device *phydev, int devad, u32 regnum,
b8554d4f 917 u16 mask, u16 set);
1878f0dc 918int phy_modify_mmd(struct phy_device *phydev, int devad, u32 regnum,
b8554d4f 919 u16 mask, u16 set);
1878f0dc 920
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921/**
922 * __phy_set_bits - Convenience function for setting bits in a PHY register
923 * @phydev: the phy_device struct
924 * @regnum: register number to write
925 * @val: bits to set
926 *
927 * The caller must have taken the MDIO bus lock.
928 */
929static inline int __phy_set_bits(struct phy_device *phydev, u32 regnum, u16 val)
930{
931 return __phy_modify(phydev, regnum, 0, val);
932}
933
934/**
935 * __phy_clear_bits - Convenience function for clearing bits in a PHY register
936 * @phydev: the phy_device struct
937 * @regnum: register number to write
938 * @val: bits to clear
939 *
940 * The caller must have taken the MDIO bus lock.
941 */
942static inline int __phy_clear_bits(struct phy_device *phydev, u32 regnum,
943 u16 val)
944{
945 return __phy_modify(phydev, regnum, val, 0);
946}
947
948/**
949 * phy_set_bits - Convenience function for setting bits in a PHY register
950 * @phydev: the phy_device struct
951 * @regnum: register number to write
952 * @val: bits to set
953 */
954static inline int phy_set_bits(struct phy_device *phydev, u32 regnum, u16 val)
955{
956 return phy_modify(phydev, regnum, 0, val);
957}
958
959/**
960 * phy_clear_bits - Convenience function for clearing bits in a PHY register
961 * @phydev: the phy_device struct
962 * @regnum: register number to write
963 * @val: bits to clear
964 */
965static inline int phy_clear_bits(struct phy_device *phydev, u32 regnum, u16 val)
966{
967 return phy_modify(phydev, regnum, val, 0);
968}
969
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970/**
971 * __phy_set_bits_mmd - Convenience function for setting bits in a register
972 * on MMD
973 * @phydev: the phy_device struct
974 * @devad: the MMD containing register to modify
975 * @regnum: register number to modify
976 * @val: bits to set
977 *
978 * The caller must have taken the MDIO bus lock.
979 */
980static inline int __phy_set_bits_mmd(struct phy_device *phydev, int devad,
981 u32 regnum, u16 val)
982{
983 return __phy_modify_mmd(phydev, devad, regnum, 0, val);
984}
985
986/**
987 * __phy_clear_bits_mmd - Convenience function for clearing bits in a register
988 * on MMD
989 * @phydev: the phy_device struct
990 * @devad: the MMD containing register to modify
991 * @regnum: register number to modify
992 * @val: bits to clear
993 *
994 * The caller must have taken the MDIO bus lock.
995 */
996static inline int __phy_clear_bits_mmd(struct phy_device *phydev, int devad,
997 u32 regnum, u16 val)
998{
999 return __phy_modify_mmd(phydev, devad, regnum, val, 0);
1000}
1001
1002/**
1003 * phy_set_bits_mmd - Convenience function for setting bits in a register
1004 * on MMD
1005 * @phydev: the phy_device struct
1006 * @devad: the MMD containing register to modify
1007 * @regnum: register number to modify
1008 * @val: bits to set
1009 */
1010static inline int phy_set_bits_mmd(struct phy_device *phydev, int devad,
1011 u32 regnum, u16 val)
1012{
1013 return phy_modify_mmd(phydev, devad, regnum, 0, val);
1014}
1015
1016/**
1017 * phy_clear_bits_mmd - Convenience function for clearing bits in a register
1018 * on MMD
1019 * @phydev: the phy_device struct
1020 * @devad: the MMD containing register to modify
1021 * @regnum: register number to modify
1022 * @val: bits to clear
1023 */
1024static inline int phy_clear_bits_mmd(struct phy_device *phydev, int devad,
1025 u32 regnum, u16 val)
1026{
1027 return phy_modify_mmd(phydev, devad, regnum, val, 0);
1028}
1029
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1030/**
1031 * phy_interrupt_is_valid - Convenience function for testing a given PHY irq
1032 * @phydev: the phy_device struct
1033 *
1034 * NOTE: must be kept in sync with addition/removal of PHY_POLL and
1035 * PHY_IGNORE_INTERRUPT
1036 */
1037static inline bool phy_interrupt_is_valid(struct phy_device *phydev)
1038{
1039 return phydev->irq != PHY_POLL && phydev->irq != PHY_IGNORE_INTERRUPT;
1040}
1041
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1042/**
1043 * phy_polling_mode - Convenience function for testing whether polling is
1044 * used to detect PHY status changes
1045 * @phydev: the phy_device struct
1046 */
1047static inline bool phy_polling_mode(struct phy_device *phydev)
1048{
1049 return phydev->irq == PHY_POLL;
1050}
1051
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1052/**
1053 * phy_has_hwtstamp - Tests whether a PHY time stamp configuration.
1054 * @phydev: the phy_device struct
1055 */
1056static inline bool phy_has_hwtstamp(struct phy_device *phydev)
1057{
4715f65f 1058 return phydev && phydev->mii_ts && phydev->mii_ts->hwtstamp;
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1059}
1060
1061/**
1062 * phy_has_rxtstamp - Tests whether a PHY supports receive time stamping.
1063 * @phydev: the phy_device struct
1064 */
1065static inline bool phy_has_rxtstamp(struct phy_device *phydev)
1066{
4715f65f 1067 return phydev && phydev->mii_ts && phydev->mii_ts->rxtstamp;
0e5dafc8
RC
1068}
1069
1070/**
1071 * phy_has_tsinfo - Tests whether a PHY reports time stamping and/or
1072 * PTP hardware clock capabilities.
1073 * @phydev: the phy_device struct
1074 */
1075static inline bool phy_has_tsinfo(struct phy_device *phydev)
1076{
4715f65f 1077 return phydev && phydev->mii_ts && phydev->mii_ts->ts_info;
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RC
1078}
1079
1080/**
1081 * phy_has_txtstamp - Tests whether a PHY supports transmit time stamping.
1082 * @phydev: the phy_device struct
1083 */
1084static inline bool phy_has_txtstamp(struct phy_device *phydev)
1085{
4715f65f 1086 return phydev && phydev->mii_ts && phydev->mii_ts->txtstamp;
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RC
1087}
1088
1089static inline int phy_hwtstamp(struct phy_device *phydev, struct ifreq *ifr)
1090{
4715f65f 1091 return phydev->mii_ts->hwtstamp(phydev->mii_ts, ifr);
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1092}
1093
1094static inline bool phy_rxtstamp(struct phy_device *phydev, struct sk_buff *skb,
1095 int type)
1096{
4715f65f 1097 return phydev->mii_ts->rxtstamp(phydev->mii_ts, skb, type);
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1098}
1099
1100static inline int phy_ts_info(struct phy_device *phydev,
1101 struct ethtool_ts_info *tsinfo)
1102{
4715f65f 1103 return phydev->mii_ts->ts_info(phydev->mii_ts, tsinfo);
0e5dafc8
RC
1104}
1105
1106static inline void phy_txtstamp(struct phy_device *phydev, struct sk_buff *skb,
1107 int type)
1108{
4715f65f 1109 phydev->mii_ts->txtstamp(phydev->mii_ts, skb, type);
0e5dafc8
RC
1110}
1111
4284b6a5
FF
1112/**
1113 * phy_is_internal - Convenience function for testing if a PHY is internal
1114 * @phydev: the phy_device struct
1115 */
1116static inline bool phy_is_internal(struct phy_device *phydev)
1117{
1118 return phydev->is_internal;
1119}
1120
32d0f783
IS
1121/**
1122 * phy_interface_mode_is_rgmii - Convenience function for testing if a
1123 * PHY interface mode is RGMII (all variants)
1124 * @mode: the phy_interface_t enum
1125 */
1126static inline bool phy_interface_mode_is_rgmii(phy_interface_t mode)
1127{
1128 return mode >= PHY_INTERFACE_MODE_RGMII &&
1129 mode <= PHY_INTERFACE_MODE_RGMII_TXID;
1130};
1131
365c1e64
RK
1132/**
1133 * phy_interface_mode_is_8023z() - does the phy interface mode use 802.3z
1134 * negotiation
1135 * @mode: one of &enum phy_interface_t
1136 *
1137 * Returns true if the phy interface mode uses the 16-bit negotiation
1138 * word as defined in 802.3z. (See 802.3-2015 37.2.1 Config_Reg encoding)
1139 */
1140static inline bool phy_interface_mode_is_8023z(phy_interface_t mode)
1141{
1142 return mode == PHY_INTERFACE_MODE_1000BASEX ||
1143 mode == PHY_INTERFACE_MODE_2500BASEX;
1144}
1145
e463d88c
FF
1146/**
1147 * phy_interface_is_rgmii - Convenience function for testing if a PHY interface
1148 * is RGMII (all variants)
1149 * @phydev: the phy_device struct
1150 */
1151static inline bool phy_interface_is_rgmii(struct phy_device *phydev)
1152{
32d0f783 1153 return phy_interface_mode_is_rgmii(phydev->interface);
5a11dd7d
FF
1154};
1155
1156/*
1157 * phy_is_pseudo_fixed_link - Convenience function for testing if this
1158 * PHY is the CPU port facing side of an Ethernet switch, or similar.
1159 * @phydev: the phy_device struct
1160 */
1161static inline bool phy_is_pseudo_fixed_link(struct phy_device *phydev)
1162{
1163 return phydev->is_pseudo_fixed_link;
e463d88c
FF
1164}
1165
78ffc4ac
RK
1166int phy_save_page(struct phy_device *phydev);
1167int phy_select_page(struct phy_device *phydev, int page);
1168int phy_restore_page(struct phy_device *phydev, int oldpage, int ret);
1169int phy_read_paged(struct phy_device *phydev, int page, u32 regnum);
1170int phy_write_paged(struct phy_device *phydev, int page, u32 regnum, u16 val);
bf22b343
HK
1171int phy_modify_paged_changed(struct phy_device *phydev, int page, u32 regnum,
1172 u16 mask, u16 set);
78ffc4ac
RK
1173int phy_modify_paged(struct phy_device *phydev, int page, u32 regnum,
1174 u16 mask, u16 set);
1175
7d49a32a 1176struct phy_device *phy_device_create(struct mii_bus *bus, int addr, u32 phy_id,
4017b4d3
SS
1177 bool is_c45,
1178 struct phy_c45_device_ids *c45_ids);
90eff909 1179#if IS_ENABLED(CONFIG_PHYLIB)
ac28b9f8 1180struct phy_device *get_phy_device(struct mii_bus *bus, int addr, bool is_c45);
4dea547f 1181int phy_device_register(struct phy_device *phy);
90eff909
FF
1182void phy_device_free(struct phy_device *phydev);
1183#else
1184static inline
1185struct phy_device *get_phy_device(struct mii_bus *bus, int addr, bool is_c45)
1186{
1187 return NULL;
1188}
1189
1190static inline int phy_device_register(struct phy_device *phy)
1191{
1192 return 0;
1193}
1194
1195static inline void phy_device_free(struct phy_device *phydev) { }
1196#endif /* CONFIG_PHYLIB */
38737e49 1197void phy_device_remove(struct phy_device *phydev);
2f5cb434 1198int phy_init_hw(struct phy_device *phydev);
481b5d93
SH
1199int phy_suspend(struct phy_device *phydev);
1200int phy_resume(struct phy_device *phydev);
9c2c2e62 1201int __phy_resume(struct phy_device *phydev);
f0f9b4ed 1202int phy_loopback(struct phy_device *phydev, bool enable);
298e54fa
RK
1203void phy_sfp_attach(void *upstream, struct sfp_bus *bus);
1204void phy_sfp_detach(void *upstream, struct sfp_bus *bus);
1205int phy_sfp_probe(struct phy_device *phydev,
1206 const struct sfp_upstream_ops *ops);
4017b4d3
SS
1207struct phy_device *phy_attach(struct net_device *dev, const char *bus_id,
1208 phy_interface_t interface);
f8f76db1 1209struct phy_device *phy_find_first(struct mii_bus *bus);
257184d7
AF
1210int phy_attach_direct(struct net_device *dev, struct phy_device *phydev,
1211 u32 flags, phy_interface_t interface);
fa94f6d9 1212int phy_connect_direct(struct net_device *dev, struct phy_device *phydev,
4017b4d3
SS
1213 void (*handler)(struct net_device *),
1214 phy_interface_t interface);
1215struct phy_device *phy_connect(struct net_device *dev, const char *bus_id,
1216 void (*handler)(struct net_device *),
1217 phy_interface_t interface);
e1393456
AF
1218void phy_disconnect(struct phy_device *phydev);
1219void phy_detach(struct phy_device *phydev);
1220void phy_start(struct phy_device *phydev);
1221void phy_stop(struct phy_device *phydev);
1222int phy_start_aneg(struct phy_device *phydev);
372788f9 1223int phy_aneg_done(struct phy_device *phydev);
2b9672dd
HK
1224int phy_speed_down(struct phy_device *phydev, bool sync);
1225int phy_speed_up(struct phy_device *phydev);
e1393456 1226
002ba705 1227int phy_restart_aneg(struct phy_device *phydev);
a9668491 1228int phy_reset_after_clk_enable(struct phy_device *phydev);
00db8189 1229
bafbdd52
SS
1230static inline void phy_device_reset(struct phy_device *phydev, int value)
1231{
1232 mdio_device_reset(&phydev->mdio, value);
1233}
1234
72ba48be 1235#define phydev_err(_phydev, format, args...) \
e5a03bfd 1236 dev_err(&_phydev->mdio.dev, format, ##args)
72ba48be 1237
c4fabb8b
AL
1238#define phydev_info(_phydev, format, args...) \
1239 dev_info(&_phydev->mdio.dev, format, ##args)
1240
ab2a605f
AL
1241#define phydev_warn(_phydev, format, args...) \
1242 dev_warn(&_phydev->mdio.dev, format, ##args)
1243
72ba48be 1244#define phydev_dbg(_phydev, format, args...) \
2eaa38d9 1245 dev_dbg(&_phydev->mdio.dev, format, ##args)
72ba48be 1246
84eff6d1
AL
1247static inline const char *phydev_name(const struct phy_device *phydev)
1248{
e5a03bfd 1249 return dev_name(&phydev->mdio.dev);
84eff6d1
AL
1250}
1251
bec170e5
HK
1252static inline void phy_lock_mdio_bus(struct phy_device *phydev)
1253{
1254 mutex_lock(&phydev->mdio.bus->mdio_lock);
1255}
1256
1257static inline void phy_unlock_mdio_bus(struct phy_device *phydev)
1258{
1259 mutex_unlock(&phydev->mdio.bus->mdio_lock);
1260}
1261
2220943a
AL
1262void phy_attached_print(struct phy_device *phydev, const char *fmt, ...)
1263 __printf(2, 3);
e27f1787
FF
1264char *phy_attached_info_irq(struct phy_device *phydev)
1265 __malloc;
2220943a 1266void phy_attached_info(struct phy_device *phydev);
5acde34a
RK
1267
1268/* Clause 22 PHY */
045925e3 1269int genphy_read_abilities(struct phy_device *phydev);
3fb69bca 1270int genphy_setup_forced(struct phy_device *phydev);
00db8189 1271int genphy_restart_aneg(struct phy_device *phydev);
2a10ab04 1272int genphy_check_and_restart_aneg(struct phy_device *phydev, bool restart);
cd34499c 1273int genphy_config_eee_advert(struct phy_device *phydev);
f4069cd7 1274int __genphy_config_aneg(struct phy_device *phydev, bool changed);
a9fa6e6a 1275int genphy_aneg_done(struct phy_device *phydev);
00db8189 1276int genphy_update_link(struct phy_device *phydev);
8d3dc3ac 1277int genphy_read_lpa(struct phy_device *phydev);
0efc286a 1278int genphy_read_status_fixed(struct phy_device *phydev);
00db8189 1279int genphy_read_status(struct phy_device *phydev);
0f0ca340
GC
1280int genphy_suspend(struct phy_device *phydev);
1281int genphy_resume(struct phy_device *phydev);
f0f9b4ed 1282int genphy_loopback(struct phy_device *phydev, bool enable);
797ac071 1283int genphy_soft_reset(struct phy_device *phydev);
f4069cd7
HK
1284
1285static inline int genphy_config_aneg(struct phy_device *phydev)
1286{
1287 return __genphy_config_aneg(phydev, false);
1288}
1289
4c8e0459
LW
1290static inline int genphy_no_ack_interrupt(struct phy_device *phydev)
1291{
1292 return 0;
1293}
1294static inline int genphy_no_config_intr(struct phy_device *phydev)
1295{
1296 return 0;
1297}
5df7af85
KH
1298int genphy_read_mmd_unsupported(struct phy_device *phdev, int devad,
1299 u16 regnum);
1300int genphy_write_mmd_unsupported(struct phy_device *phdev, int devnum,
1301 u16 regnum, u16 val);
5acde34a 1302
fa6e98ce
HK
1303/* Clause 37 */
1304int genphy_c37_config_aneg(struct phy_device *phydev);
1305int genphy_c37_read_status(struct phy_device *phydev);
1306
5acde34a
RK
1307/* Clause 45 PHY */
1308int genphy_c45_restart_aneg(struct phy_device *phydev);
1af9f168 1309int genphy_c45_check_and_restart_aneg(struct phy_device *phydev, bool restart);
5acde34a 1310int genphy_c45_aneg_done(struct phy_device *phydev);
998a8a83 1311int genphy_c45_read_link(struct phy_device *phydev);
5acde34a
RK
1312int genphy_c45_read_lpa(struct phy_device *phydev);
1313int genphy_c45_read_pma(struct phy_device *phydev);
1314int genphy_c45_pma_setup_forced(struct phy_device *phydev);
9a5dc8af 1315int genphy_c45_an_config_aneg(struct phy_device *phydev);
5acde34a 1316int genphy_c45_an_disable_aneg(struct phy_device *phydev);
ea4efe25 1317int genphy_c45_read_mdix(struct phy_device *phydev);
ac3f5533 1318int genphy_c45_pma_read_abilities(struct phy_device *phydev);
70fa3a96 1319int genphy_c45_read_status(struct phy_device *phydev);
94acaeb5 1320int genphy_c45_config_aneg(struct phy_device *phydev);
5acde34a 1321
e8a714e0
FF
1322/* The gen10g_* functions are the old Clause 45 stub */
1323int gen10g_config_aneg(struct phy_device *phydev);
e8a714e0 1324
00fde795
HK
1325static inline int phy_read_status(struct phy_device *phydev)
1326{
1327 if (!phydev->drv)
1328 return -EIO;
1329
1330 if (phydev->drv->read_status)
1331 return phydev->drv->read_status(phydev);
1332 else
1333 return genphy_read_status(phydev);
1334}
1335
00db8189 1336void phy_driver_unregister(struct phy_driver *drv);
d5bf9071 1337void phy_drivers_unregister(struct phy_driver *drv, int n);
be01da72
AL
1338int phy_driver_register(struct phy_driver *new_driver, struct module *owner);
1339int phy_drivers_register(struct phy_driver *new_driver, int n,
1340 struct module *owner);
4f9c85a1 1341void phy_state_machine(struct work_struct *work);
97b33bdf 1342void phy_queue_state_machine(struct phy_device *phydev, unsigned long jiffies);
28b2e0d2 1343void phy_mac_interrupt(struct phy_device *phydev);
29935aeb 1344void phy_start_machine(struct phy_device *phydev);
00db8189 1345void phy_stop_machine(struct phy_device *phydev);
5514174f 1346void phy_ethtool_ksettings_get(struct phy_device *phydev,
1347 struct ethtool_link_ksettings *cmd);
2d55173e
PR
1348int phy_ethtool_ksettings_set(struct phy_device *phydev,
1349 const struct ethtool_link_ksettings *cmd);
4017b4d3 1350int phy_mii_ioctl(struct phy_device *phydev, struct ifreq *ifr, int cmd);
bbbf8430 1351int phy_do_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd);
3231e5d2 1352int phy_do_ioctl_running(struct net_device *dev, struct ifreq *ifr, int cmd);
434a4315 1353void phy_request_interrupt(struct phy_device *phydev);
07b09289 1354void phy_free_interrupt(struct phy_device *phydev);
e1393456 1355void phy_print_status(struct phy_device *phydev);
f3a6bd39 1356int phy_set_max_speed(struct phy_device *phydev, u32 max_speed);
41124fa6 1357void phy_remove_link_mode(struct phy_device *phydev, u32 link_mode);
22c0ef6b 1358void phy_advertise_supported(struct phy_device *phydev);
c306ad36 1359void phy_support_sym_pause(struct phy_device *phydev);
af8d9bb2 1360void phy_support_asym_pause(struct phy_device *phydev);
0c122405
AL
1361void phy_set_sym_pause(struct phy_device *phydev, bool rx, bool tx,
1362 bool autoneg);
70814e81 1363void phy_set_asym_pause(struct phy_device *phydev, bool rx, bool tx);
22b7d299
AL
1364bool phy_validate_pause(struct phy_device *phydev,
1365 struct ethtool_pauseparam *pp);
a87ae8a9
RK
1366void phy_get_pause(struct phy_device *phydev, bool *tx_pause, bool *rx_pause);
1367void phy_resolve_pause(unsigned long *local_adv, unsigned long *partner_adv,
1368 bool *tx_pause, bool *rx_pause);
00db8189 1369
f62220d3 1370int phy_register_fixup(const char *bus_id, u32 phy_uid, u32 phy_uid_mask,
4017b4d3 1371 int (*run)(struct phy_device *));
f62220d3 1372int phy_register_fixup_for_id(const char *bus_id,
4017b4d3 1373 int (*run)(struct phy_device *));
f62220d3 1374int phy_register_fixup_for_uid(u32 phy_uid, u32 phy_uid_mask,
4017b4d3 1375 int (*run)(struct phy_device *));
f62220d3 1376
f38e7a32
WH
1377int phy_unregister_fixup(const char *bus_id, u32 phy_uid, u32 phy_uid_mask);
1378int phy_unregister_fixup_for_id(const char *bus_id);
1379int phy_unregister_fixup_for_uid(u32 phy_uid, u32 phy_uid_mask);
1380
a59a4d19
GC
1381int phy_init_eee(struct phy_device *phydev, bool clk_stop_enable);
1382int phy_get_eee_err(struct phy_device *phydev);
1383int phy_ethtool_set_eee(struct phy_device *phydev, struct ethtool_eee *data);
1384int phy_ethtool_get_eee(struct phy_device *phydev, struct ethtool_eee *data);
42e836eb 1385int phy_ethtool_set_wol(struct phy_device *phydev, struct ethtool_wolinfo *wol);
4017b4d3
SS
1386void phy_ethtool_get_wol(struct phy_device *phydev,
1387 struct ethtool_wolinfo *wol);
9d9a77ce
PR
1388int phy_ethtool_get_link_ksettings(struct net_device *ndev,
1389 struct ethtool_link_ksettings *cmd);
1390int phy_ethtool_set_link_ksettings(struct net_device *ndev,
1391 const struct ethtool_link_ksettings *cmd);
e86a8987 1392int phy_ethtool_nway_reset(struct net_device *ndev);
63490847
MW
1393int phy_package_join(struct phy_device *phydev, int addr, size_t priv_size);
1394void phy_package_leave(struct phy_device *phydev);
1395int devm_phy_package_join(struct device *dev, struct phy_device *phydev,
1396 int addr, size_t priv_size);
a59a4d19 1397
90eff909 1398#if IS_ENABLED(CONFIG_PHYLIB)
9b9a8bfc
AF
1399int __init mdio_bus_init(void);
1400void mdio_bus_exit(void);
9e8d438e
FF
1401#endif
1402
1403/* Inline function for use within net/core/ethtool.c (built-in) */
1404static inline int phy_ethtool_get_strings(struct phy_device *phydev, u8 *data)
c59530d0 1405{
9e8d438e
FF
1406 if (!phydev->drv)
1407 return -EIO;
1408
1409 mutex_lock(&phydev->lock);
1410 phydev->drv->get_strings(phydev, data);
1411 mutex_unlock(&phydev->lock);
1412
1413 return 0;
c59530d0
FF
1414}
1415
9e8d438e 1416static inline int phy_ethtool_get_sset_count(struct phy_device *phydev)
c59530d0 1417{
9e8d438e
FF
1418 int ret;
1419
1420 if (!phydev->drv)
1421 return -EIO;
1422
1423 if (phydev->drv->get_sset_count &&
1424 phydev->drv->get_strings &&
1425 phydev->drv->get_stats) {
1426 mutex_lock(&phydev->lock);
1427 ret = phydev->drv->get_sset_count(phydev);
1428 mutex_unlock(&phydev->lock);
1429
1430 return ret;
1431 }
1432
c59530d0
FF
1433 return -EOPNOTSUPP;
1434}
1435
9e8d438e
FF
1436static inline int phy_ethtool_get_stats(struct phy_device *phydev,
1437 struct ethtool_stats *stats, u64 *data)
c59530d0 1438{
9e8d438e
FF
1439 if (!phydev->drv)
1440 return -EIO;
1441
1442 mutex_lock(&phydev->lock);
1443 phydev->drv->get_stats(phydev, stats, data);
1444 mutex_unlock(&phydev->lock);
1445
1446 return 0;
c59530d0 1447}
9b9a8bfc 1448
63490847
MW
1449static inline int phy_package_read(struct phy_device *phydev, u32 regnum)
1450{
1451 struct phy_package_shared *shared = phydev->shared;
1452
1453 if (!shared)
1454 return -EIO;
1455
1456 return mdiobus_read(phydev->mdio.bus, shared->addr, regnum);
1457}
1458
1459static inline int __phy_package_read(struct phy_device *phydev, u32 regnum)
1460{
1461 struct phy_package_shared *shared = phydev->shared;
1462
1463 if (!shared)
1464 return -EIO;
1465
1466 return __mdiobus_read(phydev->mdio.bus, shared->addr, regnum);
1467}
1468
1469static inline int phy_package_write(struct phy_device *phydev,
1470 u32 regnum, u16 val)
1471{
1472 struct phy_package_shared *shared = phydev->shared;
1473
1474 if (!shared)
1475 return -EIO;
1476
1477 return mdiobus_write(phydev->mdio.bus, shared->addr, regnum, val);
1478}
1479
1480static inline int __phy_package_write(struct phy_device *phydev,
1481 u32 regnum, u16 val)
1482{
1483 struct phy_package_shared *shared = phydev->shared;
1484
1485 if (!shared)
1486 return -EIO;
1487
1488 return __mdiobus_write(phydev->mdio.bus, shared->addr, regnum, val);
1489}
1490
1491static inline bool phy_package_init_once(struct phy_device *phydev)
1492{
1493 struct phy_package_shared *shared = phydev->shared;
1494
1495 if (!shared)
1496 return false;
1497
1498 return !test_and_set_bit(PHY_SHARED_F_INIT_DONE, &shared->flags);
1499}
1500
00db8189 1501extern struct bus_type mdio_bus_type;
c31accd1 1502
648ea013
FF
1503struct mdio_board_info {
1504 const char *bus_id;
1505 char modalias[MDIO_NAME_SIZE];
1506 int mdio_addr;
1507 const void *platform_data;
1508};
1509
90eff909 1510#if IS_ENABLED(CONFIG_MDIO_DEVICE)
648ea013
FF
1511int mdiobus_register_board_info(const struct mdio_board_info *info,
1512 unsigned int n);
1513#else
1514static inline int mdiobus_register_board_info(const struct mdio_board_info *i,
1515 unsigned int n)
1516{
1517 return 0;
1518}
1519#endif
1520
1521
c31accd1
JH
1522/**
1523 * module_phy_driver() - Helper macro for registering PHY drivers
1524 * @__phy_drivers: array of PHY drivers to register
1525 *
1526 * Helper macro for PHY drivers which do not do anything special in module
1527 * init/exit. Each module may only use this macro once, and calling it
1528 * replaces module_init() and module_exit().
1529 */
1530#define phy_module_driver(__phy_drivers, __count) \
1531static int __init phy_module_init(void) \
1532{ \
be01da72 1533 return phy_drivers_register(__phy_drivers, __count, THIS_MODULE); \
c31accd1
JH
1534} \
1535module_init(phy_module_init); \
1536static void __exit phy_module_exit(void) \
1537{ \
1538 phy_drivers_unregister(__phy_drivers, __count); \
1539} \
1540module_exit(phy_module_exit)
1541
1542#define module_phy_driver(__phy_drivers) \
1543 phy_module_driver(__phy_drivers, ARRAY_SIZE(__phy_drivers))
1544
5db5ea99
FF
1545bool phy_driver_is_genphy(struct phy_device *phydev);
1546bool phy_driver_is_genphy_10g(struct phy_device *phydev);
1547
00db8189 1548#endif /* __PHY_H */