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net: phy: prepare phylib to deal with PHY's extending Clause 22
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2874c5fd 1/* SPDX-License-Identifier: GPL-2.0-or-later */
00db8189 2/*
00db8189 3 * Framework and drivers for configuring and reading different PHYs
d8de01b7 4 * Based on code in sungem_phy.c and (long-removed) gianfar_phy.c
00db8189
AF
5 *
6 * Author: Andy Fleming
7 *
8 * Copyright (c) 2004 Freescale Semiconductor, Inc.
00db8189
AF
9 */
10
11#ifndef __PHY_H
12#define __PHY_H
13
2220943a 14#include <linux/compiler.h>
00db8189 15#include <linux/spinlock.h>
13df29f6 16#include <linux/ethtool.h>
b31cdffa 17#include <linux/linkmode.h>
bac83c65 18#include <linux/mdio.h>
13df29f6 19#include <linux/mii.h>
3e3aaf64 20#include <linux/module.h>
13df29f6
MR
21#include <linux/timer.h>
22#include <linux/workqueue.h>
8626d3b4 23#include <linux/mod_devicetable.h>
00db8189 24
60063497 25#include <linux/atomic.h>
0ac49527 26
e9fbdf17 27#define PHY_DEFAULT_FEATURES (SUPPORTED_Autoneg | \
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AF
28 SUPPORTED_TP | \
29 SUPPORTED_MII)
30
e9fbdf17
FF
31#define PHY_10BT_FEATURES (SUPPORTED_10baseT_Half | \
32 SUPPORTED_10baseT_Full)
33
34#define PHY_100BT_FEATURES (SUPPORTED_100baseT_Half | \
35 SUPPORTED_100baseT_Full)
36
37#define PHY_1000BT_FEATURES (SUPPORTED_1000baseT_Half | \
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38 SUPPORTED_1000baseT_Full)
39
719655a1
AL
40extern __ETHTOOL_DECLARE_LINK_MODE_MASK(phy_basic_features) __ro_after_init;
41extern __ETHTOOL_DECLARE_LINK_MODE_MASK(phy_basic_t1_features) __ro_after_init;
42extern __ETHTOOL_DECLARE_LINK_MODE_MASK(phy_gbit_features) __ro_after_init;
43extern __ETHTOOL_DECLARE_LINK_MODE_MASK(phy_gbit_fibre_features) __ro_after_init;
44extern __ETHTOOL_DECLARE_LINK_MODE_MASK(phy_gbit_all_ports_features) __ro_after_init;
45extern __ETHTOOL_DECLARE_LINK_MODE_MASK(phy_10gbit_features) __ro_after_init;
9e857a40 46extern __ETHTOOL_DECLARE_LINK_MODE_MASK(phy_10gbit_fec_features) __ro_after_init;
719655a1
AL
47extern __ETHTOOL_DECLARE_LINK_MODE_MASK(phy_10gbit_full_features) __ro_after_init;
48
49#define PHY_BASIC_FEATURES ((unsigned long *)&phy_basic_features)
50#define PHY_BASIC_T1_FEATURES ((unsigned long *)&phy_basic_t1_features)
51#define PHY_GBIT_FEATURES ((unsigned long *)&phy_gbit_features)
52#define PHY_GBIT_FIBRE_FEATURES ((unsigned long *)&phy_gbit_fibre_features)
53#define PHY_GBIT_ALL_PORTS_FEATURES ((unsigned long *)&phy_gbit_all_ports_features)
54#define PHY_10GBIT_FEATURES ((unsigned long *)&phy_10gbit_features)
9e857a40 55#define PHY_10GBIT_FEC_FEATURES ((unsigned long *)&phy_10gbit_fec_features)
719655a1 56#define PHY_10GBIT_FULL_FEATURES ((unsigned long *)&phy_10gbit_full_features)
e9fbdf17 57
54638c6e
DE
58extern const int phy_basic_ports_array[3];
59extern const int phy_fibre_port_array[1];
60extern const int phy_all_ports_features_array[7];
3c1bcc86
AL
61extern const int phy_10_100_features_array[4];
62extern const int phy_basic_t1_features_array[2];
63extern const int phy_gbit_features_array[2];
64extern const int phy_10gbit_features_array[1];
65
c5e38a94
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66/*
67 * Set phydev->irq to PHY_POLL if interrupts are not supported,
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68 * or not desired for this PHY. Set to PHY_IGNORE_INTERRUPT if
69 * the attached driver handles the interrupt
70 */
71#define PHY_POLL -1
72#define PHY_IGNORE_INTERRUPT -2
73
a4307c0e
HK
74#define PHY_IS_INTERNAL 0x00000001
75#define PHY_RST_AFTER_CLK_EN 0x00000002
a9049e0c 76#define MDIO_DEVICE_IS_PHY 0x80000000
00db8189 77
e8a2b6a4
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78/* Interface Mode definitions */
79typedef enum {
4157ef1b 80 PHY_INTERFACE_MODE_NA,
735d8a18 81 PHY_INTERFACE_MODE_INTERNAL,
e8a2b6a4
AF
82 PHY_INTERFACE_MODE_MII,
83 PHY_INTERFACE_MODE_GMII,
84 PHY_INTERFACE_MODE_SGMII,
85 PHY_INTERFACE_MODE_TBI,
2cc70ba4 86 PHY_INTERFACE_MODE_REVMII,
e8a2b6a4
AF
87 PHY_INTERFACE_MODE_RMII,
88 PHY_INTERFACE_MODE_RGMII,
a999589c 89 PHY_INTERFACE_MODE_RGMII_ID,
7d400a4c
KP
90 PHY_INTERFACE_MODE_RGMII_RXID,
91 PHY_INTERFACE_MODE_RGMII_TXID,
4157ef1b
SG
92 PHY_INTERFACE_MODE_RTBI,
93 PHY_INTERFACE_MODE_SMII,
898dd0bd 94 PHY_INTERFACE_MODE_XGMII,
fd70f72c 95 PHY_INTERFACE_MODE_MOCA,
b9d12085 96 PHY_INTERFACE_MODE_QSGMII,
572de608 97 PHY_INTERFACE_MODE_TRGMII,
55601a88
AL
98 PHY_INTERFACE_MODE_1000BASEX,
99 PHY_INTERFACE_MODE_2500BASEX,
100 PHY_INTERFACE_MODE_RXAUI,
c125ca09
RK
101 PHY_INTERFACE_MODE_XAUI,
102 /* 10GBASE-KR, XFI, SFI - single lane 10G Serdes */
103 PHY_INTERFACE_MODE_10GKR,
4618d671 104 PHY_INTERFACE_MODE_USXGMII,
8a2fe56e 105 PHY_INTERFACE_MODE_MAX,
e8a2b6a4
AF
106} phy_interface_t;
107
1f9127ca
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108/**
109 * phy_supported_speeds - return all speeds currently supported by a phy device
110 * @phy: The phy device to return supported speeds of.
111 * @speeds: buffer to store supported speeds in.
112 * @size: size of speeds buffer.
113 *
d8de01b7
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114 * Description: Returns the number of supported speeds, and fills
115 * the speeds buffer with the supported speeds. If speeds buffer is
116 * too small to contain all currently supported speeds, will return as
1f9127ca
ZB
117 * many speeds as can fit.
118 */
119unsigned int phy_supported_speeds(struct phy_device *phy,
120 unsigned int *speeds,
121 unsigned int size);
122
8a2fe56e 123/**
d8de01b7
RD
124 * phy_modes - map phy_interface_t enum to device tree binding of phy-mode
125 * @interface: enum phy_interface_t value
126 *
127 * Description: maps 'enum phy_interface_t' defined in this file
8a2fe56e
FF
128 * into the device tree binding of 'phy-mode', so that Ethernet
129 * device driver can get phy interface from device tree.
130 */
131static inline const char *phy_modes(phy_interface_t interface)
132{
133 switch (interface) {
134 case PHY_INTERFACE_MODE_NA:
135 return "";
735d8a18
FF
136 case PHY_INTERFACE_MODE_INTERNAL:
137 return "internal";
8a2fe56e
FF
138 case PHY_INTERFACE_MODE_MII:
139 return "mii";
140 case PHY_INTERFACE_MODE_GMII:
141 return "gmii";
142 case PHY_INTERFACE_MODE_SGMII:
143 return "sgmii";
144 case PHY_INTERFACE_MODE_TBI:
145 return "tbi";
146 case PHY_INTERFACE_MODE_REVMII:
147 return "rev-mii";
148 case PHY_INTERFACE_MODE_RMII:
149 return "rmii";
150 case PHY_INTERFACE_MODE_RGMII:
151 return "rgmii";
152 case PHY_INTERFACE_MODE_RGMII_ID:
153 return "rgmii-id";
154 case PHY_INTERFACE_MODE_RGMII_RXID:
155 return "rgmii-rxid";
156 case PHY_INTERFACE_MODE_RGMII_TXID:
157 return "rgmii-txid";
158 case PHY_INTERFACE_MODE_RTBI:
159 return "rtbi";
160 case PHY_INTERFACE_MODE_SMII:
161 return "smii";
162 case PHY_INTERFACE_MODE_XGMII:
163 return "xgmii";
fd70f72c
FF
164 case PHY_INTERFACE_MODE_MOCA:
165 return "moca";
b9d12085
TP
166 case PHY_INTERFACE_MODE_QSGMII:
167 return "qsgmii";
572de608
SW
168 case PHY_INTERFACE_MODE_TRGMII:
169 return "trgmii";
55601a88
AL
170 case PHY_INTERFACE_MODE_1000BASEX:
171 return "1000base-x";
172 case PHY_INTERFACE_MODE_2500BASEX:
173 return "2500base-x";
174 case PHY_INTERFACE_MODE_RXAUI:
175 return "rxaui";
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RK
176 case PHY_INTERFACE_MODE_XAUI:
177 return "xaui";
178 case PHY_INTERFACE_MODE_10GKR:
179 return "10gbase-kr";
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180 case PHY_INTERFACE_MODE_USXGMII:
181 return "usxgmii";
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182 default:
183 return "unknown";
184 }
185}
186
00db8189 187
e8a2b6a4 188#define PHY_INIT_TIMEOUT 100000
00db8189 189#define PHY_FORCE_TIMEOUT 10
00db8189 190
e8a2b6a4 191#define PHY_MAX_ADDR 32
00db8189 192
a4d00f17 193/* Used when trying to connect to a specific phy (mii bus id:phy device id) */
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194#define PHY_ID_FMT "%s:%02x"
195
4567d686 196#define MII_BUS_ID_SIZE 61
a4d00f17 197
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JG
198/* Or MII_ADDR_C45 into regnum for read/write on mii_bus to enable the 21 bit
199 IEEE 802.3ae clause 45 addressing mode used by 10GIGE phy chips. */
200#define MII_ADDR_C45 (1<<30)
d4117d63
KHL
201#define MII_DEVADDR_C45_SHIFT 16
202#define MII_REGADDR_C45_MASK GENMASK(15, 0)
abf35df2 203
313162d0 204struct device;
9525ae83 205struct phylink;
313162d0
PG
206struct sk_buff;
207
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208/*
209 * The Bus class for PHYs. Devices which provide access to
210 * PHYs should register using this structure
211 */
00db8189 212struct mii_bus {
3e3aaf64 213 struct module *owner;
00db8189 214 const char *name;
9d9326d3 215 char id[MII_BUS_ID_SIZE];
00db8189 216 void *priv;
ccaa953e
AL
217 int (*read)(struct mii_bus *bus, int addr, int regnum);
218 int (*write)(struct mii_bus *bus, int addr, int regnum, u16 val);
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219 int (*reset)(struct mii_bus *bus);
220
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221 /*
222 * A lock to ensure that only one thing can read/write
223 * the MDIO bus at a time
224 */
35b5f6b1 225 struct mutex mdio_lock;
00db8189 226
18ee49dd 227 struct device *parent;
46abc021
LB
228 enum {
229 MDIOBUS_ALLOCATED = 1,
230 MDIOBUS_REGISTERED,
231 MDIOBUS_UNREGISTERED,
232 MDIOBUS_RELEASED,
233 } state;
234 struct device dev;
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235
236 /* list of all PHYs on bus */
7f854420 237 struct mdio_device *mdio_map[PHY_MAX_ADDR];
00db8189 238
c6883996 239 /* PHY addresses to be ignored when probing */
f896424c
MP
240 u32 phy_mask;
241
922f2dd1
FF
242 /* PHY addresses to ignore the TA/read failure */
243 u32 phy_ignore_ta_mask;
244
c5e38a94 245 /*
e7f4dc35
AL
246 * An array of interrupts, each PHY's interrupt at the index
247 * matching its address
c5e38a94 248 */
e7f4dc35 249 int irq[PHY_MAX_ADDR];
69226896
RQ
250
251 /* GPIO reset pulse width in microseconds */
252 int reset_delay_us;
d396e84c
SS
253 /* RESET GPIO descriptor pointer */
254 struct gpio_desc *reset_gpiod;
00db8189 255};
46abc021 256#define to_mii_bus(d) container_of(d, struct mii_bus, dev)
00db8189 257
eb8a54a7
TT
258struct mii_bus *mdiobus_alloc_size(size_t);
259static inline struct mii_bus *mdiobus_alloc(void)
260{
261 return mdiobus_alloc_size(0);
262}
263
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RK
264int __mdiobus_register(struct mii_bus *bus, struct module *owner);
265#define mdiobus_register(bus) __mdiobus_register(bus, THIS_MODULE)
2e888103
LB
266void mdiobus_unregister(struct mii_bus *bus);
267void mdiobus_free(struct mii_bus *bus);
6d48f44b
GS
268struct mii_bus *devm_mdiobus_alloc_size(struct device *dev, int sizeof_priv);
269static inline struct mii_bus *devm_mdiobus_alloc(struct device *dev)
270{
271 return devm_mdiobus_alloc_size(dev, 0);
272}
273
274void devm_mdiobus_free(struct device *dev, struct mii_bus *bus);
2e888103 275struct phy_device *mdiobus_scan(struct mii_bus *bus, int addr);
2e888103 276
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HK
277#define PHY_INTERRUPT_DISABLED false
278#define PHY_INTERRUPT_ENABLED true
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279
280/* PHY state machine states:
281 *
282 * DOWN: PHY device and driver are not ready for anything. probe
283 * should be called if and only if the PHY is in this state,
284 * given that the PHY device exists.
899a3cbb 285 * - PHY driver probe function will set the state to READY
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AF
286 *
287 * READY: PHY is ready to send and receive packets, but the
288 * controller is not. By default, PHYs which do not implement
899a3cbb 289 * probe will be set to this state by phy_probe().
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290 * - start will set the state to UP
291 *
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292 * UP: The PHY and attached device are ready to do work.
293 * Interrupts should be started here.
85a1f31d 294 * - timer moves to NOLINK or RUNNING
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295 *
296 * NOLINK: PHY is up, but not currently plugged in.
8deeb630 297 * - irq or timer will set RUNNING if link comes back
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298 * - phy_stop moves to HALTED
299 *
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300 * RUNNING: PHY is currently up, running, and possibly sending
301 * and/or receiving packets
8deeb630 302 * - irq or timer will set NOLINK if link goes down
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303 * - phy_stop moves to HALTED
304 *
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305 * HALTED: PHY is up, but no polling or interrupts are done. Or
306 * PHY is in an error state.
f24098f8 307 * - phy_start moves to UP
00db8189
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308 */
309enum phy_state {
4017b4d3 310 PHY_DOWN = 0,
00db8189 311 PHY_READY,
2b3e88ea 312 PHY_HALTED,
00db8189 313 PHY_UP,
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AF
314 PHY_RUNNING,
315 PHY_NOLINK,
00db8189
AF
316};
317
ac28b9f8
DD
318/**
319 * struct phy_c45_device_ids - 802.3-c45 Device Identifiers
320 * @devices_in_package: Bit vector of devices present.
321 * @device_ids: The device identifer for each present device.
322 */
323struct phy_c45_device_ids {
324 u32 devices_in_package;
325 u32 device_ids[8];
326};
c1f19b51 327
00db8189
AF
328/* phy_device: An instance of a PHY
329 *
330 * drv: Pointer to the driver for this PHY instance
00db8189 331 * phy_id: UID for this device found during discovery
ac28b9f8
DD
332 * c45_ids: 802.3-c45 Device Identifers if is_c45.
333 * is_c45: Set to true if this phy uses clause 45 addressing.
4284b6a5 334 * is_internal: Set to true if this phy is internal to a MAC.
5a11dd7d 335 * is_pseudo_fixed_link: Set to true if this phy is an Ethernet switch, etc.
3b8b11f9 336 * is_gigabit_capable: Set to true if PHY supports 1000Mbps
aae88261 337 * has_fixups: Set to true if this phy has fixups/quirks.
8a477a6f 338 * suspended: Set to true if this phy has been suspended successfully.
a3995460 339 * sysfs_links: Internal boolean tracking sysfs symbolic links setup/removal.
f0f9b4ed 340 * loopback_enabled: Set true if this phy has been loopbacked successfully.
00db8189
AF
341 * state: state of the PHY for management purposes
342 * dev_flags: Device-specific flags used by the PHY driver.
00db8189
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343 * irq: IRQ number of the PHY's interrupt (-1 if none)
344 * phy_timer: The timer for handling the state machine
00db8189
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345 * attached_dev: The attached enet driver's device instance ptr
346 * adjust_link: Callback for the enet controller to respond to
347 * changes in the link state.
00db8189 348 *
114002bc
FF
349 * speed, duplex, pause, supported, advertising, lp_advertising,
350 * and autoneg are used like in mii_if_info
00db8189
AF
351 *
352 * interrupts currently only supports enabled or disabled,
353 * but could be changed in the future to support enabling
354 * and disabling specific interrupts
355 *
356 * Contains some infrastructure for polling and interrupt
357 * handling, as well as handling shifts in PHY hardware state
358 */
359struct phy_device {
e5a03bfd
AL
360 struct mdio_device mdio;
361
00db8189
AF
362 /* Information about the PHY type */
363 /* And management functions */
364 struct phy_driver *drv;
365
00db8189
AF
366 u32 phy_id;
367
ac28b9f8 368 struct phy_c45_device_ids c45_ids;
87e5808d
HK
369 unsigned is_c45:1;
370 unsigned is_internal:1;
371 unsigned is_pseudo_fixed_link:1;
3b8b11f9 372 unsigned is_gigabit_capable:1;
87e5808d
HK
373 unsigned has_fixups:1;
374 unsigned suspended:1;
375 unsigned sysfs_links:1;
376 unsigned loopback_enabled:1;
377
378 unsigned autoneg:1;
379 /* The most recently read link state */
380 unsigned link:1;
4950c2ba 381 unsigned autoneg_complete:1;
ac28b9f8 382
695bce8f
HK
383 /* Interrupts are enabled */
384 unsigned interrupts:1;
385
00db8189
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386 enum phy_state state;
387
388 u32 dev_flags;
389
e8a2b6a4
AF
390 phy_interface_t interface;
391
c5e38a94
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392 /*
393 * forced speed & duplex (no autoneg)
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394 * partner speed & duplex & pause (autoneg)
395 */
396 int speed;
397 int duplex;
398 int pause;
399 int asym_pause;
400
3c1bcc86
AL
401 /* Union of PHY and Attached devices' supported link modes */
402 /* See ethtool.h for more info */
403 __ETHTOOL_DECLARE_LINK_MODE_MASK(supported);
404 __ETHTOOL_DECLARE_LINK_MODE_MASK(advertising);
c0ec3c27 405 __ETHTOOL_DECLARE_LINK_MODE_MASK(lp_advertising);
00db8189 406
d853d145 407 /* Energy efficient ethernet modes which should be prohibited */
408 u32 eee_broken_modes;
409
2e0bc452
ZB
410#ifdef CONFIG_LED_TRIGGER_PHY
411 struct phy_led_trigger *phy_led_triggers;
412 unsigned int phy_num_led_triggers;
413 struct phy_led_trigger *last_triggered;
3928ee64
MS
414
415 struct phy_led_trigger *led_link_trigger;
2e0bc452
ZB
416#endif
417
c5e38a94
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418 /*
419 * Interrupt number for this PHY
420 * -1 means no interrupt
421 */
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422 int irq;
423
424 /* private data pointer */
425 /* For use by PHYs to maintain extra state */
426 void *priv;
427
428 /* Interrupt and Polling infrastructure */
a390d1f3 429 struct delayed_work state_queue;
00db8189 430
35b5f6b1 431 struct mutex lock;
00db8189 432
9525ae83 433 struct phylink *phylink;
00db8189
AF
434 struct net_device *attached_dev;
435
634ec36c 436 u8 mdix;
f4ed2fe3 437 u8 mdix_ctrl;
634ec36c 438
a81497be 439 void (*phy_link_change)(struct phy_device *, bool up, bool do_carrier);
00db8189 440 void (*adjust_link)(struct net_device *dev);
00db8189 441};
e5a03bfd
AL
442#define to_phy_device(d) container_of(to_mdio_device(d), \
443 struct phy_device, mdio)
00db8189
AF
444
445/* struct phy_driver: Driver structure for a particular PHY type
446 *
a9049e0c 447 * driver_data: static driver data
00db8189
AF
448 * phy_id: The result of reading the UID registers of this PHY
449 * type, and ANDing them with the phy_id_mask. This driver
450 * only works for PHYs with IDs which match this field
451 * name: The friendly name of this PHY type
452 * phy_id_mask: Defines the important bits of the phy_id
3e64cf7a
CG
453 * features: A mandatory list of features (speed, duplex, etc)
454 * supported by this PHY
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AF
455 * flags: A bitfield defining certain other features this PHY
456 * supports (like interrupts)
457 *
00fde795
HK
458 * All functions are optional. If config_aneg or read_status
459 * are not implemented, the phy core uses the genphy versions.
460 * Note that none of these functions should be called from
461 * interrupt time. The goal is for the bus read/write functions
462 * to be able to block when the bus transaction is happening,
463 * and be freed up by an interrupt (The MPC85xx has this ability,
464 * though it is not currently supported in the driver).
00db8189
AF
465 */
466struct phy_driver {
a9049e0c 467 struct mdio_driver_common mdiodrv;
00db8189
AF
468 u32 phy_id;
469 char *name;
511e3036 470 u32 phy_id_mask;
719655a1 471 const unsigned long * const features;
00db8189 472 u32 flags;
860f6e9e 473 const void *driver_data;
00db8189 474
c5e38a94 475 /*
9df81dd7
FF
476 * Called to issue a PHY software reset
477 */
478 int (*soft_reset)(struct phy_device *phydev);
479
480 /*
c5e38a94
AF
481 * Called to initialize the PHY,
482 * including after a reset
483 */
00db8189
AF
484 int (*config_init)(struct phy_device *phydev);
485
c5e38a94
AF
486 /*
487 * Called during discovery. Used to set
488 * up device-specific structures, if any
489 */
00db8189
AF
490 int (*probe)(struct phy_device *phydev);
491
efbdfdc2
AL
492 /*
493 * Probe the hardware to determine what abilities it has.
494 * Should only set phydev->supported.
495 */
496 int (*get_features)(struct phy_device *phydev);
497
00db8189
AF
498 /* PHY Power Management */
499 int (*suspend)(struct phy_device *phydev);
500 int (*resume)(struct phy_device *phydev);
501
c5e38a94
AF
502 /*
503 * Configures the advertisement and resets
00db8189
AF
504 * autonegotiation if phydev->autoneg is on,
505 * forces the speed to the current settings in phydev
c5e38a94
AF
506 * if phydev->autoneg is off
507 */
00db8189
AF
508 int (*config_aneg)(struct phy_device *phydev);
509
76a423a3
FF
510 /* Determines the auto negotiation result */
511 int (*aneg_done)(struct phy_device *phydev);
512
00db8189
AF
513 /* Determines the negotiated speed and duplex */
514 int (*read_status)(struct phy_device *phydev);
515
516 /* Clears any pending interrupts */
517 int (*ack_interrupt)(struct phy_device *phydev);
518
519 /* Enables or disables interrupts */
520 int (*config_intr)(struct phy_device *phydev);
521
a8729eb3
AG
522 /*
523 * Checks if the PHY generated an interrupt.
524 * For multi-PHY devices with shared PHY interrupt pin
525 */
526 int (*did_interrupt)(struct phy_device *phydev);
527
49644e68
HK
528 /* Override default interrupt handling */
529 int (*handle_interrupt)(struct phy_device *phydev);
530
00db8189
AF
531 /* Clears up any memory if needed */
532 void (*remove)(struct phy_device *phydev);
533
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534 /* Returns true if this is a suitable driver for the given
535 * phydev. If NULL, matching is based on phy_id and
536 * phy_id_mask.
537 */
538 int (*match_phy_device)(struct phy_device *phydev);
539
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540 /* Handles ethtool queries for hardware time stamping. */
541 int (*ts_info)(struct phy_device *phydev, struct ethtool_ts_info *ti);
542
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543 /* Handles SIOCSHWTSTAMP ioctl for hardware time stamping. */
544 int (*hwtstamp)(struct phy_device *phydev, struct ifreq *ifr);
545
546 /*
547 * Requests a Rx timestamp for 'skb'. If the skb is accepted,
548 * the phy driver promises to deliver it using netif_rx() as
549 * soon as a timestamp becomes available. One of the
550 * PTP_CLASS_ values is passed in 'type'. The function must
551 * return true if the skb is accepted for delivery.
552 */
553 bool (*rxtstamp)(struct phy_device *dev, struct sk_buff *skb, int type);
554
555 /*
556 * Requests a Tx timestamp for 'skb'. The phy driver promises
da92b194 557 * to deliver it using skb_complete_tx_timestamp() as soon as a
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558 * timestamp becomes available. One of the PTP_CLASS_ values
559 * is passed in 'type'.
560 */
561 void (*txtstamp)(struct phy_device *dev, struct sk_buff *skb, int type);
562
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563 /* Some devices (e.g. qnap TS-119P II) require PHY register changes to
564 * enable Wake on LAN, so set_wol is provided to be called in the
565 * ethernet driver's set_wol function. */
566 int (*set_wol)(struct phy_device *dev, struct ethtool_wolinfo *wol);
567
568 /* See set_wol, but for checking whether Wake on LAN is enabled. */
569 void (*get_wol)(struct phy_device *dev, struct ethtool_wolinfo *wol);
570
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571 /*
572 * Called to inform a PHY device driver when the core is about to
573 * change the link state. This callback is supposed to be used as
574 * fixup hook for drivers that need to take action when the link
575 * state changes. Drivers are by no means allowed to mess with the
576 * PHY device structure in their implementations.
577 */
578 void (*link_change_notify)(struct phy_device *dev);
579
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580 /*
581 * Phy specific driver override for reading a MMD register.
582 * This function is optional for PHY specific drivers. When
583 * not provided, the default MMD read function will be used
584 * by phy_read_mmd(), which will use either a direct read for
585 * Clause 45 PHYs or an indirect read for Clause 22 PHYs.
586 * devnum is the MMD device number within the PHY device,
587 * regnum is the register within the selected MMD device.
588 */
589 int (*read_mmd)(struct phy_device *dev, int devnum, u16 regnum);
590
591 /*
592 * Phy specific driver override for writing a MMD register.
593 * This function is optional for PHY specific drivers. When
594 * not provided, the default MMD write function will be used
595 * by phy_write_mmd(), which will use either a direct write for
596 * Clause 45 PHYs, or an indirect write for Clause 22 PHYs.
597 * devnum is the MMD device number within the PHY device,
598 * regnum is the register within the selected MMD device.
599 * val is the value to be written.
600 */
601 int (*write_mmd)(struct phy_device *dev, int devnum, u16 regnum,
602 u16 val);
603
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604 int (*read_page)(struct phy_device *dev);
605 int (*write_page)(struct phy_device *dev, int page);
606
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607 /* Get the size and type of the eeprom contained within a plug-in
608 * module */
609 int (*module_info)(struct phy_device *dev,
610 struct ethtool_modinfo *modinfo);
611
612 /* Get the eeprom information from the plug-in module */
613 int (*module_eeprom)(struct phy_device *dev,
614 struct ethtool_eeprom *ee, u8 *data);
615
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616 /* Get statistics from the phy using ethtool */
617 int (*get_sset_count)(struct phy_device *dev);
618 void (*get_strings)(struct phy_device *dev, u8 *data);
619 void (*get_stats)(struct phy_device *dev,
620 struct ethtool_stats *stats, u64 *data);
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621
622 /* Get and Set PHY tunables */
623 int (*get_tunable)(struct phy_device *dev,
624 struct ethtool_tunable *tuna, void *data);
625 int (*set_tunable)(struct phy_device *dev,
626 struct ethtool_tunable *tuna,
627 const void *data);
f0f9b4ed 628 int (*set_loopback)(struct phy_device *dev, bool enable);
00db8189 629};
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AL
630#define to_phy_driver(d) container_of(to_mdio_common_driver(d), \
631 struct phy_driver, mdiodrv)
00db8189 632
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AF
633#define PHY_ANY_ID "MATCH ANY PHY"
634#define PHY_ANY_UID 0xffffffff
635
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636#define PHY_ID_MATCH_EXACT(id) .phy_id = (id), .phy_id_mask = GENMASK(31, 0)
637#define PHY_ID_MATCH_MODEL(id) .phy_id = (id), .phy_id_mask = GENMASK(31, 4)
638#define PHY_ID_MATCH_VENDOR(id) .phy_id = (id), .phy_id_mask = GENMASK(31, 10)
639
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640/* A Structure for boards to register fixups with the PHY Lib */
641struct phy_fixup {
642 struct list_head list;
4567d686 643 char bus_id[MII_BUS_ID_SIZE + 3];
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AF
644 u32 phy_uid;
645 u32 phy_uid_mask;
646 int (*run)(struct phy_device *phydev);
647};
648
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649const char *phy_speed_to_str(int speed);
650const char *phy_duplex_to_str(unsigned int duplex);
651
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652/* A structure for mapping a particular speed and duplex
653 * combination to a particular SUPPORTED and ADVERTISED value
654 */
655struct phy_setting {
656 u32 speed;
657 u8 duplex;
658 u8 bit;
659};
660
661const struct phy_setting *
662phy_lookup_setting(int speed, int duplex, const unsigned long *mask,
3c1bcc86 663 bool exact);
0ccb4fc6 664size_t phy_speeds(unsigned int *speeds, size_t size,
3c1bcc86 665 unsigned long *mask);
a4eaed9f 666void of_set_phy_supported(struct phy_device *phydev);
3feb9b23 667void of_set_phy_eee_broken(struct phy_device *phydev);
0ccb4fc6 668
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669/**
670 * phy_is_started - Convenience function to check whether PHY is started
671 * @phydev: The phy_device struct
672 */
673static inline bool phy_is_started(struct phy_device *phydev)
674{
a2fc9d7e 675 return phydev->state >= PHY_UP;
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HK
676}
677
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678void phy_resolve_aneg_linkmode(struct phy_device *phydev);
679
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LB
680/**
681 * phy_read - Convenience function for reading a given PHY register
682 * @phydev: the phy_device struct
683 * @regnum: register number to read
684 *
685 * NOTE: MUST NOT be called from interrupt context,
686 * because the bus read/write functions may wait for an interrupt
687 * to conclude the operation.
688 */
abf35df2 689static inline int phy_read(struct phy_device *phydev, u32 regnum)
2e888103 690{
e5a03bfd 691 return mdiobus_read(phydev->mdio.bus, phydev->mdio.addr, regnum);
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LB
692}
693
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694/**
695 * __phy_read - convenience function for reading a given PHY register
696 * @phydev: the phy_device struct
697 * @regnum: register number to read
698 *
699 * The caller must have taken the MDIO bus lock.
700 */
701static inline int __phy_read(struct phy_device *phydev, u32 regnum)
702{
703 return __mdiobus_read(phydev->mdio.bus, phydev->mdio.addr, regnum);
704}
705
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LB
706/**
707 * phy_write - Convenience function for writing a given PHY register
708 * @phydev: the phy_device struct
709 * @regnum: register number to write
710 * @val: value to write to @regnum
711 *
712 * NOTE: MUST NOT be called from interrupt context,
713 * because the bus read/write functions may wait for an interrupt
714 * to conclude the operation.
715 */
abf35df2 716static inline int phy_write(struct phy_device *phydev, u32 regnum, u16 val)
2e888103 717{
e5a03bfd 718 return mdiobus_write(phydev->mdio.bus, phydev->mdio.addr, regnum, val);
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LB
719}
720
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721/**
722 * __phy_write - Convenience function for writing a given PHY register
723 * @phydev: the phy_device struct
724 * @regnum: register number to write
725 * @val: value to write to @regnum
726 *
727 * The caller must have taken the MDIO bus lock.
728 */
729static inline int __phy_write(struct phy_device *phydev, u32 regnum, u16 val)
730{
731 return __mdiobus_write(phydev->mdio.bus, phydev->mdio.addr, regnum,
732 val);
733}
734
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735/**
736 * phy_read_mmd - Convenience function for reading a register
737 * from an MMD on a given PHY.
738 * @phydev: The phy_device struct
739 * @devad: The MMD to read from
740 * @regnum: The register on the MMD to read
741 *
742 * Same rules as for phy_read();
743 */
744int phy_read_mmd(struct phy_device *phydev, int devad, u32 regnum);
745
746/**
747 * __phy_read_mmd - Convenience function for reading a register
748 * from an MMD on a given PHY.
749 * @phydev: The phy_device struct
750 * @devad: The MMD to read from
751 * @regnum: The register on the MMD to read
752 *
753 * Same rules as for __phy_read();
754 */
755int __phy_read_mmd(struct phy_device *phydev, int devad, u32 regnum);
756
757/**
758 * phy_write_mmd - Convenience function for writing a register
759 * on an MMD on a given PHY.
760 * @phydev: The phy_device struct
761 * @devad: The MMD to write to
762 * @regnum: The register on the MMD to read
763 * @val: value to write to @regnum
764 *
765 * Same rules as for phy_write();
766 */
767int phy_write_mmd(struct phy_device *phydev, int devad, u32 regnum, u16 val);
768
769/**
770 * __phy_write_mmd - Convenience function for writing a register
771 * on an MMD on a given PHY.
772 * @phydev: The phy_device struct
773 * @devad: The MMD to write to
774 * @regnum: The register on the MMD to read
775 * @val: value to write to @regnum
776 *
777 * Same rules as for __phy_write();
778 */
779int __phy_write_mmd(struct phy_device *phydev, int devad, u32 regnum, u16 val);
780
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781int __phy_modify_changed(struct phy_device *phydev, u32 regnum, u16 mask,
782 u16 set);
783int phy_modify_changed(struct phy_device *phydev, u32 regnum, u16 mask,
784 u16 set);
788f9933 785int __phy_modify(struct phy_device *phydev, u32 regnum, u16 mask, u16 set);
2b74e5be 786int phy_modify(struct phy_device *phydev, u32 regnum, u16 mask, u16 set);
788f9933 787
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HK
788int __phy_modify_mmd_changed(struct phy_device *phydev, int devad, u32 regnum,
789 u16 mask, u16 set);
790int phy_modify_mmd_changed(struct phy_device *phydev, int devad, u32 regnum,
791 u16 mask, u16 set);
1878f0dc 792int __phy_modify_mmd(struct phy_device *phydev, int devad, u32 regnum,
b8554d4f 793 u16 mask, u16 set);
1878f0dc 794int phy_modify_mmd(struct phy_device *phydev, int devad, u32 regnum,
b8554d4f 795 u16 mask, u16 set);
1878f0dc 796
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HK
797/**
798 * __phy_set_bits - Convenience function for setting bits in a PHY register
799 * @phydev: the phy_device struct
800 * @regnum: register number to write
801 * @val: bits to set
802 *
803 * The caller must have taken the MDIO bus lock.
804 */
805static inline int __phy_set_bits(struct phy_device *phydev, u32 regnum, u16 val)
806{
807 return __phy_modify(phydev, regnum, 0, val);
808}
809
810/**
811 * __phy_clear_bits - Convenience function for clearing bits in a PHY register
812 * @phydev: the phy_device struct
813 * @regnum: register number to write
814 * @val: bits to clear
815 *
816 * The caller must have taken the MDIO bus lock.
817 */
818static inline int __phy_clear_bits(struct phy_device *phydev, u32 regnum,
819 u16 val)
820{
821 return __phy_modify(phydev, regnum, val, 0);
822}
823
824/**
825 * phy_set_bits - Convenience function for setting bits in a PHY register
826 * @phydev: the phy_device struct
827 * @regnum: register number to write
828 * @val: bits to set
829 */
830static inline int phy_set_bits(struct phy_device *phydev, u32 regnum, u16 val)
831{
832 return phy_modify(phydev, regnum, 0, val);
833}
834
835/**
836 * phy_clear_bits - Convenience function for clearing bits in a PHY register
837 * @phydev: the phy_device struct
838 * @regnum: register number to write
839 * @val: bits to clear
840 */
841static inline int phy_clear_bits(struct phy_device *phydev, u32 regnum, u16 val)
842{
843 return phy_modify(phydev, regnum, val, 0);
844}
845
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846/**
847 * __phy_set_bits_mmd - Convenience function for setting bits in a register
848 * on MMD
849 * @phydev: the phy_device struct
850 * @devad: the MMD containing register to modify
851 * @regnum: register number to modify
852 * @val: bits to set
853 *
854 * The caller must have taken the MDIO bus lock.
855 */
856static inline int __phy_set_bits_mmd(struct phy_device *phydev, int devad,
857 u32 regnum, u16 val)
858{
859 return __phy_modify_mmd(phydev, devad, regnum, 0, val);
860}
861
862/**
863 * __phy_clear_bits_mmd - Convenience function for clearing bits in a register
864 * on MMD
865 * @phydev: the phy_device struct
866 * @devad: the MMD containing register to modify
867 * @regnum: register number to modify
868 * @val: bits to clear
869 *
870 * The caller must have taken the MDIO bus lock.
871 */
872static inline int __phy_clear_bits_mmd(struct phy_device *phydev, int devad,
873 u32 regnum, u16 val)
874{
875 return __phy_modify_mmd(phydev, devad, regnum, val, 0);
876}
877
878/**
879 * phy_set_bits_mmd - Convenience function for setting bits in a register
880 * on MMD
881 * @phydev: the phy_device struct
882 * @devad: the MMD containing register to modify
883 * @regnum: register number to modify
884 * @val: bits to set
885 */
886static inline int phy_set_bits_mmd(struct phy_device *phydev, int devad,
887 u32 regnum, u16 val)
888{
889 return phy_modify_mmd(phydev, devad, regnum, 0, val);
890}
891
892/**
893 * phy_clear_bits_mmd - Convenience function for clearing bits in a register
894 * on MMD
895 * @phydev: the phy_device struct
896 * @devad: the MMD containing register to modify
897 * @regnum: register number to modify
898 * @val: bits to clear
899 */
900static inline int phy_clear_bits_mmd(struct phy_device *phydev, int devad,
901 u32 regnum, u16 val)
902{
903 return phy_modify_mmd(phydev, devad, regnum, val, 0);
904}
905
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906/**
907 * phy_interrupt_is_valid - Convenience function for testing a given PHY irq
908 * @phydev: the phy_device struct
909 *
910 * NOTE: must be kept in sync with addition/removal of PHY_POLL and
911 * PHY_IGNORE_INTERRUPT
912 */
913static inline bool phy_interrupt_is_valid(struct phy_device *phydev)
914{
915 return phydev->irq != PHY_POLL && phydev->irq != PHY_IGNORE_INTERRUPT;
916}
917
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HK
918/**
919 * phy_polling_mode - Convenience function for testing whether polling is
920 * used to detect PHY status changes
921 * @phydev: the phy_device struct
922 */
923static inline bool phy_polling_mode(struct phy_device *phydev)
924{
925 return phydev->irq == PHY_POLL;
926}
927
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FF
928/**
929 * phy_is_internal - Convenience function for testing if a PHY is internal
930 * @phydev: the phy_device struct
931 */
932static inline bool phy_is_internal(struct phy_device *phydev)
933{
934 return phydev->is_internal;
935}
936
32d0f783
IS
937/**
938 * phy_interface_mode_is_rgmii - Convenience function for testing if a
939 * PHY interface mode is RGMII (all variants)
940 * @mode: the phy_interface_t enum
941 */
942static inline bool phy_interface_mode_is_rgmii(phy_interface_t mode)
943{
944 return mode >= PHY_INTERFACE_MODE_RGMII &&
945 mode <= PHY_INTERFACE_MODE_RGMII_TXID;
946};
947
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RK
948/**
949 * phy_interface_mode_is_8023z() - does the phy interface mode use 802.3z
950 * negotiation
951 * @mode: one of &enum phy_interface_t
952 *
953 * Returns true if the phy interface mode uses the 16-bit negotiation
954 * word as defined in 802.3z. (See 802.3-2015 37.2.1 Config_Reg encoding)
955 */
956static inline bool phy_interface_mode_is_8023z(phy_interface_t mode)
957{
958 return mode == PHY_INTERFACE_MODE_1000BASEX ||
959 mode == PHY_INTERFACE_MODE_2500BASEX;
960}
961
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962/**
963 * phy_interface_is_rgmii - Convenience function for testing if a PHY interface
964 * is RGMII (all variants)
965 * @phydev: the phy_device struct
966 */
967static inline bool phy_interface_is_rgmii(struct phy_device *phydev)
968{
32d0f783 969 return phy_interface_mode_is_rgmii(phydev->interface);
5a11dd7d
FF
970};
971
972/*
973 * phy_is_pseudo_fixed_link - Convenience function for testing if this
974 * PHY is the CPU port facing side of an Ethernet switch, or similar.
975 * @phydev: the phy_device struct
976 */
977static inline bool phy_is_pseudo_fixed_link(struct phy_device *phydev)
978{
979 return phydev->is_pseudo_fixed_link;
e463d88c
FF
980}
981
78ffc4ac
RK
982int phy_save_page(struct phy_device *phydev);
983int phy_select_page(struct phy_device *phydev, int page);
984int phy_restore_page(struct phy_device *phydev, int oldpage, int ret);
985int phy_read_paged(struct phy_device *phydev, int page, u32 regnum);
986int phy_write_paged(struct phy_device *phydev, int page, u32 regnum, u16 val);
987int phy_modify_paged(struct phy_device *phydev, int page, u32 regnum,
988 u16 mask, u16 set);
989
ac28b9f8 990struct phy_device *phy_device_create(struct mii_bus *bus, int addr, int phy_id,
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991 bool is_c45,
992 struct phy_c45_device_ids *c45_ids);
90eff909 993#if IS_ENABLED(CONFIG_PHYLIB)
ac28b9f8 994struct phy_device *get_phy_device(struct mii_bus *bus, int addr, bool is_c45);
4dea547f 995int phy_device_register(struct phy_device *phy);
90eff909
FF
996void phy_device_free(struct phy_device *phydev);
997#else
998static inline
999struct phy_device *get_phy_device(struct mii_bus *bus, int addr, bool is_c45)
1000{
1001 return NULL;
1002}
1003
1004static inline int phy_device_register(struct phy_device *phy)
1005{
1006 return 0;
1007}
1008
1009static inline void phy_device_free(struct phy_device *phydev) { }
1010#endif /* CONFIG_PHYLIB */
38737e49 1011void phy_device_remove(struct phy_device *phydev);
2f5cb434 1012int phy_init_hw(struct phy_device *phydev);
481b5d93
SH
1013int phy_suspend(struct phy_device *phydev);
1014int phy_resume(struct phy_device *phydev);
9c2c2e62 1015int __phy_resume(struct phy_device *phydev);
f0f9b4ed 1016int phy_loopback(struct phy_device *phydev, bool enable);
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SS
1017struct phy_device *phy_attach(struct net_device *dev, const char *bus_id,
1018 phy_interface_t interface);
f8f76db1 1019struct phy_device *phy_find_first(struct mii_bus *bus);
257184d7
AF
1020int phy_attach_direct(struct net_device *dev, struct phy_device *phydev,
1021 u32 flags, phy_interface_t interface);
fa94f6d9 1022int phy_connect_direct(struct net_device *dev, struct phy_device *phydev,
4017b4d3
SS
1023 void (*handler)(struct net_device *),
1024 phy_interface_t interface);
1025struct phy_device *phy_connect(struct net_device *dev, const char *bus_id,
1026 void (*handler)(struct net_device *),
1027 phy_interface_t interface);
e1393456
AF
1028void phy_disconnect(struct phy_device *phydev);
1029void phy_detach(struct phy_device *phydev);
1030void phy_start(struct phy_device *phydev);
1031void phy_stop(struct phy_device *phydev);
1032int phy_start_aneg(struct phy_device *phydev);
372788f9 1033int phy_aneg_done(struct phy_device *phydev);
2b9672dd
HK
1034int phy_speed_down(struct phy_device *phydev, bool sync);
1035int phy_speed_up(struct phy_device *phydev);
e1393456 1036
002ba705 1037int phy_restart_aneg(struct phy_device *phydev);
a9668491 1038int phy_reset_after_clk_enable(struct phy_device *phydev);
00db8189 1039
bafbdd52
SS
1040static inline void phy_device_reset(struct phy_device *phydev, int value)
1041{
1042 mdio_device_reset(&phydev->mdio, value);
1043}
1044
72ba48be 1045#define phydev_err(_phydev, format, args...) \
e5a03bfd 1046 dev_err(&_phydev->mdio.dev, format, ##args)
72ba48be 1047
c4fabb8b
AL
1048#define phydev_info(_phydev, format, args...) \
1049 dev_info(&_phydev->mdio.dev, format, ##args)
1050
ab2a605f
AL
1051#define phydev_warn(_phydev, format, args...) \
1052 dev_warn(&_phydev->mdio.dev, format, ##args)
1053
72ba48be 1054#define phydev_dbg(_phydev, format, args...) \
2eaa38d9 1055 dev_dbg(&_phydev->mdio.dev, format, ##args)
72ba48be 1056
84eff6d1
AL
1057static inline const char *phydev_name(const struct phy_device *phydev)
1058{
e5a03bfd 1059 return dev_name(&phydev->mdio.dev);
84eff6d1
AL
1060}
1061
2220943a
AL
1062void phy_attached_print(struct phy_device *phydev, const char *fmt, ...)
1063 __printf(2, 3);
1064void phy_attached_info(struct phy_device *phydev);
5acde34a
RK
1065
1066/* Clause 22 PHY */
af6b6967 1067int genphy_config_init(struct phy_device *phydev);
045925e3 1068int genphy_read_abilities(struct phy_device *phydev);
3fb69bca 1069int genphy_setup_forced(struct phy_device *phydev);
00db8189 1070int genphy_restart_aneg(struct phy_device *phydev);
cd34499c 1071int genphy_config_eee_advert(struct phy_device *phydev);
f4069cd7 1072int __genphy_config_aneg(struct phy_device *phydev, bool changed);
a9fa6e6a 1073int genphy_aneg_done(struct phy_device *phydev);
00db8189
AF
1074int genphy_update_link(struct phy_device *phydev);
1075int genphy_read_status(struct phy_device *phydev);
0f0ca340
GC
1076int genphy_suspend(struct phy_device *phydev);
1077int genphy_resume(struct phy_device *phydev);
f0f9b4ed 1078int genphy_loopback(struct phy_device *phydev, bool enable);
797ac071 1079int genphy_soft_reset(struct phy_device *phydev);
f4069cd7
HK
1080
1081static inline int genphy_config_aneg(struct phy_device *phydev)
1082{
1083 return __genphy_config_aneg(phydev, false);
1084}
1085
0878fff1
FF
1086static inline int genphy_no_soft_reset(struct phy_device *phydev)
1087{
1088 return 0;
1089}
4c8e0459
LW
1090static inline int genphy_no_ack_interrupt(struct phy_device *phydev)
1091{
1092 return 0;
1093}
1094static inline int genphy_no_config_intr(struct phy_device *phydev)
1095{
1096 return 0;
1097}
5df7af85
KH
1098int genphy_read_mmd_unsupported(struct phy_device *phdev, int devad,
1099 u16 regnum);
1100int genphy_write_mmd_unsupported(struct phy_device *phdev, int devnum,
1101 u16 regnum, u16 val);
5acde34a
RK
1102
1103/* Clause 45 PHY */
1104int genphy_c45_restart_aneg(struct phy_device *phydev);
1af9f168 1105int genphy_c45_check_and_restart_aneg(struct phy_device *phydev, bool restart);
5acde34a 1106int genphy_c45_aneg_done(struct phy_device *phydev);
998a8a83 1107int genphy_c45_read_link(struct phy_device *phydev);
5acde34a
RK
1108int genphy_c45_read_lpa(struct phy_device *phydev);
1109int genphy_c45_read_pma(struct phy_device *phydev);
1110int genphy_c45_pma_setup_forced(struct phy_device *phydev);
9a5dc8af 1111int genphy_c45_an_config_aneg(struct phy_device *phydev);
5acde34a 1112int genphy_c45_an_disable_aneg(struct phy_device *phydev);
ea4efe25 1113int genphy_c45_read_mdix(struct phy_device *phydev);
ac3f5533 1114int genphy_c45_pma_read_abilities(struct phy_device *phydev);
70fa3a96 1115int genphy_c45_read_status(struct phy_device *phydev);
5acde34a 1116
e8a714e0
FF
1117/* The gen10g_* functions are the old Clause 45 stub */
1118int gen10g_config_aneg(struct phy_device *phydev);
e8a714e0 1119
00fde795
HK
1120static inline int phy_read_status(struct phy_device *phydev)
1121{
1122 if (!phydev->drv)
1123 return -EIO;
1124
1125 if (phydev->drv->read_status)
1126 return phydev->drv->read_status(phydev);
1127 else
1128 return genphy_read_status(phydev);
1129}
1130
00db8189 1131void phy_driver_unregister(struct phy_driver *drv);
d5bf9071 1132void phy_drivers_unregister(struct phy_driver *drv, int n);
be01da72
AL
1133int phy_driver_register(struct phy_driver *new_driver, struct module *owner);
1134int phy_drivers_register(struct phy_driver *new_driver, int n,
1135 struct module *owner);
4f9c85a1 1136void phy_state_machine(struct work_struct *work);
97b33bdf 1137void phy_queue_state_machine(struct phy_device *phydev, unsigned long jiffies);
28b2e0d2 1138void phy_mac_interrupt(struct phy_device *phydev);
29935aeb 1139void phy_start_machine(struct phy_device *phydev);
00db8189
AF
1140void phy_stop_machine(struct phy_device *phydev);
1141int phy_ethtool_sset(struct phy_device *phydev, struct ethtool_cmd *cmd);
5514174f 1142void phy_ethtool_ksettings_get(struct phy_device *phydev,
1143 struct ethtool_link_ksettings *cmd);
2d55173e
PR
1144int phy_ethtool_ksettings_set(struct phy_device *phydev,
1145 const struct ethtool_link_ksettings *cmd);
4017b4d3 1146int phy_mii_ioctl(struct phy_device *phydev, struct ifreq *ifr, int cmd);
434a4315 1147void phy_request_interrupt(struct phy_device *phydev);
07b09289 1148void phy_free_interrupt(struct phy_device *phydev);
e1393456 1149void phy_print_status(struct phy_device *phydev);
f3a6bd39 1150int phy_set_max_speed(struct phy_device *phydev, u32 max_speed);
41124fa6 1151void phy_remove_link_mode(struct phy_device *phydev, u32 link_mode);
22c0ef6b 1152void phy_advertise_supported(struct phy_device *phydev);
c306ad36 1153void phy_support_sym_pause(struct phy_device *phydev);
af8d9bb2 1154void phy_support_asym_pause(struct phy_device *phydev);
0c122405
AL
1155void phy_set_sym_pause(struct phy_device *phydev, bool rx, bool tx,
1156 bool autoneg);
70814e81 1157void phy_set_asym_pause(struct phy_device *phydev, bool rx, bool tx);
22b7d299
AL
1158bool phy_validate_pause(struct phy_device *phydev,
1159 struct ethtool_pauseparam *pp);
00db8189 1160
f62220d3 1161int phy_register_fixup(const char *bus_id, u32 phy_uid, u32 phy_uid_mask,
4017b4d3 1162 int (*run)(struct phy_device *));
f62220d3 1163int phy_register_fixup_for_id(const char *bus_id,
4017b4d3 1164 int (*run)(struct phy_device *));
f62220d3 1165int phy_register_fixup_for_uid(u32 phy_uid, u32 phy_uid_mask,
4017b4d3 1166 int (*run)(struct phy_device *));
f62220d3 1167
f38e7a32
WH
1168int phy_unregister_fixup(const char *bus_id, u32 phy_uid, u32 phy_uid_mask);
1169int phy_unregister_fixup_for_id(const char *bus_id);
1170int phy_unregister_fixup_for_uid(u32 phy_uid, u32 phy_uid_mask);
1171
a59a4d19
GC
1172int phy_init_eee(struct phy_device *phydev, bool clk_stop_enable);
1173int phy_get_eee_err(struct phy_device *phydev);
1174int phy_ethtool_set_eee(struct phy_device *phydev, struct ethtool_eee *data);
1175int phy_ethtool_get_eee(struct phy_device *phydev, struct ethtool_eee *data);
42e836eb 1176int phy_ethtool_set_wol(struct phy_device *phydev, struct ethtool_wolinfo *wol);
4017b4d3
SS
1177void phy_ethtool_get_wol(struct phy_device *phydev,
1178 struct ethtool_wolinfo *wol);
9d9a77ce
PR
1179int phy_ethtool_get_link_ksettings(struct net_device *ndev,
1180 struct ethtool_link_ksettings *cmd);
1181int phy_ethtool_set_link_ksettings(struct net_device *ndev,
1182 const struct ethtool_link_ksettings *cmd);
e86a8987 1183int phy_ethtool_nway_reset(struct net_device *ndev);
a59a4d19 1184
90eff909 1185#if IS_ENABLED(CONFIG_PHYLIB)
9b9a8bfc
AF
1186int __init mdio_bus_init(void);
1187void mdio_bus_exit(void);
9e8d438e
FF
1188#endif
1189
1190/* Inline function for use within net/core/ethtool.c (built-in) */
1191static inline int phy_ethtool_get_strings(struct phy_device *phydev, u8 *data)
c59530d0 1192{
9e8d438e
FF
1193 if (!phydev->drv)
1194 return -EIO;
1195
1196 mutex_lock(&phydev->lock);
1197 phydev->drv->get_strings(phydev, data);
1198 mutex_unlock(&phydev->lock);
1199
1200 return 0;
c59530d0
FF
1201}
1202
9e8d438e 1203static inline int phy_ethtool_get_sset_count(struct phy_device *phydev)
c59530d0 1204{
9e8d438e
FF
1205 int ret;
1206
1207 if (!phydev->drv)
1208 return -EIO;
1209
1210 if (phydev->drv->get_sset_count &&
1211 phydev->drv->get_strings &&
1212 phydev->drv->get_stats) {
1213 mutex_lock(&phydev->lock);
1214 ret = phydev->drv->get_sset_count(phydev);
1215 mutex_unlock(&phydev->lock);
1216
1217 return ret;
1218 }
1219
c59530d0
FF
1220 return -EOPNOTSUPP;
1221}
1222
9e8d438e
FF
1223static inline int phy_ethtool_get_stats(struct phy_device *phydev,
1224 struct ethtool_stats *stats, u64 *data)
c59530d0 1225{
9e8d438e
FF
1226 if (!phydev->drv)
1227 return -EIO;
1228
1229 mutex_lock(&phydev->lock);
1230 phydev->drv->get_stats(phydev, stats, data);
1231 mutex_unlock(&phydev->lock);
1232
1233 return 0;
c59530d0 1234}
9b9a8bfc 1235
00db8189 1236extern struct bus_type mdio_bus_type;
c31accd1 1237
648ea013
FF
1238struct mdio_board_info {
1239 const char *bus_id;
1240 char modalias[MDIO_NAME_SIZE];
1241 int mdio_addr;
1242 const void *platform_data;
1243};
1244
90eff909 1245#if IS_ENABLED(CONFIG_MDIO_DEVICE)
648ea013
FF
1246int mdiobus_register_board_info(const struct mdio_board_info *info,
1247 unsigned int n);
1248#else
1249static inline int mdiobus_register_board_info(const struct mdio_board_info *i,
1250 unsigned int n)
1251{
1252 return 0;
1253}
1254#endif
1255
1256
c31accd1
JH
1257/**
1258 * module_phy_driver() - Helper macro for registering PHY drivers
1259 * @__phy_drivers: array of PHY drivers to register
1260 *
1261 * Helper macro for PHY drivers which do not do anything special in module
1262 * init/exit. Each module may only use this macro once, and calling it
1263 * replaces module_init() and module_exit().
1264 */
1265#define phy_module_driver(__phy_drivers, __count) \
1266static int __init phy_module_init(void) \
1267{ \
be01da72 1268 return phy_drivers_register(__phy_drivers, __count, THIS_MODULE); \
c31accd1
JH
1269} \
1270module_init(phy_module_init); \
1271static void __exit phy_module_exit(void) \
1272{ \
1273 phy_drivers_unregister(__phy_drivers, __count); \
1274} \
1275module_exit(phy_module_exit)
1276
1277#define module_phy_driver(__phy_drivers) \
1278 phy_module_driver(__phy_drivers, ARRAY_SIZE(__phy_drivers))
1279
5db5ea99
FF
1280bool phy_driver_is_genphy(struct phy_device *phydev);
1281bool phy_driver_is_genphy_10g(struct phy_device *phydev);
1282
00db8189 1283#endif /* __PHY_H */