projects / mirror_ubuntu-bionic-kernel.git / blame
| Commit | Line | Data |
|---|---|---|
| 3bfb1d20 | 1 | /* |
| dd5720b3 | 2 | * Driver for the Synopsys DesignWare DMA Controller |
| 3bfb1d20 HS |
3 | * |
| 4 | * Copyright (C) 2007 Atmel Corporation | |
| aecb7b64 | 5 | * Copyright (C) 2010-2011 ST Microelectronics |
| 3bfb1d20 HS |
6 | * |
| 7 | * This program is free software; you can redistribute it and/or modify | |
| 8 | * it under the terms of the GNU General Public License version 2 as | |
| 9 | * published by the Free Software Foundation. | |
| 10 | */ | |
| 3d588f83 AS |
11 | #ifndef _PLATFORM_DATA_DMA_DW_H |
| 12 | #define _PLATFORM_DATA_DMA_DW_H | |
| 3bfb1d20 | 13 | |
| 3d588f83 | 14 | #include <linux/device.h> |
| 3bfb1d20 | 15 | |
| d8ded50f | 16 | #define DW_DMA_MAX_NR_MASTERS 4 |
| bd2c6636 | 17 | #define DW_DMA_MAX_NR_CHANNELS 8 |
| d8ded50f | 18 | |
| a9ddb575 VK |
19 | /** |
| 20 | * struct dw_dma_slave - Controller-specific information about a slave | |
| 21 | * | |
| cfd8fef3 | 22 | * @dma_dev: required DMA master device |
| 7e1e2f27 AS |
23 | * @src_id: src request line |
| 24 | * @dst_id: dst request line | |
| c422025c AS |
25 | * @m_master: memory master for transfers on allocated channel |
| 26 | * @p_master: peripheral master for transfers on allocated channel | |
| c072e113 | 27 | * @hs_polarity:set active low polarity of handshake interface |
| a9ddb575 VK |
28 | */ |
| 29 | struct dw_dma_slave { | |
| 30 | struct device *dma_dev; | |
| 7e1e2f27 AS |
31 | u8 src_id; |
| 32 | u8 dst_id; | |
| c422025c AS |
33 | u8 m_master; |
| 34 | u8 p_master; | |
| c072e113 | 35 | bool hs_polarity; |
| a9ddb575 VK |
36 | }; |
| 37 | ||
| 3bfb1d20 HS |
38 | /** |
| 39 | * struct dw_dma_platform_data - Controller configuration parameters | |
| 40 | * @nr_channels: Number of channels supported by hardware (max 8) | |
| 95ea759e JI |
41 | * @is_private: The device channels should be marked as private and not for |
| 42 | * by the general purpose DMA channel allocator. | |
| df5c7386 | 43 | * @is_memcpy: The device channels do support memory-to-memory transfers. |
| 199244d6 | 44 | * @is_idma32: The type of the DMA controller is iDMA32 |
| 177d2bf5 VK |
45 | * @chan_allocation_order: Allocate channels starting from 0 or 7 |
| 46 | * @chan_priority: Set channel priority increasing from 0 to 7 or 7 to 0. | |
| 4a63a8b3 | 47 | * @block_size: Maximum block size supported by the controller |
| a0982004 AS |
48 | * @nr_masters: Number of AHB masters supported by the controller |
| 49 | * @data_width: Maximum data width supported by hardware per AHB master | |
| 2e65060e | 50 | * (in bytes, power of 2) |
| bd2c6636 | 51 | * @multi_block: Multi block transfers supported by hardware per channel. |
| 6e9c7a36 | 52 | * @protctl: Protection control signals setting per channel. |
| 3bfb1d20 HS |
53 | */ |
| 54 | struct dw_dma_platform_data { | |
| 55 | unsigned int nr_channels; | |
| 95ea759e | 56 | bool is_private; |
| df5c7386 | 57 | bool is_memcpy; |
| 199244d6 | 58 | bool is_idma32; |
| b0c3130d VK |
59 | #define CHAN_ALLOCATION_ASCENDING 0 /* zero to seven */ |
| 60 | #define CHAN_ALLOCATION_DESCENDING 1 /* seven to zero */ | |
| 61 | unsigned char chan_allocation_order; | |
| 93317e8e VK |
62 | #define CHAN_PRIORITY_ASCENDING 0 /* chan0 highest */ |
| 63 | #define CHAN_PRIORITY_DESCENDING 1 /* chan7 highest */ | |
| 64 | unsigned char chan_priority; | |
| 161c3d04 | 65 | unsigned int block_size; |
| a0982004 | 66 | unsigned char nr_masters; |
| d8ded50f | 67 | unsigned char data_width[DW_DMA_MAX_NR_MASTERS]; |
| bd2c6636 | 68 | unsigned char multi_block[DW_DMA_MAX_NR_CHANNELS]; |
| 6e9c7a36 CL |
69 | #define CHAN_PROTCTL_PRIVILEGED BIT(0) |
| 70 | #define CHAN_PROTCTL_BUFFERABLE BIT(1) | |
| 71 | #define CHAN_PROTCTL_CACHEABLE BIT(2) | |
| 72 | #define CHAN_PROTCTL_MASK GENMASK(2, 0) | |
| 73 | unsigned char protctl; | |
| 3bfb1d20 HS |
74 | }; |
| 75 | ||
| 3d588f83 | 76 | #endif /* _PLATFORM_DATA_DMA_DW_H */ |