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1 | /* |
2 | * include/linux/platform_data/pxa_sdhci.h | |
536ac998 ZG |
3 | * |
4 | * Copyright 2010 Marvell | |
5 | * Zhangfei Gao <zhangfei.gao@marvell.com> | |
6 | * | |
7 | * PXA Platform - SDHCI platform data definitions | |
8 | * | |
9 | * This program is free software; you can redistribute it and/or modify | |
10 | * it under the terms of the GNU General Public License version 2 as | |
11 | * published by the Free Software Foundation. | |
12 | */ | |
13 | ||
bfed345e ZG |
14 | #ifndef _PXA_SDHCI_H_ |
15 | #define _PXA_SDHCI_H_ | |
536ac998 ZG |
16 | |
17 | /* pxa specific flag */ | |
18 | /* Require clock free running */ | |
a702c8ab ZG |
19 | #define PXA_FLAG_ENABLE_CLOCK_GATING (1<<0) |
20 | /* card always wired to host, like on-chip emmc */ | |
21 | #define PXA_FLAG_CARD_PERMANENT (1<<1) | |
15ec4461 PR |
22 | /* Board design supports 8-bit data on SD/SDIO BUS */ |
23 | #define PXA_FLAG_SD_8_BIT_CAPABLE_SLOT (1<<2) | |
24 | ||
536ac998 ZG |
25 | /* |
26 | * struct pxa_sdhci_platdata() - Platform device data for PXA SDHCI | |
536ac998 | 27 | * @flags: flags for platform requirement |
a702c8ab ZG |
28 | * @clk_delay_cycles: |
29 | * mmp2: each step is roughly 100ps, 5bits width | |
30 | * pxa910: each step is 1ns, 4bits width | |
31 | * @clk_delay_sel: select clk_delay, used on pxa910 | |
32 | * 0: choose feedback clk | |
33 | * 1: choose feedback clk + delay value | |
34 | * 2: choose internal clk | |
35 | * @clk_delay_enable: enable clk_delay or not, used on pxa910 | |
36 | * @ext_cd_gpio: gpio pin used for external CD line | |
37 | * @ext_cd_gpio_invert: invert values for external CD gpio line | |
38 | * @max_speed: the maximum speed supported | |
39 | * @host_caps: Standard MMC host capabilities bit field. | |
40 | * @quirks: quirks of platfrom | |
7c52d7bb | 41 | * @quirks2: quirks2 of platfrom |
a702c8ab | 42 | * @pm_caps: pm_caps of platfrom |
536ac998 ZG |
43 | */ |
44 | struct sdhci_pxa_platdata { | |
a702c8ab ZG |
45 | unsigned int flags; |
46 | unsigned int clk_delay_cycles; | |
47 | unsigned int clk_delay_sel; | |
48 | bool clk_delay_enable; | |
49 | unsigned int ext_cd_gpio; | |
50 | bool ext_cd_gpio_invert; | |
536ac998 | 51 | unsigned int max_speed; |
5f1a4dd0 LJ |
52 | u32 host_caps; |
53 | u32 host_caps2; | |
536ac998 | 54 | unsigned int quirks; |
7c52d7bb | 55 | unsigned int quirks2; |
a702c8ab ZG |
56 | unsigned int pm_caps; |
57 | }; | |
bfed345e | 58 | #endif /* _PXA_SDHCI_H_ */ |