[mirror_ubuntu-artful-kernel.git] / include / linux / power / smartreflex.h

/*
 * OMAP Smartreflex Defines and Routines
 *
 * Author: Thara Gopinath	<thara@ti.com>
 *
 * Copyright (C) 2010 Texas Instruments, Inc.
 * Thara Gopinath <thara@ti.com>
 *
 * Copyright (C) 2008 Nokia Corporation
 * Kalle Jokiniemi
 *
 * Copyright (C) 2007 Texas Instruments, Inc.
 * Lesly A M <x0080970@ti.com>
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */

#ifndef __POWER_SMARTREFLEX_H
#define __POWER_SMARTREFLEX_H

#include <linux/types.h>
#include <linux/platform_device.h>

#include <plat/voltage.h>

/*
 * Different Smartreflex IPs version. The v1 is the 65nm version used in
 * OMAP3430. The v2 is the update for the 45nm version of the IP
 * used in OMAP3630 and OMAP4430
 */
#define SR_TYPE_V1	1
#define SR_TYPE_V2	2

/* SMART REFLEX REG ADDRESS OFFSET */
#define SRCONFIG		0x00
#define SRSTATUS		0x04
#define SENVAL			0x08
#define SENMIN			0x0C
#define SENMAX			0x10
#define SENAVG			0x14
#define AVGWEIGHT		0x18
#define NVALUERECIPROCAL	0x1c
#define SENERROR_V1		0x20
#define ERRCONFIG_V1		0x24
#define IRQ_EOI			0x20
#define IRQSTATUS_RAW		0x24
#define IRQSTATUS		0x28
#define IRQENABLE_SET		0x2C
#define IRQENABLE_CLR		0x30
#define SENERROR_V2		0x34
#define ERRCONFIG_V2		0x38

/* Bit/Shift Positions */

/* SRCONFIG */
#define SRCONFIG_ACCUMDATA_SHIFT	22
#define SRCONFIG_SRCLKLENGTH_SHIFT	12
#define SRCONFIG_SENNENABLE_V1_SHIFT	5
#define SRCONFIG_SENPENABLE_V1_SHIFT	3
#define SRCONFIG_SENNENABLE_V2_SHIFT	1
#define SRCONFIG_SENPENABLE_V2_SHIFT	0
#define SRCONFIG_CLKCTRL_SHIFT		0

#define SRCONFIG_ACCUMDATA_MASK		(0x3ff << 22)

#define SRCONFIG_SRENABLE		BIT(11)
#define SRCONFIG_SENENABLE		BIT(10)
#define SRCONFIG_ERRGEN_EN		BIT(9)
#define SRCONFIG_MINMAXAVG_EN		BIT(8)
#define SRCONFIG_DELAYCTRL		BIT(2)

/* AVGWEIGHT */
#define AVGWEIGHT_SENPAVGWEIGHT_SHIFT	2
#define AVGWEIGHT_SENNAVGWEIGHT_SHIFT	0

/* NVALUERECIPROCAL */
#define NVALUERECIPROCAL_SENPGAIN_SHIFT	20
#define NVALUERECIPROCAL_SENNGAIN_SHIFT	16
#define NVALUERECIPROCAL_RNSENP_SHIFT	8
#define NVALUERECIPROCAL_RNSENN_SHIFT	0

/* ERRCONFIG */
#define ERRCONFIG_ERRWEIGHT_SHIFT	16
#define ERRCONFIG_ERRMAXLIMIT_SHIFT	8
#define ERRCONFIG_ERRMINLIMIT_SHIFT	0

#define SR_ERRWEIGHT_MASK		(0x07 << 16)
#define SR_ERRMAXLIMIT_MASK		(0xff << 8)
#define SR_ERRMINLIMIT_MASK		(0xff << 0)

#define ERRCONFIG_VPBOUNDINTEN_V1	BIT(31)
#define ERRCONFIG_VPBOUNDINTST_V1	BIT(30)
#define	ERRCONFIG_MCUACCUMINTEN		BIT(29)
#define ERRCONFIG_MCUACCUMINTST		BIT(28)
#define	ERRCONFIG_MCUVALIDINTEN		BIT(27)
#define ERRCONFIG_MCUVALIDINTST		BIT(26)
#define ERRCONFIG_MCUBOUNDINTEN		BIT(25)
#define	ERRCONFIG_MCUBOUNDINTST		BIT(24)
#define	ERRCONFIG_MCUDISACKINTEN	BIT(23)
#define ERRCONFIG_VPBOUNDINTST_V2	BIT(23)
#define ERRCONFIG_MCUDISACKINTST	BIT(22)
#define ERRCONFIG_VPBOUNDINTEN_V2	BIT(22)

#define ERRCONFIG_STATUS_V1_MASK	(ERRCONFIG_VPBOUNDINTST_V1 | \
					ERRCONFIG_MCUACCUMINTST | \
					ERRCONFIG_MCUVALIDINTST | \
					ERRCONFIG_MCUBOUNDINTST | \
					ERRCONFIG_MCUDISACKINTST)
/* IRQSTATUS */
#define IRQSTATUS_MCUACCUMINT		BIT(3)
#define IRQSTATUS_MCVALIDINT		BIT(2)
#define IRQSTATUS_MCBOUNDSINT		BIT(1)
#define IRQSTATUS_MCUDISABLEACKINT	BIT(0)

/* IRQENABLE_SET and IRQENABLE_CLEAR */
#define IRQENABLE_MCUACCUMINT		BIT(3)
#define IRQENABLE_MCUVALIDINT		BIT(2)
#define IRQENABLE_MCUBOUNDSINT		BIT(1)
#define IRQENABLE_MCUDISABLEACKINT	BIT(0)

/* Common Bit values */

#define SRCLKLENGTH_12MHZ_SYSCLK	0x3c
#define SRCLKLENGTH_13MHZ_SYSCLK	0x41
#define SRCLKLENGTH_19MHZ_SYSCLK	0x60
#define SRCLKLENGTH_26MHZ_SYSCLK	0x82
#define SRCLKLENGTH_38MHZ_SYSCLK	0xC0

/*
 * 3430 specific values. Maybe these should be passed from board file or
 * pmic structures.
 */
#define OMAP3430_SR_ACCUMDATA		0x1f4

#define OMAP3430_SR1_SENPAVGWEIGHT	0x03
#define OMAP3430_SR1_SENNAVGWEIGHT	0x03

#define OMAP3430_SR2_SENPAVGWEIGHT	0x01
#define OMAP3430_SR2_SENNAVGWEIGHT	0x01

#define OMAP3430_SR_ERRWEIGHT		0x04
#define OMAP3430_SR_ERRMAXLIMIT		0x02

struct omap_sr {
	struct list_head		node;
	struct platform_device		*pdev;
	struct omap_sr_nvalue_table	*nvalue_table;
	struct voltagedomain		*voltdm;
	struct dentry			*dbg_dir;
	unsigned int			irq;
	int				srid;
	int				ip_type;
	int				nvalue_count;
	bool				autocomp_active;
	u32				clk_length;
	u32				err_weight;
	u32				err_minlimit;
	u32				err_maxlimit;
	u32				accum_data;
	u32				senn_avgweight;
	u32				senp_avgweight;
	u32				senp_mod;
	u32				senn_mod;
	void __iomem			*base;
};

/**
 * struct omap_sr_pmic_data - Strucutre to be populated by pmic code to pass
 *				pmic specific info to smartreflex driver
 *
 * @sr_pmic_init:	API to initialize smartreflex on the PMIC side.
 */
struct omap_sr_pmic_data {
	void (*sr_pmic_init) (void);
};

/**
 * struct omap_smartreflex_dev_attr - Smartreflex Device attribute.
 *
 * @sensor_voltdm_name:       Name of voltdomain of SR instance
 */
struct omap_smartreflex_dev_attr {
	const char      *sensor_voltdm_name;
};

#ifdef CONFIG_OMAP_SMARTREFLEX
/*
 * The smart reflex driver supports CLASS1 CLASS2 and CLASS3 SR.
 * The smartreflex class driver should pass the class type.
 * Should be used to populate the class_type field of the
 * omap_smartreflex_class_data structure.
 */
#define SR_CLASS1	0x1
#define SR_CLASS2	0x2
#define SR_CLASS3	0x3

/**
 * struct omap_sr_class_data - Smartreflex class driver info
 *
 * @enable:		API to enable a particular class smaartreflex.
 * @disable:		API to disable a particular class smartreflex.
 * @configure:		API to configure a particular class smartreflex.
 * @notify:		API to notify the class driver about an event in SR.
 *			Not needed for class3.
 * @notify_flags:	specify the events to be notified to the class driver
 * @class_type:		specify which smartreflex class.
 *			Can be used by the SR driver to take any class
 *			based decisions.
 */
struct omap_sr_class_data {
	int (*enable)(struct omap_sr *sr);
	int (*disable)(struct omap_sr *sr, int is_volt_reset);
	int (*configure)(struct omap_sr *sr);
	int (*notify)(struct omap_sr *sr, u32 status);
	u8 notify_flags;
	u8 class_type;
};

/**
 * struct omap_sr_nvalue_table	- Smartreflex n-target value info
 *
 * @efuse_offs:	The offset of the efuse where n-target values are stored.
 * @nvalue:	The n-target value.
 */
struct omap_sr_nvalue_table {
	u32 efuse_offs;
	u32 nvalue;
};

/**
 * struct omap_sr_data - Smartreflex platform data.
 *
 * @ip_type:		Smartreflex IP type.
 * @senp_mod:		SENPENABLE value for the sr
 * @senn_mod:		SENNENABLE value for sr
 * @nvalue_count:	Number of distinct nvalues in the nvalue table
 * @enable_on_init:	whether this sr module needs to enabled at
 *			boot up or not.
 * @nvalue_table:	table containing the  efuse offsets and nvalues
 *			corresponding to them.
 * @voltdm:		Pointer to the voltage domain associated with the SR
 */
struct omap_sr_data {
	int				ip_type;
	u32				senp_mod;
	u32				senn_mod;
	int				nvalue_count;
	bool				enable_on_init;
	struct omap_sr_nvalue_table	*nvalue_table;
	struct voltagedomain		*voltdm;
};

/* Smartreflex module enable/disable interface */
void omap_sr_enable(struct voltagedomain *voltdm);
void omap_sr_disable(struct voltagedomain *voltdm);
void omap_sr_disable_reset_volt(struct voltagedomain *voltdm);

/* API to register the pmic specific data with the smartreflex driver. */
void omap_sr_register_pmic(struct omap_sr_pmic_data *pmic_data);

/* Smartreflex driver hooks to be called from Smartreflex class driver */
int sr_enable(struct voltagedomain *voltdm, unsigned long volt);
void sr_disable(struct voltagedomain *voltdm);
int sr_configure_errgen(struct voltagedomain *voltdm);
int sr_disable_errgen(struct voltagedomain *voltdm);
int sr_configure_minmax(struct voltagedomain *voltdm);

/* API to register the smartreflex class driver with the smartreflex driver */
int sr_register_class(struct omap_sr_class_data *class_data);
#else
static inline void omap_sr_enable(struct voltagedomain *voltdm) {}
static inline void omap_sr_disable(struct voltagedomain *voltdm) {}
static inline void omap_sr_disable_reset_volt(
		struct voltagedomain *voltdm) {}
static inline void omap_sr_register_pmic(
		struct omap_sr_pmic_data *pmic_data) {}
#endif
#endif
Commit	Line	Data
984aa6db TG	1	/*
	2	* OMAP Smartreflex Defines and Routines
	3	*
	4	* Author: Thara Gopinath <thara@ti.com>
	5	*
	6	* Copyright (C) 2010 Texas Instruments, Inc.
	7	* Thara Gopinath <thara@ti.com>
	8	*
	9	* Copyright (C) 2008 Nokia Corporation
	10	* Kalle Jokiniemi
	11	*
	12	* Copyright (C) 2007 Texas Instruments, Inc.
	13	* Lesly A M <x0080970@ti.com>
	14	*
	15	* This program is free software; you can redistribute it and/or modify
	16	* it under the terms of the GNU General Public License version 2 as
	17	* published by the Free Software Foundation.
	18	*/
	19
b86aeafc JP	20	#ifndef __POWER_SMARTREFLEX_H
b86aeafc JP	21	#define __POWER_SMARTREFLEX_H
984aa6db	22
b86aeafc	23	#include <linux/types.h>
984aa6db	24	#include <linux/platform_device.h>
e1d6f472	25
b86aeafc	26	#include <plat/voltage.h>
984aa6db TG	27
	28	/*
	29	* Different Smartreflex IPs version. The v1 is the 65nm version used in
	30	* OMAP3430. The v2 is the update for the 45nm version of the IP
	31	* used in OMAP3630 and OMAP4430
	32	*/
	33	#define SR_TYPE_V1 1
	34	#define SR_TYPE_V2 2
	35
	36	/* SMART REFLEX REG ADDRESS OFFSET */
	37	#define SRCONFIG 0x00
	38	#define SRSTATUS 0x04
	39	#define SENVAL 0x08
	40	#define SENMIN 0x0C
	41	#define SENMAX 0x10
	42	#define SENAVG 0x14
	43	#define AVGWEIGHT 0x18
	44	#define NVALUERECIPROCAL 0x1c
	45	#define SENERROR_V1 0x20
	46	#define ERRCONFIG_V1 0x24
	47	#define IRQ_EOI 0x20
	48	#define IRQSTATUS_RAW 0x24
	49	#define IRQSTATUS 0x28
	50	#define IRQENABLE_SET 0x2C
	51	#define IRQENABLE_CLR 0x30
	52	#define SENERROR_V2 0x34
	53	#define ERRCONFIG_V2 0x38
	54
	55	/* Bit/Shift Positions */
	56
	57	/* SRCONFIG */
	58	#define SRCONFIG_ACCUMDATA_SHIFT 22
	59	#define SRCONFIG_SRCLKLENGTH_SHIFT 12
	60	#define SRCONFIG_SENNENABLE_V1_SHIFT 5
	61	#define SRCONFIG_SENPENABLE_V1_SHIFT 3
	62	#define SRCONFIG_SENNENABLE_V2_SHIFT 1
	63	#define SRCONFIG_SENPENABLE_V2_SHIFT 0
	64	#define SRCONFIG_CLKCTRL_SHIFT 0
	65
	66	#define SRCONFIG_ACCUMDATA_MASK (0x3ff << 22)
	67
	68	#define SRCONFIG_SRENABLE BIT(11)
	69	#define SRCONFIG_SENENABLE BIT(10)
	70	#define SRCONFIG_ERRGEN_EN BIT(9)
	71	#define SRCONFIG_MINMAXAVG_EN BIT(8)
	72	#define SRCONFIG_DELAYCTRL BIT(2)
	73
	74	/* AVGWEIGHT */
	75	#define AVGWEIGHT_SENPAVGWEIGHT_SHIFT 2
	76	#define AVGWEIGHT_SENNAVGWEIGHT_SHIFT 0
	77
	78	/* NVALUERECIPROCAL */
	79	#define NVALUERECIPROCAL_SENPGAIN_SHIFT 20
	80	#define NVALUERECIPROCAL_SENNGAIN_SHIFT 16
	81	#define NVALUERECIPROCAL_RNSENP_SHIFT 8
	82	#define NVALUERECIPROCAL_RNSENN_SHIFT 0
	83
	84	/* ERRCONFIG */
	85	#define ERRCONFIG_ERRWEIGHT_SHIFT 16
	86	#define ERRCONFIG_ERRMAXLIMIT_SHIFT 8
	87	#define ERRCONFIG_ERRMINLIMIT_SHIFT 0
	88
	89	#define SR_ERRWEIGHT_MASK (0x07 << 16)
	90	#define SR_ERRMAXLIMIT_MASK (0xff << 8)
91	#define SR_ERRMINLIMIT_MASK (0xff << 0)
92
93	#define ERRCONFIG_VPBOUNDINTEN_V1 BIT(31)
94	#define ERRCONFIG_VPBOUNDINTST_V1 BIT(30)
95	#define ERRCONFIG_MCUACCUMINTEN BIT(29)
96	#define ERRCONFIG_MCUACCUMINTST BIT(28)
97	#define ERRCONFIG_MCUVALIDINTEN BIT(27)
98	#define ERRCONFIG_MCUVALIDINTST BIT(26)
99	#define ERRCONFIG_MCUBOUNDINTEN BIT(25)
100	#define ERRCONFIG_MCUBOUNDINTST BIT(24)
101	#define ERRCONFIG_MCUDISACKINTEN BIT(23)
102	#define ERRCONFIG_VPBOUNDINTST_V2 BIT(23)
103	#define ERRCONFIG_MCUDISACKINTST BIT(22)
104	#define ERRCONFIG_VPBOUNDINTEN_V2 BIT(22)
105
106	#define ERRCONFIG_STATUS_V1_MASK (ERRCONFIG_VPBOUNDINTST_V1 \| \
107	ERRCONFIG_MCUACCUMINTST \| \
108	ERRCONFIG_MCUVALIDINTST \| \
109	ERRCONFIG_MCUBOUNDINTST \| \
110	ERRCONFIG_MCUDISACKINTST)
111	/* IRQSTATUS */
112	#define IRQSTATUS_MCUACCUMINT BIT(3)
113	#define IRQSTATUS_MCVALIDINT BIT(2)
114	#define IRQSTATUS_MCBOUNDSINT BIT(1)
115	#define IRQSTATUS_MCUDISABLEACKINT BIT(0)
116
117	/* IRQENABLE_SET and IRQENABLE_CLEAR */
118	#define IRQENABLE_MCUACCUMINT BIT(3)
119	#define IRQENABLE_MCUVALIDINT BIT(2)
120	#define IRQENABLE_MCUBOUNDSINT BIT(1)
121	#define IRQENABLE_MCUDISABLEACKINT BIT(0)
122
123	/* Common Bit values */
124
125	#define SRCLKLENGTH_12MHZ_SYSCLK 0x3c
126	#define SRCLKLENGTH_13MHZ_SYSCLK 0x41
127	#define SRCLKLENGTH_19MHZ_SYSCLK 0x60
128	#define SRCLKLENGTH_26MHZ_SYSCLK 0x82
129	#define SRCLKLENGTH_38MHZ_SYSCLK 0xC0
130
131	/*
132	* 3430 specific values. Maybe these should be passed from board file or
133	* pmic structures.
134	*/
135	#define OMAP3430_SR_ACCUMDATA 0x1f4
136
137	#define OMAP3430_SR1_SENPAVGWEIGHT 0x03
138	#define OMAP3430_SR1_SENNAVGWEIGHT 0x03
139
140	#define OMAP3430_SR2_SENPAVGWEIGHT 0x01
141	#define OMAP3430_SR2_SENNAVGWEIGHT 0x01
142
143	#define OMAP3430_SR_ERRWEIGHT 0x04
144	#define OMAP3430_SR_ERRMAXLIMIT 0x02
145
80821c9c JP	146	struct omap_sr {
	147	struct list_head node;
	148	struct platform_device *pdev;
	149	struct omap_sr_nvalue_table *nvalue_table;
	150	struct voltagedomain *voltdm;
	151	struct dentry *dbg_dir;
	152	unsigned int irq;
	153	int srid;
	154	int ip_type;
	155	int nvalue_count;
	156	bool autocomp_active;
	157	u32 clk_length;
	158	u32 err_weight;
	159	u32 err_minlimit;
	160	u32 err_maxlimit;
	161	u32 accum_data;
	162	u32 senn_avgweight;
	163	u32 senp_avgweight;
	164	u32 senp_mod;
	165	u32 senn_mod;
	166	void __iomem *base;
	167	};
	168
984aa6db TG	169	/**
	170	* struct omap_sr_pmic_data - Strucutre to be populated by pmic code to pass
	171	* pmic specific info to smartreflex driver
	172	*
	173	* @sr_pmic_init: API to initialize smartreflex on the PMIC side.
	174	*/
	175	struct omap_sr_pmic_data {
	176	void (*sr_pmic_init) (void);
	177	};
	178
cea6b942 SG	179	/**
	180	* struct omap_smartreflex_dev_attr - Smartreflex Device attribute.
	181	*
	182	* @sensor_voltdm_name: Name of voltdomain of SR instance
	183	*/
	184	struct omap_smartreflex_dev_attr {
	185	const char *sensor_voltdm_name;
	186	};
	187
984aa6db TG	188	#ifdef CONFIG_OMAP_SMARTREFLEX
	189	/*
	190	* The smart reflex driver supports CLASS1 CLASS2 and CLASS3 SR.
	191	* The smartreflex class driver should pass the class type.
	192	* Should be used to populate the class_type field of the
	193	* omap_smartreflex_class_data structure.
	194	*/
	195	#define SR_CLASS1 0x1
	196	#define SR_CLASS2 0x2
	197	#define SR_CLASS3 0x3
	198
	199	/**
	200	* struct omap_sr_class_data - Smartreflex class driver info
	201	*
	202	* @enable: API to enable a particular class smaartreflex.
	203	* @disable: API to disable a particular class smartreflex.
	204	* @configure: API to configure a particular class smartreflex.
	205	* @notify: API to notify the class driver about an event in SR.
	206	* Not needed for class3.
	207	* @notify_flags: specify the events to be notified to the class driver
	208	* @class_type: specify which smartreflex class.
	209	* Can be used by the SR driver to take any class
	210	* based decisions.
	211	*/
	212	struct omap_sr_class_data {
80821c9c JP	213	int (enable)(struct omap_sr sr);
	214	int (disable)(struct omap_sr sr, int is_volt_reset);
	215	int (configure)(struct omap_sr sr);
	216	int (notify)(struct omap_sr sr, u32 status);
984aa6db TG	217	u8 notify_flags;
	218	u8 class_type;
	219	};
	220
	221	/**
	222	* struct omap_sr_nvalue_table - Smartreflex n-target value info
	223	*
	224	* @efuse_offs: The offset of the efuse where n-target values are stored.
	225	* @nvalue: The n-target value.
	226	*/
	227	struct omap_sr_nvalue_table {
	228	u32 efuse_offs;
	229	u32 nvalue;
	230	};
	231
	232	/**
	233	* struct omap_sr_data - Smartreflex platform data.
	234	*
	235	* @ip_type: Smartreflex IP type.
	236	* @senp_mod: SENPENABLE value for the sr
	237	* @senn_mod: SENNENABLE value for sr
	238	* @nvalue_count: Number of distinct nvalues in the nvalue table
	239	* @enable_on_init: whether this sr module needs to enabled at
	240	* boot up or not.
	241	* @nvalue_table: table containing the efuse offsets and nvalues
	242	* corresponding to them.
	243	* @voltdm: Pointer to the voltage domain associated with the SR
	244	*/
	245	struct omap_sr_data {
	246	int ip_type;
	247	u32 senp_mod;
	248	u32 senn_mod;
	249	int nvalue_count;
	250	bool enable_on_init;
	251	struct omap_sr_nvalue_table *nvalue_table;
	252	struct voltagedomain *voltdm;
	253	};
	254
	255	/* Smartreflex module enable/disable interface */
	256	void omap_sr_enable(struct voltagedomain *voltdm);
	257	void omap_sr_disable(struct voltagedomain *voltdm);
	258	void omap_sr_disable_reset_volt(struct voltagedomain *voltdm);
	259
	260	/* API to register the pmic specific data with the smartreflex driver. */
	261	void omap_sr_register_pmic(struct omap_sr_pmic_data *pmic_data);
	262
	263	/* Smartreflex driver hooks to be called from Smartreflex class driver */
	264	int sr_enable(struct voltagedomain *voltdm, unsigned long volt);
	265	void sr_disable(struct voltagedomain *voltdm);
	266	int sr_configure_errgen(struct voltagedomain *voltdm);
ad54c3dd	267	int sr_disable_errgen(struct voltagedomain *voltdm);
984aa6db TG	268	int sr_configure_minmax(struct voltagedomain *voltdm);
	269
	270	/* API to register the smartreflex class driver with the smartreflex driver */
	271	int sr_register_class(struct omap_sr_class_data *class_data);
	272	#else
	273	static inline void omap_sr_enable(struct voltagedomain *voltdm) {}
	274	static inline void omap_sr_disable(struct voltagedomain *voltdm) {}
	275	static inline void omap_sr_disable_reset_volt(
	276	struct voltagedomain *voltdm) {}
	277	static inline void omap_sr_register_pmic(
	278	struct omap_sr_pmic_data *pmic_data) {}
	279	#endif
	280	#endif