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Merge tag 'pm-5.14-rc8' of git://git.kernel.org/pub/scm/linux/kernel/git/rafael/linux-pm
[mirror_ubuntu-jammy-kernel.git] / include / linux / qcom_scm.h
CommitLineData
97fb5e8d 1/* SPDX-License-Identifier: GPL-2.0-only */
65f0c90b 2/* Copyright (c) 2010-2015, 2018-2019 The Linux Foundation. All rights reserved.
2ce76a6a 3 * Copyright (C) 2015 Linaro Ltd.
2a1eb58a 4 */
4de43476
KG		 5#ifndef __QCOM_SCM_H
6#define __QCOM_SCM_H
2a1eb58a 7
2076607a 8#include <linux/err.h>
29ff62f7
JC		 9#include <linux/types.h>
10#include <linux/cpumask.h>
11
e1279912
SV		 12#define QCOM_SCM_VERSION(major, minor) (((major) << 16) | ((minor) & 0xFF))
13#define QCOM_SCM_CPU_PWR_DOWN_L2_ON 0x0
14#define QCOM_SCM_CPU_PWR_DOWN_L2_OFF 0x1
9626b699 15#define QCOM_SCM_HDCP_MAX_REQ_CNT 5
16
17struct qcom_scm_hdcp_req {
18 u32 addr;
19 u32 val;
20};
21
d82bd359
AKD		 22struct qcom_scm_vmperm {
23 int vmid;
24 int perm;
25};
26
b0a1614f
RC		 27enum qcom_scm_ocmem_client {
28 QCOM_SCM_OCMEM_UNUSED_ID = 0x0,
29 QCOM_SCM_OCMEM_GRAPHICS_ID,
30 QCOM_SCM_OCMEM_VIDEO_ID,
31 QCOM_SCM_OCMEM_LP_AUDIO_ID,
32 QCOM_SCM_OCMEM_SENSORS_ID,
33 QCOM_SCM_OCMEM_OTHER_OS_ID,
34 QCOM_SCM_OCMEM_DEBUG_ID,
35};
36
0434a406
RC		 37enum qcom_scm_sec_dev_id {
38 QCOM_SCM_MDSS_DEV_ID = 1,
39 QCOM_SCM_OCMEM_DEV_ID = 5,
40 QCOM_SCM_PCIE0_DEV_ID = 11,
41 QCOM_SCM_PCIE1_DEV_ID = 12,
42 QCOM_SCM_GFX_DEV_ID = 18,
43 QCOM_SCM_UFS_DEV_ID = 19,
44 QCOM_SCM_ICE_DEV_ID = 20,
45};
46
0f206514
EB		 47enum qcom_scm_ice_cipher {
48 QCOM_SCM_ICE_CIPHER_AES_128_XTS = 0,
49 QCOM_SCM_ICE_CIPHER_AES_128_CBC = 1,
50 QCOM_SCM_ICE_CIPHER_AES_256_XTS = 3,
51 QCOM_SCM_ICE_CIPHER_AES_256_CBC = 4,
52};
53
d82bd359
AKD		 54#define QCOM_SCM_VMID_HLOS 0x3
55#define QCOM_SCM_VMID_MSS_MSA 0xF
cc53aabc
GS		 56#define QCOM_SCM_VMID_WLAN 0x18
57#define QCOM_SCM_VMID_WLAN_CE 0x19
d82bd359
AKD		 58#define QCOM_SCM_PERM_READ 0x4
59#define QCOM_SCM_PERM_WRITE 0x2
60#define QCOM_SCM_PERM_EXEC 0x1
61#define QCOM_SCM_PERM_RW (QCOM_SCM_PERM_READ | QCOM_SCM_PERM_WRITE)
62#define QCOM_SCM_PERM_RWX (QCOM_SCM_PERM_RW | QCOM_SCM_PERM_EXEC)
63
e1279912 64#if IS_ENABLED(CONFIG_QCOM_SCM)
65f0c90b
EB		 65extern bool qcom_scm_is_available(void);
66
e1279912
SV		 67extern int qcom_scm_set_cold_boot_addr(void *entry, const cpumask_t *cpus);
68extern int qcom_scm_set_warm_boot_addr(void *entry, const cpumask_t *cpus);
65f0c90b
EB		 69extern void qcom_scm_cpu_power_down(u32 flags);
70extern int qcom_scm_set_remote_state(u32 state, u32 id);
71
f01e90fe 72extern int qcom_scm_pas_init_image(u32 peripheral, const void *metadata,
e1279912 73 size_t size);
f01e90fe 74extern int qcom_scm_pas_mem_setup(u32 peripheral, phys_addr_t addr,
e1279912 75 phys_addr_t size);
f01e90fe
BA		 76extern int qcom_scm_pas_auth_and_reset(u32 peripheral);
77extern int qcom_scm_pas_shutdown(u32 peripheral);
65f0c90b
EB		 78extern bool qcom_scm_pas_supported(u32 peripheral);
79
80extern int qcom_scm_io_readl(phys_addr_t addr, unsigned int *val);
81extern int qcom_scm_io_writel(phys_addr_t addr, unsigned int val);
82
0434a406 83extern bool qcom_scm_restore_sec_cfg_available(void);
a2c680c6 84extern int qcom_scm_restore_sec_cfg(u32 device_id, u32 spare);
b182cc4d
SV		 85extern int qcom_scm_iommu_secure_ptbl_size(u32 spare, size_t *size);
86extern int qcom_scm_iommu_secure_ptbl_init(u64 addr, u32 size, u32 spare);
6d885330
SV		 87extern int qcom_scm_mem_protect_video_var(u32 cp_start, u32 cp_size,
88 u32 cp_nonpixel_start,
89 u32 cp_nonpixel_size);
65f0c90b
EB		 90extern int qcom_scm_assign_mem(phys_addr_t mem_addr, size_t mem_sz,
91 unsigned int *src,
92 const struct qcom_scm_vmperm *newvm,
93 unsigned int dest_cnt);
94
95extern bool qcom_scm_ocmem_lock_available(void);
96extern int qcom_scm_ocmem_lock(enum qcom_scm_ocmem_client id, u32 offset,
97 u32 size, u32 mode);
98extern int qcom_scm_ocmem_unlock(enum qcom_scm_ocmem_client id, u32 offset,
99 u32 size);
100
0f206514
EB		 101extern bool qcom_scm_ice_available(void);
102extern int qcom_scm_ice_invalidate_key(u32 index);
103extern int qcom_scm_ice_set_key(u32 index, const u8 *key, u32 key_size,
104 enum qcom_scm_ice_cipher cipher,
105 u32 data_unit_size);
106
65f0c90b
EB		 107extern bool qcom_scm_hdcp_available(void);
108extern int qcom_scm_hdcp_req(struct qcom_scm_hdcp_req *req, u32 req_cnt,
109 u32 *resp);
110
5eb0e0e4 111extern int qcom_scm_qsmmu500_wait_safe_toggle(bool en);
e1279912 112#else
16ad9501
JM		 113
114#include <linux/errno.h>
115
e1279912 116static inline bool qcom_scm_is_available(void) { return false; }
65f0c90b
EB		 117
118static inline int qcom_scm_set_cold_boot_addr(void *entry,
119 const cpumask_t *cpus) { return -ENODEV; }
120static inline int qcom_scm_set_warm_boot_addr(void *entry,
121 const cpumask_t *cpus) { return -ENODEV; }
122static inline void qcom_scm_cpu_power_down(u32 flags) {}
123static inline u32 qcom_scm_set_remote_state(u32 state,u32 id)
124 { return -ENODEV; }
125
e1279912 126static inline int qcom_scm_pas_init_image(u32 peripheral, const void *metadata,
65f0c90b 127 size_t size) { return -ENODEV; }
e1279912 128static inline int qcom_scm_pas_mem_setup(u32 peripheral, phys_addr_t addr,
65f0c90b
EB		 129 phys_addr_t size) { return -ENODEV; }
130static inline int qcom_scm_pas_auth_and_reset(u32 peripheral)
131 { return -ENODEV; }
e1279912 132static inline int qcom_scm_pas_shutdown(u32 peripheral) { return -ENODEV; }
65f0c90b
EB		 133static inline bool qcom_scm_pas_supported(u32 peripheral) { return false; }
134
135static inline int qcom_scm_io_readl(phys_addr_t addr, unsigned int *val)
136 { return -ENODEV; }
137static inline int qcom_scm_io_writel(phys_addr_t addr, unsigned int val)
138 { return -ENODEV; }
139
a6a0bc7c 140static inline bool qcom_scm_restore_sec_cfg_available(void) { return false; }
65f0c90b
EB		 141static inline int qcom_scm_restore_sec_cfg(u32 device_id, u32 spare)
142 { return -ENODEV; }
143static inline int qcom_scm_iommu_secure_ptbl_size(u32 spare, size_t *size)
144 { return -ENODEV; }
145static inline int qcom_scm_iommu_secure_ptbl_init(u64 addr, u32 size, u32 spare)
146 { return -ENODEV; }
6d885330
SV		 147extern inline int qcom_scm_mem_protect_video_var(u32 cp_start, u32 cp_size,
148 u32 cp_nonpixel_start,
149 u32 cp_nonpixel_size)
150 { return -ENODEV; }
65f0c90b
EB		 151static inline int qcom_scm_assign_mem(phys_addr_t mem_addr, size_t mem_sz,
152 unsigned int *src, const struct qcom_scm_vmperm *newvm,
153 unsigned int dest_cnt) { return -ENODEV; }
154
155static inline bool qcom_scm_ocmem_lock_available(void) { return false; }
156static inline int qcom_scm_ocmem_lock(enum qcom_scm_ocmem_client id, u32 offset,
157 u32 size, u32 mode) { return -ENODEV; }
158static inline int qcom_scm_ocmem_unlock(enum qcom_scm_ocmem_client id,
159 u32 offset, u32 size) { return -ENODEV; }
160
0f206514
EB		 161static inline bool qcom_scm_ice_available(void) { return false; }
162static inline int qcom_scm_ice_invalidate_key(u32 index) { return -ENODEV; }
163static inline int qcom_scm_ice_set_key(u32 index, const u8 *key, u32 key_size,
164 enum qcom_scm_ice_cipher cipher,
165 u32 data_unit_size) { return -ENODEV; }
166
65f0c90b
EB		 167static inline bool qcom_scm_hdcp_available(void) { return false; }
168static inline int qcom_scm_hdcp_req(struct qcom_scm_hdcp_req *req, u32 req_cnt,
169 u32 *resp) { return -ENODEV; }
170
171static inline int qcom_scm_qsmmu500_wait_safe_toggle(bool en)
172 { return -ENODEV; }
e1279912 173#endif
2a1eb58a 174#endif
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