[mirror_ubuntu-artful-kernel.git] / include / linux / sh_dma.h

/*
 * Header for the new SH dmaengine driver
 *
 * Copyright (C) 2010 Guennadi Liakhovetski <g.liakhovetski@gmx.de>
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */
#ifndef SH_DMA_H
#define SH_DMA_H

#include <linux/list.h>
#include <linux/dmaengine.h>

/* Used by slave DMA clients to request DMA to/from a specific peripheral */
struct sh_dmae_slave {
	unsigned int			slave_id; /* Set by the platform */
	struct device			*dma_dev; /* Set by the platform */
	const struct sh_dmae_slave_config	*config;  /* Set by the driver */
};

struct sh_dmae_regs {
	u32 sar; /* SAR / source address */
	u32 dar; /* DAR / destination address */
	u32 tcr; /* TCR / transfer count */
};

struct sh_desc {
	struct sh_dmae_regs hw;
	struct list_head node;
	struct dma_async_tx_descriptor async_tx;
	enum dma_transfer_direction direction;
	dma_cookie_t cookie;
	size_t partial;
	int chunks;
	int mark;
};

struct sh_dmae_slave_config {
	unsigned int			slave_id;
	dma_addr_t			addr;
	u32				chcr;
	char				mid_rid;
};

struct sh_dmae_channel {
	unsigned int	offset;
	unsigned int	dmars;
	unsigned int	dmars_bit;
	unsigned int	chclr_offset;
};

struct sh_dmae_pdata {
	const struct sh_dmae_slave_config *slave;
	int slave_num;
	const struct sh_dmae_channel *channel;
	int channel_num;
	unsigned int ts_low_shift;
	unsigned int ts_low_mask;
	unsigned int ts_high_shift;
	unsigned int ts_high_mask;
	const unsigned int *ts_shift;
	int ts_shift_num;
	u16 dmaor_init;
	unsigned int chcr_offset;
	u32 chcr_ie_bit;

	unsigned int dmaor_is_32bit:1;
	unsigned int needs_tend_set:1;
	unsigned int no_dmars:1;
	unsigned int chclr_present:1;
	unsigned int slave_only:1;
};

/* DMA register */
#define SAR	0x00
#define DAR	0x04
#define TCR	0x08
#define CHCR	0x0C
#define DMAOR	0x40

#define TEND	0x18 /* USB-DMAC */

/* DMAOR definitions */
#define DMAOR_AE	0x00000004
#define DMAOR_NMIF	0x00000002
#define DMAOR_DME	0x00000001

/* Definitions for the SuperH DMAC */
#define REQ_L	0x00000000
#define REQ_E	0x00080000
#define RACK_H	0x00000000
#define RACK_L	0x00040000
#define ACK_R	0x00000000
#define ACK_W	0x00020000
#define ACK_H	0x00000000
#define ACK_L	0x00010000
#define DM_INC	0x00004000
#define DM_DEC	0x00008000
#define DM_FIX	0x0000c000
#define SM_INC	0x00001000
#define SM_DEC	0x00002000
#define SM_FIX	0x00003000
#define RS_IN	0x00000200
#define RS_OUT	0x00000300
#define TS_BLK	0x00000040
#define TM_BUR	0x00000020
#define CHCR_DE	0x00000001
#define CHCR_TE	0x00000002
#define CHCR_IE	0x00000004

#endif
Commit	Line	Data
b2623a61 MD	1	/*
	2	* Header for the new SH dmaengine driver
	3	*
	4	* Copyright (C) 2010 Guennadi Liakhovetski <g.liakhovetski@gmx.de>
	5	*
	6	* This program is free software; you can redistribute it and/or modify
	7	* it under the terms of the GNU General Public License version 2 as
	8	* published by the Free Software Foundation.
	9	*/
	10	#ifndef SH_DMA_H
	11	#define SH_DMA_H
	12
	13	#include <linux/list.h>
	14	#include <linux/dmaengine.h>
	15
	16	/* Used by slave DMA clients to request DMA to/from a specific peripheral */
	17	struct sh_dmae_slave {
	18	unsigned int slave_id; /* Set by the platform */
	19	struct device dma_dev; / Set by the platform */
5bac942d	20	const struct sh_dmae_slave_config config; / Set by the driver */
b2623a61 MD	21	};
	22
	23	struct sh_dmae_regs {
	24	u32 sar; /* SAR / source address */
	25	u32 dar; /* DAR / destination address */
	26	u32 tcr; /* TCR / transfer count */
	27	};
	28
	29	struct sh_desc {
	30	struct sh_dmae_regs hw;
	31	struct list_head node;
	32	struct dma_async_tx_descriptor async_tx;
db8196df	33	enum dma_transfer_direction direction;
b2623a61 MD	34	dma_cookie_t cookie;
	35	size_t partial;
	36	int chunks;
	37	int mark;
	38	};
5bac942d	39
b2623a61 MD	40	struct sh_dmae_slave_config {
	41	unsigned int slave_id;
	42	dma_addr_t addr;
	43	u32 chcr;
	44	char mid_rid;
	45	};
	46
	47	struct sh_dmae_channel {
	48	unsigned int offset;
	49	unsigned int dmars;
	50	unsigned int dmars_bit;
c11b46c3	51	unsigned int chclr_offset;
b2623a61 MD	52	};
	53
	54	struct sh_dmae_pdata {
5bac942d	55	const struct sh_dmae_slave_config *slave;
b2623a61	56	int slave_num;
5bac942d	57	const struct sh_dmae_channel *channel;
b2623a61 MD	58	int channel_num;
	59	unsigned int ts_low_shift;
	60	unsigned int ts_low_mask;
	61	unsigned int ts_high_shift;
	62	unsigned int ts_high_mask;
5bac942d	63	const unsigned int *ts_shift;
b2623a61 MD	64	int ts_shift_num;
b2623a61 MD	65	u16 dmaor_init;
5899a723	66	unsigned int chcr_offset;
67c6269e	67	u32 chcr_ie_bit;
e76c3af8 KM	68
e76c3af8 KM	69	unsigned int dmaor_is_32bit:1;
260bf2c5 KM	70	unsigned int needs_tend_set:1;
260bf2c5 KM	71	unsigned int no_dmars:1;
c11b46c3	72	unsigned int chclr_present:1;
e9c8d7a0	73	unsigned int slave_only:1;
b2623a61 MD	74	};
	75
	76	/* DMA register */
	77	#define SAR 0x00
	78	#define DAR 0x04
	79	#define TCR 0x08
	80	#define CHCR 0x0C
	81	#define DMAOR 0x40
	82
260bf2c5 KM	83	#define TEND 0x18 /* USB-DMAC */
260bf2c5 KM	84
b2623a61 MD	85	/* DMAOR definitions */
	86	#define DMAOR_AE 0x00000004
	87	#define DMAOR_NMIF 0x00000002
	88	#define DMAOR_DME 0x00000001
	89
	90	/* Definitions for the SuperH DMAC */
	91	#define REQ_L 0x00000000
	92	#define REQ_E 0x00080000
	93	#define RACK_H 0x00000000
	94	#define RACK_L 0x00040000
	95	#define ACK_R 0x00000000
	96	#define ACK_W 0x00020000
	97	#define ACK_H 0x00000000
	98	#define ACK_L 0x00010000
	99	#define DM_INC 0x00004000
	100	#define DM_DEC 0x00008000
	101	#define DM_FIX 0x0000c000
	102	#define SM_INC 0x00001000
	103	#define SM_DEC 0x00002000
	104	#define SM_FIX 0x00003000
	105	#define RS_IN 0x00000200
	106	#define RS_OUT 0x00000300
	107	#define TS_BLK 0x00000040
	108	#define TM_BUR 0x00000020
	109	#define CHCR_DE 0x00000001
	110	#define CHCR_TE 0x00000002
	111	#define CHCR_IE 0x00000004
	112
	113	#endif