projects / mirror_ubuntu-artful-kernel.git / blame
| Commit | Line | Data |
|---|---|---|
| b2623a61 MD |
1 | /* |
| 2 | * Header for the new SH dmaengine driver | |
| 3 | * | |
| 4 | * Copyright (C) 2010 Guennadi Liakhovetski <g.liakhovetski@gmx.de> | |
| 5 | * | |
| 6 | * This program is free software; you can redistribute it and/or modify | |
| 7 | * it under the terms of the GNU General Public License version 2 as | |
| 8 | * published by the Free Software Foundation. | |
| 9 | */ | |
| 10 | #ifndef SH_DMA_H | |
| 11 | #define SH_DMA_H | |
| 12 | ||
| 13 | #include <linux/list.h> | |
| 14 | #include <linux/dmaengine.h> | |
| 15 | ||
| 16 | /* Used by slave DMA clients to request DMA to/from a specific peripheral */ | |
| 17 | struct sh_dmae_slave { | |
| 18 | unsigned int slave_id; /* Set by the platform */ | |
| 19 | struct device *dma_dev; /* Set by the platform */ | |
| 5bac942d | 20 | const struct sh_dmae_slave_config *config; /* Set by the driver */ |
| b2623a61 MD |
21 | }; |
| 22 | ||
| 23 | struct sh_dmae_regs { | |
| 24 | u32 sar; /* SAR / source address */ | |
| 25 | u32 dar; /* DAR / destination address */ | |
| 26 | u32 tcr; /* TCR / transfer count */ | |
| 27 | }; | |
| 28 | ||
| 29 | struct sh_desc { | |
| 30 | struct sh_dmae_regs hw; | |
| 31 | struct list_head node; | |
| 32 | struct dma_async_tx_descriptor async_tx; | |
| 33 | enum dma_data_direction direction; | |
| 34 | dma_cookie_t cookie; | |
| 35 | size_t partial; | |
| 36 | int chunks; | |
| 37 | int mark; | |
| 38 | }; | |
| 5bac942d | 39 | |
| b2623a61 MD |
40 | struct sh_dmae_slave_config { |
| 41 | unsigned int slave_id; | |
| 42 | dma_addr_t addr; | |
| 43 | u32 chcr; | |
| 44 | char mid_rid; | |
| 45 | }; | |
| 46 | ||
| 47 | struct sh_dmae_channel { | |
| 48 | unsigned int offset; | |
| 49 | unsigned int dmars; | |
| 50 | unsigned int dmars_bit; | |
| 51 | }; | |
| 52 | ||
| 53 | struct sh_dmae_pdata { | |
| 5bac942d | 54 | const struct sh_dmae_slave_config *slave; |
| b2623a61 | 55 | int slave_num; |
| 5bac942d | 56 | const struct sh_dmae_channel *channel; |
| b2623a61 MD |
57 | int channel_num; |
| 58 | unsigned int ts_low_shift; | |
| 59 | unsigned int ts_low_mask; | |
| 60 | unsigned int ts_high_shift; | |
| 61 | unsigned int ts_high_mask; | |
| 5bac942d | 62 | const unsigned int *ts_shift; |
| b2623a61 MD |
63 | int ts_shift_num; |
| 64 | u16 dmaor_init; | |
| 5899a723 | 65 | unsigned int chcr_offset; |
| 67c6269e | 66 | u32 chcr_ie_bit; |
| e76c3af8 KM |
67 | |
| 68 | unsigned int dmaor_is_32bit:1; | |
| b2623a61 MD |
69 | }; |
| 70 | ||
| 71 | /* DMA register */ | |
| 72 | #define SAR 0x00 | |
| 73 | #define DAR 0x04 | |
| 74 | #define TCR 0x08 | |
| 75 | #define CHCR 0x0C | |
| 76 | #define DMAOR 0x40 | |
| 77 | ||
| 78 | /* DMAOR definitions */ | |
| 79 | #define DMAOR_AE 0x00000004 | |
| 80 | #define DMAOR_NMIF 0x00000002 | |
| 81 | #define DMAOR_DME 0x00000001 | |
| 82 | ||
| 83 | /* Definitions for the SuperH DMAC */ | |
| 84 | #define REQ_L 0x00000000 | |
| 85 | #define REQ_E 0x00080000 | |
| 86 | #define RACK_H 0x00000000 | |
| 87 | #define RACK_L 0x00040000 | |
| 88 | #define ACK_R 0x00000000 | |
| 89 | #define ACK_W 0x00020000 | |
| 90 | #define ACK_H 0x00000000 | |
| 91 | #define ACK_L 0x00010000 | |
| 92 | #define DM_INC 0x00004000 | |
| 93 | #define DM_DEC 0x00008000 | |
| 94 | #define DM_FIX 0x0000c000 | |
| 95 | #define SM_INC 0x00001000 | |
| 96 | #define SM_DEC 0x00002000 | |
| 97 | #define SM_FIX 0x00003000 | |
| 98 | #define RS_IN 0x00000200 | |
| 99 | #define RS_OUT 0x00000300 | |
| 100 | #define TS_BLK 0x00000040 | |
| 101 | #define TM_BUR 0x00000020 | |
| 102 | #define CHCR_DE 0x00000001 | |
| 103 | #define CHCR_TE 0x00000002 | |
| 104 | #define CHCR_IE 0x00000004 | |
| 105 | ||
| 106 | #endif |