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1 | /* sm501-regs.h |
2 | * | |
3 | * Copyright 2006 Simtec Electronics | |
4 | * | |
5 | * This program is free software; you can redistribute it and/or modify | |
6 | * it under the terms of the GNU General Public License version 2 as | |
7 | * published by the Free Software Foundation. | |
8 | * | |
9 | * Silicon Motion SM501 register definitions | |
10 | */ | |
11 | ||
12 | /* System Configuration area */ | |
13 | /* System config base */ | |
14 | #define SM501_SYS_CONFIG (0x000000) | |
15 | ||
16 | /* config 1 */ | |
17 | #define SM501_SYSTEM_CONTROL (0x000000) | |
18 | #define SM501_MISC_CONTROL (0x000004) | |
19 | ||
20 | #define SM501_MISC_BUS_SH (0x0) | |
21 | #define SM501_MISC_BUS_PCI (0x1) | |
22 | #define SM501_MISC_BUS_XSCALE (0x2) | |
23 | #define SM501_MISC_BUS_NEC (0x6) | |
24 | #define SM501_MISC_BUS_MASK (0x7) | |
25 | ||
26 | #define SM501_MISC_VR_62MB (1<<3) | |
27 | #define SM501_MISC_CDR_RESET (1<<7) | |
28 | #define SM501_MISC_USB_LB (1<<8) | |
29 | #define SM501_MISC_USB_SLAVE (1<<9) | |
30 | #define SM501_MISC_BL_1 (1<<10) | |
31 | #define SM501_MISC_MC (1<<11) | |
32 | #define SM501_MISC_DAC_POWER (1<<12) | |
33 | #define SM501_MISC_IRQ_INVERT (1<<16) | |
34 | #define SM501_MISC_SH (1<<17) | |
35 | ||
36 | #define SM501_MISC_HOLD_EMPTY (0<<18) | |
37 | #define SM501_MISC_HOLD_8 (1<<18) | |
38 | #define SM501_MISC_HOLD_16 (2<<18) | |
39 | #define SM501_MISC_HOLD_24 (3<<18) | |
40 | #define SM501_MISC_HOLD_32 (4<<18) | |
41 | #define SM501_MISC_HOLD_MASK (7<<18) | |
42 | ||
43 | #define SM501_MISC_FREQ_12 (1<<24) | |
44 | #define SM501_MISC_PNL_24BIT (1<<25) | |
45 | #define SM501_MISC_8051_LE (1<<26) | |
46 | ||
47 | ||
48 | ||
49 | #define SM501_GPIO31_0_CONTROL (0x000008) | |
50 | #define SM501_GPIO63_32_CONTROL (0x00000C) | |
51 | #define SM501_DRAM_CONTROL (0x000010) | |
52 | ||
53 | /* command list */ | |
54 | #define SM501_ARBTRTN_CONTROL (0x000014) | |
55 | ||
56 | /* command list */ | |
57 | #define SM501_COMMAND_LIST_STATUS (0x000024) | |
58 | ||
59 | /* interrupt debug */ | |
60 | #define SM501_RAW_IRQ_STATUS (0x000028) | |
61 | #define SM501_RAW_IRQ_CLEAR (0x000028) | |
62 | #define SM501_IRQ_STATUS (0x00002C) | |
63 | #define SM501_IRQ_MASK (0x000030) | |
64 | #define SM501_DEBUG_CONTROL (0x000034) | |
65 | ||
66 | /* power management */ | |
67 | #define SM501_CURRENT_GATE (0x000038) | |
68 | #define SM501_CURRENT_CLOCK (0x00003C) | |
69 | #define SM501_POWER_MODE_0_GATE (0x000040) | |
70 | #define SM501_POWER_MODE_0_CLOCK (0x000044) | |
71 | #define SM501_POWER_MODE_1_GATE (0x000048) | |
72 | #define SM501_POWER_MODE_1_CLOCK (0x00004C) | |
73 | #define SM501_SLEEP_MODE_GATE (0x000050) | |
74 | #define SM501_POWER_MODE_CONTROL (0x000054) | |
75 | ||
76 | /* power gates for units within the 501 */ | |
77 | #define SM501_GATE_HOST (0) | |
78 | #define SM501_GATE_MEMORY (1) | |
79 | #define SM501_GATE_DISPLAY (2) | |
80 | #define SM501_GATE_2D_ENGINE (3) | |
81 | #define SM501_GATE_CSC (4) | |
82 | #define SM501_GATE_ZVPORT (5) | |
83 | #define SM501_GATE_GPIO (6) | |
84 | #define SM501_GATE_UART0 (7) | |
85 | #define SM501_GATE_UART1 (8) | |
86 | #define SM501_GATE_SSP (10) | |
87 | #define SM501_GATE_USB_HOST (11) | |
88 | #define SM501_GATE_USB_GADGET (12) | |
89 | #define SM501_GATE_UCONTROLLER (17) | |
90 | #define SM501_GATE_AC97 (18) | |
91 | ||
92 | /* panel clock */ | |
93 | #define SM501_CLOCK_P2XCLK (24) | |
94 | /* crt clock */ | |
95 | #define SM501_CLOCK_V2XCLK (16) | |
96 | /* main clock */ | |
97 | #define SM501_CLOCK_MCLK (8) | |
98 | /* SDRAM controller clock */ | |
99 | #define SM501_CLOCK_M1XCLK (0) | |
100 | ||
101 | /* config 2 */ | |
102 | #define SM501_PCI_MASTER_BASE (0x000058) | |
103 | #define SM501_ENDIAN_CONTROL (0x00005C) | |
104 | #define SM501_DEVICEID (0x000060) | |
105 | /* 0x050100A0 */ | |
106 | ||
107 | #define SM501_PLLCLOCK_COUNT (0x000064) | |
108 | #define SM501_MISC_TIMING (0x000068) | |
109 | #define SM501_CURRENT_SDRAM_CLOCK (0x00006C) | |
110 | ||
111 | /* GPIO base */ | |
112 | #define SM501_GPIO (0x010000) | |
113 | #define SM501_GPIO_DATA_LOW (0x00) | |
114 | #define SM501_GPIO_DATA_HIGH (0x04) | |
115 | #define SM501_GPIO_DDR_LOW (0x08) | |
116 | #define SM501_GPIO_DDR_HIGH (0x0C) | |
117 | #define SM501_GPIO_IRQ_SETUP (0x10) | |
118 | #define SM501_GPIO_IRQ_STATUS (0x14) | |
119 | #define SM501_GPIO_IRQ_RESET (0x14) | |
120 | ||
121 | /* I2C controller base */ | |
122 | #define SM501_I2C (0x010040) | |
123 | #define SM501_I2C_BYTE_COUNT (0x00) | |
124 | #define SM501_I2C_CONTROL (0x01) | |
125 | #define SM501_I2C_STATUS (0x02) | |
126 | #define SM501_I2C_RESET (0x02) | |
127 | #define SM501_I2C_SLAVE_ADDRESS (0x03) | |
128 | #define SM501_I2C_DATA (0x04) | |
129 | ||
130 | /* SSP base */ | |
131 | #define SM501_SSP (0x020000) | |
132 | ||
133 | /* Uart 0 base */ | |
134 | #define SM501_UART0 (0x030000) | |
135 | ||
136 | /* Uart 1 base */ | |
137 | #define SM501_UART1 (0x030020) | |
138 | ||
139 | /* USB host port base */ | |
140 | #define SM501_USB_HOST (0x040000) | |
141 | ||
142 | /* USB slave/gadget base */ | |
143 | #define SM501_USB_GADGET (0x060000) | |
144 | ||
145 | /* USB slave/gadget data port base */ | |
146 | #define SM501_USB_GADGET_DATA (0x070000) | |
147 | ||
148 | /* Display contoller/video engine base */ | |
149 | #define SM501_DC (0x080000) | |
150 | ||
151 | /* common defines for the SM501 address registers */ | |
152 | #define SM501_ADDR_FLIP (1<<31) | |
153 | #define SM501_ADDR_EXT (1<<27) | |
154 | #define SM501_ADDR_CS1 (1<<26) | |
155 | #define SM501_ADDR_MASK (0x3f << 26) | |
156 | ||
157 | #define SM501_FIFO_MASK (0x3 << 16) | |
158 | #define SM501_FIFO_1 (0x0 << 16) | |
159 | #define SM501_FIFO_3 (0x1 << 16) | |
160 | #define SM501_FIFO_7 (0x2 << 16) | |
161 | #define SM501_FIFO_11 (0x3 << 16) | |
162 | ||
163 | /* common registers for panel and the crt */ | |
164 | #define SM501_OFF_DC_H_TOT (0x000) | |
165 | #define SM501_OFF_DC_V_TOT (0x008) | |
166 | #define SM501_OFF_DC_H_SYNC (0x004) | |
167 | #define SM501_OFF_DC_V_SYNC (0x00C) | |
168 | ||
169 | #define SM501_DC_PANEL_CONTROL (0x000) | |
170 | ||
171 | #define SM501_DC_PANEL_CONTROL_FPEN (1<<27) | |
172 | #define SM501_DC_PANEL_CONTROL_BIAS (1<<26) | |
173 | #define SM501_DC_PANEL_CONTROL_DATA (1<<25) | |
174 | #define SM501_DC_PANEL_CONTROL_VDD (1<<24) | |
175 | #define SM501_DC_PANEL_CONTROL_DP (1<<23) | |
176 | ||
177 | #define SM501_DC_PANEL_CONTROL_TFT_888 (0<<21) | |
178 | #define SM501_DC_PANEL_CONTROL_TFT_333 (1<<21) | |
179 | #define SM501_DC_PANEL_CONTROL_TFT_444 (2<<21) | |
180 | ||
181 | #define SM501_DC_PANEL_CONTROL_DE (1<<20) | |
182 | ||
183 | #define SM501_DC_PANEL_CONTROL_LCD_TFT (0<<18) | |
184 | #define SM501_DC_PANEL_CONTROL_LCD_STN8 (1<<18) | |
185 | #define SM501_DC_PANEL_CONTROL_LCD_STN12 (2<<18) | |
186 | ||
187 | #define SM501_DC_PANEL_CONTROL_CP (1<<14) | |
188 | #define SM501_DC_PANEL_CONTROL_VSP (1<<13) | |
189 | #define SM501_DC_PANEL_CONTROL_HSP (1<<12) | |
190 | #define SM501_DC_PANEL_CONTROL_CK (1<<9) | |
191 | #define SM501_DC_PANEL_CONTROL_TE (1<<8) | |
192 | #define SM501_DC_PANEL_CONTROL_VPD (1<<7) | |
193 | #define SM501_DC_PANEL_CONTROL_VP (1<<6) | |
194 | #define SM501_DC_PANEL_CONTROL_HPD (1<<5) | |
195 | #define SM501_DC_PANEL_CONTROL_HP (1<<4) | |
196 | #define SM501_DC_PANEL_CONTROL_GAMMA (1<<3) | |
197 | #define SM501_DC_PANEL_CONTROL_EN (1<<2) | |
198 | ||
199 | #define SM501_DC_PANEL_CONTROL_8BPP (0<<0) | |
200 | #define SM501_DC_PANEL_CONTROL_16BPP (1<<0) | |
201 | #define SM501_DC_PANEL_CONTROL_32BPP (2<<0) | |
202 | ||
203 | ||
204 | #define SM501_DC_PANEL_PANNING_CONTROL (0x004) | |
205 | #define SM501_DC_PANEL_COLOR_KEY (0x008) | |
206 | #define SM501_DC_PANEL_FB_ADDR (0x00C) | |
207 | #define SM501_DC_PANEL_FB_OFFSET (0x010) | |
208 | #define SM501_DC_PANEL_FB_WIDTH (0x014) | |
209 | #define SM501_DC_PANEL_FB_HEIGHT (0x018) | |
210 | #define SM501_DC_PANEL_TL_LOC (0x01C) | |
211 | #define SM501_DC_PANEL_BR_LOC (0x020) | |
212 | #define SM501_DC_PANEL_H_TOT (0x024) | |
213 | #define SM501_DC_PANEL_H_SYNC (0x028) | |
214 | #define SM501_DC_PANEL_V_TOT (0x02C) | |
215 | #define SM501_DC_PANEL_V_SYNC (0x030) | |
216 | #define SM501_DC_PANEL_CUR_LINE (0x034) | |
217 | ||
218 | #define SM501_DC_VIDEO_CONTROL (0x040) | |
219 | #define SM501_DC_VIDEO_FB0_ADDR (0x044) | |
220 | #define SM501_DC_VIDEO_FB_WIDTH (0x048) | |
221 | #define SM501_DC_VIDEO_FB0_LAST_ADDR (0x04C) | |
222 | #define SM501_DC_VIDEO_TL_LOC (0x050) | |
223 | #define SM501_DC_VIDEO_BR_LOC (0x054) | |
224 | #define SM501_DC_VIDEO_SCALE (0x058) | |
225 | #define SM501_DC_VIDEO_INIT_SCALE (0x05C) | |
226 | #define SM501_DC_VIDEO_YUV_CONSTANTS (0x060) | |
227 | #define SM501_DC_VIDEO_FB1_ADDR (0x064) | |
228 | #define SM501_DC_VIDEO_FB1_LAST_ADDR (0x068) | |
229 | ||
230 | #define SM501_DC_VIDEO_ALPHA_CONTROL (0x080) | |
231 | #define SM501_DC_VIDEO_ALPHA_FB_ADDR (0x084) | |
232 | #define SM501_DC_VIDEO_ALPHA_FB_OFFSET (0x088) | |
233 | #define SM501_DC_VIDEO_ALPHA_FB_LAST_ADDR (0x08C) | |
234 | #define SM501_DC_VIDEO_ALPHA_TL_LOC (0x090) | |
235 | #define SM501_DC_VIDEO_ALPHA_BR_LOC (0x094) | |
236 | #define SM501_DC_VIDEO_ALPHA_SCALE (0x098) | |
237 | #define SM501_DC_VIDEO_ALPHA_INIT_SCALE (0x09C) | |
238 | #define SM501_DC_VIDEO_ALPHA_CHROMA_KEY (0x0A0) | |
239 | #define SM501_DC_VIDEO_ALPHA_COLOR_LOOKUP (0x0A4) | |
240 | ||
241 | #define SM501_DC_PANEL_HWC_BASE (0x0F0) | |
242 | #define SM501_DC_PANEL_HWC_ADDR (0x0F0) | |
243 | #define SM501_DC_PANEL_HWC_LOC (0x0F4) | |
244 | #define SM501_DC_PANEL_HWC_COLOR_1_2 (0x0F8) | |
245 | #define SM501_DC_PANEL_HWC_COLOR_3 (0x0FC) | |
246 | ||
247 | #define SM501_HWC_EN (1<<31) | |
248 | ||
249 | #define SM501_OFF_HWC_ADDR (0x00) | |
250 | #define SM501_OFF_HWC_LOC (0x04) | |
251 | #define SM501_OFF_HWC_COLOR_1_2 (0x08) | |
252 | #define SM501_OFF_HWC_COLOR_3 (0x0C) | |
253 | ||
254 | #define SM501_DC_ALPHA_CONTROL (0x100) | |
255 | #define SM501_DC_ALPHA_FB_ADDR (0x104) | |
256 | #define SM501_DC_ALPHA_FB_OFFSET (0x108) | |
257 | #define SM501_DC_ALPHA_TL_LOC (0x10C) | |
258 | #define SM501_DC_ALPHA_BR_LOC (0x110) | |
259 | #define SM501_DC_ALPHA_CHROMA_KEY (0x114) | |
260 | #define SM501_DC_ALPHA_COLOR_LOOKUP (0x118) | |
261 | ||
262 | #define SM501_DC_CRT_CONTROL (0x200) | |
263 | ||
264 | #define SM501_DC_CRT_CONTROL_TVP (1<<15) | |
265 | #define SM501_DC_CRT_CONTROL_CP (1<<14) | |
266 | #define SM501_DC_CRT_CONTROL_VSP (1<<13) | |
267 | #define SM501_DC_CRT_CONTROL_HSP (1<<12) | |
268 | #define SM501_DC_CRT_CONTROL_VS (1<<11) | |
269 | #define SM501_DC_CRT_CONTROL_BLANK (1<<10) | |
270 | #define SM501_DC_CRT_CONTROL_SEL (1<<9) | |
271 | #define SM501_DC_CRT_CONTROL_TE (1<<8) | |
272 | #define SM501_DC_CRT_CONTROL_PIXEL_MASK (0xF << 4) | |
273 | #define SM501_DC_CRT_CONTROL_GAMMA (1<<3) | |
274 | #define SM501_DC_CRT_CONTROL_ENABLE (1<<2) | |
275 | ||
276 | #define SM501_DC_CRT_CONTROL_8BPP (0<<0) | |
277 | #define SM501_DC_CRT_CONTROL_16BPP (1<<0) | |
278 | #define SM501_DC_CRT_CONTROL_32BPP (2<<0) | |
279 | ||
280 | #define SM501_DC_CRT_FB_ADDR (0x204) | |
281 | #define SM501_DC_CRT_FB_OFFSET (0x208) | |
282 | #define SM501_DC_CRT_H_TOT (0x20C) | |
283 | #define SM501_DC_CRT_H_SYNC (0x210) | |
284 | #define SM501_DC_CRT_V_TOT (0x214) | |
285 | #define SM501_DC_CRT_V_SYNC (0x218) | |
286 | #define SM501_DC_CRT_SIGNATURE_ANALYZER (0x21C) | |
287 | #define SM501_DC_CRT_CUR_LINE (0x220) | |
288 | #define SM501_DC_CRT_MONITOR_DETECT (0x224) | |
289 | ||
290 | #define SM501_DC_CRT_HWC_BASE (0x230) | |
291 | #define SM501_DC_CRT_HWC_ADDR (0x230) | |
292 | #define SM501_DC_CRT_HWC_LOC (0x234) | |
293 | #define SM501_DC_CRT_HWC_COLOR_1_2 (0x238) | |
294 | #define SM501_DC_CRT_HWC_COLOR_3 (0x23C) | |
295 | ||
296 | #define SM501_DC_PANEL_PALETTE (0x400) | |
297 | ||
298 | #define SM501_DC_VIDEO_PALETTE (0x800) | |
299 | ||
300 | #define SM501_DC_CRT_PALETTE (0xC00) | |
301 | ||
302 | /* Zoom Video port base */ | |
303 | #define SM501_ZVPORT (0x090000) | |
304 | ||
305 | /* AC97/I2S base */ | |
306 | #define SM501_AC97 (0x0A0000) | |
307 | ||
308 | /* 8051 micro controller base */ | |
309 | #define SM501_UCONTROLLER (0x0B0000) | |
310 | ||
311 | /* 8051 micro controller SRAM base */ | |
312 | #define SM501_UCONTROLLER_SRAM (0x0C0000) | |
313 | ||
314 | /* DMA base */ | |
315 | #define SM501_DMA (0x0D0000) | |
316 | ||
317 | /* 2d engine base */ | |
318 | #define SM501_2D_ENGINE (0x100000) | |
319 | #define SM501_2D_SOURCE (0x00) | |
320 | #define SM501_2D_DESTINATION (0x04) | |
321 | #define SM501_2D_DIMENSION (0x08) | |
322 | #define SM501_2D_CONTROL (0x0C) | |
323 | #define SM501_2D_PITCH (0x10) | |
324 | #define SM501_2D_FOREGROUND (0x14) | |
325 | #define SM501_2D_BACKGROUND (0x18) | |
326 | #define SM501_2D_STRETCH (0x1C) | |
327 | #define SM501_2D_COLOR_COMPARE (0x20) | |
328 | #define SM501_2D_COLOR_COMPARE_MASK (0x24) | |
329 | #define SM501_2D_MASK (0x28) | |
330 | #define SM501_2D_CLIP_TL (0x2C) | |
331 | #define SM501_2D_CLIP_BR (0x30) | |
332 | #define SM501_2D_MONO_PATTERN_LOW (0x34) | |
333 | #define SM501_2D_MONO_PATTERN_HIGH (0x38) | |
334 | #define SM501_2D_WINDOW_WIDTH (0x3C) | |
335 | #define SM501_2D_SOURCE_BASE (0x40) | |
336 | #define SM501_2D_DESTINATION_BASE (0x44) | |
337 | #define SM501_2D_ALPHA (0x48) | |
338 | #define SM501_2D_WRAP (0x4C) | |
339 | #define SM501_2D_STATUS (0x50) | |
340 | ||
341 | #define SM501_CSC_Y_SOURCE_BASE (0xC8) | |
342 | #define SM501_CSC_CONSTANTS (0xCC) | |
343 | #define SM501_CSC_Y_SOURCE_X (0xD0) | |
344 | #define SM501_CSC_Y_SOURCE_Y (0xD4) | |
345 | #define SM501_CSC_U_SOURCE_BASE (0xD8) | |
346 | #define SM501_CSC_V_SOURCE_BASE (0xDC) | |
347 | #define SM501_CSC_SOURCE_DIMENSION (0xE0) | |
348 | #define SM501_CSC_SOURCE_PITCH (0xE4) | |
349 | #define SM501_CSC_DESTINATION (0xE8) | |
350 | #define SM501_CSC_DESTINATION_DIMENSION (0xEC) | |
351 | #define SM501_CSC_DESTINATION_PITCH (0xF0) | |
352 | #define SM501_CSC_SCALE_FACTOR (0xF4) | |
353 | #define SM501_CSC_DESTINATION_BASE (0xF8) | |
354 | #define SM501_CSC_CONTROL (0xFC) | |
355 | ||
356 | /* 2d engine data port base */ | |
357 | #define SM501_2D_ENGINE_DATA (0x110000) |