[mirror_ubuntu-bionic-kernel.git] / include / linux / spi / adi_spi3.h

/*
 * Analog Devices SPI3 controller driver
 *
 * Copyright (c) 2014 Analog Devices Inc.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 */

#ifndef _ADI_SPI3_H_
#define _ADI_SPI3_H_

#include <linux/types.h>

/* SPI_CONTROL */
#define SPI_CTL_EN                  0x00000001    /* Enable */
#define SPI_CTL_MSTR                0x00000002    /* Master/Slave */
#define SPI_CTL_PSSE                0x00000004    /* controls modf error in master mode */
#define SPI_CTL_ODM                 0x00000008    /* Open Drain Mode */
#define SPI_CTL_CPHA                0x00000010    /* Clock Phase */
#define SPI_CTL_CPOL                0x00000020    /* Clock Polarity */
#define SPI_CTL_ASSEL               0x00000040    /* Slave Select Pin Control */
#define SPI_CTL_SELST               0x00000080    /* Slave Select Polarity in-between transfers */
#define SPI_CTL_EMISO               0x00000100    /* Enable MISO */
#define SPI_CTL_SIZE                0x00000600    /* Word Transfer Size */
#define SPI_CTL_SIZE08              0x00000000    /* SIZE: 8 bits */
#define SPI_CTL_SIZE16              0x00000200    /* SIZE: 16 bits */
#define SPI_CTL_SIZE32              0x00000400    /* SIZE: 32 bits */
#define SPI_CTL_LSBF                0x00001000    /* LSB First */
#define SPI_CTL_FCEN                0x00002000    /* Flow-Control Enable */
#define SPI_CTL_FCCH                0x00004000    /* Flow-Control Channel Selection */
#define SPI_CTL_FCPL                0x00008000    /* Flow-Control Polarity */
#define SPI_CTL_FCWM                0x00030000    /* Flow-Control Water-Mark */
#define SPI_CTL_FIFO0               0x00000000    /* FCWM: TFIFO empty or RFIFO Full */
#define SPI_CTL_FIFO1               0x00010000    /* FCWM: TFIFO 75% or more empty or RFIFO 75% or more full */
#define SPI_CTL_FIFO2               0x00020000    /* FCWM: TFIFO 50% or more empty or RFIFO 50% or more full */
#define SPI_CTL_FMODE               0x00040000    /* Fast-mode Enable */
#define SPI_CTL_MIOM                0x00300000    /* Multiple I/O Mode */
#define SPI_CTL_MIO_DIS             0x00000000    /* MIOM: Disable */
#define SPI_CTL_MIO_DUAL            0x00100000    /* MIOM: Enable DIOM (Dual I/O Mode) */
#define SPI_CTL_MIO_QUAD            0x00200000    /* MIOM: Enable QUAD (Quad SPI Mode) */
#define SPI_CTL_SOSI                0x00400000    /* Start on MOSI */
/* SPI_RX_CONTROL */
#define SPI_RXCTL_REN               0x00000001    /* Receive Channel Enable */
#define SPI_RXCTL_RTI               0x00000004    /* Receive Transfer Initiate */
#define SPI_RXCTL_RWCEN             0x00000008    /* Receive Word Counter Enable */
#define SPI_RXCTL_RDR               0x00000070    /* Receive Data Request */
#define SPI_RXCTL_RDR_DIS           0x00000000    /* RDR: Disabled */
#define SPI_RXCTL_RDR_NE            0x00000010    /* RDR: RFIFO not empty */
#define SPI_RXCTL_RDR_25            0x00000020    /* RDR: RFIFO 25% full */
#define SPI_RXCTL_RDR_50            0x00000030    /* RDR: RFIFO 50% full */
#define SPI_RXCTL_RDR_75            0x00000040    /* RDR: RFIFO 75% full */
#define SPI_RXCTL_RDR_FULL          0x00000050    /* RDR: RFIFO full */
#define SPI_RXCTL_RDO               0x00000100    /* Receive Data Over-Run */
#define SPI_RXCTL_RRWM              0x00003000    /* FIFO Regular Water-Mark */
#define SPI_RXCTL_RWM_0             0x00000000    /* RRWM: RFIFO Empty */
#define SPI_RXCTL_RWM_25            0x00001000    /* RRWM: RFIFO 25% full */
#define SPI_RXCTL_RWM_50            0x00002000    /* RRWM: RFIFO 50% full */
#define SPI_RXCTL_RWM_75            0x00003000    /* RRWM: RFIFO 75% full */
#define SPI_RXCTL_RUWM              0x00070000    /* FIFO Urgent Water-Mark */
#define SPI_RXCTL_UWM_DIS           0x00000000    /* RUWM: Disabled */
#define SPI_RXCTL_UWM_25            0x00010000    /* RUWM: RFIFO 25% full */
#define SPI_RXCTL_UWM_50            0x00020000    /* RUWM: RFIFO 50% full */
#define SPI_RXCTL_UWM_75            0x00030000    /* RUWM: RFIFO 75% full */
#define SPI_RXCTL_UWM_FULL          0x00040000    /* RUWM: RFIFO full */
/* SPI_TX_CONTROL */
#define SPI_TXCTL_TEN               0x00000001    /* Transmit Channel Enable */
#define SPI_TXCTL_TTI               0x00000004    /* Transmit Transfer Initiate */
#define SPI_TXCTL_TWCEN             0x00000008    /* Transmit Word Counter Enable */
#define SPI_TXCTL_TDR               0x00000070    /* Transmit Data Request */
#define SPI_TXCTL_TDR_DIS           0x00000000    /* TDR: Disabled */
#define SPI_TXCTL_TDR_NF            0x00000010    /* TDR: TFIFO not full */
#define SPI_TXCTL_TDR_25            0x00000020    /* TDR: TFIFO 25% empty */
#define SPI_TXCTL_TDR_50            0x00000030    /* TDR: TFIFO 50% empty */
#define SPI_TXCTL_TDR_75            0x00000040    /* TDR: TFIFO 75% empty */
#define SPI_TXCTL_TDR_EMPTY         0x00000050    /* TDR: TFIFO empty */
#define SPI_TXCTL_TDU               0x00000100    /* Transmit Data Under-Run */
#define SPI_TXCTL_TRWM              0x00003000    /* FIFO Regular Water-Mark */
#define SPI_TXCTL_RWM_FULL          0x00000000    /* TRWM: TFIFO full */
#define SPI_TXCTL_RWM_25            0x00001000    /* TRWM: TFIFO 25% empty */
#define SPI_TXCTL_RWM_50            0x00002000    /* TRWM: TFIFO 50% empty */
#define SPI_TXCTL_RWM_75            0x00003000    /* TRWM: TFIFO 75% empty */
#define SPI_TXCTL_TUWM              0x00070000    /* FIFO Urgent Water-Mark */
#define SPI_TXCTL_UWM_DIS           0x00000000    /* TUWM: Disabled */
#define SPI_TXCTL_UWM_25            0x00010000    /* TUWM: TFIFO 25% empty */
#define SPI_TXCTL_UWM_50            0x00020000    /* TUWM: TFIFO 50% empty */
#define SPI_TXCTL_UWM_75            0x00030000    /* TUWM: TFIFO 75% empty */
#define SPI_TXCTL_UWM_EMPTY         0x00040000    /* TUWM: TFIFO empty */
/* SPI_CLOCK */
#define SPI_CLK_BAUD                0x0000FFFF    /* Baud Rate */
/* SPI_DELAY */
#define SPI_DLY_STOP                0x000000FF    /* Transfer delay time in multiples of SCK period */
#define SPI_DLY_LEADX               0x00000100    /* Extended (1 SCK) LEAD Control */
#define SPI_DLY_LAGX                0x00000200    /* Extended (1 SCK) LAG control */
/* SPI_SSEL */
#define SPI_SLVSEL_SSE1             0x00000002    /* SPISSEL1 Enable */
#define SPI_SLVSEL_SSE2             0x00000004    /* SPISSEL2 Enable */
#define SPI_SLVSEL_SSE3             0x00000008    /* SPISSEL3 Enable */
#define SPI_SLVSEL_SSE4             0x00000010    /* SPISSEL4 Enable */
#define SPI_SLVSEL_SSE5             0x00000020    /* SPISSEL5 Enable */
#define SPI_SLVSEL_SSE6             0x00000040    /* SPISSEL6 Enable */
#define SPI_SLVSEL_SSE7             0x00000080    /* SPISSEL7 Enable */
#define SPI_SLVSEL_SSEL1            0x00000200    /* SPISSEL1 Value */
#define SPI_SLVSEL_SSEL2            0x00000400    /* SPISSEL2 Value */
#define SPI_SLVSEL_SSEL3            0x00000800    /* SPISSEL3 Value */
#define SPI_SLVSEL_SSEL4            0x00001000    /* SPISSEL4 Value */
#define SPI_SLVSEL_SSEL5            0x00002000    /* SPISSEL5 Value */
#define SPI_SLVSEL_SSEL6            0x00004000    /* SPISSEL6 Value */
#define SPI_SLVSEL_SSEL7            0x00008000    /* SPISSEL7 Value */
/* SPI_RWC */
#define SPI_RWC_VALUE               0x0000FFFF    /* Received Word-Count */
/* SPI_RWCR */
#define SPI_RWCR_VALUE              0x0000FFFF    /* Received Word-Count Reload */
/* SPI_TWC */
#define SPI_TWC_VALUE               0x0000FFFF    /* Transmitted Word-Count */
/* SPI_TWCR */
#define SPI_TWCR_VALUE              0x0000FFFF    /* Transmitted Word-Count Reload */
/* SPI_IMASK */
#define SPI_IMSK_RUWM               0x00000002    /* Receive Urgent Water-Mark Interrupt Mask */
#define SPI_IMSK_TUWM               0x00000004    /* Transmit Urgent Water-Mark Interrupt Mask */
#define SPI_IMSK_ROM                0x00000010    /* Receive Over-Run Error Interrupt Mask */
#define SPI_IMSK_TUM                0x00000020    /* Transmit Under-Run Error Interrupt Mask */
#define SPI_IMSK_TCM                0x00000040    /* Transmit Collision Error Interrupt Mask */
#define SPI_IMSK_MFM                0x00000080    /* Mode Fault Error Interrupt Mask */
#define SPI_IMSK_RSM                0x00000100    /* Receive Start Interrupt Mask */
#define SPI_IMSK_TSM                0x00000200    /* Transmit Start Interrupt Mask */
#define SPI_IMSK_RFM                0x00000400    /* Receive Finish Interrupt Mask */
#define SPI_IMSK_TFM                0x00000800    /* Transmit Finish Interrupt Mask */
/* SPI_IMASKCL */
#define SPI_IMSK_CLR_RUW            0x00000002    /* Receive Urgent Water-Mark Interrupt Mask */
#define SPI_IMSK_CLR_TUWM           0x00000004    /* Transmit Urgent Water-Mark Interrupt Mask */
#define SPI_IMSK_CLR_ROM            0x00000010    /* Receive Over-Run Error Interrupt Mask */
#define SPI_IMSK_CLR_TUM            0x00000020    /* Transmit Under-Run Error Interrupt Mask */
#define SPI_IMSK_CLR_TCM            0x00000040    /* Transmit Collision Error Interrupt Mask */
#define SPI_IMSK_CLR_MFM            0x00000080    /* Mode Fault Error Interrupt Mask */
#define SPI_IMSK_CLR_RSM            0x00000100    /* Receive Start Interrupt Mask */
#define SPI_IMSK_CLR_TSM            0x00000200    /* Transmit Start Interrupt Mask */
#define SPI_IMSK_CLR_RFM            0x00000400    /* Receive Finish Interrupt Mask */
#define SPI_IMSK_CLR_TFM            0x00000800    /* Transmit Finish Interrupt Mask */
/* SPI_IMASKST */
#define SPI_IMSK_SET_RUWM           0x00000002    /* Receive Urgent Water-Mark Interrupt Mask */
#define SPI_IMSK_SET_TUWM           0x00000004    /* Transmit Urgent Water-Mark Interrupt Mask */
#define SPI_IMSK_SET_ROM            0x00000010    /* Receive Over-Run Error Interrupt Mask */
#define SPI_IMSK_SET_TUM            0x00000020    /* Transmit Under-Run Error Interrupt Mask */
#define SPI_IMSK_SET_TCM            0x00000040    /* Transmit Collision Error Interrupt Mask */
#define SPI_IMSK_SET_MFM            0x00000080    /* Mode Fault Error Interrupt Mask */
#define SPI_IMSK_SET_RSM            0x00000100    /* Receive Start Interrupt Mask */
#define SPI_IMSK_SET_TSM            0x00000200    /* Transmit Start Interrupt Mask */
#define SPI_IMSK_SET_RFM            0x00000400    /* Receive Finish Interrupt Mask */
#define SPI_IMSK_SET_TFM            0x00000800    /* Transmit Finish Interrupt Mask */
/* SPI_STATUS */
#define SPI_STAT_SPIF               0x00000001    /* SPI Finished */
#define SPI_STAT_RUWM               0x00000002    /* Receive Urgent Water-Mark Breached */
#define SPI_STAT_TUWM               0x00000004    /* Transmit Urgent Water-Mark Breached */
#define SPI_STAT_ROE                0x00000010    /* Receive Over-Run Error Indication */
#define SPI_STAT_TUE                0x00000020    /* Transmit Under-Run Error Indication */
#define SPI_STAT_TCE                0x00000040    /* Transmit Collision Error Indication */
#define SPI_STAT_MODF               0x00000080    /* Mode Fault Error Indication */
#define SPI_STAT_RS                 0x00000100    /* Receive Start Indication */
#define SPI_STAT_TS                 0x00000200    /* Transmit Start Indication */
#define SPI_STAT_RF                 0x00000400    /* Receive Finish Indication */
#define SPI_STAT_TF                 0x00000800    /* Transmit Finish Indication */
#define SPI_STAT_RFS                0x00007000    /* SPI_RFIFO status */
#define SPI_STAT_RFIFO_EMPTY        0x00000000    /* RFS: RFIFO Empty */
#define SPI_STAT_RFIFO_25           0x00001000    /* RFS: RFIFO 25% Full */
#define SPI_STAT_RFIFO_50           0x00002000    /* RFS: RFIFO 50% Full */
#define SPI_STAT_RFIFO_75           0x00003000    /* RFS: RFIFO 75% Full */
#define SPI_STAT_RFIFO_FULL         0x00004000    /* RFS: RFIFO Full */
#define SPI_STAT_TFS                0x00070000    /* SPI_TFIFO status */
#define SPI_STAT_TFIFO_FULL         0x00000000    /* TFS: TFIFO full */
#define SPI_STAT_TFIFO_25           0x00010000    /* TFS: TFIFO 25% empty */
#define SPI_STAT_TFIFO_50           0x00020000    /* TFS: TFIFO 50% empty */
#define SPI_STAT_TFIFO_75           0x00030000    /* TFS: TFIFO 75% empty */
#define SPI_STAT_TFIFO_EMPTY        0x00040000    /* TFS: TFIFO empty */
#define SPI_STAT_FCS                0x00100000    /* Flow-Control Stall Indication */
#define SPI_STAT_RFE                0x00400000    /* SPI_RFIFO Empty */
#define SPI_STAT_TFF                0x00800000    /* SPI_TFIFO Full */
/* SPI_ILAT */
#define SPI_ILAT_RUWMI              0x00000002    /* Receive Urgent Water Mark Interrupt */
#define SPI_ILAT_TUWMI              0x00000004    /* Transmit Urgent Water Mark Interrupt */
#define SPI_ILAT_ROI                0x00000010    /* Receive Over-Run Error Indication */
#define SPI_ILAT_TUI                0x00000020    /* Transmit Under-Run Error Indication */
#define SPI_ILAT_TCI                0x00000040    /* Transmit Collision Error Indication */
#define SPI_ILAT_MFI                0x00000080    /* Mode Fault Error Indication */
#define SPI_ILAT_RSI                0x00000100    /* Receive Start Indication */
#define SPI_ILAT_TSI                0x00000200    /* Transmit Start Indication */
#define SPI_ILAT_RFI                0x00000400    /* Receive Finish Indication */
#define SPI_ILAT_TFI                0x00000800    /* Transmit Finish Indication */
/* SPI_ILATCL */
#define SPI_ILAT_CLR_RUWMI          0x00000002    /* Receive Urgent Water Mark Interrupt */
#define SPI_ILAT_CLR_TUWMI          0x00000004    /* Transmit Urgent Water Mark Interrupt */
#define SPI_ILAT_CLR_ROI            0x00000010    /* Receive Over-Run Error Indication */
#define SPI_ILAT_CLR_TUI            0x00000020    /* Transmit Under-Run Error Indication */
#define SPI_ILAT_CLR_TCI            0x00000040    /* Transmit Collision Error Indication */
#define SPI_ILAT_CLR_MFI            0x00000080    /* Mode Fault Error Indication */
#define SPI_ILAT_CLR_RSI            0x00000100    /* Receive Start Indication */
#define SPI_ILAT_CLR_TSI            0x00000200    /* Transmit Start Indication */
#define SPI_ILAT_CLR_RFI            0x00000400    /* Receive Finish Indication */
#define SPI_ILAT_CLR_TFI            0x00000800    /* Transmit Finish Indication */

/*
 * adi spi3 registers layout
 */
struct adi_spi_regs {
	u32 revid;
	u32 control;
	u32 rx_control;
	u32 tx_control;
	u32 clock;
	u32 delay;
	u32 ssel;
	u32 rwc;
	u32 rwcr;
	u32 twc;
	u32 twcr;
	u32 reserved0;
	u32 emask;
	u32 emaskcl;
	u32 emaskst;
	u32 reserved1;
	u32 status;
	u32 elat;
	u32 elatcl;
	u32 reserved2;
	u32 rfifo;
	u32 reserved3;
	u32 tfifo;
};

#define MAX_CTRL_CS          8  /* cs in spi controller */

/* device.platform_data for SSP controller devices */
struct adi_spi3_master {
	u16 num_chipselect;
	u16 pin_req[7];
};

/* spi_board_info.controller_data for SPI slave devices,
 * copied to spi_device.platform_data ... mostly for dma tuning
 */
struct adi_spi3_chip {
	u32 control;
	u16 cs_chg_udelay; /* Some devices require 16-bit delays */
	u32 tx_dummy_val; /* tx value for rx only transfer */
	bool enable_dma;
};

#endif /* _ADI_SPI3_H_ */
Commit	Line	Data
e578bbde SJ	1	/*
	2	* Analog Devices SPI3 controller driver
	3	*
766e3721	4	* Copyright (c) 2014 Analog Devices Inc.
e578bbde SJ	5	*
	6	* This program is free software; you can redistribute it and/or modify
	7	* it under the terms of the GNU General Public License version 2 as
	8	* published by the Free Software Foundation.
	9	*
	10	* This program is distributed in the hope that it will be useful,
	11	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	12	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	13	* GNU General Public License for more details.
e578bbde SJ	14	*/
e578bbde SJ	15
766e3721 SJ	16	#ifndef _ADI_SPI3_H_
766e3721 SJ	17	#define _ADI_SPI3_H_
e578bbde SJ	18
	19	#include <linux/types.h>
	20
	21	/* SPI_CONTROL */
	22	#define SPI_CTL_EN 0x00000001 /* Enable */
	23	#define SPI_CTL_MSTR 0x00000002 /* Master/Slave */
	24	#define SPI_CTL_PSSE 0x00000004 /* controls modf error in master mode */
	25	#define SPI_CTL_ODM 0x00000008 /* Open Drain Mode */
	26	#define SPI_CTL_CPHA 0x00000010 /* Clock Phase */
	27	#define SPI_CTL_CPOL 0x00000020 /* Clock Polarity */
	28	#define SPI_CTL_ASSEL 0x00000040 /* Slave Select Pin Control */
	29	#define SPI_CTL_SELST 0x00000080 /* Slave Select Polarity in-between transfers */
	30	#define SPI_CTL_EMISO 0x00000100 /* Enable MISO */
	31	#define SPI_CTL_SIZE 0x00000600 /* Word Transfer Size */
	32	#define SPI_CTL_SIZE08 0x00000000 /* SIZE: 8 bits */
	33	#define SPI_CTL_SIZE16 0x00000200 /* SIZE: 16 bits */
	34	#define SPI_CTL_SIZE32 0x00000400 /* SIZE: 32 bits */
	35	#define SPI_CTL_LSBF 0x00001000 /* LSB First */
	36	#define SPI_CTL_FCEN 0x00002000 /* Flow-Control Enable */
	37	#define SPI_CTL_FCCH 0x00004000 /* Flow-Control Channel Selection */
	38	#define SPI_CTL_FCPL 0x00008000 /* Flow-Control Polarity */
	39	#define SPI_CTL_FCWM 0x00030000 /* Flow-Control Water-Mark */
	40	#define SPI_CTL_FIFO0 0x00000000 /* FCWM: TFIFO empty or RFIFO Full */
	41	#define SPI_CTL_FIFO1 0x00010000 /* FCWM: TFIFO 75% or more empty or RFIFO 75% or more full */
	42	#define SPI_CTL_FIFO2 0x00020000 /* FCWM: TFIFO 50% or more empty or RFIFO 50% or more full */
	43	#define SPI_CTL_FMODE 0x00040000 /* Fast-mode Enable */
	44	#define SPI_CTL_MIOM 0x00300000 /* Multiple I/O Mode */
	45	#define SPI_CTL_MIO_DIS 0x00000000 /* MIOM: Disable */
	46	#define SPI_CTL_MIO_DUAL 0x00100000 /* MIOM: Enable DIOM (Dual I/O Mode) */
	47	#define SPI_CTL_MIO_QUAD 0x00200000 /* MIOM: Enable QUAD (Quad SPI Mode) */
	48	#define SPI_CTL_SOSI 0x00400000 /* Start on MOSI */
	49	/* SPI_RX_CONTROL */
	50	#define SPI_RXCTL_REN 0x00000001 /* Receive Channel Enable */
	51	#define SPI_RXCTL_RTI 0x00000004 /* Receive Transfer Initiate */
	52	#define SPI_RXCTL_RWCEN 0x00000008 /* Receive Word Counter Enable */
	53	#define SPI_RXCTL_RDR 0x00000070 /* Receive Data Request */
	54	#define SPI_RXCTL_RDR_DIS 0x00000000 /* RDR: Disabled */
	55	#define SPI_RXCTL_RDR_NE 0x00000010 /* RDR: RFIFO not empty */
	56	#define SPI_RXCTL_RDR_25 0x00000020 /* RDR: RFIFO 25% full */
	57	#define SPI_RXCTL_RDR_50 0x00000030 /* RDR: RFIFO 50% full */
	58	#define SPI_RXCTL_RDR_75 0x00000040 /* RDR: RFIFO 75% full */
	59	#define SPI_RXCTL_RDR_FULL 0x00000050 /* RDR: RFIFO full */
	60	#define SPI_RXCTL_RDO 0x00000100 /* Receive Data Over-Run */
	61	#define SPI_RXCTL_RRWM 0x00003000 /* FIFO Regular Water-Mark */
	62	#define SPI_RXCTL_RWM_0 0x00000000 /* RRWM: RFIFO Empty */
	63	#define SPI_RXCTL_RWM_25 0x00001000 /* RRWM: RFIFO 25% full */
	64	#define SPI_RXCTL_RWM_50 0x00002000 /* RRWM: RFIFO 50% full */
	65	#define SPI_RXCTL_RWM_75 0x00003000 /* RRWM: RFIFO 75% full */
	66	#define SPI_RXCTL_RUWM 0x00070000 /* FIFO Urgent Water-Mark */
	67	#define SPI_RXCTL_UWM_DIS 0x00000000 /* RUWM: Disabled */
	68	#define SPI_RXCTL_UWM_25 0x00010000 /* RUWM: RFIFO 25% full */
	69	#define SPI_RXCTL_UWM_50 0x00020000 /* RUWM: RFIFO 50% full */
	70	#define SPI_RXCTL_UWM_75 0x00030000 /* RUWM: RFIFO 75% full */
	71	#define SPI_RXCTL_UWM_FULL 0x00040000 /* RUWM: RFIFO full */
	72	/* SPI_TX_CONTROL */
	73	#define SPI_TXCTL_TEN 0x00000001 /* Transmit Channel Enable */
	74	#define SPI_TXCTL_TTI 0x00000004 /* Transmit Transfer Initiate */
	75	#define SPI_TXCTL_TWCEN 0x00000008 /* Transmit Word Counter Enable */
	76	#define SPI_TXCTL_TDR 0x00000070 /* Transmit Data Request */
	77	#define SPI_TXCTL_TDR_DIS 0x00000000 /* TDR: Disabled */
	78	#define SPI_TXCTL_TDR_NF 0x00000010 /* TDR: TFIFO not full */
	79	#define SPI_TXCTL_TDR_25 0x00000020 /* TDR: TFIFO 25% empty */
	80	#define SPI_TXCTL_TDR_50 0x00000030 /* TDR: TFIFO 50% empty */
	81	#define SPI_TXCTL_TDR_75 0x00000040 /* TDR: TFIFO 75% empty */
82	#define SPI_TXCTL_TDR_EMPTY 0x00000050 /* TDR: TFIFO empty */
83	#define SPI_TXCTL_TDU 0x00000100 /* Transmit Data Under-Run */
84	#define SPI_TXCTL_TRWM 0x00003000 /* FIFO Regular Water-Mark */
85	#define SPI_TXCTL_RWM_FULL 0x00000000 /* TRWM: TFIFO full */
86	#define SPI_TXCTL_RWM_25 0x00001000 /* TRWM: TFIFO 25% empty */
87	#define SPI_TXCTL_RWM_50 0x00002000 /* TRWM: TFIFO 50% empty */
88	#define SPI_TXCTL_RWM_75 0x00003000 /* TRWM: TFIFO 75% empty */
89	#define SPI_TXCTL_TUWM 0x00070000 /* FIFO Urgent Water-Mark */
90	#define SPI_TXCTL_UWM_DIS 0x00000000 /* TUWM: Disabled */
91	#define SPI_TXCTL_UWM_25 0x00010000 /* TUWM: TFIFO 25% empty */
92	#define SPI_TXCTL_UWM_50 0x00020000 /* TUWM: TFIFO 50% empty */
93	#define SPI_TXCTL_UWM_75 0x00030000 /* TUWM: TFIFO 75% empty */
94	#define SPI_TXCTL_UWM_EMPTY 0x00040000 /* TUWM: TFIFO empty */
95	/* SPI_CLOCK */
96	#define SPI_CLK_BAUD 0x0000FFFF /* Baud Rate */
97	/* SPI_DELAY */
98	#define SPI_DLY_STOP 0x000000FF /* Transfer delay time in multiples of SCK period */
99	#define SPI_DLY_LEADX 0x00000100 /* Extended (1 SCK) LEAD Control */
100	#define SPI_DLY_LAGX 0x00000200 /* Extended (1 SCK) LAG control */
101	/* SPI_SSEL */
102	#define SPI_SLVSEL_SSE1 0x00000002 /* SPISSEL1 Enable */
103	#define SPI_SLVSEL_SSE2 0x00000004 /* SPISSEL2 Enable */
104	#define SPI_SLVSEL_SSE3 0x00000008 /* SPISSEL3 Enable */
105	#define SPI_SLVSEL_SSE4 0x00000010 /* SPISSEL4 Enable */
106	#define SPI_SLVSEL_SSE5 0x00000020 /* SPISSEL5 Enable */
107	#define SPI_SLVSEL_SSE6 0x00000040 /* SPISSEL6 Enable */
108	#define SPI_SLVSEL_SSE7 0x00000080 /* SPISSEL7 Enable */
109	#define SPI_SLVSEL_SSEL1 0x00000200 /* SPISSEL1 Value */
110	#define SPI_SLVSEL_SSEL2 0x00000400 /* SPISSEL2 Value */
111	#define SPI_SLVSEL_SSEL3 0x00000800 /* SPISSEL3 Value */
112	#define SPI_SLVSEL_SSEL4 0x00001000 /* SPISSEL4 Value */
113	#define SPI_SLVSEL_SSEL5 0x00002000 /* SPISSEL5 Value */
114	#define SPI_SLVSEL_SSEL6 0x00004000 /* SPISSEL6 Value */
115	#define SPI_SLVSEL_SSEL7 0x00008000 /* SPISSEL7 Value */
116	/* SPI_RWC */
117	#define SPI_RWC_VALUE 0x0000FFFF /* Received Word-Count */
118	/* SPI_RWCR */
119	#define SPI_RWCR_VALUE 0x0000FFFF /* Received Word-Count Reload */
120	/* SPI_TWC */
121	#define SPI_TWC_VALUE 0x0000FFFF /* Transmitted Word-Count */
122	/* SPI_TWCR */
123	#define SPI_TWCR_VALUE 0x0000FFFF /* Transmitted Word-Count Reload */
124	/* SPI_IMASK */
125	#define SPI_IMSK_RUWM 0x00000002 /* Receive Urgent Water-Mark Interrupt Mask */
126	#define SPI_IMSK_TUWM 0x00000004 /* Transmit Urgent Water-Mark Interrupt Mask */
127	#define SPI_IMSK_ROM 0x00000010 /* Receive Over-Run Error Interrupt Mask */
128	#define SPI_IMSK_TUM 0x00000020 /* Transmit Under-Run Error Interrupt Mask */
129	#define SPI_IMSK_TCM 0x00000040 /* Transmit Collision Error Interrupt Mask */
130	#define SPI_IMSK_MFM 0x00000080 /* Mode Fault Error Interrupt Mask */
131	#define SPI_IMSK_RSM 0x00000100 /* Receive Start Interrupt Mask */
132	#define SPI_IMSK_TSM 0x00000200 /* Transmit Start Interrupt Mask */
133	#define SPI_IMSK_RFM 0x00000400 /* Receive Finish Interrupt Mask */
134	#define SPI_IMSK_TFM 0x00000800 /* Transmit Finish Interrupt Mask */
135	/* SPI_IMASKCL */
136	#define SPI_IMSK_CLR_RUW 0x00000002 /* Receive Urgent Water-Mark Interrupt Mask */
137	#define SPI_IMSK_CLR_TUWM 0x00000004 /* Transmit Urgent Water-Mark Interrupt Mask */
138	#define SPI_IMSK_CLR_ROM 0x00000010 /* Receive Over-Run Error Interrupt Mask */
139	#define SPI_IMSK_CLR_TUM 0x00000020 /* Transmit Under-Run Error Interrupt Mask */
140	#define SPI_IMSK_CLR_TCM 0x00000040 /* Transmit Collision Error Interrupt Mask */
141	#define SPI_IMSK_CLR_MFM 0x00000080 /* Mode Fault Error Interrupt Mask */
142	#define SPI_IMSK_CLR_RSM 0x00000100 /* Receive Start Interrupt Mask */
143	#define SPI_IMSK_CLR_TSM 0x00000200 /* Transmit Start Interrupt Mask */
144	#define SPI_IMSK_CLR_RFM 0x00000400 /* Receive Finish Interrupt Mask */
145	#define SPI_IMSK_CLR_TFM 0x00000800 /* Transmit Finish Interrupt Mask */
146	/* SPI_IMASKST */
147	#define SPI_IMSK_SET_RUWM 0x00000002 /* Receive Urgent Water-Mark Interrupt Mask */
148	#define SPI_IMSK_SET_TUWM 0x00000004 /* Transmit Urgent Water-Mark Interrupt Mask */
149	#define SPI_IMSK_SET_ROM 0x00000010 /* Receive Over-Run Error Interrupt Mask */
150	#define SPI_IMSK_SET_TUM 0x00000020 /* Transmit Under-Run Error Interrupt Mask */
151	#define SPI_IMSK_SET_TCM 0x00000040 /* Transmit Collision Error Interrupt Mask */
152	#define SPI_IMSK_SET_MFM 0x00000080 /* Mode Fault Error Interrupt Mask */
153	#define SPI_IMSK_SET_RSM 0x00000100 /* Receive Start Interrupt Mask */
154	#define SPI_IMSK_SET_TSM 0x00000200 /* Transmit Start Interrupt Mask */
155	#define SPI_IMSK_SET_RFM 0x00000400 /* Receive Finish Interrupt Mask */
156	#define SPI_IMSK_SET_TFM 0x00000800 /* Transmit Finish Interrupt Mask */
157	/* SPI_STATUS */
158	#define SPI_STAT_SPIF 0x00000001 /* SPI Finished */
159	#define SPI_STAT_RUWM 0x00000002 /* Receive Urgent Water-Mark Breached */
160	#define SPI_STAT_TUWM 0x00000004 /* Transmit Urgent Water-Mark Breached */
161	#define SPI_STAT_ROE 0x00000010 /* Receive Over-Run Error Indication */
162	#define SPI_STAT_TUE 0x00000020 /* Transmit Under-Run Error Indication */
163	#define SPI_STAT_TCE 0x00000040 /* Transmit Collision Error Indication */
164	#define SPI_STAT_MODF 0x00000080 /* Mode Fault Error Indication */
165	#define SPI_STAT_RS 0x00000100 /* Receive Start Indication */
166	#define SPI_STAT_TS 0x00000200 /* Transmit Start Indication */
167	#define SPI_STAT_RF 0x00000400 /* Receive Finish Indication */
168	#define SPI_STAT_TF 0x00000800 /* Transmit Finish Indication */
169	#define SPI_STAT_RFS 0x00007000 /* SPI_RFIFO status */
170	#define SPI_STAT_RFIFO_EMPTY 0x00000000 /* RFS: RFIFO Empty */
171	#define SPI_STAT_RFIFO_25 0x00001000 /* RFS: RFIFO 25% Full */
172	#define SPI_STAT_RFIFO_50 0x00002000 /* RFS: RFIFO 50% Full */
173	#define SPI_STAT_RFIFO_75 0x00003000 /* RFS: RFIFO 75% Full */
174	#define SPI_STAT_RFIFO_FULL 0x00004000 /* RFS: RFIFO Full */
175	#define SPI_STAT_TFS 0x00070000 /* SPI_TFIFO status */
176	#define SPI_STAT_TFIFO_FULL 0x00000000 /* TFS: TFIFO full */
177	#define SPI_STAT_TFIFO_25 0x00010000 /* TFS: TFIFO 25% empty */
178	#define SPI_STAT_TFIFO_50 0x00020000 /* TFS: TFIFO 50% empty */
179	#define SPI_STAT_TFIFO_75 0x00030000 /* TFS: TFIFO 75% empty */
180	#define SPI_STAT_TFIFO_EMPTY 0x00040000 /* TFS: TFIFO empty */
181	#define SPI_STAT_FCS 0x00100000 /* Flow-Control Stall Indication */
182	#define SPI_STAT_RFE 0x00400000 /* SPI_RFIFO Empty */
183	#define SPI_STAT_TFF 0x00800000 /* SPI_TFIFO Full */
184	/* SPI_ILAT */
185	#define SPI_ILAT_RUWMI 0x00000002 /* Receive Urgent Water Mark Interrupt */
186	#define SPI_ILAT_TUWMI 0x00000004 /* Transmit Urgent Water Mark Interrupt */
187	#define SPI_ILAT_ROI 0x00000010 /* Receive Over-Run Error Indication */
188	#define SPI_ILAT_TUI 0x00000020 /* Transmit Under-Run Error Indication */
189	#define SPI_ILAT_TCI 0x00000040 /* Transmit Collision Error Indication */
190	#define SPI_ILAT_MFI 0x00000080 /* Mode Fault Error Indication */
191	#define SPI_ILAT_RSI 0x00000100 /* Receive Start Indication */
192	#define SPI_ILAT_TSI 0x00000200 /* Transmit Start Indication */
193	#define SPI_ILAT_RFI 0x00000400 /* Receive Finish Indication */
194	#define SPI_ILAT_TFI 0x00000800 /* Transmit Finish Indication */
195	/* SPI_ILATCL */
196	#define SPI_ILAT_CLR_RUWMI 0x00000002 /* Receive Urgent Water Mark Interrupt */
197	#define SPI_ILAT_CLR_TUWMI 0x00000004 /* Transmit Urgent Water Mark Interrupt */
198	#define SPI_ILAT_CLR_ROI 0x00000010 /* Receive Over-Run Error Indication */
199	#define SPI_ILAT_CLR_TUI 0x00000020 /* Transmit Under-Run Error Indication */
200	#define SPI_ILAT_CLR_TCI 0x00000040 /* Transmit Collision Error Indication */
201	#define SPI_ILAT_CLR_MFI 0x00000080 /* Mode Fault Error Indication */
202	#define SPI_ILAT_CLR_RSI 0x00000100 /* Receive Start Indication */
203	#define SPI_ILAT_CLR_TSI 0x00000200 /* Transmit Start Indication */
204	#define SPI_ILAT_CLR_RFI 0x00000400 /* Receive Finish Indication */
205	#define SPI_ILAT_CLR_TFI 0x00000800 /* Transmit Finish Indication */
206
207	/*
766e3721	208	* adi spi3 registers layout
e578bbde	209	*/
766e3721	210	struct adi_spi_regs {
e578bbde SJ	211	u32 revid;
	212	u32 control;
	213	u32 rx_control;
	214	u32 tx_control;
	215	u32 clock;
	216	u32 delay;
	217	u32 ssel;
	218	u32 rwc;
	219	u32 rwcr;
	220	u32 twc;
	221	u32 twcr;
	222	u32 reserved0;
	223	u32 emask;
	224	u32 emaskcl;
	225	u32 emaskst;
	226	u32 reserved1;
	227	u32 status;
	228	u32 elat;
	229	u32 elatcl;
	230	u32 reserved2;
	231	u32 rfifo;
	232	u32 reserved3;
	233	u32 tfifo;
	234	};
	235
	236	#define MAX_CTRL_CS 8 /* cs in spi controller */
	237
	238	/* device.platform_data for SSP controller devices */
766e3721	239	struct adi_spi3_master {
e578bbde SJ	240	u16 num_chipselect;
	241	u16 pin_req[7];
	242	};
	243
	244	/* spi_board_info.controller_data for SPI slave devices,
	245	* copied to spi_device.platform_data ... mostly for dma tuning
	246	*/
766e3721	247	struct adi_spi3_chip {
e578bbde SJ	248	u32 control;
	249	u16 cs_chg_udelay; /* Some devices require 16-bit delays */
	250	u32 tx_dummy_val; /* tx value for rx only transfer */
	251	bool enable_dma;
	252	};
	253
766e3721	254	#endif /* _ADI_SPI3_H_ */